Semiconductor device and method of manufacturing the same

Abstract

The embodiment of the present disclosure provides a preparation method of a semiconductor device, which comprises: providing a substrate, the substrate having a shallow trench isolation structure therein; forming a word line trench in the shallow trench isolation structure, the word line trench being provided with a gate insulation layer on the sidewall; forming a titanium nitride blocking layer, the titanium nitride blocking layer covering the surface of the gate insulation layer; and depositing a metal molybdenum gate, the metal molybdenum gate being selectively deposited on the titanium nitride blocking layer. The preparation method utilizes the property of selective deposition of the metal molybdenum gate, so that the metal molybdenum gate is only deposited on the titanium nitride blocking layer and is not deposited on other structures, thereby eliminating the need for an additional etching back step, simplifying the preparation process, reducing the process difficulty, and the resistivity of the metal molybdenum gate is lower than that of a TIN / W film, which is conducive to reducing the gate resistance and improving the performance of the semiconductor device.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more particularly to a semiconductor device and a method for fabricating the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor storage device in computers, consisting of many repeating memory cells. Each memory cell typically includes a capacitor and a transistor.

[0003] As the integration density of dynamic random access memory (DRAM) continues to increase, while studying the arrangement of transistors in DRAM array structures and how to reduce the size of individual functional devices in DRAM array structures, it is also necessary to consider the impact of small-sized functional devices on the overall electrical performance of semiconductor structures.

[0004] When using a vertical gate-all-around (GAA) transistor structure as a dynamic random access memory (DRAM) select transistor, its area can reach 4F² (F: the minimum pattern size achievable under given process conditions). In principle, higher density efficiency can be achieved. However, this places higher demands on the potential control and leakage prevention performance between small-sized functional devices, as well as on the overall electrical performance of the semiconductor structure. Summary of the Invention

[0005] The technical problem to be solved by this disclosure is to provide a semiconductor device and a method for fabricating the same, which can reduce the gate resistance and improve the performance of the semiconductor device.

[0006] To address the aforementioned technical problems, this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate having a shallow trench isolation structure; forming word line trenches in the shallow trench isolation structure, wherein a gate insulating layer is disposed on the sidewalls of the word line trenches; forming a titanium nitride barrier layer covering the surface of the gate insulating layer; and depositing a molybdenum metal gate, wherein the molybdenum metal gate is selectively deposited on the titanium nitride barrier layer.

[0007] In one embodiment, the step of forming a word line trench in the shallow trench isolation structure includes: etching the shallow trench isolation structure to form the word line trench, wherein the sidewalls of the word line trench expose the substrate; and oxidizing the substrate or depositing an oxide layer to form the gate insulating layer.

[0008] In one embodiment, the word line trench includes a first region and a second region, the first region and the second region being arranged in a direction perpendicular to the top surface of the substrate, and the second region being adjacent to the top surface of the substrate. The step of forming the word line trench further includes: forming an isolation layer on the sidewall of the second region of the word line trench, the sidewall of the first region of the word line trench exposing the substrate; and forming the gate insulating layer on the substrate surface exposed in the first region.

[0009] In one embodiment, the step of forming the gate insulating layer on the substrate surface exposed in the first region includes: oxidizing the substrate surface exposed in the first region to form the gate insulating layer, wherein the surface of the insulating layer protrudes from the surface of the gate insulating layer in a direction parallel to the top surface of the substrate.

[0010] In one embodiment, the step of forming the gate insulating layer on the substrate surface exposed in the first region includes: depositing an oxide layer on the substrate surface exposed in the first region to form the gate insulating layer.

[0011] In one embodiment, the step of forming an isolation layer on the sidewall of the second region of the word line groove includes: filling the word line groove with an isolation material layer; patterning the isolation material layer, and retaining the isolation material layer located on the sidewall of the second region of the word line groove as the isolation layer.

[0012] In one embodiment, the step of forming a titanium nitride barrier layer includes: depositing a titanium nitride barrier layer material, the titanium nitride barrier layer material covering the surface of the isolation layer, the surface of the gate insulating layer, and the bottom surface of the word line trench; removing the titanium nitride barrier layer material from the surface of the isolation layer and the bottom surface of the word line trench, and the remaining titanium nitride barrier layer material on the surface of the gate insulating layer serving as the titanium nitride barrier layer.

[0013] In one embodiment, after the step of depositing the molybdenum metal gate, the method further includes the step of forming a fill layer that at least fills the first region of the word line trench.

[0014] In one embodiment, the method of depositing a molybdenum metal gate includes: using molybdenum pentachloride and hydrogen as precursors, selectively depositing a molybdenum metal gate on the surface of the titanium nitride barrier layer using an atomic layer deposition process.

[0015] This disclosure also provides a semiconductor device comprising: a substrate having a shallow trench isolation structure therein, and a word line trench disposed within the shallow trench isolation structure; a gate structure disposed within the word line trench, the gate structure comprising a titanium nitride barrier layer and a molybdenum gate disposed sequentially, wherein the top surface of the molybdenum gate is flush with the top surface of the titanium nitride barrier layer in a direction perpendicular to the top surface of the substrate; and a gate insulating layer disposed between the substrate and the gate structure.

[0016] In one embodiment, the word line trench includes a first region and a second region, the first region and the second region are arranged in a direction perpendicular to the top surface of the substrate, and the second region is adjacent to the top surface of the substrate. The gate structure is disposed in the first region of the word line trench, and the isolation layer is disposed in the second region of the word line trench.

[0017] In one embodiment, the surface of the isolation layer protrudes beyond the surface of the gate insulating layer in a direction parallel to the top surface of the substrate.

[0018] In one embodiment, in a direction parallel to the top surface of the substrate, the surface of the isolation layer is flush with or protrudes from the surface of the titanium nitride barrier layer.

[0019] In one embodiment, a filler layer is also included, which at least fills the first region of the word line groove.

[0020] In one embodiment, the filler layer also covers the top surface of the substrate.

[0021] The semiconductor device and its fabrication method provided in this disclosure utilize the selective deposition property of the molybdenum gate, so that the molybdenum gate is deposited only on the titanium nitride barrier layer and not on other structures, such as substrates, isolation layers, or protective layers. This eliminates the need for additional back etching steps, simplifies the fabrication process, reduces the process difficulty, and the resistivity of the molybdenum gate is lower than that of the TIN / W film, which helps to reduce gate resistance and improve the performance of the semiconductor device. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the steps in the fabrication method of the semiconductor device provided in the embodiments of this disclosure;

[0023] Figures 2-8 This is a schematic diagram of the semiconductor structure formed by the main steps of the preparation method provided in the embodiments of this disclosure. Detailed Implementation

[0024] The specific embodiments of the semiconductor device and its fabrication method provided in this disclosure are described in detail below with reference to the accompanying drawings. The semiconductor device described in this specific embodiment may be, but is not limited to, DRAM.

[0025] Figure 1 This is a schematic diagram illustrating the steps of a semiconductor device fabrication method provided in this disclosure embodiment. Please refer to [link / reference]. Figure 1 The fabrication method includes: step S10, providing a substrate having a shallow trench isolation structure; step S11, forming a word line trench in the shallow trench isolation structure, wherein a gate insulating layer is disposed on the sidewall of the word line trench; step S12, forming a titanium nitride barrier layer, wherein the titanium nitride barrier layer covers the surface of the gate insulating layer; and step S13, depositing a molybdenum metal gate, wherein the molybdenum metal gate is selectively deposited on the titanium nitride barrier layer.

[0026] In the semiconductor device fabrication method provided in this disclosure, molybdenum is used as the gate electrode. The molybdenum gate electrode can be selectively deposited on the titanium nitride barrier layer instead of on the substrate. If tungsten is used as the gate electrode, it is necessary to deposit the tungsten and then etch it back to form the tungsten gate electrode. Therefore, compared to using tungsten as the gate electrode, the molybdenum gate electrode provided in this disclosure is deposited only on the titanium nitride barrier layer. Thus, there is no need to perform the etch-back step, simplifying the fabrication process and reducing the difficulty of semiconductor device fabrication.

[0027] The following is combined Figures 1 to 8 The method for fabricating the semiconductor device provided in the embodiments of this disclosure will be described in detail, wherein, Figures 2-8 This is a schematic diagram of the semiconductor structure formed by the main steps of the preparation method provided in the embodiments of this disclosure.

[0028] Please see Figure 1 and Figure 2 Step S10: Provide a substrate 200, wherein the substrate 200 has a shallow trench isolation structure 201.

[0029] The substrate 200 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate, etc. The substrate 200 may also be a substrate containing other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. The substrate 200 may also be a stacked structure, such as a silicon / germanium-silicon stack, etc. Furthermore, the substrate 200 may be an ion-doped substrate, which may be P-type doped or N-type doped. Multiple peripheral devices, such as field-effect transistors, capacitors, inductors, and / or diodes, may also be formed in the substrate 200. In this embodiment, the substrate 200 is a silicon substrate, which also includes other device structures, such as transistor structures and metal wiring structures, but these are not shown as they are not relevant to this invention.

[0030] The shallow trench isolation structure 201 is disposed within the substrate 200, with its upper surface exposed to the substrate 200. In this embodiment, the surface of the substrate 200 has a protective layer 202, which may be an oxide, such as silicon dioxide, used to protect the substrate 200 during semiconductor processing.

[0031] As an example, this disclosure provides a method for forming the shallow trench isolation structure 201, the method comprising: forming a shallow trench extending toward the interior of the substrate 200 within the substrate 200; and filling the shallow trench with an isolation material to form the shallow trench isolation structure 201. The isolation material may be an oxide or a composite layer of oxide and nitride. In this embodiment, silicon dioxide is used as an example of the isolation material.

[0032] Please see Figure 1 and Figure 5 In step S11, a word line trench 210 is formed in the shallow trench isolation structure 201, and a gate insulating layer 220 is provided on the sidewall of the word line trench 210.

[0033] In this step, the word line trench 210 extends a set distance into the shallow trench isolation structure 201, the bottom surface of the word line trench 210 is the surface of the shallow trench isolation structure 201, and the gate insulating layer 220 covers part of the sidewall of the word line trench 210.

[0034] Specifically, in this embodiment, the word line trench 210 includes a first region 210A and a second region 210B. The first region 210A and the second region 210B are arranged along a direction perpendicular to the top surface of the substrate 200 (as shown by the Y direction in the figure), and the second region 210B is adjacent to the top surface of the substrate 200. The gate insulating layer 220 covers the sidewall of the first region 210A of the word line trench 210, and an isolation layer 230 is formed on the sidewall of the second region 210B of the word line trench 210.

[0035] As an example, this disclosure provides a method for forming the word line groove 210. The method includes the following steps:

[0036] Please see Figure 3 The shallow trench isolation structure 201 is etched to form the word line trench 210, and the sidewalls of the word line trench 210 expose the substrate 200. In this step, the word line trench 210 is formed using photolithography and etching processes, and the word line trench 210 extends a predetermined distance into the shallow trench isolation structure 201. In this embodiment, the protective layer 202 on the surface of the substrate 200 is also penetrated by the word line trench 210.

[0037] Please see Figure 4 An isolation layer 230 is formed on the sidewall of the second region 210B of the word line trench 210, exposing the substrate 200 on the sidewall of the first region 210A of the word line trench 210. The isolation layer 230 may be a silicon nitride layer. In this step, the surface of the isolation layer 230 protrudes beyond the surface of the substrate 200 exposed by the first region 210A of the word line trench 210 in a direction parallel to the top surface of the substrate 200 (as shown by the X direction in the figure). The isolation layer 230 can be used to limit the height of the subsequently formed gate structure 240 from the top surface of the substrate 200, thereby enabling controllability of the formation position of the gate structure 240.

[0038] Specifically, in this step, the method for forming the isolation layer 230 includes:

[0039] An isolation material layer is filled within the word line trench 210. For example, silicon nitride is filled within the word line trench 210. Due to limitations in semiconductor manufacturing processes, the isolation material layer covers not only the inner wall of the word line trench 210 but also the top surface of the substrate 200. In this embodiment, the isolation material layer also covers the surface of the protective layer 202. In other embodiments, the isolation material layer completely fills the word line trench 210 and covers the surface of the protective layer 202.

[0040] The isolation material layer is patterned, retaining the isolation material layer located on the sidewall of the second region 210B of the word line trench 210 as the isolation layer 230. In this step, photolithography and etching processes are used to remove the isolation material layer on the surface of the protective layer 202, the sidewall of the first region 210A of the word line trench 210, and the bottom surface of the word line trench 210, retaining the isolation material layer located on the sidewall of the second region 210B of the word line trench 210 as the isolation layer 230. It is understood that in some embodiments, due to semiconductor process limitations, the isolation material layer on the sidewall of the second region 210B of the word line trench 210 is also thinned when the isolation material layer is removed.

[0041] Please see Figure 5 The substrate 200 is oxidized or an oxide layer is deposited to form the gate insulating layer 220. Specifically, the gate insulating layer 220 is formed on the surface of the substrate 200 exposed in the first region 210A.

[0042] For example, in this embodiment, the substrate 200 exposed in the first region 210A is oxidized to form the gate insulating layer 220. The oxidation process includes thermal oxidation, where an oxidizing agent such as oxygen or water vapor reacts with the exposed substrate 200 at a high temperature to generate silicon dioxide, forming an oxide layer that serves as the gate insulating layer 220. The gate insulating layer 220 formed by thermal oxidation exhibits high repeatability and stability, which is beneficial for improving the reliability of semiconductor devices. In this step, since the gate insulating layer 220 is formed using a thermal oxidation method and grows towards the interior of the substrate 200, the surface of the gate insulating layer 220 is positioned at the same location as the surface of the substrate 200. However, the isolation layer 230 is formed on the surface of the substrate 200 and does not grow towards the interior. Therefore, in a direction parallel to the top surface of the substrate 200 (as shown by direction X in the figure), the surface of the isolation layer 230 protrudes beyond the surface of the gate insulating layer 220. The interface between the isolation layer 230 and the substrate 200 is flush with the surface of the gate insulating layer 220. Thus, the thickness of the subsequently formed titanium nitride barrier layer 241 can be limited by the thickness of the isolation layer 230. Furthermore, since the gate insulating layer 220 grows towards the interior of the silicon substrate 200 and does not occupy the width of the word line trench 210, a wider molybdenum gate 242 can be formed with the same width of the word line trench 210.

[0043] In other embodiments, an oxide layer may be deposited on the surface of the substrate 200 exposed in the first region 210A to form the gate insulating layer 220. The deposition process includes, but is not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof. In these embodiments, since the gate insulating layer 220 is deposited on the surface of the substrate 200 using a deposition process, i.e., covering the surface of the substrate 200 rather than growing into the interior of the substrate 200, the surface of the gate insulating layer 220 protrudes from the surface of the substrate 200. In some embodiments, in a direction parallel to the top surface of the substrate 200 (as shown by the X direction in the figure), the surface of the gate insulating layer 220 is flush with the surface of the isolation layer 230; while in other embodiments, the surface of the isolation layer 230 protrudes from the surface of the gate insulating layer 220.

[0044] Please see Figure 1 and Figure 6 In step S12, a titanium nitride barrier layer 241 is formed, which covers the surface of the gate insulating layer 220. In this step, the titanium nitride barrier layer 241 is formed only on the surface of the gate insulating layer 220 and does not cover the surface of the isolation layer 230. The titanium nitride barrier layer 241 is used to prevent the subsequently formed molybdenum gate 242 from diffusing into the substrate 200.

[0045] In this embodiment, the surface of the isolation layer 230 is flush with the surface of the titanium nitride barrier layer 241 in a direction parallel to the top surface of the substrate 200 (as shown by the X direction in the figure). In other embodiments, the surface of the isolation layer 230 protrudes from the surface of the titanium nitride barrier layer 241 in a direction parallel to the top surface of the substrate 200 (as shown by the X direction in the figure).

[0046] As an example, this disclosure provides a method for forming the titanium nitride barrier layer 241. The method includes the following steps:

[0047] A titanium nitride barrier layer 241 is deposited, which covers the surface of the isolation layer 230, the surface of the gate insulating layer 220, and the bottom surface of the word line trench 210. In this step, the deposition process includes, but is not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof. In this step, the titanium nitride barrier layer 241 is also deposited on the surface of the protective layer 202.

[0048] The titanium nitride barrier layer 241 material on the surface of the isolation layer 230 and the bottom surface of the word line trench 210 is removed, and the remaining titanium nitride barrier layer 241 material on the surface of the gate insulating layer 220 serves as the titanium nitride barrier layer 241. Specifically, in this step, the titanium nitride barrier layer 241 material is etched back to remove the titanium nitride barrier layer 241 material covering the surface of the isolation layer 230, the bottom surface of the word line trench 210, and the surface of the protective layer 202, and the remaining titanium nitride barrier layer 241 material on the surface of the gate insulating layer 220 serves as the titanium nitride barrier layer 241. It is understood that, due to limitations in semiconductor processes, the titanium nitride barrier layer 241 material on the surface of the gate insulating layer 220 may also be thinned in this step.

[0049] In this step, a dry etching process can be used to etch back the titanium nitride barrier layer 241 material. The dry etching process is anisotropic etching, and the lateral etching rate is much smaller than the longitudinal etching rate. This causes the titanium nitride barrier layer 241 material located below the isolation layer 230 in the direction perpendicular to the top surface of the semiconductor (as shown in the Y direction in the figure) to be blocked by the isolation layer 230 and retained, thus forming the titanium nitride barrier layer 241. Therefore, in some embodiments, the thickness of the titanium nitride barrier layer 241 can be limited by the thickness of the isolation layer 230, thereby achieving controllability of the thickness of the titanium nitride barrier layer 241.

[0050] Please see Figure 1 and Figure 7 In step S13, a molybdenum metal gate 242 is deposited, which is selectively deposited on the titanium nitride barrier layer 241.

[0051] The selective deposition of the molybdenum gate 242 on the titanium nitride barrier layer 241 means that the molybdenum gate 242 material is deposited only on the titanium nitride barrier layer 241, and not on the substrate 200, the isolation layer 230, and the protective layer 202. In this step, the molybdenum gate 242 exhibits high selectivity for different materials during deposition, depositing only on the titanium nitride barrier layer 241. This avoids the need for a subsequent etching process after forming the gate material layer, saving process steps, reducing semiconductor manufacturing complexity, and improving the reliability of the semiconductor device. Simultaneously, the resistivity of the molybdenum gate 242 is lower than that of the TIN / W film, which helps reduce gate resistance and improve the performance of the semiconductor device.

[0052] As an example, this disclosure provides a method for depositing a molybdenum metal gate 242, the method comprising: selectively depositing a molybdenum metal layer on the surface of a titanium nitride barrier layer 241 using molybdenum pentachloride (MoCl5) and hydrogen (H2) as precursors via atomic layer deposition. Molybdenum pentachloride (MoCl5) and hydrogen (H2) as precursors can only deposit a molybdenum film on the titanium nitride barrier layer 241, and cannot grow on the substrate 200, the isolation layer 230, and the protective layer 202. This ensures that after this step, the molybdenum metal gate 242 is formed only on the titanium nitride barrier layer 241, eliminating the need for additional etch-back steps.

[0053] The titanium nitride barrier layer 241 and the molybdenum gate 242 constitute the gate structure 240 of the transistor.

[0054] After depositing the molybdenum metal gate 242, the following steps are also included: Please refer to Figure 8 A fill layer 250 is formed, which at least fills the first region 210A of the word line trench 210. In this step, the fill layer 250 fills the region of the word line trench 210 that is not filled by the molybdenum gate 242, the titanium nitride barrier layer 241, and the isolation layer 230. In this embodiment, the fill layer 250 also covers the surface of the protective layer 202 to protect the molybdenum gate 242 and the substrate 200 in subsequent semiconductor processes. The method also includes a step of planarizing the fill layer 250 to obtain a flat surface of the fill layer 250, thereby providing a good substrate plane for subsequent semiconductor processes and reducing the difficulty of semiconductor process fabrication.

[0055] The filling layer 250 and the isolation layer 230 are made of the same material, for example, both are silicon nitride layers, in order to further improve the bonding between the filling layer 250 and the isolation layer 230 and enhance their protective effect on the semiconductor device.

[0056] The semiconductor device fabrication method provided in this disclosure utilizes the selective deposition property of the molybdenum gate 242, so that the molybdenum gate 242 is deposited only on the titanium nitride barrier layer 241 and not on other structures, such as the substrate 200, the isolation layer 230, or the protective layer 202. This eliminates the need for additional etch-back steps, simplifies the fabrication process, reduces the process difficulty, and the resistivity of the molybdenum gate 242 is lower than that of the TIN / W film, which helps to reduce the gate resistance and improve the performance of the semiconductor device.

[0057] This disclosure also provides a semiconductor device. Please refer to [link to relevant documentation]. Figure 8The semiconductor device includes a substrate 200, a gate structure 240, and a gate insulating layer 220. The substrate 200 has a shallow trench isolation structure 201 and a word line trench 210 (see [link to documentation]). Figure 5 The gate structure 240 is disposed within the shallow trench isolation structure 201. The gate structure 240 includes a titanium nitride barrier layer 241 and a molybdenum gate 242 sequentially disposed therefrom. In a direction perpendicular to the top surface of the substrate 200, the top surface of the molybdenum gate 242 is flush with the top surface of the titanium nitride barrier layer 241. A gate insulating layer 220 is disposed between the substrate 200 and the gate structure 240. The gate insulating layer 220 serves as an insulating layer between the gate structure 240 and the substrate 200, and the titanium nitride barrier layer 241 covers the gate insulating layer 220.

[0058] The shallow trench isolation structure 201 is formed within the substrate 200, and includes, but is not limited to, an oxide filling layer 250 or a composite filling layer 250 of oxide and nitride. In this embodiment, the surface of the substrate 200 has a protective layer 202, which may be an oxide, such as silicon dioxide, for protecting the substrate 200. The shallow trench isolation structure 201 penetrates the protective layer 202.

[0059] The word line trench 210 extends a predetermined distance into the shallow trench isolation structure 201, and the bottom surface of the word line trench 210 is the surface of the shallow trench isolation structure 201. The predetermined distance can be set according to semiconductor process requirements and specifications. In this embodiment, the word line trench 210 includes a first region 210A and a second region 210B. The first region 210A and the second region 210B are arranged along a direction perpendicular to the top surface of the substrate 200 (as shown in the Y direction), and the second region 210B is adjacent to the top surface of the substrate 200. The gate structure 240 is disposed in the first region 210A of the word line trench 210, and the isolation layer 230 is disposed in the second region 210B of the word line trench 210.

[0060] The isolation layer 230 covers the inner wall of the second region 210B of the word line trench 210. The isolation layer 230 may be a silicon nitride layer, which can be used to limit the height of the gate structure 240 from the top surface of the substrate 200, thereby achieving controllability of the position of the gate structure 240. In this embodiment, in a direction parallel to the top surface of the substrate 200 (as shown by the X direction in the figure), the surface of the isolation layer 230 protrudes from the surface of the gate insulating layer 220, the interface between the isolation layer 230 and the substrate 200 is flush with the surface of the gate insulating layer 220, and the surface of the isolation layer 230 is flush with the surface of the titanium nitride barrier layer 241, that is, the thickness of the isolation layer 230 is the same as the thickness of the titanium nitride barrier layer 241. Therefore, the thickness of the subsequently formed titanium nitride barrier layer 241 can be limited by the thickness of the isolation layer 230.

[0061] In other embodiments, the thickness of the isolation layer 230 is not limited to being the same as the thickness of the titanium nitride barrier layer 241. Specifically, in a direction parallel to the top surface of the substrate 200, the surface of the isolation layer 230 protrudes beyond the surface of the titanium nitride barrier layer 241, meaning the thickness of the isolation layer 230 is greater than the thickness of the titanium nitride barrier layer 241, allowing for the formation of a wider molybdenum gate 242 with the same width of the word line trench 210.

[0062] The titanium nitride barrier layer 241 is disposed on the gate insulating layer 220, that is, the titanium nitride barrier layer 241 covers the gate insulating layer 220, and the titanium nitride barrier layer 241 is used to prevent the subsequently formed metal molybdenum gate 242 from diffusing into the substrate 200.

[0063] The metal film gate covers the titanium nitride barrier layer 241. Since the molybdenum metal gate 242 is selectively deposited on the titanium nitride barrier layer 241 and not on the substrate 200, the isolation layer 230, and the protective layer 202, the molybdenum metal gate 242 only covers the titanium nitride barrier layer 241. The resistivity of the molybdenum metal gate 242 is lower than that of the TIN / W film, which is beneficial for reducing gate resistance and improving the performance of the semiconductor device.

[0064] In this embodiment, the semiconductor device further includes a filler layer 250, which at least fills the first region 210A of the word line trench 210. Specifically, the filler layer 250 covers the top surface of the gate structure 240 and the surface of the isolation layer 230, and fills the gaps in the first word line trench 210, thereby protecting the semiconductor device.

[0065] The filler layer 250 also covers the top surface of the substrate 200. In this embodiment, due to the presence of the protective layer 202, the filler layer 250 covers the surface of the protective layer 202 on the top surface of the substrate 200 to further provide protection. The filler layer 250 and the isolation layer 230 are made of the same material, for example, both are silicon nitride layers, to further improve the bonding between the filler layer 250 and the isolation layer 230, and enhance their protective effect on the semiconductor device.

[0066] The semiconductor device provided in this embodiment utilizes molybdenum metal as a gate. The resistivity of the molybdenum metal gate 242 is lower than that of the TIN / W film, which helps to reduce the gate resistance and improve the reliability of the semiconductor device.

[0067] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, wherein the substrate has a shallow trench isolation structure; A word line trench is formed in the shallow trench isolation structure, and a gate insulating layer is provided on the sidewall of the word line trench. A titanium nitride barrier layer is formed, which covers the surface of the gate insulating layer; A molybdenum metal gate is deposited, which is selectively deposited on the titanium nitride barrier layer; The step of forming word line grooves in the shallow trench isolation structure includes: The shallow trench isolation structure is etched to form the word line trench, and the sidewalls of the word line trench expose the substrate; The substrate is oxidized or an oxide layer is deposited to form the gate insulating layer; the word line trench includes a first region and a second region, the first region and the second region are arranged in a direction perpendicular to the top surface of the substrate, and the second region is adjacent to the top surface of the substrate. The step of forming the word line trench further includes: forming an isolation layer on the sidewall of the second region of the word line trench, and exposing the substrate on the sidewall of the first region of the word line trench. The gate insulating layer is formed on the substrate surface exposed in the first region.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming the gate insulating layer on the substrate surface exposed in the first region includes: oxidizing the substrate surface exposed in the first region to form the gate insulating layer, wherein the surface of the insulating layer protrudes from the surface of the gate insulating layer in a direction parallel to the top surface of the substrate.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming the gate insulating layer on the substrate surface exposed in the first region includes: depositing an oxide layer on the substrate surface exposed in the first region to form the gate insulating layer.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming an isolation layer on the sidewall of the second region of the letter groove includes: A layer of insulating material is filled into the groove of the letter line. The isolation material layer is patterned, and the isolation material layer located on the sidewall of the second region of the letter groove is retained as the isolation layer.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The steps for forming the titanium nitride barrier layer include: A titanium nitride barrier layer material is deposited, the titanium nitride barrier layer material covering the surface of the isolation layer, the surface of the gate insulating layer, and the bottom surface of the word line trench; Remove the titanium nitride barrier layer material from the surface of the isolation layer and the bottom of the word line trench, and use the remaining titanium nitride barrier layer material on the surface of the gate insulating layer as the titanium nitride barrier layer.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, Following the step of depositing the molybdenum metal gate, the following steps are also included: A fill layer is formed, which at least fills the first region of the word line groove.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, Methods for depositing molybdenum metal gates include: Using molybdenum pentachloride and hydrogen as precursors, a molybdenum metal gate is selectively deposited on the surface of the titanium nitride barrier layer using an atomic layer deposition process.

8. A semiconductor device, characterized in that, include: A substrate having a shallow trench isolation structure therein, with word line trenches disposed within the shallow trench isolation structure; A gate structure is disposed in the word line trench. The gate structure includes a titanium nitride barrier layer and a metal molybdenum gate disposed sequentially. In the direction perpendicular to the top surface of the substrate, the top surface of the metal molybdenum gate is flush with the top surface of the titanium nitride barrier layer. A gate insulating layer is disposed between the substrate and the gate structure; the word line trench includes a first region and a second region, the first region and the second region are arranged in a direction perpendicular to the top surface of the substrate, and the second region is adjacent to the top surface of the substrate; the gate structure is disposed in the first region of the word line trench, and the isolation layer is disposed in the second region of the word line trench.

9. The semiconductor device according to claim 8, characterized in that, In a direction parallel to the top surface of the substrate, the surface of the isolation layer protrudes beyond the surface of the gate insulating layer.

10. The semiconductor device according to claim 8, characterized in that, In a direction parallel to the top surface of the substrate, the surface of the isolation layer is flush with or protrudes from the surface of the titanium nitride barrier layer.

11. The semiconductor device according to claim 8, characterized in that, It also includes a filler layer that at least fills the first region of the word line groove.

12. The semiconductor device according to claim 11, characterized in that, The filler layer also covers the top surface of the substrate.

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