Method for preparing semiconductor structure and semiconductor structure

Abstract

The present application relates to a method for manufacturing a semiconductor structure and a semiconductor structure, including: providing a substrate; forming a first metal structure and a first interlayer dielectric layer on the substrate; wherein, the first metal structure includes a first electrode plate, a first lead-out wire, and a second lead-out wire, and the first electrode plate, the first lead-out wire, and the second lead-out wire form a first groove; the first interlayer dielectric layer fills the first groove; removing a part of the first interlayer dielectric layer to expose the sidewalls of the first lead-out wire and the second lead-out wire; forming a second interlayer dielectric layer on the exposed sidewalls of the first lead-out wire and the second lead-out wire and on the side of the first interlayer dielectric layer away from the first electrode plate; forming a second metal structure and a third interlayer dielectric layer on the side of the second interlayer dielectric layer away from the first groove; wherein, the second metal structure includes a second electrode plate, a third lead-out wire, and a fourth lead-out wire. Using the manufacturing method of the present application can reduce the manufacturing difficulty of the MIM capacitor.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and particularly to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] A Metal-Insulator-Metal (MIM) capacitor consists of two electrodes and an insulating layer between the electrodes, and has advantages such as high small loss, high withstand voltage, and low equivalent series resistance.

[0003] Generally, multiple photomasks can be used to respectively define the positions of the lower electrode, the upper electrode, the metal connection line, and the connection via, and then etching and deposition are performed to finally form the required MIM capacitor connection structure. However, as the device size shrinks, it is difficult to manufacture small-sized and high-quality MIM capacitors with the existing manufacturing processes. Summary of the Invention

[0004] Based on this, it is necessary to provide a method for manufacturing a semiconductor structure and a semiconductor structure that can manufacture small-sized and high-quality MIM capacitors.

[0005] To achieve the above object, on the one hand, the present application provides a method for manufacturing a semiconductor structure, including:

[0006] Providing a substrate;

[0007] Forming a first metal structure and a first interlayer dielectric layer on the substrate; wherein, the first metal structure includes a first electrode plate, a first lead-out wire, and a second lead-out wire, a first end of the first electrode plate is in contact with the first lead-out wire, and a second end of the first electrode plate is in contact with the second lead-out wire to form a first groove; the first interlayer dielectric layer fills the first groove;

[0008] Removing a part of the first interlayer dielectric layer to expose the side walls of the first lead-out wire and the second lead-out wire;

[0009] Forming a second interlayer dielectric layer on the exposed side walls of the first lead-out wire, the second lead-out wire, and on a side of the first interlayer dielectric layer away from the first electrode plate;

[0010] Forming a second metal structure and a third interlayer dielectric layer on a side of the second interlayer dielectric layer away from the first groove; wherein, the second metal structure includes a second electrode plate, a third lead-out wire, and a fourth lead-out wire, a first end of the second electrode plate is in contact with the third lead-out wire, and a second end of the second electrode plate is in contact with the fourth lead-out wire to form a second groove, and the third interlayer dielectric layer fills the second groove.

[0011] In one embodiment, forming a second interlayer dielectric layer on the sidewalls of the exposed first lead-out line, the sidewalls of the second lead-out line, and the side of the first interlayer dielectric layer away from the first electrode plate includes:

[0012] Forming a first dielectric material layer on the first metal structure and the first interlayer dielectric layer;

[0013] At least removing the first dielectric material layer on the top surfaces of the first lead-out line and the second lead-out line to form the second interlayer dielectric layer, which is flush with the first lead-out line and the second lead-out line.

[0014] In one embodiment, forming a first metal structure and a first interlayer dielectric layer on the substrate includes:

[0015] Forming the first electrode plate and the first interlayer dielectric layer on the substrate;

[0016] Forming a first metal material layer on the surface of the substrate and the first interlayer dielectric layer;

[0017] Removing the first metal material layer on the top surface of the first interlayer dielectric layer and part of the first metal material layer on the substrate to form the first lead-out line and the second lead-out line respectively located at both ends of the first electrode plate.

[0018] In one embodiment, forming a first metal structure and a first interlayer dielectric layer on the substrate includes:

[0019] Forming a fourth interlayer dielectric layer with a third groove on the substrate; the third groove exposes the substrate;

[0020] Sequentially forming a first metal material layer and a second dielectric material layer on the surface of the third groove and the fourth interlayer dielectric layer;

[0021] Performing a grinding process on the first metal material layer and the second dielectric material layer to expose the fourth interlayer dielectric layer; the remaining first metal material layer constitutes the first metal structure, and the remaining second dielectric material layer constitutes the first interlayer dielectric layer.

[0022] In one embodiment, the method further includes:

[0023] The thickness of the second interlayer dielectric layer in the direction perpendicular to the top surface of the substrate is greater than or equal to 500 angstroms.

[0024] In one embodiment, forming a second metal structure and a third interlayer dielectric layer on the side of the second interlayer dielectric layer away from the first groove includes:

[0025] At least on the exposed surface of the second interlayer dielectric layer, a second metal material layer and a third dielectric material layer are sequentially formed;

[0026] The second metal material layer and the third dielectric material layer are subjected to a grinding process to expose the second interlayer dielectric layer; the remaining second metal material layer constitutes the second metal structure, and the remaining third dielectric material layer constitutes the third interlayer dielectric layer.

[0027] In one embodiment, after forming the second metal structure and the third interlayer dielectric layer in the first groove, it further includes:

[0028] A first connecting member is formed on the exposed surface of the first lead-out wire or the second lead-out wire;

[0029] A second connecting member is formed on the exposed surface of the third lead-out wire or the fourth lead-out wire.

[0030] In one embodiment, the thickness of the first electrode plate in the direction perpendicular to the top surface of the substrate ranges from 700 angstroms to 1500 angstroms.

[0031] In one embodiment, the method further includes at least one of the following features:

[0032] The thickness of the first lead-out wire and the second lead-out wire in the direction of the interval arrangement of the first lead-out wire and the second lead-out wire ranges from 40 nanometers to 80 nanometers;

[0033] The height of the first lead-out wire and the second lead-out wire in the direction perpendicular to the top surface of the substrate ranges from 2000 angstroms to 3000 angstroms;

[0034] The thickness of the third lead-out wire and the fourth lead-out wire in the direction of the interval arrangement of the first lead-out wire and the second lead-out wire ranges from 40 nanometers to 80 nanometers.

[0035] In a second aspect, the present application further provides a semiconductor structure, which is prepared by using the preparation method of the semiconductor structure described in any one of the embodiments of the present application.

[0036] In the above semiconductor structure and its manufacturing method, by providing a substrate, a first metal structure and a first interlayer dielectric layer are formed on the substrate. Among them, the first metal structure includes a first electrode plate, a first lead-out wire and a second lead-out wire. The first electrode plate can serve as the lower electrode plate of the finally formed MIM capacitor, and the first lead-out wire and the second lead-out wire can be used to lead out the first electrode plate. Further, a part of the first interlayer dielectric layer is removed to expose the side walls of the first lead-out wire and the second lead-out wire, and a second interlayer dielectric layer is formed on the exposed side walls of the first lead-out wire, the second lead-out wire, and the side of the first interlayer dielectric layer away from the first electrode plate. The remaining first interlayer dielectric layer and the second interlayer dielectric layer can serve as the capacitor dielectric layer of the finally formed MIM capacitor. The capacitance value of the MIM capacitor can be adjusted by controlling the thickness of the remaining first interlayer dielectric layer and the thickness of the formed second interlayer dielectric layer. Additionally, by controlling the thickness of the second interlayer dielectric layer, electrical crosstalk caused by the too-close distance between adjacent lead-out wires can be avoided. Moreover, the second interlayer dielectric layer inherits the cross-sectional shape of the first metal structure. The second electrode plate, the third lead-out wire, the fourth lead-out wire, and the third interlayer dielectric layer can be formed by a deposition process using the shape of the second interlayer dielectric layer, without the need for photolithography to form connection vias, which not only reduces the process difficulty but also saves photomasks and reduces the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0038] Figure 1 It is a schematic flowchart of the manufacturing method of the MIM capacitor provided in an embodiment;

[0039] Figure 2a It is a schematic cross-sectional structure diagram of the structure obtained in step S104 in the manufacturing method of the MIM capacitor provided in an embodiment;

[0040] Figure 2b It is a schematic cross-sectional structure diagram of the structure obtained in step S106 in the manufacturing method of the MIM capacitor provided in an embodiment;

[0041] Figure 2c It is a schematic cross-sectional structure diagram of the structure obtained in step S108 in the manufacturing method of the MIM capacitor provided in an embodiment;

[0042] Figure 2d It is a schematic cross-sectional structure diagram of the structure obtained in step S110 in the manufacturing method of the MIM capacitor provided in an embodiment;

[0043] Figure 2e Schematic cross-sectional structure diagram of the structure obtained in step S112 of the method for preparing a MIM capacitor provided in an embodiment;

[0044] Figure 2f Schematic cross-sectional structure diagram of the structure obtained in step S114 of the method for preparing a MIM capacitor provided in an embodiment;

[0045] Figure 2g Schematic cross-sectional structure diagram of the structure obtained in step S116 of the method for preparing a MIM capacitor provided in an embodiment;

[0046] Figure 3 Flow chart of the method for preparing a semiconductor structure provided in an embodiment;

[0047] Figure 4a Schematic cross-sectional structure diagram of the structure obtained in step S702 of the method for preparing a semiconductor structure provided in an embodiment;

[0048] Figure 4b Schematic cross-sectional structure diagram of the structure obtained in step S704 of the method for preparing a semiconductor structure provided in an embodiment;

[0049] Figure 4c Schematic cross-sectional structure diagram of the structure obtained in step S304 of the method for preparing a semiconductor structure provided in an embodiment;

[0050] Figure 4d Schematic cross-sectional structure diagram of the structure obtained in step S306 of the method for preparing a semiconductor structure provided in an embodiment;

[0051] Figure 4e Schematic cross-sectional structure diagram of the structure obtained in step S602 of the method for preparing a semiconductor structure provided in an embodiment;

[0052] Figure 4f Schematic cross-sectional structure diagram of the structure obtained in step S308 of the method for preparing a semiconductor structure provided in an embodiment;

[0053] Figure 4g Schematic cross-sectional structure diagram of the structure obtained in step S504 of the method for preparing a semiconductor structure provided in an embodiment;

[0054] Figure 4h Schematic cross-sectional structure diagram of the structure obtained in step S902 of the method for preparing a semiconductor structure provided in an embodiment;

[0055] Figure 4i Schematic cross-sectional structure diagram of the structure obtained in step S310 of the method for preparing a semiconductor structure provided in an embodiment;

[0056] Figure 4j Schematic cross-sectional structure of the structure obtained by the steps in the method for preparing a semiconductor structure provided in an embodiment: forming a first connecting member on the exposed surface of the second lead-out wire and forming a second connecting member on the exposed surface of the third lead-out wire;

[0057] Figure 5a Schematic cross-sectional structure of the structure obtained by step S802 in the method for preparing a semiconductor structure provided in an embodiment;

[0058] Figure 5b Schematic cross-sectional structure of the structure obtained by step S804 in the method for preparing a semiconductor structure provided in an embodiment;

[0059] Figure 5c Schematic cross-sectional structure of the structure obtained by step S304 in the method for preparing a semiconductor structure provided in another embodiment;

[0060] Figure 5d Schematic cross-sectional structure of the structure obtained by step S306 in the method for preparing a semiconductor structure provided in another embodiment;

[0061] Figure 5e Schematic cross-sectional structure of the structure obtained by step S602 in the method for preparing a semiconductor structure provided in another embodiment;

[0062] Figure 5f Schematic cross-sectional structure of the structure obtained by step S308 in the method for preparing a semiconductor structure provided in another embodiment;

[0063] Figure 5g Schematic cross-sectional structure of the structure obtained by step S504 in the method for preparing a semiconductor structure provided in another embodiment;

[0064] Figure 5h Schematic cross-sectional structure of the structure obtained by step S902 in the method for preparing a semiconductor structure provided in another embodiment;

[0065] Figure 5i Schematic cross-sectional structure of the structure obtained by step S310 in the method for preparing a semiconductor structure provided in another embodiment;

[0066] Figure 5j Schematic cross-sectional structure of the structure obtained by the steps in the method for preparing a semiconductor structure provided in another embodiment: forming a first connecting member on the exposed surface of the second lead-out wire and forming a second connecting member on the exposed surface of the third lead-out wire;

[0067] Figure 6 Flow chart of step S308 in the method for preparing a semiconductor structure provided in an embodiment;

[0068] Figure 7 It is a flowchart of step S304 in the manufacturing method of the semiconductor structure provided in an embodiment.

[0069] Figure 8 It is a flowchart of step S304 in the manufacturing method of the semiconductor structure provided in another embodiment.

[0070] Figure 9 It is a flowchart of step S310 in the manufacturing method of the semiconductor structure provided in an embodiment.

[0071] Explanation of reference numerals:

[0072] 101 - Substrate, 102 - First dielectric layer, 103 - Lower electrode plate, 104 - First patterned photoresist layer, 105 - Second dielectric layer, 106 - Upper electrode plate, 107 - Second patterned photoresist layer, 108 - Third dielectric layer, 109 - Third patterned photoresist layer, 110 - Metal connection groove, 111 - Connection via, 112 - Metal material, 410 - First metal structure, 412 - First electrode plate, 414 - First lead wire, 416 - Second lead wire, 420 - First interlayer dielectric layer, 422 - Second dielectric material layer, 430 - First metal material layer, 440 - First dielectric material layer, 442 - Second interlayer dielectric layer, 450 - Second metal material layer, 460 - Third dielectric material layer, 462 - Third interlayer dielectric layer, 470 - Second metal structure, 472 - Second electrode plate, 474 - Third lead wire, 476 - Fourth lead wire, 482 - First connector, 484 - Second connector, 490 - Fourth interlayer dielectric layer, 492 - Third groove. Detailed implementation manners

[0073] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0075] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various layers, these layers should not be limited by these terms. These terms are only used to distinguish one layer from another. Thus, without departing from the teachings of the present application, the first layer discussed below may be referred to as the second layer or a portion thereof.

[0076] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0077] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / include" or "has" etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0078] In an embodiment of the present application, the substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side. In an embodiment of the present application, the side of the first metal structure in contact with the substrate is taken as the top surface of the substrate, and the side opposite to the top surface is taken as the bottom surface of the substrate.

[0079] Please refer to Figure 1 、 Figures 2a - 2g , in some general techniques, forming a MIM capacitor connection structure may include: step S102 - step S116.

[0080] Step S102: Provide a substrate; the substrate includes a substrate 101 and a first dielectric layer 102 located on the top surface of the substrate 101;

[0081] Step S104: Based on the first patterned photoresist layer 104, form a lower electrode plate 103 on the first dielectric layer 102 by using a photolithography process;

[0082] Step S106: Remove the first patterned photoresist layer 104, and form a second dielectric layer 105 on the first dielectric layer 102 by using a chemical vapor deposition process. The top surface of the second dielectric layer 105 is higher than the top surface of the lower electrode plate 103;

[0083] Step S108: Based on the second patterned photoresist layer 107, form an upper electrode plate 106 on the second dielectric layer 105 by using a photolithography process;

[0084] Step S110: Remove the second patterned photoresist layer 107, and form a third dielectric layer 108 on the second dielectric layer 105 by using a chemical vapor deposition process. The top surface of the third dielectric layer 108 is higher than the top surface of the upper electrode plate 106;

[0085] Step S112: Based on the third patterned photoresist layer 109, form two spaced metal connection grooves 110 in the third dielectric layer 108 by using a photolithography process;

[0086] Step S114: Based on a fourth patterned photoresist layer (not shown), form connection vias 111 in the third dielectric layer 108 at the bottom of the two metal connection grooves 110 by using a photolithography process; the connection vias 111 expose the lower electrode plate 103 and the upper electrode plate 106;

[0087] Step S116: Form a metal material 112 in the metal connection grooves 110 and the connection vias 111 by using a Physical Vapor Deposition (PVD) process, and planarize the metal material 112 by using a Chemical-Mechanical Polishing (CMP) process.

[0088] As described in the background art, as the size of the MIM capacitor device shrinks, the sizes of the metal connection grooves 110 and the connection vias 111 also become smaller and smaller, increasing the difficulty of the lithography process. At the same time, during the filling process of the metal connection grooves 110 and the connection vias 111 with a high aspect ratio, it is easy to form air gaps in the metal connection grooves 110 and the connection vias 111 due to the premature sealing of the metal material 112, resulting in low performance of the MIM capacitor. In addition, in order to ensure the density of the metal material 112 in the metal connection grooves 110 and the connection vias 111, usually 2 to 3 times the volume of the metal connection grooves 110 and the connection vias 111 of the metal material 112 is required, resulting in serious material waste and high mask costs for multiple lithography processes.

[0089] Based on the above problems, please refer to Figure 3 , this application provides a method for manufacturing a semiconductor structure, including step S302 - step S310.

[0090] Step S302, provide a substrate.

[0091] Among them, the substrate 101 can be composed of semiconductor materials, insulating materials, conductor materials, or any combination thereof. The substrate 101 can be a single-layer structure or a multi-layer structure. For example, the substrate 101 can be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate 101 can be a layered substrate 101 including, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator. Therefore, the type of the substrate 101 should not limit the protection scope of the present disclosure.

[0092] A shallow trench isolation structure (Shallow Trench Isolation, abbreviated as STI) can be formed in the substrate 101, and the shallow trench isolation structure can isolate several spaced-apart active areas (Active Area, abbreviated as AA) in the substrate 101. The active area can include multiple doped areas for forming devices such as transistors. Therefore, the structure in the substrate 101 in this application is not specifically limited.

[0093] Step S304, form a first metal structure and a first interlayer dielectric layer on the substrate.

[0094] As Figure 4c or Figure 5cAs shown, the first metal structure 410 includes a first electrode plate 412, a first lead 414, and a second lead 416. The first end of the first electrode plate 412 is in contact with the first lead 414, and the second end of the first electrode plate 412 is in contact with the second lead 416 to form a first groove. The extending direction of the first electrode plate 412 is parallel to the extending direction of the substrate 101. The first electrode plate 412 can be used as the lower electrode plate of the finally formed MIM capacitor. The extending directions of the first lead 414 and the second lead 416 are perpendicular to the extending direction of the first electrode plate 412 respectively. The first lead 414 and the second lead 416 can be used to lead out the first electrode plate 412 and connect it to a metal layer or other external circuits.

[0095] The material of the first electrode plate 412 includes but is not limited to one or more of cobalt (Co), nickel (Ni), titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al). A deposition process such as Physical Vapor Deposition (PVD), magnetron sputtering process, or evaporation process can be used to form the first electrode plate 412 on the substrate 101.

[0096] The materials of the first lead 414 and the second lead 416 can be the same as or different from that of the first electrode plate 412. Exemplarily, the materials of the first lead 414 and the second lead 416 include but are not limited to one or more of cobalt (Co), nickel (Ni), titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al).

[0097] The first interlayer dielectric layer 420 fills the first groove. The material of the first interlayer dielectric layer 420 includes but is not limited to nitrides, for example, it can be silicon oxynitride, silicon nitride, or a composition thereof. A deposition process such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP) process, or Plasma-Enhanced Chemical Vapor Deposition (PECVD) process can be used to form the first interlayer dielectric layer 420.

[0098] Step S306: Remove a part of the first interlayer dielectric layer to expose the sidewalls of the first lead and the second lead.

[0099] As Figure 4d OrFigure 5d As shown, a wet etching process can be used to remove a part of the first interlayer dielectric layer to expose the sidewalls of the first lead 414 and the sidewalls of the second lead 416.

[0100] Step S308: Form a second interlayer dielectric layer on the sidewalls of the exposed first lead, the sidewalls of the second lead, and the side of the first interlayer dielectric layer away from the first electrode plate.

[0101] As Figure 4f or Figure 5f shown, deposition processes such as CVD, ALD, HDP, or PECVD can be used to form a second interlayer dielectric layer 442 on the sidewalls of the exposed first lead 414, the sidewalls of the second lead 416, and the side of the first interlayer dielectric layer 420 away from the first electrode plate 412. The material of the second interlayer dielectric layer 442 includes but is not limited to nitrides, for example, it can be silicon oxynitride, silicon nitride, or a combination thereof.

[0102] Step S310: Form a second metal structure 470 and a third interlayer dielectric layer on the side of the second interlayer dielectric layer away from the first groove.

[0103] As Figure 4i or Figure 5i shown, the second metal structure 470 includes a second electrode plate 472, a third lead 474, and a fourth lead 476. The first end of the second electrode plate 472 is in contact with the third lead 474, and the second end of the second electrode plate 472 is in contact with the fourth lead 476 to form a second groove. The extending direction of the second electrode plate 472 is parallel to the extending direction of the substrate 101, and the second electrode plate 472 can be used as the upper electrode plate of the MIM capacitor. The extending directions of the third lead 474 and the fourth lead 476 are perpendicular to the extending direction of the substrate 101 respectively, and the third lead 474 and the fourth lead 476 are used to lead out the second electrode plate 472 to be connected to other metal layers or an external circuit. In addition, the first interlayer dielectric layer 420 and the second interlayer dielectric layer 442 between the second electrode plate 472 and the first electrode plate 412 can be used as the capacitor dielectric layer of the finally formed MIM capacitor, wherein the thickness of the partial capacitor dielectric layer perpendicular to the substrate 101 is different from the thickness of the partial capacitor dielectric layer parallel to the substrate 101.

[0104] The second electrode plate 472, the third lead 474, and the fourth lead 476 are made of the same material, including but not limited to one or more of cobalt (Co), nickel (Ni), titanium (Ti), titanium nitride (TiN), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al).

[0105] The third interlayer dielectric layer 462 fills the second groove. The material of the third interlayer dielectric layer 462 includes but is not limited to nitrides, such as silicon oxynitride, silicon nitride, or their combinations.

[0106] In the embodiment of the present application, by providing a substrate 101, a first metal structure 410 and a first interlayer dielectric layer 420 are formed on the substrate 101. Among them, the first metal structure 410 includes a first electrode plate 412, a first lead wire 414, and a second lead wire 416. The first electrode plate 412 can be used as the lower electrode plate of the finally formed MIM capacitor, and the first lead wire 414 and the second lead wire 416 can be used to lead out the first electrode plate 412; further, a part of the first interlayer dielectric layer is removed to expose the side walls of the first lead wire 414 and the second lead wire 416, and a second interlayer dielectric layer 442 is formed on the exposed side walls of the first lead wire 414, the second lead wire 416, and the side of the first interlayer dielectric layer 420 away from the first electrode plate 412. Among them, the remaining first interlayer dielectric layer 420 and the second interlayer dielectric layer 442 can be used as the capacitive dielectric layer of the finally formed MIM capacitor. The capacitance value of the MIM capacitor can be adjusted by controlling the thickness of the remaining first interlayer dielectric layer 420 and the thickness of the formed second interlayer dielectric layer 442. The thickness of the second interlayer dielectric layer 442 can also be controlled to avoid electrical crosstalk caused by the too-close distance between adjacent lead wires; in addition, the second interlayer dielectric layer 442 inherits the cross-sectional shape of the first metal structure 410. The second electrode plate 472, the third lead wire 474, the fourth lead wire 476, and the third interlayer dielectric layer 462 can be formed by using the shape of the second interlayer dielectric layer 442 through a deposition process, without the operation of lithographically forming connection through holes, which not only reduces the process difficulty but also saves photomasks and reduces the preparation cost.

[0107] In one embodiment, as Figure 6 shown, a second interlayer dielectric layer is formed on the exposed side walls of the first lead wire, the second lead wire, and the side of the first interlayer dielectric layer away from the first electrode plate, including step 602 - step 604.

[0108] Step 602, a first dielectric material layer is formed on the first metal structure and the first interlayer dielectric layer.

[0109] As Figure 4e or Figure 5e shown, a first dielectric material layer 440 can be formed on the first metal structure 410 and the first interlayer dielectric layer 420 by using a deposition process such as CVD, ALD, HDP, or PECVD.

[0110] Step 604, at least the first dielectric material layer on the top surfaces of the first lead wire and the second lead wire is removed to form the second interlayer dielectric layer.

[0111] As Figure 4f or Figure 5f shown, a dry etching process can be used to remove at least the first dielectric material layer on the top surfaces of the first lead 414 and the second lead 416. The first dielectric material layer remaining on the sidewalls of the first lead 414, the sidewalls of the second lead 416, and the surface of the first interlayer dielectric layer 420 constitutes the second interlayer dielectric layer 442. The second interlayer dielectric layer is flush with the first lead 414 and the second lead 416.

[0112] In Figure 4e the structure shown, the first dielectric material layer 440 also covers the surface of the substrate 101. When using a dry etching process to remove part of the first dielectric material layer 440, the first dielectric material layer 440 on the surface of the substrate 101 will also be removed.

[0113] In Figure 5e the structure shown, the first dielectric material layer 440 also covers the surfaces of other film layers except the first metal structure 410 and the first interlayer dielectric layer 420. When using a dry etching process to remove part of the first dielectric material layer 440, the first dielectric material layer 440 on the surfaces of other film layers will also be removed, and only the first dielectric material layer 440 on the sidewalls of the first lead 414, the sidewalls of the second lead 416, and the surface of the first interlayer dielectric layer 420 is retained.

[0114] In one embodiment, as Figure 7 shown, forming a first metal structure and a first interlayer dielectric layer on a substrate includes steps S702 - S706.

[0115] Step S702, forming a first electrode plate on the substrate and a first interlayer dielectric layer on the first electrode plate.

[0116] As Figure 4a shown, a first electrode plate 412 can be formed on the substrate 101 by using a deposition process such as CVD, ALD, HDP, or PECVD first, and then a first interlayer dielectric layer 420 is formed on the side of the first electrode plate 412 away from the substrate 101.

[0117] The thickness range of the first electrode plate 412 in the direction perpendicular to the top surface of the substrate 101 includes 700 Å - 1500 Å. The thickness of the first electrode plate 412 is associated with the resistance value of the first electrode plate 412 and will affect the resistance - capacitance delay (RC Delay) ability of the MIM capacitor. The thickness of the first electrode plate 412 in the direction perpendicular to the top surface of the substrate 101 can be 700 Å, 800 Å, 900 Å, 1000 Å, 1100 Å, 1200 Å, 1300 Å, 1400 Å, or 1500 Å, etc.

[0118] Step S704: Form a first metal material layer on the surface of the substrate and the first interlayer dielectric layer.

[0119] As Figure 4b shown, a first metal material layer 430 can be formed on the surface of the substrate 101 and the first interlayer dielectric layer 420 by using deposition processes such as CVD, ALD, HDP, or PECVD.

[0120] Step S706: Remove the first metal material layer on the top surface of the first interlayer dielectric layer and the part of the first metal material layer on the substrate to form a first lead-out wire and a second lead-out wire located at both ends of the first electrode plate respectively.

[0121] As Figure 4c shown, a self-alignment process can be used to remove the first metal material layer on the top surface of the first interlayer dielectric layer 420 and the part of the first metal material layer on the substrate 101 to form a first lead-out wire 414 and a second lead-out wire 416 located at both ends of the first electrode plate 412 respectively.

[0122] In this embodiment, by forming a first electrode plate 412 on the substrate 101 and a first interlayer dielectric layer 420 on the first electrode plate 412, forming a first metal material layer 430 on the surface of the substrate 101 and the first interlayer dielectric layer 420, and further removing the first metal material layer 430 on the top surface of the first interlayer dielectric layer 420 and the part of the first metal material layer 430 on the substrate 101 to form a first lead-out wire 414 and a second lead-out wire 416 located at both ends of the first electrode plate 412 respectively, since the width of the removed first metal material layer in the direction parallel to the substrate 101 is much larger than the widths of the first lead-out wire 414 and the second lead-out wire 416, the etching window is increased and the etching difficulty is reduced.

[0123] In one embodiment, as Figure 8 shown, forming a first metal structure and a first interlayer dielectric layer on the substrate 101 includes steps S802 - S806.

[0124] Step S802: Form a fourth interlayer dielectric layer with a third groove on the substrate; the third groove exposes the substrate.

[0125] As Figure 5a shown, a fourth interlayer dielectric layer 490 can be first formed on the substrate 101 by using a deposition process, and then a third groove 492 can be formed in the fourth interlayer dielectric layer 490 by using photolithography and etching processes. The material of the fourth interlayer dielectric layer 490 can include but is not limited to oxides, nitrides, carbon oxides, etc.

[0126] Step S804: Sequentially form a first metal material layer and a second dielectric material layer on the surface of the third groove and the fourth interlayer dielectric layer.

[0127] As shown Figure 5b in FIG., a first metal material layer 430 and a second dielectric material layer 422 may be sequentially formed on the surfaces of the third groove 492 and the fourth interlayer dielectric layer 490 through a deposition process such as CVD, ALD, HDP, or PECVD.

[0128] Step S806: Grind the first metal material layer and the second dielectric material layer to expose the fourth interlayer dielectric layer.

[0129] As shown Figure 5c in FIG., the first metal material layer 430 and the second dielectric material layer 422 are ground to expose the fourth interlayer dielectric layer 490. The remaining first metal material layer forms the first metal structure 410, and the remaining second dielectric material layer forms the first interlayer dielectric layer 420. Optionally, after forming the first metal structure 410, the fourth interlayer dielectric layer 490 may also be removed to form the structure shown Figure 4c in FIG.

[0130] Compared with the conventional method of forming connection vias by etching the dielectric layer, in this embodiment, since the width of the third groove 492 in the direction parallel to the substrate 101 is much larger than the widths of the first lead 414 and the second lead 416, by etching to form the third groove 492 and forming the first electrode plate 412, the first lead 414, and the second lead 416 in the third groove 492 through a deposition process and a grinding process, the etching window can be increased and the etching difficulty can be reduced.

[0131] In one embodiment, the thickness of the second interlayer dielectric layer 442 in the direction perpendicular to the top surface of the substrate 101 is greater than or equal to 500 angstroms.

[0132] The thickness of the second interlayer dielectric layer 442 in the direction perpendicular to the top surface of the substrate 101 is associated with the distance between the first lead 414 and the second lead 416. The thickness of the second interlayer dielectric layer 442 in the direction perpendicular to the top surface of the substrate 101 may be 500 angstroms, 600 angstroms, 700 angstroms, 800 angstroms, 900 angstroms, or 1000 angstroms, etc.

[0133] In one embodiment, as shown Figure 9 in FIG., on the side of the second interlayer dielectric layer away from the first groove, a second metal structure and a third interlayer dielectric layer are formed, including steps S902 - S904.

[0134] Step S902: At least on the exposed surface of the second interlayer dielectric layer, a second metal material layer and a third dielectric material layer are sequentially formed.

[0135] As shown Figures 4g - 4h or Figures 5g - 5hAs shown, a second metal material layer 450 and a third dielectric material layer 460 can be sequentially formed on the exposed surface of the second interlayer dielectric layer 442 through a deposition process such as CVD, ALD, HDP, or PECVD.

[0136] In Figure 4g the structure shown, the second metal material layer also covers a partial surface of the substrate 101. In Figure 5g the structure shown, the second metal material layer also covers the surface of the fourth interlayer dielectric layer 490.

[0137] Step S904: Perform a planarization process on the second metal material layer and the third dielectric material layer to expose the second interlayer dielectric layer.

[0138] As Figure 4i or Figure 5i shown, the second metal material layer 450 and the third dielectric material layer 460 can be planarized to expose the second interlayer dielectric layer 442. The remaining second metal material layer forms the second metal structure 470, and the remaining third dielectric material layer forms the third interlayer dielectric layer 462.

[0139] In this embodiment, by utilizing the topography of the second interlayer dielectric layer 442, the second electrode plate 472, the third lead 474, and the fourth lead 476 are formed, eliminating the steps of lithography and etching to form the connection vias for the third lead 474 and the fourth lead 476, reducing the process difficulty and saving photomasks. In addition, during the planarization process of the second metal material layer 450 and the third dielectric material layer 460, very little of the second metal material layer and the third dielectric material layer are removed, having little impact on the extension lengths of structures such as the second interlayer dielectric layer 442, the first lead 414, and the second lead 416 in the direction perpendicular to the substrate 101, that is, having little impact on the capacitance value of the formed MIM capacitor.

[0140] In one embodiment, after forming the second metal structure and the third interlayer dielectric layer in the first groove, the method for manufacturing the semiconductor structure further includes steps of forming a first connector on the exposed surface of the second lead and forming a second connector on the exposed surface of the third lead.

[0141] As Figure 4j or Figure 5jAs shown, the first connecting member 482 can be formed on the exposed surface of the second lead-out line 416, and the second connecting member 484 can be formed on the exposed surface of the third lead-out line 474 through deposition, photolithography, and etching processes. Specifically, a third metal material layer can be first deposited on the exposed surfaces of the first metal structure, the second interlayer dielectric layer, the second metal structure, and the third interlayer dielectric layer. Then, a part of the third metal material layer is removed, and only the third metal material layer located on the surfaces of the second lead-out line 416 and the third lead-out line 474 is retained to form the first connecting member 482 and the second connecting member 484. Since the width of the removed third metal material layer in the direction parallel to the substrate is much larger than the widths of the first connecting member 482 and the second connecting member 484, compared with the method of forming metal connection grooves in the dielectric layer through photolithography, the etching window can be increased, and the etching difficulty can be reduced.

[0142] Optionally, in one embodiment, the first connecting member 482 can also be formed on the exposed surface of the first lead-out line 414, and the second connecting member 484 can be formed on the exposed surface of the fourth lead-out line 476.

[0143] Optionally, in one embodiment, the first connecting member 482 can also be formed on the exposed surface of the first lead-out line 414, and the second connecting member 484 can be formed on the exposed surface of the third lead-out line 474.

[0144] Optionally, in one embodiment, the first connecting member 482 can also be formed on the exposed surface of the second lead-out line 416, and the second connecting member 484 can be formed on the exposed surface of the fourth lead-out line 476.

[0145] In one embodiment, the thickness range of the first lead-out line 414 and the second lead-out line 416 in the direction of the interval arrangement of the first lead-out line 414 and the second lead-out line 416 is 40 nanometers - 80 nanometers, for example, it can be 40 nanometers, 45 nanometers, 50 nanometers, 55 nanometers, 60 nanometers, 65 nanometers, 70 nanometers, 75 nanometers, or 80 nanometers, etc.

[0146] In one embodiment, the thickness range of the third lead-out line 474 and the fourth lead-out line 476 in the direction of the interval arrangement of the first lead-out line 414 and the second lead-out line 416 is 40 nanometers - 80 nanometers, for example, it can be 40 nanometers, 45 nanometers, 50 nanometers, 55 nanometers, 60 nanometers, 65 nanometers, 70 nanometers, 75 nanometers, or 80 nanometers, etc.

[0147] In one embodiment, the height range of the first lead-out line 414 and the second lead-out line 416 in a direction perpendicular to the top surface of the substrate 101 is 2000 Å - 3000 Å. For example, it can be 2000 Å, 2100 Å, 2200 Å, 2300 Å, 2400 Å, 2500 Å, 2600 Å, 2700 Å, 2800 Å, 2900 Å, or 3000 Å, etc.

[0148] It should be understood that although the steps in the above flowcharts are sequentially shown in the illustrated order, these steps are not necessarily executed in this order. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in each flowchart may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0149] In one embodiment, the present application further provides a semiconductor structure, which can be prepared by the preparation method of the semiconductor structure provided in any of the above embodiments.

[0150] As an example, please refer to Figure 4i or Figure 5i , the semiconductor structure includes a substrate 101, a first metal structure 410, a first interlayer dielectric layer 420, a second interlayer dielectric layer 442, a second metal structure 470, and a third interlayer dielectric layer 462. Among them, the first metal structure 410 includes a first electrode plate 412, a first lead-out line 414, and a second lead-out line 416. The first end of the first electrode plate 412 is in contact with the first lead-out line 414, and the second end of the first electrode plate 412 is in contact with the second lead-out line 416 to form a first groove. The first interlayer dielectric layer 420 is located on the side of the first electrode plate 412 away from the substrate 101, and the second interlayer dielectric layer 442 is located on the side of the first dielectric layer 420 away from the first electrode plate 412, as well as on the sidewalls of the first lead-out line 414 and the second lead-out line 416. The second metal structure 470 includes a second electrode plate 472, a third lead-out line 474, and a fourth lead-out line 476. The first end of the second electrode plate 472 is in contact with the third lead-out line 474, and the second end of the second electrode plate 472 is in contact with the fourth lead-out line 476 to form a second groove. The third interlayer dielectric layer 462 fills the second groove.

[0151] Among them, the first electrode plate 412, the first interlayer dielectric layer 420, the second interlayer dielectric layer 442, and the second electrode plate 472 form a MIM capacitor. The first lead 414 and the second lead 416 can be used to lead out the first electrode plate 412 for connection with other structures, and the third lead 474 and the fourth lead 476 can be used to lead out the second electrode plate 472 for connection with other structures.

[0152] For the specific limitations of each film layer in this semiconductor structure, reference can be made to the description of the preparation method of the semiconductor structure in the foregoing text, which will not be elaborated here.

[0153] The preparation method of the semiconductor structure and the semiconductor structure of this application have the following unexpected beneficial effects:

[0154] First, in the process of forming the first metal structure 410, the positions of the first lead 414 and the second lead 416 are defined by removing the film layer whose width in the direction parallel to the substrate is much larger than the widths of the first lead 414 and the second lead 416. Compared with the traditional method of forming connection through holes by lithography of the dielectric layer, the etching window is increased and the etching difficulty is reduced.

[0155] Second, the first interlayer dielectric layer 420 and the second interlayer dielectric layer 442 serve as the capacitance dielectric layers of the finally formed MIM capacitor. The capacitance value of the MIM capacitor can be adjusted by controlling the thickness of the reserved first interlayer dielectric layer 420 and the thickness of the formed second interlayer dielectric layer 442, realizing the controllability of the capacitance value of the MIM capacitor. Also, by controlling the thickness of the second interlayer dielectric layer 442, the electrical crosstalk caused by the too-close distance between adjacent leads can be avoided.

[0156] Third, in the process of forming the second metal structure 470, since the second interlayer dielectric layer 442 inherits the cross-sectional shape of the first metal structure 410 and presents a "concave" shape, the second electrode plate 472, the third lead 474, the fourth lead 476, and the third interlayer dielectric layer 462 can be formed by a deposition process using the shape of the second interlayer dielectric layer 442, without the operation of lithography to form connection through holes. This not only reduces the process difficulty but also saves the photomask and reduces the preparation cost.

[0157] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0158] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0159] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; A first metal structure and a first interlayer dielectric layer are formed on the substrate; wherein the first metal structure includes a first electrode plate, a first lead wire and a second lead wire, a first end of the first electrode plate contacts the first lead wire, and a second end of the first electrode plate contacts the second lead wire to form a first groove; and the first interlayer dielectric layer fills the first groove; Removing a portion of the first interlayer dielectric layer to expose the sidewalls of the first lead wire and the sidewalls of the second lead wire; A second interlayer dielectric layer is formed on the exposed sidewalls of the first lead wire, the sidewalls of the second lead wire, and the side of the first interlayer dielectric layer away from the first electrode plate; in the direction from the substrate to the second interlayer dielectric layer, the second interlayer dielectric layer located on the sidewalls of the first lead wire and the second interlayer dielectric layer located on the sidewalls of the second lead wire are flush with the first lead wire, and the top surface height of the second interlayer dielectric layer located on the surface of the first interlayer dielectric layer is lower than the top surface height of the first lead wire; A second metal structure and a third interlayer dielectric layer are formed on a side of the second interlayer dielectric layer away from the first groove; wherein the second metal structure includes a second electrode plate, a third lead wire, and a fourth lead wire, the first end of the second electrode plate contacts the third lead wire, and the second end of the second electrode plate contacts the fourth lead wire to form a second groove, and the third interlayer dielectric layer fills the second groove.

2. The method according to claim 1, characterized in that The second interlayer dielectric layer is formed on the exposed sidewall of the first lead wire, the sidewall of the second lead wire, and the side of the first interlayer dielectric layer away from the first electrode plate, including: forming a first dielectric material layer on the first metal structure and the first interlayer dielectric layer; At least the first dielectric material layer on the top surface of the first lead and the second lead is removed to form the second interlayer dielectric layer, wherein the second interlayer dielectric layer located on the side wall of the first lead and the second interlayer dielectric layer on the side wall of the second lead are flush with the first lead and the second lead, and the top surface height of the second interlayer dielectric layer located on the surface of the first interlayer dielectric layer is lower than the top surface height of the first lead.

3. The method according to claim 1, characterized in that The step of forming a first metal structure and a first interlayer dielectric layer on the substrate comprises: forming the first electrode plate and a first interlayer dielectric layer located on the first electrode plate on the substrate; forming a first metal material layer on the surface of the substrate and the first interlayer dielectric layer; The first metal material layer located on the top surface of the first interlayer dielectric layer and a portion of the first metal material layer located on the substrate are removed to form the first lead wire and the second lead wire respectively located at two ends of the first electrode plate.

4. The method according to claim 1, characterized in that: The step of forming a first metal structure and a first interlayer dielectric layer on the substrate comprises: forming a fourth interlayer dielectric layer having a third groove on the substrate; the third groove exposes the substrate; forming a first metal material layer and a second dielectric material layer in sequence on the surfaces of the third groove and the fourth interlayer dielectric layer; The first metal material layer and the second dielectric material layer are subjected to grinding treatment to expose the fourth interlayer dielectric layer; the remaining first metal material layer constitutes the first metal structure, and the remaining second dielectric material layer constitutes the first interlayer dielectric layer.

5. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: The thickness of the second interlayer dielectric layer along a direction perpendicular to the top surface of the substrate is greater than or equal to 500 angstroms.

6. The method according to claim 1, characterized in that A second metal structure and a third interlayer dielectric layer are formed on a side of the second interlayer dielectric layer away from the first groove, including: forming a second metal material layer and a third dielectric material layer in sequence at least on the exposed surface of the second interlayer dielectric layer; The second metal material layer and the third dielectric material layer are subjected to grinding treatment to expose the second interlayer dielectric layer; the remaining second metal material layer constitutes the second metal structure, and the remaining third dielectric material layer constitutes the third interlayer dielectric layer.

7. The method according to claim 1, characterized in that After forming a second metal structure and a third interlayer dielectric layer in the first groove, the method further includes: forming a first connecting member on an exposed surface of the first lead wire or the second lead wire; A second connection member is formed on an exposed surface of the third lead wire or the fourth lead wire.

8. The method according to claim 1, characterized in that The thickness of the first electrode plate along a direction perpendicular to the top surface of the substrate ranges from 700 angstroms to 1500 angstroms.

9. The method according to claim 1, characterized in that: The method further comprises at least one of the following features: The thickness of the first lead wire and the second lead wire along the direction in which the first lead wire and the second lead wire are arranged spaced apart is in the range of 40 nanometers to 80 nanometers; The height of the first lead wire and the second lead wire in a direction perpendicular to the top surface of the substrate ranges from 2000 angstroms to 3000 angstroms; The thickness of the third lead wire and the fourth lead wire along the direction in which the first lead wire and the second lead wire are arranged at intervals ranges from 40 nanometers to 80 nanometers.

10. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 1 to 9.

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