Techniques for operating switched mode power supply

Abstract

Techniques and apparatus for transitioning between various operating modes of a switched mode power supply (SMPS) in a wireless local area network (WLAN) device powered by a button cell in an effort to maintain performance and functionality of the WLAN device and efficiency of the SMPS. One example apparatus is an integrated circuit (IC) for power management. The IC generally includes a first port for coupling to a battery and a first terminal of a capacitive element; a second port for coupling to a second terminal of the capacitive element; an SMPS, the SMPS having an input coupled to the first port; and a switch coupled between the second port and a reference potential node of the IC.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 18 / 446,332 filed on August 8, 2023, which claims priority to U.S. Provisional Patent Application No. 63 / 491,680 filed on March 22, 2023 and U.S. Provisional Patent Application No. 63 / 370,878 filed on August 9, 2022, all of which are hereby incorporated by reference in their entirety. Technical Field

[0003] Certain aspects of the present disclosure relate generally to electronic circuits, and more particularly to switch-mode power supplies. Background Art

[0004] A voltage regulator provides a constant direct current (DC) output voltage regardless of changes in load current or input voltage. Voltage regulators can be classified as linear regulators or switching regulators. Although linear regulators are small and compact, many applications can benefit from the improved efficiency of switching regulators. For example, linear regulators can be implemented by low dropout (LDO) regulators. Switching regulators can be implemented by switch mode power supplies (SMPS) such as buck converters, boost converters, buck-boost converters, or charge pumps.

[0005] For example, a buck converter is a type of SMPS that typically includes: (1) a high-side switch coupled between a relatively high voltage rail and a switch node, (2) a low-side switch coupled between the switch node and a relatively low voltage rail, (3) and an inductor coupled between the switch node and a load (e.g., represented by a shunt capacitor element). The high-side switch and the low-side switch may be implemented using transistors, but the low-side switch may alternatively be implemented using a diode.

[0006] A power management unit (PMU) is used to manage the power requirements of a host system and may include and / or control one or more voltage regulators (e.g., LDOs and / or SMPSs). A PMU may be used in battery-powered devices such as mobile phones, tablets, laptops, wearable devices, etc. to control the flow and direction of power in the device. The PMU may perform various functions for the device, such as DC to DC conversion (e.g., using a voltage regulator as described above), battery charging, power source selection, voltage scaling, power sequencing, etc. Summary of the invention

[0007] The systems, methods, and devices of the present disclosure each have several aspects, no single one of which is solely responsible for its desirable characteristics. Without limiting the scope of the present disclosure as expressed in the appended claims, some features will now be briefly discussed. After considering this discussion, and particularly after reading the section entitled "Detailed Description of the Invention," one will understand how the features of the present disclosure provide the advantages described herein.

[0008] Certain aspects of the present disclosure are generally directed to a wireless local area network (WLAN) device that includes a switch mode power supply and a coin cell battery coupled to the switch mode power supply and configured to supply power to the switch mode power supply.

[0009] Certain aspects of the present disclosure generally relate to techniques for rapidly transitioning between various operating modes of a switch-mode power supply in a WLAN device powered by a coin cell battery in an effort to maintain performance, functionality, and efficiency.

[0010] Certain aspects of the present disclosure provide an integrated circuit (IC) for power management. The IC generally includes: a first port for coupling to a battery and a first terminal of a capacitive element; a second port for coupling to a second terminal of the capacitive element; a switch mode power supply (SMPS) having an input coupled to the first port; and a switch coupled between the second port and a reference potential node of the IC.

[0011] Certain aspects of the present disclosure provide a WLAN device including an IC as described herein. The WLAN device also includes: a battery having a first terminal coupled to the first port and having a second terminal coupled to a reference potential node of the IC; and a capacitive element coupled between the first port and the second port of the IC.

[0012] Certain aspects of the present disclosure provide a circuit for controlling an output stage of an SMPS. The circuit generally includes: a comparator having a first input coupled to a reference voltage node and having a second input coupled to an output of the SMPS; and a logic component having an input coupled to the output of the comparator and having an output coupled to a control input of the SMPS, wherein the logic component is configured to generate a first pulse to temporarily enable the output stage of the SMPS based on a regulated voltage at the second input of the comparator being lower than a reference voltage at the first input of the comparator, the first pulse being further generated based on a clock signal.

[0013] Certain aspects of the present disclosure provide a method for controlling an output stage of an SMPS. The method generally includes: comparing a reference voltage with a regulated voltage at an output of the SMPS via a comparator; and generating a first pulse to temporarily enable the output stage of the SMPS based on the regulated voltage being lower than the reference voltage via a logic component coupled to the output of the comparator, the first pulse being further generated based on a clock signal.

[0014] To achieve the aforementioned and related purposes, one or more aspects include the features fully described below and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail certain exemplary features of the one or more aspects. However, these features indicate only some of the various ways in which the principles of the various aspects can be employed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more specific description briefly summarized above can be obtained by reference to various aspects, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only certain typical aspects of the present disclosure and are therefore not to be considered as limiting the scope thereof, as the specification may admit to other equally effective aspects.

[0016] Figure 1 is a block diagram of an example device including a battery coupled to a power management unit (PMU) in accordance with certain aspects of the present disclosure.

[0017] Figure 2 is a block diagram of an example PMU powered by a coin cell battery in accordance with certain aspects of the present disclosure.

[0018] Figure 3 An example switched mode power supply (SMPS) according to certain aspects of the present disclosure is illustrated.

[0019] Figure 4 is a timing diagram illustrating an inductor current of an SMPS according to certain aspects of the present disclosure.

[0020] Figure 5 is a block diagram of example components of an ultra low power mode (ULPM) in a SMPS according to certain aspects of the present disclosure.

[0021] Figure 6 is a timing diagram illustrating signals of a ULPM controller according to certain aspects of the present disclosure.

[0022] Figure 7 is a timing diagram illustrating an inductor current of an SMPS in response to an activation pulse according to certain aspects of the present disclosure.

[0023] Figure 8is a flow chart illustrating example operations for controlling an output stage of a SMPS according to certain aspects of the present disclosure.

[0024] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0025] Certain aspects of the present disclosure relate to devices and techniques for operating a switched mode power supply (SMPS). In some implementations, the SMPS may be powered by a button cell, which may have a high impedance. In some aspects, when the SMPS consumes a small amount of power from the button cell (e.g., in a receive mode), power from the battery may be stored in a capacitive element. When the SMPS later consumes more power from the button cell (e.g., in a transmit mode), power for the SMPS may be provided from both the button cell and the capacitive element. Thus, the total current consumed by the transmit mode is obtained from the battery during a longer time window, thereby reducing the impact of the high impedance associated with the button cell on the operation of the SMPS.

[0026] Some aspects of the present disclosure relate to a controller configured to operate an SMPS in a low power mode. For example, in the low power mode, the controller may compare the output voltage (Vout) of the SMPS with a reference voltage (Vref), and based thereon, generate a pulse (also referred to herein as a "one shot pulse" or "activation pulse") that temporarily enables the output stage of the SMPS. In some cases, the controller may monitor the duration of a tri-state phase of the SMPS. The tri-state phase duration may indicate a load current of the SMPS. Based on the tri-state phase duration falling below a threshold (e.g., indicating an increased load current), the controller may increase the duration of the activation pulse for temporarily enabling the SMPS, thereby increasing the inductor current to supply the increased load.

[0027] The various aspects of the present disclosure are described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms, and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. Instead, these aspects are provided so that the present disclosure will be thorough and complete, and the protection scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings of this article, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the disclosure disclosed herein, whether it is implemented independently or in combination with any other aspect of the present disclosure. For example, any number of aspects set forth herein can be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such a device or method that is practiced using other structures, functionality, or structure and functionality in addition to or different from the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein can be embodied by one or more elements of the present invention.

[0028] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0029] As used herein, the term "connected with" in various tenses of the verb "connect" may mean that element A is directly connected to element B or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the context of electronic components, the term "connected with" may also be used herein to mean that wires, traces, or other conductive materials are used to electrically connect element A and element B (and any components electrically connected therebetween).

[0030] Example Device

[0031] It should be understood that various aspects of the present disclosure can be used for various applications. Although the present disclosure is not limited to this aspect, the circuits disclosed herein can be used in any of a variety of suitable devices, such as power supplies, battery charging circuits or power management circuits for communication systems, video codecs, audio equipment (such as music players and microphones), televisions, camera equipment, and / or test equipment (such as oscilloscopes). By way of example only, communication systems intended to be included within the scope of the present disclosure include cellular radiotelephone communication systems, satellite communication systems, two-way radio communication systems, one-way pagers, two-way pagers, personal communication systems (PCS), personal digital assistants (PDAs), Internet of Things (IoT) devices, etc.

[0032] Figure 1An example device 100 is illustrated in which aspects of the present disclosure may be implemented. Device 100 may be a battery-driven device such as a cellular phone, a PDA, a handheld device, a wireless device, a laptop, a tablet computer, a smart phone, a wearable device, an augmented reality device, or the like.

[0033] The device 100 may include a processor 104 that controls the operation of the device 100. The processor 104 may also be referred to as a central processing unit (CPU). A memory 106, which may include both read-only memory (ROM) and random access memory (RAM), provides instructions and data to the processor 104. A portion of the memory 106 may also include non-volatile random access memory (NVRAM). The processor 104 typically performs logical and arithmetic operations based on program instructions stored in the memory 106.

[0034] In some aspects, the device 100 may also include a housing 108, which may include a transmitter 110 and a receiver 112 to allow data to be sent and received between the device 100 and a remote location. For some aspects, the transmitter 110 and the receiver 112 may be combined into a transceiver 114. One or more antennas 116 may be attached to or otherwise mechanically coupled to the housing 108 and electrically coupled to the transceiver 114. The device 100 may also include (not shown) multiple transmitters, multiple receivers, and / or multiple transceivers.

[0035] The device 100 may also include a signal detector 118, which may be used to detect and quantify the signal level received by the transceiver 114. The signal detector 118 may detect signal parameters such as total energy, energy per subcarrier per symbol, and power spectral density and other signal parameters. The device 100 may also include a digital signal processor (DSP) 120 for processing signals.

[0036] Device 100 may also include a battery 122 for powering various components of device 100. For certain aspects, battery 122 may be a coin cell battery, such as a CR2032 battery, which is a circular lithium battery and is capable of delivering 220 milliamp hours (mAh).

[0037] The device 100 may also include a power management unit (PMU) 123 for managing power from the battery to various components of the device 100. At least a portion of the PMU 123 may be implemented in one or more power management integrated circuits (power management ICs or PMICs). The PMU 123 may perform various functions for the device 100, such as DC to DC conversion, battery charging, power source selection, voltage scaling, power sequencing, etc. For example, the PMU 123 may include a battery charging circuit (e.g., a master-slave battery charging circuit) for charging the battery 122. The PMU 123 may include one or more power supply circuits, which may include at least one low dropout (LDO) voltage regulator 124 and / or at least one switch mode power supply (SMPS) 125. The switch mode power supply may be implemented by any of a variety of suitable switch mode power supply circuit topologies, such as a buck converter, a boost converter, a buck-boost converter, or a charge pump. In some aspects, the SMPS may operate in a low power mode, as described in more detail herein.

[0038] The various components of the device 100 may be coupled together via a bus system 126, which may include a power bus, a control signal bus, and / or a status signal bus in addition to a data bus. Additionally or alternatively, various combinations of components of the device 100 may be coupled together via one or more other suitable technologies.

[0039] Example Switch Mode Power Supply (SMPS)

[0040] Micropower Wi-Fi technology (e.g., under the IEEE 802.11 family of standards, such as IEEE 802.11n) enables Wi-Fi devices to operate on coin-cell batteries (e.g., CR2032 batteries) and achieve usable battery life. For certain aspects, such micropower Wi-Fi technology can be used for extended personal area network (XPAN) applications.

[0041] Figure 22 is a block diagram of an example power management unit (PMU) 200 powered by a coin cell battery 202 according to certain aspects of the present disclosure. PMU 200 may include at least one switch mode power supply (SMPS). For example, PMU 200 may include two switch mode power supplies, as shown, labeled "SMPS1" and "SMPS2". The SMPS may generate a regulated voltage (Vreg, also referred to herein as an output voltage (Vout)) based on power from the coin cell battery 202. PMU 200 may also include a normally-on low dropout regulator 204 (labeled "AON LDO"), an oscillator low dropout regulator 206 (labeled "OSC LDO"), and an oscillator 208 (labeled "OSC"). As shown, using switch 210, AON LDO 204 may be operated based on the voltage at the terminals of the coin cell battery 202 or the regulated voltage generated by SMPS1. Normally-on low dropout regulator 204 may generate regulated voltages for normally-on domains and some memory structures of a system on chip (SOC). The oscillator 208 may be used as a sleep mode clock source, powered by a regulated voltage generated by the oscillator low dropout regulator 206 .

[0042] In the case of micro-power Wi-Fi, a wireless local area network (WLAN) integrated circuit (IC) may be powered by a single coin cell battery. In this case, a switching regulator (e.g., inside PMU 200) may provide programmable regulated voltages for analog portions (e.g., radio frequency (RF) transmitters and / or receivers) and digital portions (e.g., system on chip (SOC)) that are part of the WLAN IC. For example, SMPS1 and SMPS2 may be used as regulators for a radio frequency (RF) front end (RFFE) circuit and a system on chip (SOC), respectively. The switching regulators (e.g., SMPS1 and SMPS2) may be specified to operate over a wide input voltage variation range associated with a large source impedance of a coin cell battery (e.g., a 3.3V coin cell battery that varies between 3.6V and 1.8V). The switching regulators may be specified to maintain high efficiency over a wide load current range (e.g., as large as 100mA to 200mA when transmitting, and as small as 1μA to 2μA in deep sleep mode). Furthermore, the switching regulator may be specified to reconfigure the operating mode quickly enough to seamlessly maintain RF performance and SOC functionality and improve efficiency.

[0043] To meet these design specifications, according to certain aspects of the present disclosure, the SMPS can be designed to operate according to a pulse width modulation (PWM) mode, a pulse frequency modulation (PFM) mode, and an ultra low power mode (ULPM). The operating modes can share the same output stage of the SMPS (e.g., a p-type metal oxide semiconductor (PMOS) and / or n-type metal oxide semiconductor (NMOS) power field effect transistor (FET) of a buck converter) in a time-sharing manner.

[0044] When the WLAN IC switches from the receiver mode to the transmitter mode with the large output power (Pout) from the power amplifier (PA) in the transmit chain, the SMPS can be reconfigured from the PFM mode to the PWM mode. To achieve this, the foot switch 212 (labeled as "S1") can be coupled between the battery capacitor element 214 (labeled as "C1") and the reference potential node (e.g., electrical ground). In some aspects, the switch 212 can be implemented as an NMOS transistor. In the receiver mode, the switch 212 can be closed to slowly charge the capacitor element 214 with power from the button battery 202. During the transmitter mode, the current consumed by the PMU 200 for operating the PA to amplify the signal for transmission can be provided from the battery 202 and the battery capacitor element 214. The total current consumed by the transmit mode is obtained from the battery 202 during a longer time window, thereby reducing the supply voltage drop caused by the battery source impedance. When entering the sleep mode, the foot switch 212 can be disconnected to avoid (or at least reduce) the leakage current associated with the capacitor element 214.

[0045] In some aspects, PMU 200 (e.g., a PMU integrated circuit (IC)) may include port 240 for coupling to battery 202 and a first terminal of capacitive element 214. PMU 200 may also include port 250 for coupling to a second terminal of capacitive element 214. SMPS 1 may have an input coupled to port 240. Switch 212 may be coupled between port 250 and a reference potential node of PMU 200.

[0046] Figure 3 An example SMPS 300 according to certain aspects of the present disclosure is illustrated. As shown, the SMPS 300 may include an output stage having a high-side switch 302 (e.g., a PMOS FET) and a low-side switch 304 (e.g., an NMOS FET). During the charging phase, the high-side switch 302 may be closed, thereby coupling the inductive element between the voltage rail (Vdd) and an output node 308 providing an output voltage Vout. During the charging phase, current is provided from the voltage rail to the inductive element 306, thereby increasing the inductive current. During the discharge phase, the switch 302 may be opened, and the switch 304 may be closed, thereby coupling the inductive element 306 between a reference potential node (e.g., electrical ground) and the output node 308, thereby reducing the inductive current. In some cases, after the charging phase and the discharge phase, the output stage may enter a tri-state phase, during which both switches 302 and 304 are disconnected, as described in more detail herein.

[0047] Capacitive element 310 may be coupled between output node 308 and a reference potential node. The output voltage Vout may be provided to an input of an error amplifier 312 (labeled "EA"). Another input of the error amplifier 312 may receive a reference voltage (Vref). During PWM mode, the error amplifier 312 may be enabled and compare Vout with Vref to generate an error voltage provided to a controller 318. Based on the error voltage, the controller 318 generates a switching signal (e.g., a PWM signal) to control switches 302, 304 and regulate Vout.

[0048] During PFM mode, the error amplifier may be disabled. During PFM mode, the comparator 322 may be enabled. The comparator 322 may receive and compare Vout with Vref to generate a comparison signal, based on which the controller 318 may control the switches 302, 304 via the PFM signal to regulate Vout. The comparator 322 consumes less power than the error amplifier 312, reducing the power consumption of the PMU during PFM mode compared to PWM mode.

[0049] In some aspects of the present disclosure, a controller for an SMPS may receive a transmit enable signal from a physical (PHY) layer before actual transmission (e.g., a few μs before), thereby allowing the SMPS to begin reconfiguring from a PFM mode to a PWM mode. In the PFM mode, a low power clamp circuit 320 may be enabled. The clamp circuit 320 may be coupled to the output of the error amplifier 312. A capacitive element 314 (e.g., a compensation capacitor) may be coupled between the output of the error amplifier 312 and a reference potential node. For the PWM mode to start, the voltage at the output of the error amplifier 312 may have to reach a voltage threshold (e.g., 1 volt) after being enabled, which may result in a delay in starting the PWM mode and signal transmission. In some aspects of the present disclosure, the clamp circuit 320 may charge (e.g., pre-charge) the capacitive element 314 during the PFM mode before switching to the PWM mode in response to receiving a transmit enable signal from the PHY layer. Therefore, once the PWM mode starts, the voltage at the output of the error amplifier 312 may already be at the voltage threshold for starting the PWM mode of operation. Thus, the idle time in the SMPS associated with transitioning from PFM mode to PWM mode may be reduced, allowing the PA to start up faster for signaling.

[0050] Figure 44 is a timing diagram 400 illustrating an inductor current (e.g., a current across the inductor element 306) of an SMPS according to certain aspects of the present disclosure. As shown, during a high-side (HS) phase (e.g., when the HS switch 302 is closed), the inductor current increases, and during a low-side (LS) phase (e.g., when the LS switch 304 is closed), the inductor current decreases. After the HS phase and the LS phase, a tri-state phase 406 may occur during which both switches 302, 304 are open.

[0051] Certain aspects of the present disclosure provide techniques for automatically switching between PFM mode and PWM mode based on the duration of a tri-state phase. When the SMPS experiences a relatively mild load current change in functional mode (e.g., due to temperature changes or during low PA output power conditions), an automatic switching finite state machine (FSM) (e.g., in controller 318) may be enabled. In this manner, automatic reconfiguration from PWM mode to PFM mode (or vice versa) may occur. When enabled, the independent FSM may digitize the duration that the SMPS output stage remains in the tri-state phase. In other words, the FSM may include a time-to-digital converter (TDC) that may output a digital signal indicating the duration of the tri-state phase (e.g., may output a duration t1, t2, t3, etc., such as Figure 4 ). The digital output may indicate how active the SMPS voltage is and may be used to meter the amount of load current of the SMPS. For example, a decrease in the duration of the three-state phase may indicate an increase in load current and vice versa. The digital output indicating the duration of the three-state phase may be compared to a programmable threshold with hysteresis. Then, based on the comparison with the programmable threshold, the SMPS may determine to switch to PFM mode (when in PWM mode) or to switch to PWM mode (when in PFM mode). For example, when the digital output drops below a first threshold, the SMPS may switch from PFM mode to operate in PWM mode. When the digital output increases above a second threshold, the SMPS may switch from PWM mode to operate in PFM mode. The hysteresis first threshold may be less than the second threshold.

[0052] In some aspects of the present disclosure, when an electronic device (e.g., a WLAN IC) including an SMPS enters a sleep mode, the SMPS may be reconfigured to enter ULPM. During ULPM, a sleep clock source (e.g., for a WLAN IC) may be used to maintain the sleep mode of the SOC. Figure 2The oscillator 208 described above drives the synchronization clock. The internal nodes of the sleep clock source, which can operate at a multiple (e.g., twice) of the frequency of the sleep clock, can be tapped to increase the load current handling capability (e.g., for high temperature situations). In addition to the low-power comparator, the mixed signal FSM of the controller operates in an event-driven manner to reduce the current consumption of the controller, as described in more detail herein. When the comparator detects a reduced regulated output (e.g., a reduced Vout of the SMPS), the comparator can trigger a programmable short pulse (e.g., referred to herein as a single shot pulse or activation pulse) to enable the SMPS output stage. The comparator output can then be automatically reset after a delay to continue monitoring the regulated output. The time difference between adjacent short pulses can be adjusted by the sleep clock (e.g., using an automatic fail-safe controller) to facilitate controller functionality under large load conditions.

[0053] Figure 5 Example components of a ULPM controller 500 according to certain aspects of the present disclosure are illustrated. Figure 6 6 is a timing diagram 600 illustrating signals of ULPM controller 500 according to certain aspects of the present disclosure. As shown, ULPM controller 500 may operate using a synchronous clock (labeled “CLK”) that may be generated by oscillator 514 (e.g., a 64 kHz oscillator, which may be an on-chip oscillator). Oscillator 514 may correspond to Figure 2 Oscillator 514 may also be used as a SOC system clock after being divided using divider 516 (e.g., a divide-by-2 divider labeled "divide-by-2"). ULPM controller 500 controls the same SMPS output stage used during PWM mode and PFM mode in a time-sharing manner.

[0054] As shown, the ULPM controller 500 may include a comparator 502 that may receive a regulated output voltage (Vreg) and a reference voltage (Vref). Vreg may correspond to Vout at the output node 308, as for Figure 3As described. The comparator 502 compares Vreg with Vref and generates a comparator output signal (e.g., labeled "comp.out"). The comparator 502 can be the only circuit of the ULPM controller 500 that is normally open. All other circuits can be enabled only when used by the ULPM controller. When Vreg is greater than Vref, the comparator output signal (comp.out) is logic low. As shown, the output of the comparator 502 is provided to the input of the AND gate 504. Therefore, when the comparator output signal (comp.out) is logic low, the output signal of the AND gate is logic low, resulting in a one-shot output signal (labeled "oneShot.out") at the output of the one-shot circuit 508 (e.g., also referred to herein as a "pulse generating circuit") being logic low. The one-shot output signal is provided to the SMPS output stage controller 510 (e.g., corresponding to Figure 3 318), thereby causing the SMPS to be in an idle mode (eg, a tri-state mode) because the one-shot output signal is logic low. When the comparator output signal is logic low, the ULPM controller 500 may not consume any power except for the comparator 502.

[0055] When Vreg becomes lower than Vref, the comparator output signal transitions to a logical high. A clock signal can be used to capture the transition of the comparator output signal. For example, the comparator output signal can be provided to an input of an AND gate 504, wherein another input of the AND gate 504 is configured to receive an inversion of a failsafe output signal (labeled as "failsafe.out"). As shown in timing diagram 600, when the comparator output signal initially transitions to a logical high, the failsafe output signal is a logical low. Therefore, the comparator output signal transitions to a logical high, thereby causing the output signal of the AND gate 504 (e.g., referred to as a failsafe comparator output signal, labeled as "fs.comp.out") to also transition to a logical high.

[0056] As shown, n flip-flops 506 may be coupled to the output of AND gate 504, where n is any positive integer. The n flip-flops may be chained together, where the output of one flip-flop is coupled to the input of the next flip-flop. A clock signal may be provided to the clock inputs of the n flip-flops 506.

[0057] As shown in the timing diagram 600, at time 1, the first of the n flip-flops 506 samples the comparator output signal as a logic high. The sampled logic high propagates from one flip-flop to another (of the n flip-flops) until the last of the flip-flops generates a logic high signal at time 2 (e.g., after n-1 clock cycles). The logic high signal at the output of the last of the flip-flops is provided to the one-shot circuit 508. At time 3, the one-shot circuit 508 generates a one-shot pulse 602 (labeled "oneShot.out") at the input of the output stage controller 510, as shown. The one-shot pulse 602 is used to drive Figure 3 HS switch 302 is shown. Therefore, when the one shot pulse 602 is logic high, the HS switch 302 is closed, resulting in the HS phase (eg, Figure 4 HS stage 402 shown).

[0058] The one shot pulse 602 briefly enables the SMPS output stage and the zero crossing detector of the SMPS. Figure 3 As shown, the zero crossing detector 330 can be coupled to the switch node 332 of the SMPS. After the rising edge of the one shot pulse 602, the HS switch 302 is closed, and the voltage at the switch node 332 increases. At the falling edge of the one shot pulse 602, the HS switch 302 is opened, and the LS switch 304 is closed (e.g., causing Figure 4 LS phase 404 is shown), thereby reducing the voltage at switch node 332. Zero crossing detector 330 detects when the voltage at switch node 332 reaches zero volts and transmits an indication to controller 318, and controller turns off switch 304. Using zero crossing detector 330, the output stage of the SMPS returns to three-state without wasting SMPS inductor energy because the transition to three-state occurs when the voltage at switch node 332 is zero.

[0059] After generating the one-shot pulse 602, the regulated voltage Vreg may increase above Vref, causing the comparator output signal (comp.out) to transition to a logic low. However, if Vreg remains below Vref, the comparator output signal may remain at a logic high, as shown in the timing diagram 600. Figure 6As shown, at time 4, the fail-safe controller 512 detects the one-shot pulse 602. As shown, the fail-safe controller 512 may generate a delayed and extended pulse (e.g., failsafe.out) of one clock cycle pulse width at the next falling clock edge after the one-shot pulse 602. At time 5, despite the comparator output signal being a logic high, the first of the n flip-flops samples a logic low due to the fail-safe logic. In other words, even though the comparator output signal is a logic high, the output of the AND gate 504 (e.g., fs.comp.out) is a logic low because the logic high failsafe.out signal is provided to the inverting input of the AND gate 504. At time 6, the first of the n flip-flops samples a logic high at the next rising edge of the clock signal, thereby generating a low-to-high transition used by the one-shot circuit 508 to output another one-shot pulse 604 at time 7. This process may be repeated until Vreg increases above Vref.

[0060] Certain aspects of the present disclosure relate to generating successive one shot pulses with increasing pulse durations to increase Vreg above Vref. For example, one shot circuit 508 may be configured to generate one shot pulse 604 having a pulse duration longer than one shot pulse 602 based on the duration of the tri-state phase.

[0061] Figure 7 7 is a timing diagram 700 illustrating the inductor current of an SMPS in response to a one-shot pulse according to certain aspects of the present disclosure. Figure 4 As described, as the SMPS load current increases, the duration of the three-state stage (e.g., duration t1, t2, t3, t4, ...) may decrease. In some aspects, the duration of the three-state stage may be counted using a system sleep clock (e.g., converted to a digital signal using a TDC). Once the digital value becomes less than a threshold value (e.g., duration t3 becomes less than a threshold value), the one-shot pulse width may be increased, as shown. For example, duration t3 (or a digital signal representing duration t3) may be less than a threshold value, and the subsequent one-shot pulse may have an increased pulse width compared to the previous one-shot pulse (e.g., before the three-state stage with duration t3). The increased one-shot pulse width increases the inductor current (e.g., increased inductor current peak 702). Due to the increased one-shot pulse width and the increased inductor current, the three-state stage may have an increased duration t4.

[0062] As described above, the ULPM controller 500 may output delayed and widened pulses, thereby generating continuous one-shot pulses provided to the output stage controller 510 to increase Vreg above Vref. Certain aspects of the present disclosure provide a current limiting function that balances SMPS efficiency and load current handling capability without a current limiter circuit. In some aspects, the automatic fail-safe controller 512 may compare adjacent pulse inputs and may ignore the latter pulse if the latter pulse arrives too early. If the duration between two consecutive one-shot pulses is less than a threshold, the automatic fail-safe controller 512 may fail. Therefore, if the duration from the latter pulse to the previous pulse is less than a threshold, the automatic fail-safe controller 512 may ignore the latter pulse.

[0063] With the SMPS described herein, an electronic device (e.g., a WLAN IC) can be powered using a coin cell battery (e.g., CR2032). It is known that the source impedance of a coin cell battery increases over time. In some aspects, the usable life of the coin cell battery can be increased by limiting the peak current under PA operation. An appropriate dynamic error vector magnitude (EVM) can be achieved with minimal (or at least reduced) SMPS current consumption to prepare for the transition from PFM mode to PWM mode. Hardware-based automatic switching between PWM mode and PFM mode can maintain the SMPS in a desired efficiency state.

[0064] Figure 8 is a flow diagram illustrating example operations 800 for controlling an output stage of a switched mode power supply (SMPS), in accordance with certain aspects of the present disclosure. Operations 800 may be performed, for example, by a power control circuit, such as the ULPM controller 500.

[0065] At block 802, the power control circuit compares (e.g., via comparator 502) a reference voltage (e.g., Vref) with a regulated voltage (e.g., Vreg) at an output of the SMPS. At block 804, the power control circuit generates a first pulse (e.g., Vreg) based on the regulated voltage being lower than the reference voltage via a logic component coupled to the output of the comparator. Figure 6 A single-shot pulse 602 of the embodiment of the present invention is used to temporarily enable the output stage of the SMPS. Enabling the output stage of the SMPS may include closing a high-side (HS) switch of the output stage during the first pulse (e.g., Figure 3 The first pulse may be generated based on the clock signal. In some aspects, the first pulse may be generated based on the SMPS being in a low power mode.

[0066] In some aspects, after generating the first pulse, the power control circuit generates a second pulse based on the regulated voltage being lower than the reference voltage (eg, Figure 6The one-shot pulse 604 of the SMPS is used to temporarily enable the output stage of the SMPS. In some aspects, the duration of the second pulse is greater than the duration of the first pulse. Generating the second pulse includes setting the duration of the second pulse to be greater than the duration of the first pulse based on the duration of the three-state phase of the SMPS being less than a threshold. The three-state phase may be after generating the first pulse and before generating the second pulse.

[0067] In some aspects, the power control circuit detects the first pulse via a controller (e.g., fail-safe controller 512). The power control circuit may delay generation of the second pulse based on detection of the first pulse. Generation of the second pulse may be delayed for a duration associated with a period of the clock signal.

[0068] Example aspects

[0069] Aspect 1. An integrated circuit (IC) for power management, the IC comprising: a first port, the first port being used to couple to a first terminal of a battery and a capacitor element; a second port, the second port being used to couple to a second terminal of the capacitor element; a switched mode power supply (SMPS), the switched mode power supply (SMPS) having an input portion coupled to the first port; and a switch, the switch being coupled between the second port and a reference potential node of the IC.

[0070] Aspect 2. The IC of aspect 1, wherein the switch is configured to be opened during a pulse frequency modulation (PFM) mode of the SMPS.

[0071] Aspect 3. An IC according to aspect 2, wherein the switch is configured to be closed before the SMPS changes from the PFM mode to a pulse width modulation (PWM) mode, and wherein the switch is configured to remain closed after the SMPS changes to the PWM mode.

[0072] Aspect 4. The IC of aspect 3, wherein the switch is configured to close 50 ms to 150 ms before the SMPS changes from the PFM mode to the PWM mode.

[0073] Aspect 5. An IC according to any one of Aspects 1-4, wherein the IC further comprises a logic component coupled to the SMPS, wherein the logic component is configured to: determine an amount of time that an output stage of the SMPS is in a three-state mode; and automatically select between a pulse frequency modulation (PFM) mode and a pulse width modulation (PWM) mode for the SMPS based on the amount of time.

[0074] Aspect 6. An IC according to Aspect 5, wherein in order to automatically select between the PFM mode and the PWM mode for the SMPS, the logic component is configured to: select the PFM mode when the amount of time is greater than a first threshold time; and select the PWM mode when the amount of time is less than a second threshold time.

[0075] Aspect 7. An IC according to any one of Aspects 1-6, the IC further comprising: a comparator having a first input coupled to a reference voltage node and having a second input coupled to an output of the SMPS; and a logic component having an input coupled to the output of the comparator and having an output coupled to a control input of the SMPS, wherein when the SMPS is in a low power mode and when the regulated voltage at the second input of the comparator is lower than a reference voltage at the first input of the comparator, the logic component is configured to trigger a pulse to temporarily enable the output stage of the SMPS.

[0076] Aspect 8. The IC of aspect 7, wherein the SMPS is in the low power mode and when the regulated voltage is above the reference voltage, the logic component is configured to keep the SMPS idle.

[0077] Aspect 9. An IC according to any one of aspects 7-8, wherein when the SMPS is in the low power mode and when the regulated voltage is higher than the reference voltage, the comparator is configured to draw current but the logic component is disabled.

[0078] Aspect 10. A wireless local area network (WLAN) device, comprising the IC according to Aspect 1, the wireless local area network (WLAN) device also comprising: the battery, the battery having a first terminal coupled to the first port and having a second terminal coupled to the reference potential node of the IC; and the capacitive element, the capacitive element coupled between the first port and the second port of the IC.

[0079] Aspect 11. The WLAN device according to aspect 10, wherein the battery is a button battery.

[0080] Aspect 12. The WLAN device according to aspect 11, wherein the button battery is a CR2032 battery.

[0081] Aspect 13. A method of using, operating or forming an IC or a device according to any one of aspects 1-12.

[0082] Aspect 14: An integrated circuit (IC) for power management, the IC comprising: a first port, the first port being used to couple to a first terminal of a battery and a capacitor element; a second port, the second port being used to couple to a second terminal of the capacitor element; a switching mode power supply (SMPS), the switching mode power supply (SMPS) having an input portion coupled to the first port; and a switch, the switch being coupled between the second port and a reference potential node of the IC.

[0083] Aspect 15: The IC of aspect 14, wherein the switch is configured to be open during a pulse frequency modulation (PFM) mode of the SMPS.

[0084] Aspect 16: An IC according to aspect 15 or 2, wherein the switch is configured to close before the SMPS changes from the PFM mode to the pulse width modulation (PWM) mode, and wherein the switch is configured to remain closed after the SMPS changes to the PWM mode.

[0085] Aspect 17: The IC of any of aspects 16-16, wherein the switch is configured to close 50 ms to 150 ms before the SMPS changes from the PFM mode to the PWM mode.

[0086] Aspect 18: An IC according to any one of Aspects 14-17, wherein the IC also includes a logic component coupled to the SMPS, and the logic component is configured to: determine the amount of time that the output stage of the SMPS is in a three-state mode; and based on the amount of time, automatically select between a pulse frequency modulation (PFM) mode and a pulse width modulation (PWM) mode for the SMPS.

[0087] Aspect 19: An IC according to any of Aspects 18-18, wherein in order to automatically select between the PFM mode and the PWM mode for the SMPS, the logic component is configured to: select the PFM mode based on the amount of time being greater than a first threshold time; and select the PWM mode based on the amount of time being less than a second threshold time.

[0088] Aspect 20: An IC according to any one of Aspects 14-19, the IC further comprising: a comparator having a first input coupled to a reference voltage node and having a second input coupled to an output of the SMPS; and a logic component having an input coupled to the output of the comparator and having an output coupled to a control input of the SMPS, wherein when the SMPS is in a low power mode and when the regulated voltage at the second input of the comparator is lower than the reference voltage at the first input of the comparator, the logic component is configured to trigger a pulse to temporarily enable the output stage of the SMPS.

[0089] Aspect 21: The IC of any of aspects 20-20, wherein when the SMPS is in the low power mode and when the regulated voltage is above the reference voltage, the logic component is configured to keep the SMPS idle.

[0090] Aspect 22: The IC of any of aspects 20-21, wherein when the SMPS is in the low power mode and when the regulated voltage is above the reference voltage, the comparator is configured to draw current but the logic component is disabled.

[0091] Aspect 23: A wireless local area network (WLAN) device, comprising an IC according to any one of Aspects 14-22, the wireless local area network (WLAN) device also comprising: the battery, the battery having a first terminal coupled to the first port and having a second terminal coupled to the reference potential node of the IC; and the capacitive element, the capacitive element coupled between the first port and the second port of the IC.

[0092] Aspect 24: The WLAN device according to any one of aspects 23-23, wherein the battery is a button battery.

[0093] Aspect 25: A circuit for controlling an output stage of a switched mode power supply (SMPS), the circuit comprising: a comparator having a first input coupled to a reference voltage node and having a second input coupled to an output of the SMPS; and a logic component having an input coupled to the output of the comparator and having an output coupled to a control input of the SMPS, wherein the logic component is configured to generate a first pulse to temporarily enable the output stage of the SMPS based on a regulated voltage at the second input of the comparator being lower than a reference voltage at the first input of the comparator, the first pulse being further generated based on a clock signal.

[0094] Aspect 26: The circuit of any of Aspects 25-25, wherein the logic component is configured to generate the first pulse based on the SMPS being in a low power mode.

[0095] Aspect 27: A circuit according to any one of Aspects 25-26, wherein the logic component is also configured to generate a second pulse to temporarily enable the output stage of the SMPS after generating the first pulse based on the regulated voltage at the second input of the comparator being lower than the reference voltage at the first input of the comparator.

[0096] Aspect 28: The circuit of any of Aspects 27-27, wherein the duration of the second pulse is greater than the duration of the first pulse.

[0097] Aspect 29: A circuit according to any one of Aspects 28-28, wherein the logic component is configured to set the duration of the second pulse to be greater than the duration of the first pulse based on the duration of a three-state phase of the SMPS being less than a threshold, the three-state phase being after generating the first pulse and before generating the second pulse.

[0098] Aspect 30: A circuit according to any one of Aspects 25-29, wherein the logic component includes: one or more flip-flops, the one or more flip-flops are coupled to the output portion of the comparator and have a clock input portion configured to receive the clock signal; and a pulse generating circuit, the pulse generating circuit is coupled to the one or more flip-flops and is configured to generate the first pulse to enable the output stage of the SMPS.

[0099] Aspect 31: A circuit according to any one of Aspects 30-30, wherein the circuit further includes: an AND gate having a first input coupled to the output of the comparator and an output coupled to the one or more triggers; and a controller having an input coupled to the output of the pulse generating circuit and an output coupled to the second input of the AND gate.

[0100] Aspect 32: The circuit of any of Aspects 31-31, wherein the controller is configured to provide a second pulse to the second input of the AND gate based on the first pulse.

[0101] Aspect 33: The circuit according to any one of aspects 32-32, wherein: the clock input section of the controller is configured to receive the clock signal; and the duration of the second pulse is associated with a period of the clock signal.

[0102] Aspect 34: The circuit of any of Aspects 33-33, wherein the second input of the AND gate comprises an inverting input, and wherein the second pulse is logic high during the period of the clock signal.

[0103] Aspect 35: The circuit of any of Aspects 25-34, wherein enabling the output stage of the SMPS comprises closing a high-side (HS) switch of the output stage during the first pulse.

[0104] Aspect 36: A method for controlling an output stage of a switched mode power supply (SMPS), the method comprising: comparing a reference voltage with a regulated voltage at an output portion of the SMPS via a comparator; and generating a first pulse via a logic component coupled to the output portion of the comparator to temporarily enable the output stage of the SMPS based on the regulated voltage being lower than the reference voltage, the first pulse being further generated based on a clock signal.

[0105] Aspect 37: The method according to any one of aspects 36-36, wherein the first pulse is generated based on the SMPS being in a low power mode.

[0106] Aspect 38: The method of any of aspects 36-37, further comprising, after generating the first pulse, generating a second pulse to temporarily enable the output stage of the SMPS based on the regulated voltage being lower than the reference voltage.

[0107] Aspect 39: A method according to any one of Aspects 38-38, wherein the duration of the second pulse is greater than the duration of the first pulse.

[0108] Aspect 40: A method according to any one of Aspects 39-39, wherein generating the second pulse includes setting the duration of the second pulse to be greater than the duration of the first pulse based on the duration of a three-state phase of the SMPS being less than a threshold, the three-state phase being after generating the first pulse and before generating the second pulse.

[0109] Aspect 41: The method according to any one of aspects 38-40, the method further comprising: detecting the first pulse via a controller; and delaying the generation of the second pulse based on the detection of the first pulse.

[0110] Aspect 42: A method according to any of Aspects 41-41, wherein the generation of the second pulse is delayed for a duration associated with a period of the clock signal.

[0111] Aspect 43: The method of any of aspects 36-42, wherein enabling the output stage of the SMPS comprises closing a high-side (HS) switch of the output stage during the first pulse.

[0112] Additional considerations

[0113] The various operations of the above method may be performed by any suitable components capable of performing the corresponding functions. These components may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs) or processors. Generally, where there are operations illustrated in the accompanying drawings, those operations may have corresponding corresponding components plus functional components with similar numbers.

[0114] As used herein, the term "determining" encompasses a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, a database, or another data structure), ascertaining, etc. In addition, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. In addition, "determining" may include resolving, selecting, choosing, establishing, etc.

[0115] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including single members). For example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple of the same elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc or any other ordering of a, b, and c).

[0116] The methods disclosed herein include one or more steps or actions for implementing the described methods. The steps and / or actions of the methods may be interchangeable with each other without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0117] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. An integrated circuit (IC) for power management, the IC comprising: a first port for coupling to a battery and a first terminal of a capacitive element; a second port for coupling to a second terminal of the capacitive element; a switched mode power supply (SMPS) having an input coupled to the first port; and A switch is coupled between the second port and a reference potential node of the IC.

2. The IC of claim 1, wherein the switch is configured to be turned off during a pulse frequency modulation (PFM) mode of the SMPS.

3. The IC of claim 2, wherein the switch is configured to be closed before the SMPS changes from the PFM mode to a pulse width modulation (PWM) mode, and wherein the switch is configured to remain closed after the SMPS changes to the PWM mode. 4 . The IC of claim 3 , wherein the switch is configured to close 50 ms to 150 ms before the SMPS changes from the PFM mode to the PWM mode.

5. The IC of claim 1 , further comprising a logic component coupled to the SMPS, the logic component being configured to: determining an amount of time an output stage of the SMPS is in a tri-state mode; and Based on the amount of time, a pulse frequency modulation (PFM) mode and a pulse width modulation (PWM) mode are automatically selected for the SMPS.

6. The IC of claim 5, wherein to automatically select between the PFM mode and the PWM mode for the SMPS, the logic component is configured to: selecting the PFM mode based on the amount of time being greater than a first threshold time; and The PWM mode is selected based on the amount of time being less than a second threshold time.

7. The IC of claim 1 , further comprising: a comparator having a first input coupled to a reference voltage node and having a second input coupled to an output of the SMPS; and a logic component having an input coupled to the output of the comparator and having an output coupled to a control input of the SMPS, wherein when the SMPS is in a low power mode and when a regulated voltage at the second input of the comparator is lower than a reference voltage at the first input of the comparator, the logic component is configured to trigger a pulse to temporarily enable an output stage of the SMPS.

8. The IC of claim 7, wherein when the SMPS is in the low power mode and when the regulated voltage is above the reference voltage, the logic component is configured to keep the SMPS idle.

9. The IC of claim 7, wherein when the SMPS is in the low power mode and when the regulated voltage is above the reference voltage, the comparator is configured to draw current but the logic component is disabled.

10. A wireless local area network (WLAN) device, comprising the IC according to claim 1, wherein the wireless local area network (WLAN) device further comprises: the battery having a first terminal coupled to the first port and having a second terminal coupled to the reference potential node of the IC; and The capacitive element is coupled between the first port and the second port of the IC. The WLAN device according to claim 10 , wherein the battery is a button battery.

12. A circuit for controlling an output stage of a switched mode power supply (SMPS), the circuit comprising: a comparator having a first input coupled to a reference voltage node and having a second input coupled to an output of the SMPS; and a logic component having an input coupled to the output of the comparator and having an output coupled to a control input of the SMPS, wherein the logic component is configured to generate a first pulse to temporarily enable the output stage of the SMPS based on a regulated voltage at the second input of the comparator being lower than a reference voltage at the first input of the comparator, the first pulse being further generated based on a clock signal.

13. The circuit of claim 12, wherein the logic component is configured to generate the first pulse based on the SMPS being in a low power mode.

14. The circuit of claim 12 , wherein the logic component is further configured to generate a second pulse to temporarily enable the output stage of the SMPS based on the regulated voltage at the second input of the comparator being lower than the reference voltage at the first input of the comparator after generating the first pulse.

15. The circuit of claim 14, wherein a duration of the second pulse is greater than a duration of the first pulse.

16. The circuit of claim 15, wherein the logic component is configured to set the duration of the second pulse to be greater than the duration of the first pulse based on a duration of a tri-state phase of the SMPS being less than a threshold, the tri-state phase being after generating the first pulse and before generating the second pulse.

17. The circuit of claim 12, wherein the logic component comprises: one or more flip-flops coupled to an output of the comparator and having a clock input configured to receive the clock signal; and A pulse generating circuit is coupled to the one or more flip-flops and is configured to generate the first pulse to enable the output stage of the SMPS.

18. The circuit of claim 17, further comprising: an AND gate having a first input coupled to the output of the comparator and an output coupled to the one or more flip-flops; and A controller has an input coupled to the output of the pulse generating circuit and an output coupled to the second input of the AND gate.

19. The circuit of claim 18, wherein the controller is configured to provide a second pulse to the second input of the AND gate based on the first pulse.

20. The circuit of claim 19, wherein: A clock input of the controller is configured to receive the clock signal; and The duration of the second pulse is correlated to a period of the clock signal.

21. The circuit of claim 20, wherein the second input of the AND gate comprises an inverting input, and wherein the second pulse is logic high during the period of the clock signal.

22. The circuit of claim 12, wherein enabling the output stage of the SMPS comprises closing a high-side (HS) switch of the output stage during the first pulse.

23. A method for controlling an output stage of a switched mode power supply (SMPS), the method comprising: comparing a reference voltage to a regulated voltage at an output of the SMPS via a comparator; as well as A first pulse is generated via a logic component coupled to an output of the comparator to temporarily enable the output stage of the SMPS based on the regulated voltage being lower than the reference voltage, the first pulse being further generated based on a clock signal.

24. The method of claim 23, wherein the first pulse is generated based on the SMPS being in a low power mode.

25. The method of claim 23, further comprising, after generating the first pulse, generating a second pulse to temporarily enable the output stage of the SMPS based on the regulated voltage being lower than the reference voltage.

26. The method of claim 25, wherein the duration of the second pulse is greater than the duration of the first pulse.

27. The method of claim 26, wherein generating the second pulse comprises setting the duration of the second pulse to be greater than the duration of the first pulse based on a duration of a tri-state phase of the SMPS being less than a threshold, the tri-state phase being after generating the first pulse and before generating the second pulse.

28. The method according to claim 25, further comprising: detecting, via a controller, the first pulse; as well as The generating of the second pulse is delayed based on the detecting of the first pulse.

29. The method of claim 28, wherein the generation of the second pulse is delayed for a duration associated with a period of the clock signal.

30. The method of claim 23, wherein enabling the output stage of the SMPS comprises closing a high-side (HS) switch of the output stage during the first pulse.

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