Semiconductor device

Abstract

A semiconductor device includes a transistor portion and a diode portion disposed in parallel with the transistor portion. The transistor portion includes a first contact portion in which a first mesa portion of the plurality of mesa portions is in contact with the metal electrode, and a second contact portion in which a second mesa portion of the plurality of mesa portions disposed farther from the diode portion than the first mesa portion is in contact with the metal electrode. The lower end of the second contact portion is disposed above the lower end of the first contact portion.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] In a semiconductor device having a transistor portion and a diode portion, there is known a structure in which a defect region is locally formed in the diode portion and the transistor portion to adjust the carrier lifetime (see, for example, Patent Document 1). In addition, in a semiconductor device, there is known a structure in which an electrode is connected to a semiconductor substrate using a trench-shaped contact portion (see, for example, Patent Document 2).

[0003] Patent document 1: WO2021 / 145079 Patent Document 2: Japanese Patent No. 7085975 Summary of the invention

[0004] Technical issues In a semiconductor device including a transistor portion and a diode portion, it is preferable to improve characteristics such as reverse recovery loss of the diode portion and threshold voltage of the transistor portion.

[0005] Technical Solution In order to solve the above-mentioned problems, in a first aspect of the present invention, a semiconductor device having a semiconductor substrate having an upper surface and a lower surface is provided. The semiconductor device may include a transistor portion provided on the semiconductor substrate. Any of the semiconductor devices may include a diode portion provided on the semiconductor substrate and arranged in parallel with the transistor portion in a first direction. In any of the semiconductor devices, the transistor portion and the diode portion may each include: a metal electrode provided above the upper surface of the semiconductor substrate; a plurality of groove portions provided from the upper surface of the semiconductor substrate to the inside and arranged in parallel in the first direction; and a plurality of mesa portions which are portions of the semiconductor substrate sandwiched by two of the groove portions in the first direction. In any of the semiconductor devices, the transistor portion may include a first contact portion for a first mesa portion of the plurality of mesa portions to contact the metal electrode. In any of the semiconductor devices, the transistor portion may include a second contact portion for a second mesa portion of the plurality of mesa portions which is arranged farther from the diode portion than the first mesa portion to contact the metal electrode. In any of the above-mentioned semiconductor devices, the lower end of the second contact portion may be arranged above the lower end of the first contact portion.

[0006] In any of the semiconductor devices described above, the first mesa portion may include an emitter region of a first conductivity type exposed on the upper surface of the semiconductor substrate. In any of the semiconductor devices described above, the first mesa portion may include a contact region of a second conductivity type exposed on the upper surface of the semiconductor substrate. In any of the semiconductor devices described above, the first mesa portion may include a first plug region of a second conductivity type that is disposed in contact with the lower end of the first contact portion and has a doping concentration higher than that of the contact region.

[0007] In any of the semiconductor devices described above, the second mesa portion may include the emitter region. In any of the semiconductor devices described above, the second mesa portion may include the contact region. In any of the semiconductor devices described above, the second mesa portion may include a second plug region of the second conductivity type that is disposed in contact with the lower end of the second contact portion and has a doping concentration higher than that of the contact region. In any of the semiconductor devices described above, the first plug region may be disposed at a position lower than the second plug region.

[0008] In any of the above semiconductor devices, a dose of the first plug region and a dose of the second plug region may be the same.

[0009] In any of the semiconductor devices described above, the first mesa portion may have a length in a second direction different from the first direction when viewed from above, and the emitter region and the contact region are alternately arranged along the second direction. Any of the semiconductor devices described above may include the first plug region in any cross section perpendicular to the second direction and passing through the contact region.

[0010] Any of the semiconductor devices described above may not have the first plug region in any cross section that is perpendicular to the second direction and passes through the emitter region.

[0011] In any of the semiconductor devices described above, the second mesa portion may have a length in a second direction different from the first direction when viewed from above, and the emitter region and the contact region are alternately arranged along the second direction. In any of the semiconductor devices described above, the second plug region may be provided in any cross section perpendicular to the second direction and passing through the contact region.

[0012] Any of the above-mentioned semiconductor devices may not have the second plug region in any cross section perpendicular to the second direction and passing through the emitter region.

[0013] In any of the above semiconductor devices, the first contact portion may include a trench contact portion in which the metal electrode is disposed inside the semiconductor substrate.

[0014] In any of the above-mentioned semiconductor devices, a lower end of the second contact portion may be arranged on the upper surface of the semiconductor substrate.

[0015] In any of the semiconductor devices described above, the diode portion may include a third contact portion for contacting a third mesa portion of the plurality of mesa portions with the metal electrode. In any of the semiconductor devices described above, a lower end of the third contact portion may be arranged above a lower end of the first contact portion.

[0016] In any of the semiconductor devices described above, the diode portion may include a third contact portion for contacting a third mesa portion of the plurality of mesa portions with the metal electrode. In any of the semiconductor devices described above, a lower end of the third contact portion may be arranged below a lower end of the second contact portion.

[0017] In any of the semiconductor devices described above, the diode portion may include a third contact portion for contacting a third mesa portion of the plurality of mesa portions with the metal electrode. In any of the semiconductor devices described above, a lower end of the third contact portion may be disposed at the same depth as a lower end of the second contact portion.

[0018] In any of the semiconductor devices described above, the third mesa portion may include an anode region of the second conductivity type, the anode region of the second conductivity type being disposed in contact with the upper surface of the semiconductor substrate. In any of the semiconductor devices described above, the third mesa portion may include a third plug region of the second conductivity type, the third plug region of the second conductivity type being disposed in contact with the lower end of the third contact portion, and having a doping concentration higher than that of the anode region.

[0019] In any of the semiconductor devices described above, the mesa portion of the transistor portion may include a base region of the second conductivity type disposed below the emitter region. In any of the semiconductor devices described above, the third mesa portion may include an anode region of the second conductivity type, the anode region of the second conductivity type being disposed in contact with the upper surface of the semiconductor substrate and having a doping concentration lower than that of the base region.

[0020] Any of the above-mentioned semiconductor devices may include, in at least one of the transistor portion and the diode portion, a lifetime adjustment region which is arranged on the upper surface side of the semiconductor substrate and includes a lifetime suppressor for adjusting the lifetime of carriers.

[0021] In any of the above-mentioned semiconductor devices, the lifetime adjustment region may be arranged below the first mesa portion.

[0022] In any of the above semiconductor devices, the lifetime adjustment region may be provided below the first mesa portion and at least one of the diode portion.

[0023] In any of the above-mentioned semiconductor devices, the lifetime adjustment region may be provided under the first mesa portion, under the second mesa portion, and at least any one of the diode portion.

[0024] In any of the semiconductor devices described above, the transistor portion may include an adjustment region, in which the lifetime adjustment region is provided extending from the diode portion. In any of the semiconductor devices described above, the transistor portion may include a non-adjustment region, which is arranged in parallel with the adjustment region in the first direction and in which the lifetime adjustment region is not provided. In any of the semiconductor devices described above, the first mesa portion and the first contact portion may be arranged in the adjustment region. In any of the semiconductor devices described above, the second mesa portion and the second contact portion may be arranged in the non-adjustment region.

[0025] In a plan view, the area of ​​the non-adjustment region of any of the above semiconductor devices is larger than the area of ​​the adjustment region.

[0026] In any of the above-mentioned semiconductor devices, in the transistor portion, the number of the second mesa portions may be greater than the number of the first mesa portions.

[0027] In any of the above-mentioned semiconductor devices, in the transistor portion, a threshold voltage of the second mesa portion may be lower than a threshold voltage of the first mesa portion.

[0028] In any of the semiconductor devices described above, the transistor portion may include two or more of the first mesa portions arranged in parallel in the first direction. In any of the semiconductor devices described above, the trench contact portion of at least one of the first mesa portions may be provided at a position deeper than the trench contact portion of the first mesa portion arranged at a position closer to the diode portion than the first mesa portion.

[0029] In any of the above semiconductor devices, the metal electrodes in the first contact portion and the second contact portion may include a barrier metal. In any of the above semiconductor devices, the barrier metal may include titanium.

[0030] In any of the above semiconductor devices, the metal electrode in the third contact portion may include a barrier metal. In any of the above semiconductor devices, the barrier metal may include titanium.

[0031] The above-mentioned invention summary does not list all the essential features of the present invention. In addition, sub-combinations of these feature groups can also become inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 1 is a plan view showing an example of a semiconductor device 100 according to an embodiment of the present invention.

[0033] Figure 2 yes Figure 1 Magnified view of area D in FIG.

[0034] Figure 3 It is shown Figure 2 A diagram showing an example of an ee cross section.

[0035] Figure 4A It is an enlarged view of the first stage surface portion 61 , the second stage surface portion 62 , and the third stage surface portion 63 and their vicinities.

[0036] Figure 4B This is another example of an enlarged view of the first stage surface portion 61 , the second stage surface portion 62 , and the third stage surface portion 63 and their vicinities.

[0037] Figure 5 It is shown Figure 2 FIG. 1 is a diagram showing an example of an ff cross section.

[0038] Fig. 6A yes Figure 5 An enlarged view of the first stage surface 61 , the second stage surface 62 , and the vicinity of the third stage surface 63 is shown.

[0039] Figure 6B yes Figure 5 Another example of the enlarged view of the vicinity of the first stage surface portion 61 , the second stage surface portion 62 , and the third stage surface portion 63 is shown.

[0040] Fig. 7A It is shown Fig. 6A A diagram showing an example of doping concentration distribution at the aa line and the bb line.

[0041] Figure 7B It is shown Figure 6B A diagram showing an example of doping concentration distribution at the aa line and the bb line.

[0042] Fig. 8A It is an enlarged view of the periphery of the first contact portion 211 .

[0043] Figure 8B It is an enlarged view of the periphery of the second contact portion 212 .

[0044] Fig. 9 This is a diagram showing another example of the ee cross section.

[0045] Fig.10 2 is a diagram showing an example of arrangement of the adjustment region 201 and the non-adjustment region 202 in a plan view.

[0046] Fig.11 This is a diagram showing another example of the ee cross section.

[0047] Fig.12 This is a diagram showing another example of the ee cross section.

[0048] Fig.13 This is a diagram showing another example of the ee cross section.

[0049] Fig.14 This is a diagram showing another example of the ee cross section.

[0050] Fig.15 This is a diagram showing another example of the ee cross section.

[0051] Fig.16 This is a diagram showing another example of the ee cross section.

[0052] Fig.17 It is an enlarged view of the first stage surface portion 61 , the second stage surface portion 62 , and the third stage surface portion 63 and their vicinities.

[0053] Explanation of symbols 10…semiconductor substrate, 11…well region, 12…emitter region, 14…base region, 15…contact region, 16…accumulation region, 17…trench contact portion, 18…drift region, 20…buffer region, 21…upper surface, 22…collector region, 23…lower surface, 24…collector electrode, 29…straight portion, 30…dummy trench portion, 31…front end portion, 32…dummy insulating film, 34…dummy conductive portion, 38…interlayer insulating film, 39…straight portion, 40…gate trench portion, 41…front end portion, 42…gate insulating film, 44…gate conductive portion, 52…emitter electrode, 54…contact hole, 60…terasa portion, 61…first terrace portion, 62…second terrace portion, 63…third terrace portion, 64…fourth terrace portion, 70…transistor portion, 80…second terrace portion Pole portion, 81…extension region, 82…cathode region, 90…edge termination structure portion, 100…semiconductor device, 130…peripheral gate wiring, 131…active side gate wiring, 160…active portion, 162…end edge, 164…gate pad, 200…boundary region, 201…adjustment region, 202…non-adjustment region, 204…lattice defect, 206…lifetime adjustment region, 211…first contact portion, 212…second contact portion, 213…third contact portion, 221…first plug region, 222…second plug region, 223…third plug region, 231…peak, 232…peak, 241, 242…junction portion, 251…upper portion, 252…barrier metal portion, 253…first layer, 254…second layer, 255…silicide layer. DETAILED DESCRIPTION

[0054] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention involved in the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the technical means of the invention.

[0055] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of a substrate, layer, or other component is referred to as an upper surface, and the other is referred to as a lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when the semiconductor device is installed.

[0056] In this specification, sometimes the rectangular coordinate axes of the X-axis, Y-axis and Z-axis are used to explain technical matters. The rectangular coordinate axes are only used to determine the relative positions of the components and are not limited to specific directions. For example, the Z-axis is not limited to indicating the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions to each other. When the Z-axis direction is recorded without recording the positive or negative, it refers to the direction parallel to the +Z-axis and the -Z-axis.

[0057] In this specification, the orthogonal axes parallel to the upper surface and the lower surface of the semiconductor substrate are referred to as the X-axis and the Y-axis. In addition, the axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. In addition, in this specification, the direction parallel to the upper surface and the lower surface of the semiconductor substrate, including the X-axis and the Y-axis, is sometimes referred to as the horizontal direction.

[0058] The region from the center in the depth direction of the semiconductor substrate to the upper surface of the semiconductor substrate is sometimes referred to as the upper surface side. Similarly, the region from the center in the depth direction of the semiconductor substrate to the lower surface of the semiconductor substrate is sometimes referred to as the lower surface side.

[0059] In this specification, the term "same" or "equal" may include a case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0060] In this specification, the conductivity type of the doped region doped with impurities is set to P type or N type for description. In this specification, impurities sometimes specifically refer to any one of N type donors and P type acceptors, and sometimes are described as dopants. In this specification, doping refers to introducing donors or acceptors into a semiconductor substrate to make it a semiconductor showing N type conductivity or a semiconductor showing P type conductivity.

[0061] In this specification, the doping concentration refers to the concentration of donors or acceptors in thermal equilibrium. In this specification, the net doping concentration refers to the actual concentration obtained by adding the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge. As an example, if the donor concentration is N D And the acceptor concentration is set to N A, then the net doping concentration at any position becomes N D -N A In this specification, the net doping concentration may be described simply as the doping concentration.

[0062] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of accepting electrons from a semiconductor. Donors and acceptors are not limited to the impurities themselves. For example, a VOH defect formed by a combination of vacancies (V), oxygen (O), and hydrogen (H) present in a semiconductor functions as an electron donor. A hydrogen donor may be a donor formed by a combination of at least a vacancy (V) and hydrogen (H). Alternatively, interstitial Si-H formed by a combination of interstitial silicon (Si-i) and hydrogen in a silicon semiconductor also functions as an electron donor. In this specification, VOH defects or interstitial Si-H are sometimes referred to as hydrogen donors.

[0063] In this specification, the semiconductor substrate has N-type body donors distributed throughout. Body donors are donors formed by dopants that are roughly uniformly contained in the ingot when the ingot that becomes the raw material of the semiconductor substrate is manufactured. The body donor in this example is an element other than hydrogen. The dopant of the body donor is, for example, phosphorus, antimony, arsenic, selenium or sulfur, but is not limited to this. The body donor in this example is phosphorus. The body donor is also included in the P-type region. The semiconductor substrate can be a wafer cut from a semiconductor ingot or a chip obtained by singulating the wafer. The semiconductor ingot can be manufactured by any one of the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), and the floating zone melting method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration contained in the substrate manufactured by the MCZ method is 1×10 17 ~7×10 17 / cm 3 The oxygen concentration of the substrate produced by the FZ method is 1×10 15 ~5×10 16 / cm 3 The side with a high oxygen concentration tends to generate hydrogen donors more easily. The body donor concentration can use the chemical concentration of the body donor distributed throughout the semiconductor substrate, or it can be a value between 90% and 100% of the chemical concentration. In addition, the semiconductor substrate can also use an undoped substrate that does not contain dopants such as phosphorus. In this case, the body donor concentration (D0) of the undoped substrate is, for example, 1×10 10 / cm 3 Above and 5×10 12 / cm 3 The bulk donor concentration (D0) of the undoped substrate is preferably 1×10 11 / cm 3 The bulk donor concentration (D0) of the undoped substrate is preferably 5×10 12 / cm3 Hereinafter, each concentration in the present invention may be a value at room temperature. As an example, a value at room temperature may be a value at 300K (Kelvin) (about 26.9° C.).

[0064] In this specification, when it is recorded as P+ type or N+ type, it means that the doping concentration is higher than the doping concentration of P type or N type, and when it is recorded as P- type or N- type, it means that the doping concentration is lower than the doping concentration of P type or N type. In addition, when it is recorded as P++ type or N++ type in this specification, it means that the doping concentration is higher than the doping concentration of P+ type or N+ type. The units in this specification are SI units unless otherwise specified. Sometimes cm is used to represent the unit of length, but each calculation can be performed after conversion to meters (m).

[0065] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the state of electrical activation. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The above-mentioned net doping concentration can be measured by voltage-capacitance determination (CV method). In addition, the carrier concentration measured by diffusion resistance determination (SR method) can be used as the net doping concentration. The carrier concentration measured by the CV method or the SR method can be set to a value in thermal equilibrium. In addition, in the N-type region, since the donor concentration is sufficiently large compared to the acceptor concentration, the carrier concentration in the region can be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in the region can be used as the acceptor concentration. In this specification, the doping concentration in the N-type region is sometimes referred to as the donor concentration, and the doping concentration in the P-type region is sometimes referred to as the acceptor concentration.

[0066] When the concentration distribution of the donor, acceptor or net doping has a peak, the peak value can be used as the concentration of the donor, acceptor or net doping in the region. When the concentration of the donor, acceptor or net doping is almost uniform, the average value of the concentration of the donor, acceptor or net doping in the region can be used as the concentration of the donor, acceptor or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm 3 or / cm 3 This unit is used for the donor or acceptor concentration or chemical concentration in a semiconductor substrate. The description of atoms can be omitted.

[0067] The carrier concentration measured by the SR method can be lower than the concentration of donors or acceptors. In the range where the current flows when measuring the diffusion resistance, the carrier mobility of the semiconductor substrate is sometimes lower than the value in the crystalline state. The reduction in carrier mobility is caused by the disorder (disorder) of the crystal structure caused by lattice defects, etc., which causes the carriers to scatter.

[0068] The concentration of donors or acceptors calculated from the carrier concentration measured by the CV method or the SR method can be lower than the chemical concentration of the element representing the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic that becomes a donor or the acceptor concentration of boron that becomes an acceptor in a silicon semiconductor is about 99% of their chemical concentration. On the other hand, the donor concentration of hydrogen that becomes a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen.

[0069] Figure 1 FIG. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Figure 1 , the positions of the components projected onto the upper surface of the semiconductor substrate 10 are shown. Figure 1 , only some components of the semiconductor device 100 are shown, and other components are omitted.

[0070] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has an edge 162 when viewed from above. In this specification, the condition referred to as viewed from above refers to the condition observed from the upper surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two sets of edge 162 that are opposite to each other when viewed from above. Figure 1 In the embodiment, the X-axis and the Y-axis are parallel to any one of the end sides 162. In addition, the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0071] The semiconductor substrate 10 is provided with an active portion 160. The active portion 160 is a region where a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but Figure 1 The active portion 160 may refer to a region overlapping with the emitting electrode in a plan view. In addition, a region sandwiched between the active portions 160 in a plan view may also be included in the active portion 160.

[0072] The active portion 160 includes a transistor portion 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor) and a diode portion 80 including a diode element such as a freewheeling diode (FWD). Figure 1 In the example of FIG. 1 , transistor units 70 and diode units 80 are alternately arranged along a predetermined first direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT). In the X-axis direction, a boundary region is arranged between the transistor unit 70 and the diode unit 80, but Figure 1Omitted in .

[0073] exist Figure 1 In the figure, the region where the transistor portion 70 is arranged is marked with a symbol "I", and the region where the diode portion 80 is arranged is marked with a symbol "F". In this specification, a direction different from the first direction in a plan view is sometimes referred to as a second direction (in Figure 1 The second direction may be a direction perpendicular to the first direction. The transistor portion 70 and the diode portion 80 may each have a long side in the second direction. That is, the length of the transistor portion 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is greater than the width in the X-axis direction. The second direction of the transistor portion 70 and the diode portion 80 may be the same as the long side direction of each groove portion and the long side direction of the mesa portion described later.

[0074] The diode portion 80 has an N+ type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode portion 80. That is, the diode portion 80 is a region overlapping with the cathode region when viewed from above. On the lower surface of the semiconductor substrate 10, a P+ type collector region may be provided in a region other than the cathode region. In this specification, an extension region 81 in which the diode portion 80 is extended in the Y-axis direction to the gate wiring described later is sometimes also included in the diode portion 80. A collector region is provided on the lower surface of the extension region 81.

[0075] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. In addition, the transistor section 70 has an N type emitter region, a P type base region, and a gate structure having a gate conductive portion and a gate insulating film periodically arranged on the upper surface side of the semiconductor substrate 10.

[0076] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is arranged near the end 162. The vicinity of the end 162 refers to the area between the end 162 and the emitter electrode when viewed from above. When the semiconductor device 100 is installed, each pad can be connected to an external circuit via wiring such as a wire.

[0077] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 to the gate trench portion. Figure 1 In FIG. 1 , the gate wiring is marked with oblique hatching.

[0078] The gate wiring of this example has a peripheral gate wiring 130 and an active side gate wiring 131. The peripheral gate wiring 130 is arranged between the active portion 160 and the edge 162 of the semiconductor substrate 10 when viewed from above. The peripheral gate wiring 130 of this example surrounds the active portion 160 when viewed from above. The area surrounded by the peripheral gate wiring 130 when viewed from above can be regarded as the active portion 160. In addition, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than the base region described later, and is formed from the upper surface of the semiconductor substrate 10 to a position deeper than the base region. The area surrounded by the well region when viewed from above can be regarded as the active portion 160.

[0079] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is arranged above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring made of aluminum or the like, or a wiring formed of a semiconductor such as polysilicon doped with impurities.

[0080] The active-side gate wiring 131 is provided in the active portion 160. By providing the active-side gate wiring 131 in the active portion 160, it is possible to reduce the variation in wiring length from the gate pad 164 in each region of the semiconductor substrate 10.

[0081] The peripheral gate wiring 130 and the active-side gate wiring 131 are connected to the gate groove portion of the active portion 160. The peripheral gate wiring 130 and the active-side gate wiring 131 are arranged above the semiconductor substrate 10. The peripheral gate wiring 130 and the active-side gate wiring 131 may be metal wiring including aluminum or the like, or wiring formed of a semiconductor such as polysilicon doped with impurities.

[0082] The active-side gate wiring 131 may be connected to the peripheral gate wiring 130. The active-side gate wiring 131 of this example is provided so as to extend from the peripheral gate wiring 130 on one side sandwiching the active portion 160 to the peripheral gate wiring 130 on the other side in the X-axis direction in a manner that crosses the active portion 160 at approximately the center in the Y-axis direction. When the active portion 160 is divided by the active-side gate wiring 131, the transistor portion 70 and the diode portion 80 may be alternately arranged in the X-axis direction in each divided region.

[0083] The semiconductor device 100 may include a temperature sensing portion (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detecting portion (not shown) which simulates the operation of a transistor portion provided in the active portion 160 .

[0084] The semiconductor device 100 of this example includes an edge termination structure portion 90 between the active portion 160 and the edge 162 when viewed from above. The edge termination structure portion 90 of this example is arranged between the peripheral gate wiring 130 and the edge 162. The edge termination structure portion 90 alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure portion 90 may include at least one of a guard ring, a field plate, and a surface electric field reduction device that surrounds the active portion 160 and is provided in an annular shape.

[0085] Figure 2 yes Figure 1 1 is an enlarged view of region D in FIG. Region D is a region including transistor portion 70, diode portion 80, and active-side gate wiring 131. Figure 1 Although omitted in the figure, a boundary region 200 is arranged between the transistor portion 70 and the diode portion 80 in the X-axis direction. The semiconductor device 100 of this example includes a gate groove portion 40, a dummy groove portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10. The gate groove portion 40 and the dummy groove portion 30 are each an example of a groove portion. In addition, the semiconductor device 100 of this example includes an emitter electrode 52 and an active side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 is an example of a metal electrode. The emitter electrode 52 and the active side gate wiring 131 are provided separately from each other.

[0086] An interlayer insulating film is provided between the emitter electrode 52 and the active-side gate wiring 131 and the upper surface of the semiconductor substrate 10, but Figure 2 The interlayer insulating film of this example is provided with a contact hole 54 so as to penetrate the interlayer insulating film. Figure 2 In FIG. 1 , each contact hole 54 is marked with oblique hatching.

[0087] The emitter electrode 52 is disposed above the gate groove portion 40, the dummy groove portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through the contact hole 54. In addition, the emitter electrode 52 is connected to the dummy conductive portion in the dummy groove portion 30 through the contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy groove portion 30 at the front end of the dummy groove portion 30 in the Y-axis direction. The dummy conductive portion of the dummy groove portion 30 may not be connected to the emitter electrode 52 and the gate conductive portion, and may be controlled to a potential different from the potential of the emitter electrode 52 and the potential of the gate conductive portion.

[0088] The active side gate wiring 131 is connected to the gate groove portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 can be connected to the gate conductive portion of the gate groove portion 40 at the front end portion 41 of the gate groove portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy groove portion 30.

[0089] The emitter electrode 52 is formed of a material including metal. Figure 2 , the range in which the emitter electrode 52 is provided is shown. For example, at least a part of the emitter electrode 52 is formed of aluminum or an aluminum-silicon alloy such as a metal alloy such as AlSi, AlSiCu, etc. The emitter electrode 52 may have a barrier metal formed of titanium, a titanium compound, etc. in the lower layer of the region formed of aluminum, etc. Further, a plug portion formed by burying tungsten, etc. in a manner in contact with the barrier metal and aluminum, etc., may be provided in the contact hole.

[0090] The well region 11 is provided so as to overlap with the active side gate wiring 131. The well region 11 is also provided to extend with a predetermined width in a range not overlapping with the active side gate wiring 131. The well region 11 of this example is provided to be separated from the end of the contact hole 54 in the Y-axis direction toward the active side gate wiring 131 side. The well region 11 is a region of the second conductivity type having a higher doping concentration than the doping concentration of the base region 14. The base region 14 of this example is of P- type, and the well region 11 is of P+ type.

[0091] The transistor section 70, the diode section 80 and the boundary region 200 each have a plurality of groove sections arranged in a first direction. In the transistor section 70 of this example, one or more gate groove sections 40 and one or more dummy groove sections 30 are alternately arranged along the first direction. In the diode section 80 of this example, a plurality of dummy groove sections 30 are arranged along the first direction. In the diode section 80 of this example, no gate groove section 40 is arranged. In the boundary region 200 of this example, a plurality of dummy groove sections 30 are arranged along the first direction. In the boundary region 200 of this example, no gate groove section 40 is arranged.

[0092] The gate trench portion 40 of this example may include two straight line portions 39 extending along a second direction perpendicular to the first direction (portions forming a straight line trench along the second direction), and a front end portion 41 connecting the two straight line portions 39 . Figure 2 The second direction in is the Y-axis direction.

[0093] At least a portion of the tip portion 41 is preferably curved in a plan view. The tip portion 41 connects the ends of the two straight portions 39 in the Y-axis direction, thereby alleviating electric field concentration at the ends of the straight portions 39 .

[0094] In the transistor portion 70, the dummy trench portion 30 is provided between the respective straight line portions 39 of the gate trench portion 40. One dummy trench portion 30 may be provided between the respective straight line portions 39, or a plurality of dummy trench portions 30 may be provided. The dummy trench portion 30 may have a straight line shape extending in the second direction, or may have a straight line portion 29 and a front end portion 31 similarly to the gate trench portion 40. Figure 2 The semiconductor device 100 shown includes both a linear dummy trench portion 30 having no front end portion 31 and a dummy trench portion 30 having a front end portion 31 .

[0095] The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 in a plan view. That is, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. Thus, the electric field concentration at the bottom of each trench portion can be alleviated.

[0096] A mesa portion 60 is provided between each groove portion in the first direction. The mesa portion 60 refers to an area clamped by the groove portion inside the semiconductor substrate 10. As an example, the upper end of the mesa portion 60 is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of the groove portion. The mesa portion 60 of this example is arranged to extend along the groove in the second direction (Y-axis direction) on the upper surface of the semiconductor substrate 10. The mesa portion 60 of the transistor portion 70, the mesa portion 60 of the diode portion 80, and the mesa portion 60 of the boundary region 200 may have different structures. In the case of simply referring to the mesa portion 60 in this specification, it refers to the mesa portion 60 of each transistor portion 70, the mesa portion 60 of the diode portion 80, and the mesa portion 60 of the boundary region 200.

[0097] The base region 14 is provided in each mesa portion 60. Of the base region 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion 60, a region that is disposed closest to the active-side gate wiring 131 is referred to as a base region 14-e. Figure 2 In the figure, a base region 14-e is shown as being arranged at the end of one side in the second direction of each mesa portion, but a base region 14-e is also arranged at the end of the other side of each mesa portion. In each mesa portion, at least one of an emitter region 12 of a first conductivity type and a contact region 15 of a second conductivity type can be arranged in the region sandwiched by the base region 14-e when viewed from above. The emitter region 12 in this example is of N+ type, and the contact region 15 is of P+ type. The emitter region 12 and the contact region 15 can be arranged between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0098] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided to be in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0099] The contact regions 15 and emitter regions 12 in the mesa portion 60 are respectively arranged from the groove portion on one side to the groove portion on the other side in the X-axis direction. As an example, the contact regions 15 and emitter regions 12 of the mesa portion 60 are alternately arranged along the second direction (Y-axis direction) of the groove portion.

[0100] In other examples, the contact region 15 and the emitter region 12 of the mesa portion 60 may be arranged in stripes along the second direction (Y-axis direction) of the groove portion. For example, the emitter region 12 is arranged in the region connected to the groove portion, and the contact region 15 is arranged in the region sandwiched by the emitter region 12.

[0101] The emitter region 12 is not provided in the mesa portion 60 of the diode portion 80 and the boundary region 200. The base region 14 and the contact region 15 may be provided on the upper surface of the mesa portion 60 of the diode portion 80 and the boundary region 200. The contact region 15 may be provided in the region of the upper surface of the mesa portion 60 sandwiched by the base region 14-e in a manner connected to each base region 14-e. The base region 14 may be provided in the region of the upper surface of the mesa portion 60 of the diode portion 80 sandwiched by the contact region 15. The base region 14 may be arranged in the entire region sandwiched by the contact region 15. The mesa portion 60 of the boundary region 200 may have the same structure as the mesa portion 60 of the diode portion 80, or may have a different structure from the mesa portion 60 of the diode portion 80. The mesa portion 60 of the boundary region 200 of this example is provided with the contact region 15 in the entire region sandwiched by the base region 14-e. That is, the area of ​​the contact region 15 of the mesa portion 60 of the boundary region 200 may be larger than the area of ​​the contact region 15 of the mesa portion 60 of the diode portion 80. In this case, holes in the semiconductor substrate 10 are easily extracted to the emitter electrode 52 via the mesa portion 60 of the boundary region 200.

[0102] In other examples, the mesa portion 60 of the boundary region 200 may be a P-type impurity region having a doping concentration equal to or lower than the doping concentration of the base region 14 of the transistor portion 70. The P-type impurity region may occupy the entire mesa portion 60 of the boundary region 200, and other regions may also be provided in the mesa portion 60 of the boundary region 200. By providing a P-type impurity region having a doping concentration lower than the doping concentration of the base region 14 in the mesa portion 60 of the boundary region 200, the injection of holes from the mesa portion 60 of the boundary region 200 can be suppressed, thereby reducing reverse recovery loss.

[0103] In addition, an N-type impurity region having a doping concentration equal to or lower than that of the emitter region 12 may be provided in the mesa portion 60 of the boundary region 200. However, in this case, the gate groove portion 40 is not provided in the boundary region 200. In addition, the groove portion at the boundary between the transistor portion 70 and the boundary region 200 is a dummy groove portion 30. Since the N-type impurity region of the mesa portion 60 of the boundary region 200 is not connected to the gate groove portion 40, a current greater than that of the transistor portion 70 will not flow in the boundary region 200. Thus, the injection of holes from the mesa portion 60 of the boundary region 200 can be suppressed, and the reverse recovery loss can be reduced.

[0104] A contact hole 54 is provided above each mesa portion 60. The contact hole 54 is arranged in a region sandwiched by the base region 14-e. The contact hole 54 of this example is provided above each region of the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 is not provided in a region corresponding to the base region 14-e and the well region 11. The contact hole 54 may be arranged at the center of the mesa portion 60 in the first direction (X-axis direction).

[0105] In the diode portion 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. On the lower surface of the semiconductor substrate 10, a P+ type collector region 22 may be provided in a region where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. Figure 2 In FIG. 8 , the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line.

[0106] The cathode region 82 is configured to be away from the well region 11 in the Y-axis direction. Thus, the distance between the P-type region (well region 11) formed to a deep position with a high doping concentration and the cathode region 82 can be ensured, and the withstand voltage can be improved. The end of the cathode region 82 in the Y-axis direction of this example is configured to be farther away from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In other examples, the end of the cathode region 82 in the Y-axis direction can be configured between the well region 11 and the contact hole 54.

[0107] Figure 3 It is shown Figure 2 The ee cross section is an example of an ee cross section. The ee cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. The semiconductor device 100 of this example includes the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24 in this cross section.

[0108] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one of an insulating film such as silicate glass to which impurities such as boron or phosphorus are added, a thermal oxide film, and other insulating films. Figure 2 The contact hole 54 described in FIG.

[0109] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 contacts the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction. The emitter electrode 52 may have a barrier metal containing titanium in a portion in contact with the upper surface 21 of the semiconductor substrate 10. The barrier metal may have a titanium nitride layer or a stacked structure of a titanium nitride layer and a titanium layer. The emitter electrode 52 may also have a plug portion of tungsten or the like filled in the contact hole 54. The plug portion may also be provided in a trench contact portion described later.

[0110] The semiconductor substrate 10 has an N-type or N-type drift region 18 . The drift region 18 is provided in each of the transistor portion 70 , the diode portion 80 , and the boundary region 200 .

[0111] In this example, the plurality of mesa portions 60 include a first mesa portion 61, a second mesa portion 62, a third mesa portion 63, and a fourth mesa portion 64. The first mesa portion 61 and the second mesa portion 62 are provided in the transistor portion 70, the third mesa portion 63 is provided in the diode portion 80, and the fourth mesa portion 64 is provided in the boundary region 200.

[0112] In the first mesa portion 61 and the second mesa portion 62 of the transistor portion 70, an N+ type emitter region 12 and a P type base region 14 are sequentially provided from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region 16 may be provided in the first mesa portion 61 and the second mesa portion 62. The accumulation region 16 is arranged between the base region 14 and the drift region 18.

[0113] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0114] The base region 14 is provided below the emitter region 12. The base region 14 of this example is provided to be in contact with the emitter region 12. The base region 14 may be in contact with the groove portions on both sides of the first mesa portion 61 and the second mesa portion 62.

[0115] The accumulation region 16 is disposed below the base region 14. The accumulation region 16 is an N+ type region having a higher doping concentration than the drift region 18. That is, the donor concentration of the accumulation region 16 is higher than that of the drift region 18. By providing a high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be increased and the on-state voltage can be reduced. The accumulation region 16 can be disposed to cover the entire lower surface of the base region 14 in the first terrace portion 61 and the second terrace portion 62.

[0116] In the third terrace portion 63 of the diode portion 80, a P-type base region 14 is provided in contact with the upper surface 21 of the semiconductor substrate 10. In this specification, the base region 14 of the third terrace portion 63 is sometimes referred to as an anode region. The doping concentration of the base region 14 of the third terrace portion 63 may be the same as the doping concentration of the base region 14 of the first terrace portion 61 and the second terrace portion 62, or may be lower than the doping concentration of the base region 14 of the first terrace portion 61 and the second terrace portion 62. A drift region 18 is provided below the base region 14. In the third terrace portion 63, an accumulation region 16 may be provided below the base region 14.

[0117] In the fourth terrace portion 64 of the boundary region 200 of this example, a P+ type contact region 15 is provided in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the contact region 15. A base region 14 may be provided between the contact region 15 and the drift region 18. In the fourth terrace portion 64, an accumulation region 16 may be provided below the base region 14.

[0118] In each transistor portion 70, diode portion 80 and boundary region 200, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have a concentration peak having a higher doping concentration than the doping concentration of the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. In addition, the doping concentration of the drift region 18 may use the average value of the doping concentration in a region where the doping concentration distribution is almost flat.

[0119] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peak of the buffer region 20 may be set at the same depth position as, for example, a chemical concentration peak of hydrogen (protons) or phosphorus. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0120] In the transistor portion 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14 or may contain an acceptor different from the base region 14. The acceptor of the collector region 22 is, for example, boron.

[0121] In the diode portion 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. It should be noted that the elements that serve as donors and acceptors in each region are not limited to the above examples.

[0122] In the boundary region 200, a collector region 22 of P+ type is provided below the buffer region 20. The collector region 22 of the boundary region 200 may have the same doping concentration as that of the boundary region 200 of the transistor portion 70. The boundary position between the cathode region 82 and the collector region 22 in the X-axis direction may be set as the boundary position between the diode portion 80 and the boundary region 200 in the X-axis direction. In other examples, in the boundary region 200, a part or all of the collector region 22 may be replaced with the cathode region 82. In the case where the cathode region 82 is provided on the lower surface of the boundary region 200, the region where the contact region 15 and the base region 14 are alternately arranged in the region sandwiched by the base region 14-e may be set as the diode portion 80, and the region where the contact region 15 is arranged in the entire region sandwiched by the base region 14-e may be set as the boundary region 200. In the case where the cathode region 82 is provided on the lower surface of the boundary region 200, the boundary region 200 may also be regarded as a part of the diode portion 80.

[0123] The gate groove portion 40 that is connected to the emitter region 12 and is closest to the diode portion 80 in the X-axis direction is set as the boundary position between the transistor portion 70 and the boundary region 200 (or the diode portion 80) in the X-axis direction. The center position of the gate groove portion 40 in the X-axis direction can be set as the boundary position between the transistor portion 70 and the boundary region 200 (or the diode portion 80) in the X-axis direction. Of the two groove portions that are connected to the emitter region 12 that is closest to the diode portion 80 in the X-axis direction, the groove portion on the diode portion 80 side can be a dummy groove portion 30. The dummy groove portion 30 in this case can be set as the boundary position between the transistor portion 70 and the boundary region 200 (or the diode portion 80) in the X-axis direction.

[0124] The emitter region 12 may also be provided in the boundary region 200. However, in this case, the gate groove portion 40 is not provided in the boundary region 200. In addition, the groove portion at the boundary position between the transistor portion 70 and the boundary region 200 is a dummy groove portion 30. That is, no transistor operation occurs in the boundary region 200. The gate groove portion 40 may also be provided in the boundary region 200. However, in this case, the emitter region 12 is not provided in the boundary region 200. That is, no transistor operation occurs in the boundary region 200.

[0125] The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0126] One or more gate groove portions 40 and one or more dummy groove portions 30 are provided on the upper surface 21 side of the semiconductor substrate 10. Each groove portion is provided to penetrate the base region 14 from the upper surface 21 of the semiconductor substrate 10 and reach below the base region 14. In the region where at least any one of the emitter region 12, the contact region 15 and the storage region 16 is provided, each groove portion also penetrates these doping regions. The groove portion penetrating the doping region is not limited to the sequence of forming the groove portion after the doping region is formed. The case where the doping region is formed between the groove portions after the groove portions are formed is also included in the case where the groove portion penetrates the doping region.

[0127] As described above, the gate trench portion 40 and the dummy trench portion 30 are provided in the transistor portion 70. In this example, the dummy trench portion 30 is provided in the diode portion 80 and the boundary region 200, and the gate trench portion 40 is not provided. However, the gate trench portion 40 or the dummy trench portion 30 may be provided at the boundary between the boundary region 200 and the transistor portion 70.

[0128] It should be noted that the boundary region 200 is a buffer structure for configuring the different structures of the transistor portion 70 and the diode portion 80 in parallel. Therefore, the width of the boundary region 200 in the X-axis direction may also be shorter. For example, the fourth stage portion 64 of the boundary region 200 may be provided over a width of one or several. In another example, the boundary region 200 may not be provided.

[0129] The width of the boundary region 200 in the X-axis direction can be set wider over the plurality of fourth mesa portions 64. This can suppress the influence of the transistor portion 70 on the characteristics of the diode portion 80, for example, the influence of the operation of the gate trench portion 40 and the discharge or injection of holes in the contact region 15 on the forward voltage and reverse recovery characteristics. The number of mesa portions refers to the number of mesa portions arranged in parallel in the X-axis direction.

[0130] The gate trench portion 40 includes a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided in a manner covering the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench at a position further inside than the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0131] The gate conductive portion 44 can be set longer than the base region 14 in the depth direction. The gate groove portion 40 at the cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. If a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an inversion layer of electrons is formed in the surface layer of the interface in the base region 14 that is connected to the gate groove portion 40.

[0132] The dummy groove portion 30 may have the same structure as the gate groove portion 40 in this cross section. The dummy groove portion 30 includes a dummy groove provided on the upper surface 21 of the semiconductor substrate 10, a dummy insulating film 32 and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided in a manner covering the inner wall of the dummy groove. The dummy conductive portion 34 is provided inside the dummy groove and at a position closer to the inner side than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0133] The gate trench 40 and the dummy trench 30 of this example are covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench 30 and the gate trench 40 may be curved surfaces convex downward (curved in cross section).

[0134] The transistor portion 70 includes a first contact portion 211 and a second contact portion 212. The first contact portion 211 is a portion where the first mesa portion 61 and the emitter electrode 52 are in contact. The second contact portion 212 is a portion where the second mesa portion 62 and the emitter electrode 52 are in contact. The second mesa portion 62 is arranged to be farther from the diode portion 80 in the X-axis direction than the first mesa portion 61. That is, in the X-axis direction, the distance between the diode portion 80 and the second mesa portion 62 is greater than the distance between the diode portion 80 and the first mesa portion 61. Similarly, the second contact portion 212 is arranged to be farther from the diode portion 80 in the X-axis direction than the first contact portion 211. That is, in the X-axis direction, the distance between the diode portion 80 and the second contact portion 212 is greater than the distance between the diode portion 80 and the first contact portion 211.

[0135] The semiconductor device 100 may include a lifetime adjustment region 206 including a lifetime inhibitor for adjusting the lifetime of carriers. The lifetime adjustment region 206 in this example is a region where the lifetime of charge carriers is locally short. Charge carriers are electrons or holes. Charge carriers are sometimes simply referred to as carriers. The lifetime adjustment region 206 in this example is formed by injecting charged particles such as helium ions from the upper surface 21 side of the semiconductor substrate 10. In this example, the concentration distribution of helium, etc. in the depth direction of the semiconductor substrate 10 may have a shape such that a tail is drawn from the lifetime adjustment region 206 to the upper surface 21 of the semiconductor substrate 10. That is, the concentration of helium, etc. ( / cm 3 ) may decrease monotonically from the lifetime adjustment zone 206 to the upper surface 21. The concentration of helium, etc. at the upper surface 21 may be greater than 0. On the other hand, in the direction from the lifetime adjustment zone 206 toward the lower surface 23, the concentration of helium, etc. may have a shape such that a tail is drawn. Among them, the concentration of helium, etc. in the tail toward the lower surface 23 decreases more sharply than the concentration of helium, etc. in the tail toward the upper surface 21. The concentration of helium, etc. at the lower surface 23 is lower than the concentration of helium, etc. at the upper surface 21. The concentration of helium, etc. at the upper surface 21 may be below the measurement limit or may be 0. It should be noted that the lifetime adjustment zone 206 may also be formed by injecting charged particles such as helium ions from the lower surface 23 side of the semiconductor substrate 10.

[0136] By injecting charged particles such as helium ions into the semiconductor substrate 10, lattice defects such as vacancies 204 are formed near the injection position. The lattice defects 204 generate recombination centers. The lattice defects 204 can be mainly composed of vacancies such as monoatomic vacancies (V) and diatomic vacancies (VV), and can be dislocations, interstitial atoms, or transition metals. For example, atoms adjacent to the vacancies have dangling bonds. In a broad sense, the lattice defects 204 can also include donors and / or acceptors, but in this specification, the lattice defects 204 mainly composed of vacancies are sometimes referred to as vacancy-type lattice defects, vacancy-type defects, or simply lattice defects. In this specification, the lattice defects 204 are sometimes referred to as recombination centers that help recombination of carriers and are simply referred to as recombination centers or lifetime inhibitors. The lifetime inhibitor can be formed by injecting helium ions into the semiconductor substrate 10. The helium chemical concentration can be used as the density of the lattice defects 204. It should be noted that the lifetime inhibitor formed by implanting helium ions is sometimes terminated by hydrogen present in the buffer region 20, so the depth position of the density peak of the lifetime inhibitor is sometimes inconsistent with the depth position of the helium chemical concentration peak. In addition, when hydrogen ions are implanted into the semiconductor substrate 10, the lifetime inhibitor may be formed in the hydrogen ion passage region closer to the implantation surface than the range.

[0137] Lattice defect 204 is an example of a lifetime inhibitor. Figure 3 The lattice defects 204 at the injection position of the charged particles are schematically shown by the × mark. In the region where a large number of lattice defects 204 remain, carriers are captured by the lattice defects 204, so the lifetime of the carriers is shortened. By adjusting the lifetime of the carriers, the reverse recovery time, reverse recovery loss and other characteristics of the diode portion 80 can be adjusted. In the depth direction of the semiconductor substrate 10, the position where the carrier lifetime presents a minimum value can be set as the depth position of the lifetime adjustment region 206.

[0138] The lifetime adjustment region 206 is arranged on the upper surface 21 side of the semiconductor substrate 10. The upper surface 21 side refers to the region from the center position in the depth direction of the semiconductor substrate 10 to the upper surface 21 of the semiconductor substrate 10. The lifetime adjustment region 206 of this example is arranged below the lower end of the groove portion.

[0139] In addition, when the lifetime adjustment zone 206 is formed by irradiation with a particle beam with high penetrating power such as an electron beam, lattice defects are formed approximately uniformly from the upper surface 21 to the lower surface 23 of the semiconductor substrate 10, but at this time it can also be considered that the depth position of the lifetime adjustment zone 206 is configured on the upper surface 21 side of the semiconductor substrate 10.

[0140] The lifetime adjustment region 206 may be provided in at least one of the transistor portion 70 and the diode portion 80. When the semiconductor device 100 has the boundary region 200, the lifetime adjustment region 206 may also be provided in the boundary region 200. The lifetime adjustment region 206 may be provided in the entire diode portion 80 in the X-axis direction. The lifetime adjustment region 206 may also be provided in the entire boundary region 200.

[0141] The lifetime adjustment zone 206 of the diode section 80 can be set to extend to a part of the transistor section 70 in the X-axis direction. The lifetime adjustment zone 206 of the diode section 80 is set at the same depth position as the lifetime adjustment zone 206 of the transistor section 70. In the transistor section 70, the area where the lifetime adjustment zone 206 is set is set as the adjustment zone 201, and the area where the lifetime adjustment zone 206 is not set is set as the non-adjustment zone 202. The non-adjustment zone 202 is a region where the carrier lifetime at the same depth position as the lifetime adjustment zone 206 is longer than the carrier lifetime of the lifetime adjustment zone 206 of the diode section 80. The non-adjustment zone 202 can also be a region where charged particles such as helium ions are not injected to form lifetime inhibitors such as lattice defects 204. The chemical concentration ( / cm 3 ) can be the same as the chemical concentration of the charged particles at the center of the drift region 18 in the Z-axis direction.

[0142] A life adjustment zone 206 may be provided below at least a portion of the first terrace portion 61 and the first contact portion 211. A life adjustment zone 206 may be provided below a portion of the first terrace portion 61 and the first contact portion 211, or below all of the first terrace portion 61 and the first contact portion 211. A life adjustment zone 206 may be provided below at least a portion of the second terrace portion 62 and the second contact portion 212. A life adjustment zone 206 may be provided below a portion of the second terrace portion 62 and the second contact portion 212, or below all of the second terrace portion 62 and the second contact portion 212.

[0143] The lifetime adjustment region 206 may be provided below the first mesa portion 61 and at least one of the diode portion 80. Figure 3 In the example of FIG. 5 , the lifetime adjustment region 206 is provided below the first mesa portion 61 and in both the diode portion 80 .

[0144] The lifetime adjustment region 206 may be provided below the first mesa portion 61, below the second mesa portion 62, and at least one of the diode portion 80. Figure 3 In the example of FIG. 8 , the lifetime adjustment region 206 is provided below the first mesa portion 61 , below the second mesa portion 62 , and throughout the diode portion 80 .

[0145] The diode portion 80 has a third contact portion 213 for contacting the third mesa portion 63 and the emitter electrode 52. The third contact portion 213 may be provided for a portion of the third mesa portion 63, or for all of the third mesa portion 63. The boundary region 200 has a third contact portion 213 for contacting the fourth mesa portion 64 and the emitter electrode 52. That is, the boundary region 200 has a third contact portion 213 having the same structure as that of the diode portion 80. The third contact portion 213 may be provided for a portion of the fourth mesa portion 64, or for all of the fourth mesa portion 64.

[0146] In this example, each contact portion refers to an interface where the emitter electrode 52 contacts the semiconductor substrate 10. The contact portion may include a surface of the emitter electrode 52 and a surface of the semiconductor substrate 10. In the case where a metal silicide layer is formed at the interface between the emitter electrode 52 and the semiconductor substrate 10, the metal silicide layer may be included in the emitter electrode 52 (metal electrode). That is, the interface between the metal silicide layer and the semiconductor substrate 10 may be set as a contact portion.

[0147] A trench contact portion 17 may be provided in at least a portion of the mesa portion 60. The trench contact portion 17 is a portion where a metal electrode such as the emitter electrode 52 is provided inside the semiconductor substrate 10. A groove is formed in the upper surface 21 of the semiconductor substrate 10 exposed by the contact hole 54, and a metal electrode is filled in the groove to form the trench contact portion 17. In the mesa portion 60 provided with the trench contact portion 17, the region in the trench contact portion 17 where the mesa portion 60 contacts the metal electrode such as the emitter electrode 52 corresponds to the contact portion. Figure 3 In the example of FIG. 1 , the groove contact portion 17 is provided on the first land portion 61 .

[0148] A plug region may be provided in at least a portion of the mesa portion 60 in a region connected to the lower end of the contact portion. The plug region is a P++ type region having a doping concentration higher than that of the contact region 15. Figure 3 In the example of FIG. 1 , a third plug region 223 is provided in contact with the third contact portion 213 .

[0149] Figure 3 The first contact portion 211 of the first mesa portion 61 shown may be provided at a depth shallower than the lower end of the emitter region 12. It should be noted that the first plug region 221 is not provided at the lower end of the first contact portion 211. In other examples, the first contact portion 211 may be provided at a depth reaching the base region 14, or the first plug region 221 may be provided in a manner connected to the lower end of the first contact portion 211.

[0150] Figure 4A FIG. 6 is an enlarged view of the vicinity of the first stage surface 61, the second stage surface 62, and the third stage surface 63. Figure 4AIn the figure, a first stage portion 61, a second stage portion 62, and a third stage portion 63 are shown respectively, and the area between the stage portions is omitted.

[0151] The depth position of the lower end of the first contact portion 211 is set to Z1, the depth position of the lower end of the second contact portion 212 is set to Z2, and the depth position of the lower end of the third contact portion 213 is set to Z3. The lower end of each contact portion refers to the portion configured at the bottom of the interface between the metal electrode and the semiconductor substrate 10. The depth position Z2 is configured at a position higher than the depth position Z1. That is, the depth position Z1 is farther from the upper surface 21 of the semiconductor substrate 10 than the depth position Z2. Figure 4A In the example of , the depth position Z1 is a position below the upper surface 21 of the semiconductor substrate 10, and the depth position Z2 is the same depth position as the upper surface 21 of the semiconductor substrate 10. In another example, the depth position Z2 may be a position between the depth position Z1 and the upper surface 21 of the semiconductor substrate 10. In this case, with the upper surface 21 of the semiconductor substrate 10 as a reference, the depth position Z2 may be a depth less than half of the depth position Z1, or may be a depth less than 1 / 4.

[0152] If there are a large number of holes in the transistor section 70 near the diode section 80, the reverse recovery loss of the diode section 80 increases, and the forward voltage decreases. In the semiconductor device 100 of this example, the depth position Z1 of the first contact section 211 is made deeper than the depth position Z2 of the second contact section 212. Thus, a part of the contact region 15 provided in the first terrace section 61 is removed. Therefore, the holes injected from the first terrace section 61 into the drift region 18 can be reduced. In addition, by deepening the first contact section 211, it is easy to extract holes from the semiconductor substrate 10 to the emitter electrode 52 in the first terrace section 61. Therefore, the reverse recovery loss of the diode section 80 can be reduced, and the forward voltage can be increased.

[0153] Among the mesa portions 60 of the transistor portion 70, one or more mesa portions 60 closest to the diode portion 80 may be the first mesa portion 61, and the remaining mesa portions 60 may be the second mesa portion 62. In the transistor portion 70, two or more mesa portions 60 close to the diode portion 80 may be the first mesa portion 61. In the transistor portion 70, the number of the first mesa portions 61 may be less than the number of the second mesa portions 62, may be more than the number of the second mesa portions 62, or may be the same number. The depth position Z1 of the first contact portion 211 may be shallower than the emitter region 12, or may be deeper than the emitter region 12.

[0154] The lower end of the third contact portion 213 of this example is arranged at a position higher than the first contact portion 211. The depth position Z3 of the third contact portion 213 may be the same as the depth position Z2 of the second contact portion 212, or the depth position Z3 of the third contact portion 213 may be arranged between the depth position Z2 and the depth position Z1. In addition, the depth position Z3 of the third contact portion 213 may be the same as the depth position Z1 of the first contact portion 211.

[0155] The third mesa portion 63 is provided in contact with the lower end of the third contact portion 213, and may include a P++ type third plug region 223 having a doping concentration higher than that of the base region 14 (anode region). The doping concentration of the third plug region 223 may be higher than that of the contact region 15. The doping concentration of the base region 14 (anode region) of the third mesa portion 63 may be lower than that of the base region 14 of the transistor portion 70. In this case, the injection of holes from the third mesa portion 63 into the drift region 18 can be suppressed.

[0156] By irradiating the upper surface 21 with charged particles, a lifetime adjustment region 206 is formed in the adjustment region 201 (see Figure 3 ). On the other hand, there is a case where an energy level is formed in the gate insulating film 42 of the adjustment region 201 by irradiation with charged particles, and the threshold voltage (on voltage, off voltage) in the adjustment region 201 is lower than the threshold voltage in the non-adjustment region 202. If the threshold voltage is lowered, the turn-off timing is delayed, so the turn-off of the adjustment region 201 is delayed compared to the non-adjustment region 202, and there is a case where the current is concentrated in the adjustment region 201 and the tolerance is reduced.

[0157] In the case where the transistor portion 70 is provided with the adjustment region 201 and the non-adjustment region 202, at least one first mesa portion 61 may be arranged in the adjustment region 201, and at least one second mesa portion 62 may be arranged in the non-adjustment region 202. All mesa portions 60 in the adjustment region 201 may be the first mesa portion 61. Thus, in the adjustment region 201, holes are easily extracted from the semiconductor substrate 10 to the emitter electrode 52. Therefore, even if the current is concentrated in the adjustment region 201, the reduction in tolerance can be suppressed. All mesa portions 60 in the non-adjustment region 202 may be the second mesa portion 62.

[0158] Figure 4B FIG. 6 is an enlarged view of the vicinity of the first stage surface 61, the second stage surface 62, and the third stage surface 63. Figure 4B In FIG. 6 , a first stage portion 61 , a second stage portion 62 , and a third stage portion 63 are respectively shown, and the area between the stage portions is omitted. Figure 4B and Figure 4AThe difference lies in that a barrier metal portion 252 is provided in the first contact portion 211 , the second contact portion 212 , and the third contact portion 213 , and an accumulation region 16 is provided on the lower surface of the base region 14 of the first mesa portion 61 and the second mesa portion 62 .

[0159] The emitter electrode 52 (metal electrode) of this example includes a barrier metal portion 252 and an upper portion 251. The barrier metal portion 252 is provided above the upper surface 21 of the semiconductor substrate 10. The barrier metal portion 252 is provided at least on the bottom surface of the contact hole 54 or the trench contact portion 17. The barrier metal portion 252 may be provided at the lower end of each contact portion. The barrier metal portion 252 may be in contact with the semiconductor substrate 10. The barrier metal portion 252 may also be provided on the side of the contact hole 54 and the trench contact portion 17. The barrier metal portion 252 may be provided on the upper surface of the interlayer insulating film 38, or may not be provided on the upper surface of the interlayer insulating film 38.

[0160] The barrier metal portion 252 is formed of a material having a higher hydrogen storage property than the upper portion 251. Thus, hydrogen ions are prevented from invading the semiconductor substrate 10. The barrier metal portion 252 of this example includes titanium. The barrier metal portion 252 may include a titanium nitride layer. The barrier metal portion 252 may also be a stacked film of a titanium layer and a titanium nitride layer.

[0161] The upper portion 251 is arranged above the barrier metal portion 252. The upper portion 251 is also arranged above the interlayer insulating film 38. The upper portion 251 is formed of a material different from the barrier metal portion 252. The upper portion 251 of this example does not contain titanium. As an example, the upper portion 251 contains aluminum. The upper portion 251 can be an alloy of aluminum and silicon. The upper portion 251 inside the contact hole 54 or the trench contact portion 17 can include a plug portion composed of tungsten or the like, and the plug portion can also be arranged above the interlayer insulating film 38. In addition, in this example, by providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be improved and the on-voltage can be reduced. Figure 4B and Figure 4A The difference is that the barrier metal portion 252 is provided. When the barrier metal portion 252 is provided as in this example, the same Figure 4A Same effect.

[0162] Figure 5 It is shown Figure 2 FIG. ff is an example of an ff cross section of FIG. The ff cross section is an XZ plane passing through the contact region 15 and the cathode region 82. In the ff cross section, the contact region 15 is configured to replace Figure 3 The emitter region 12 in the ee section is shown. The other structures are the same as those in the ee section. In the ff section, the structures of the first contact portion 211, the second contact portion 212 and the third contact portion 213 are also the same as those in the ee section.

[0163] The first terrace portion 61 of this example is provided in contact with the lower end of the first contact portion 211 and has a P++ type first plug region 221 having a doping concentration higher than that of the contact region 15. At least a portion of the first plug region 221 is provided so as to overlap with the contact region 15 in a plan view. That is, the first plug region 221 is provided on any XZ cross section passing through the contact region 15. The first plug region 221 may be provided on an XZ cross section passing through the center of the contact region 15 in the Z-axis direction. A portion of the first plug region 221 may also overlap with the emitter region 12 in a plan view. The first plug region 221 may be provided in an end region of the emitter region 12 that is in contact with the contact region 15. The first plug region 221 may not be provided in any XZ cross section passing through the emitter region 12. For example, the first plug region 221 may not be provided on an XZ cross section passing through the center of the emitter region 12 in the Z-axis direction. The entire first plug region 221 may be provided so as to overlap with the contact region 15. In this case, the first plug region 221 does not overlap the emitter region 12 in a plan view. The first terrace portion 61 of this example can reduce the high-concentration portion of the contact region 15 by providing the trench contact portion 17, thereby reducing hole injection.

[0164] The second mesa portion 62 of this example is provided in contact with the lower end of the second contact portion 212, and has a P++ type second plug region 222 with a doping concentration higher than that of the contact region 15. At least a portion of the second plug region 222 is provided so as to overlap with the contact region 15 when viewed from above. That is, the second plug region 222 is provided in any XZ cross section passing through the contact region 15. The second plug region 222 may be provided in the XZ cross section passing through the center of the Z-axis direction of the contact region 15. A portion of the second plug region 222 may overlap with the emitter region 12 when viewed from above. The second plug region 222 may be provided in the end region of the emitter region 12 that is in contact with the contact region 15. The second plug region 222 may not be provided in any XZ cross section passing through the emitter region 12. For example, the second plug region 222 may not be provided in the XZ cross section passing through the center of the Z-axis direction of the emitter region 12. The entire second plug region 222 may also be provided to overlap with the contact region 15. In this case, the second plug region 222 does not overlap with the emitter region 12 in a plan view. By providing each plug region, it is easy to extract holes in each mesa portion, thereby suppressing a reduction in tolerance.

[0165] Fig. 6A yes Figure 5 The enlarged view of the vicinity of the first stage surface 61, the second stage surface 62 and the third stage surface 63 is shown. Fig. 6A In the figure, a first stage portion 61, a second stage portion 62 and a third stage portion 63 are shown respectively, and the area between the stage portions is omitted. The structure of the third stage portion 63 is similar to Figure 4A The third terrace portion 63 shown is identical.

[0166] The first surface 61 is relative to Figure 4A The structure shown in FIG. 1 has a contact region 15 instead of the emitter region 12, and has a first plug region 221 in contact with the lower end of the first contact portion 211. Figure 4A The second surface portion 62 is relative to Figure 4A The structure shown in FIG. 1 has a contact region 15 instead of the emitter region 12, and has a second plug region 222 in contact with the lower end of the second contact portion 212. Figure 4A Same as the example.

[0167] The first plug region 221 can be set at a position lower than the second plug region 222. Each plug region is a high-concentration P++ type region. Therefore, if each plug region is arranged near the channel region (the contact portion between the base region 14 and the gate trench portion 40), the acceptor injected into the plug region is easily diffused into the channel region, and the doping concentration of the channel region becomes higher. If the doping concentration of the channel region becomes higher, the threshold voltage increases.

[0168] In this example, the first plug region 221 is formed deeper than the second plug region 222. Therefore, the threshold voltage of the first mesa portion 61 can be relatively increased. Thus, the reduction in the threshold voltage of the first mesa portion 61 caused by the formation of the lifetime adjustment region 206 can be offset.

[0169] The first plug region 221 and the second plug region 222 can be formed by treating the plug region with different doses ( / cm 2 ) is formed by injecting impurities. Thus, the threshold voltage of each mesa portion can be adjusted with higher precision. For example, the difference in dose between the first plug region 221 and the second plug region 222 can be set according to the amount of change in the threshold voltage of the first mesa portion 61 caused by the formation of the lifetime adjustment region 206. Thus, the change in threshold voltage can be offset with high precision. The first plug region 221 and the second plug region 222 can also be formed by injecting impurities with the same dose. In this case, the semiconductor device can be manufactured by a simple process.

[0170] Figure 6B yes Figure 5 The enlarged view of the vicinity of the first stage surface 61, the second stage surface 62 and the third stage surface 63 is shown. Figure 6B In the figure, a first stage portion 61, a second stage portion 62 and a third stage portion 63 are shown respectively, and the area between the stage portions is omitted. The structure of the third stage portion 63 is similar to Figure 4B The third terrace portion 63 shown is identical.

[0171] Figure 6B and Fig. 6AThe difference is that the barrier metal portion 252 is provided in the first contact portion 211, the second contact portion 212, and the third contact portion 213, and the accumulation region 16 is provided on the lower surface of the base region 14 of the first terrace portion 61 and the second terrace portion 62. Even when the barrier metal portion 252 and the accumulation region 16 are provided as in this example, the same Fig. 6A In addition, in this example, since the accumulation region 16 is provided, the carrier injection enhancement effect (IE effect) can be improved and the on-voltage can be reduced.

[0172] Fig. 7A It is shown Fig. 6A 1 is a diagram of an example of doping concentration distribution at line aa and line bb. Line aa is a line parallel to the Z axis passing through the second plug region 222. Line bb is a line parallel to the Z axis passing through the first plug region 221. The first plug region 221 and the second plug region 222 have a first peak 231 and a second peak 232 of doping concentration. The second plug region 222 has a junction 242 of doping concentration at the boundary with the contact region 15. The first plug region 221 of this example does not have a valley of doping concentration at the boundary with the contact region 15, but may have a junction that becomes a valley.

[0173] The dose of the second plug region 222 is set to D2, and the dose of the first plug region 221 is set to D1. The dose D2 can use the value obtained by integrating the doping concentration from the lower end position Z2 of the second contact portion 212 to the joint portion 242 of the doping concentration in the depth direction. Similarly, the dose D1 can use the value obtained by integrating the doping concentration from the lower end position Z1 of the first contact portion 211 to the joint portion 241 of the doping concentration in the depth direction. In the case where there is no valley of doping concentration at the boundary between the first plug region 221 and the contact region 15, the value obtained by integrating the doping concentration from the depth position Z1 over a predetermined depth distance L2 can also be used as the dose D1. The distance L2 is, for example, the distance in the depth direction from the depth position Z2 in the second plug region 222 to the joint portion 242. That is, in the first plug region 221 and the second plug region 222, the value obtained by integrating the doping concentration over the same distance L2 can be used as each dose. In another example, the value obtained by integrating the doping concentration from the lower end position (Z1 or Z2) of each contact portion to the peak (peak 231 or peak 232) of the doping concentration may be used as an index representing each dose. In addition, the doping concentration at the peak (peak 231 or peak 232) of the doping concentration may be used as an index representing each dose.

[0174] As described above, the dose D1 and the dose D2 may be the same. The same doses may allow an error of ±20%, an error of ±10%, or an error of ±5%.

[0175] Figure 7B It is shown Figure 6B FIG. 2 is a diagram of an example of doping concentration distribution at line aa and line bb of FIG. 2. Line aa is a line parallel to the Z axis passing through the second plug region 222. Line bb is a line parallel to the Z axis passing through the first plug region 221. The first plug region 221 and the second plug region 222 have a first peak 231 and a second peak 232 of doping concentration.

[0176] The dose of the second plug region 222 is set to D2, and the dose of the first plug region 221 is set to D1. The dose D2 can use the value obtained by integrating the doping concentration from the lower end position Z2 of the second contact portion 212 to the joint portion 242 of the doping concentration in the depth direction. Similarly, the dose D1 can use the value obtained by integrating the doping concentration from the lower end position Z1 of the first contact portion 211 to the joint portion 241 of the doping concentration in the depth direction. The value obtained by integrating the doping concentration from the depth position Z1 over a predetermined depth distance L2 can also be used as the dose D1. The distance L2 is, for example, the distance in the depth direction from the depth position Z2 in the second plug region 222 to the joint portion 242. That is, in the first plug region 221 and the second plug region 222, the value obtained by integrating the doping concentration over the same distance L2 can be used as each dose. In another example, the value obtained by integrating the doping concentration from the lower end position (Z1 or Z2) of each contact portion to the peak of the doping concentration (the first peak 231 or the second peak 232) can also be used as an index representing the respective doses. In addition, the doping concentration at the peak of the doping concentration (the first peak 231 or the second peak 232) can also be used as an index representing the respective doses. The first contact portion 211, which is the bottom of the trench contact portion 17, is connected to a region in the contact region 15 where the doping concentration is lower than the doping concentration of the second contact portion 212. As a result, compared with the case where the lower end position Z1 of the first contact portion 211 and the lower end position Z2 of the second contact portion 212 are at the same depth, the injection of holes from the first terrace portion 61 is reduced, and the reverse recovery loss becomes smaller. Therefore, by providing the trench contact portion 17 in the first terrace portion 61 of the transistor portion 70, the reverse recovery loss can be reduced.

[0177] As described above, the dose D1 and the dose D2 may be the same. The so-called same dose means that an error of ±20%, an error of ±10%, or an error of ±5% may be allowed. Ion implantation is performed in such a way that the first contact portion 211 and the second contact portion 212 are exposed to form the first plug region 221 and the second plug region 222. The concentration difference of the doping concentration of the contact region 15 of the first contact portion 211 and the second contact portion 212 is sufficiently small compared to the doping concentration of the formed first peak 231 and the second peak 232.

[0178] Fig. 7A and Figure 7B Shows Fig. 6A and Figure 6B This is an example of the doping concentration distribution at the aa line and the bb line of FIG. 1 , but the doping concentration distribution is not limited to this distribution. For example, Fig. 6A The doping concentration distribution at the aa line and bb line can be Figure 7B The doping concentration distribution may also be other doping concentration distributions. Figure 6B The doping concentration distribution at the aa line and bb line can be Fig. 7A The doping concentration distribution may also be other doping concentration distributions.

[0179] Fig. 8A 2 is an enlarged view of the periphery of the first contact portion 211. The barrier metal portion 252 of this example includes a first layer 253 and a second layer 254. The first layer 253 is a titanium layer or a titanium nitride layer provided between the upper portion 251 and the semiconductor substrate 10. The second layer 254 is a titanium nitride layer provided between the first layer 253 and the semiconductor substrate 10.

[0180] The barrier metal portion 252 of the first terrace portion 61 is provided inside the contact hole 54 and the trench contact portion 17. The barrier metal portion 252 may be in contact with the semiconductor substrate 10. The barrier metal portion 252 may further include a silicide layer 255. The silicide layer 255 is formed at a position in contact with the semiconductor substrate 10. The silicide layer 255 is a layer obtained by silicide of a part of the second layer 254. At a position in contact with the semiconductor substrate 10 of the barrier metal portion 252, the second layer 254 may not be completely changed into the silicide layer 255.

[0181] Figure 8B is an enlarged view of the periphery of the second contact portion 212. Fig. 8A Similarly to the example of FIG. 2 , the barrier metal portion 252 includes a first layer 253 and a second layer 254 . In addition, the barrier metal portion 252 may include a silicide layer 255 .

[0182] The barrier metal portion 252 of the second terrace portion 62 is disposed inside the contact hole 54 and the trench contact portion 17. Therefore, the volume is larger than the volume of the barrier metal portion 252 of the first terrace portion 61. The thickness of the barrier metal portion 252 disposed on the side wall of the contact hole 54 of the first terrace portion 61 and the thickness of the barrier metal portion 252 disposed on the side wall of the contact hole 54 of the second terrace portion 62 may be the same. The barrier metal portion 252 of the first terrace portion 61 and the barrier metal portion 252 of the second terrace portion 62 may be formed using the same process.

[0183] Fig. 9A is a diagram showing another example of the ee cross section. In this example, the adjustment region 201 includes two or more first terrace portions 61 arranged in parallel in the X-axis direction. The structure of the trench contact portion 17 of the first terrace portion 61 of the semiconductor device 100 of this example is different from that of other examples described in this specification. The structure other than the trench contact portion 17 of the first terrace portion 61 is the same as any of the methods described in this specification.

[0184] In this example, the groove contact portion 17-2 of at least one first terrace portion 61 is provided at a deeper position than the groove contact portion 17-1 of the first terrace portion 61 disposed at a position closer to the diode portion 80 than the first terrace portion 61. The groove contact portion 17 of each first terrace portion 61 can be formed deeper as it is farther from the diode portion 80. However, the adjustment region 201 may be disposed adjacent to each other in the X-axis direction and include two or more groove contacts 17 of the same depth. With such a structure, the ease of extraction of holes in the adjustment region 201 can be gradually changed.

[0185] In another example, the further away from the diode portion 80, the shallower the trench contact portion 17 of each first terrace portion 61 can be formed. Since the trench contact portion 17 is deeper as it is closer to the diode portion 80, hole injection is likely to occur. In addition, since the diode portion 80 can be set to a concentration lower than the base region 14 of the transistor portion 70, the trench contact portion 17 may not be provided. If the proportion occupied by the trench contact portion 17 is also effective for threshold reduction due to hydrogen storage, the trench contact portion 17 may be provided only in the adjustment region 201 in a manner to compensate for the threshold reduction amount. In addition, the trench contact portion 17 may be provided in a portion of the transistor portion 70 close to the diode portion 80 where the hole injection is low to suppress hole injection. In addition, even if the lifetime adjustment region 206 is not made consistent with the region where the trench contact portion 17 is provided, for example, the entire surface when viewed from above may be used as the lifetime adjustment region 206 and the trench contact portion 17 may be formed locally.

[0186] The depth of each trench contact 17 can also be adjusted according to the density of the lattice defects 204 in the lifetime adjustment zone 206 below. As an example, the thinner the density of the lattice defects 204 arranged below, the shallower the trench contact 17 is formed. Thus, it is easy to offset the change in the threshold voltage. As an example, in the case where the density of the lattice defects 204 is thinner the farther away from the diode part 80, the trench contact 17 can be formed shallower the farther away from the diode part 80. Since the area of ​​the lifetime adjustment zone 206 is smaller than the area of ​​the region where the lifetime adjustment zone 206 does not exist, a planar contact can be provided in the region where the lifetime adjustment zone 206 does not exist, and a trench contact 17 can be provided in the lifetime adjustment zone 206.

[0187] Fig.102 is a diagram showing an example of the arrangement of the adjustment area 201 and the non-adjustment area 202 when viewed from above. Fig.10 In FIG. 8 , two diode units 80 and one transistor unit 70 are shown, and other regions are omitted. Fig.10 In FIG. 1 , the region where the lifetime adjustment region 206 is provided is marked with oblique hatching.

[0188] The adjustment region 201 may be provided in the entire diode section 80 in the X-axis direction. In addition, the adjustment region 201 is also provided in the region in contact with the diode section 80 (or the boundary region 200) in the transistor section 70. The area of ​​the non-adjustment region 202 in the transistor section 70 may be larger than the area of ​​the adjustment region 201. In the non-adjustment region 202, the second contact portion 212 is arranged at a position higher than the first contact portion 211. Therefore, there is a case where the threshold voltage of the non-adjustment region 202 is lower than the threshold voltage of the adjustment region 201. In this case, by increasing the area of ​​the non-adjustment region 202, even if the non-adjustment region 202 is turned off later than the adjustment region 201, the local concentration of current can be suppressed.

[0189] In the transistor portion 70, the second mesa portion 62 (see Figure 3 The number of the first face 61 (refer to Figure 3 The number of the non-adjustment area 202 and the adjustment area 201 is large. Thus, even if the non-adjustment area 202 is turned off slower than the adjustment area 201, the current can be suppressed from being concentrated locally. In the transistor part 70, the threshold voltage of the second mesa part 62 can be lower than the threshold voltage of the first mesa part 61. By adjusting the depth of the groove contact part 17 at the first mesa part 61 and the dose of each plug area, the threshold voltage of each mesa part can be adjusted. It should be noted that the threshold voltage of the mesa part refers to the voltage at which at least one channel region at the mesa part changes from being turned off to being turned on. The groove contact part 17 can also be formed only in the diode part 80. In this case, the threshold reduction caused by the barrier metal can be improved. In addition, the groove contact part 17 can also be formed only in the transistor part 70. In this case, it is effective in the case where the injection is desired to be increased in a resonant type device, etc.

[0190] Fig.11 is a diagram showing another example of the ee cross section. Figure 3 Compared with the structure described in , the lifetime adjustment region 206, the adjustment region 201, the non-adjustment region 202, the first terrace portion 61, and the second terrace portion 62 are arranged differently. The other structures are the same as those of the semiconductor device 100 of any embodiment described in this specification.

[0191] exist Figure 3In the semiconductor device 100 shown, all the mesa portions 60 in the adjustment region 201 are first mesa portions 61, and all the mesa portions 60 in the non-adjustment region 202 are second mesa portions 62. In the semiconductor device 100 of this example, the non-adjustment region 202 includes the first mesa portion 61. The mesa portions 60 in the non-adjustment region 202 other than the first mesa portion 61 are second mesa portions 62. All the mesa portions 60 in the adjustment region 201 may be the first mesa portion 61.

[0192] Among the land portions 60 of the non-adjustment area 202, one or more land portions 60 closest to the adjustment area 201 may be the first land portion 61. Fig.11 In the example of FIG. 1 , in the non-adjustment area 202, the mesa portion 60 closest to the adjustment area 201 is the first mesa portion 61. In other examples, in the non-adjustment area 202, two or more mesa portions 60 closest to the adjustment area 201 may be the first mesa portion 61. In addition, the first mesa portion 61 may be located on the boundary between the adjustment area 201 and the non-adjustment area 202.

[0193] Fig.12 is a diagram showing another example of the ee cross section. Figure 3 Compared with the structure described in the specification, the lifetime adjustment region 206, the adjustment region 201, the non-adjustment region 202, the first terrace portion 61 and the second terrace portion 62 are arranged differently. The other structures are the same as the semiconductor device 100 of any embodiment described in this specification. In the semiconductor device 100 of this example, the adjustment region 201 includes the second mesa portion 62. The mesa portions 60 in the adjustment region 201 other than the second mesa portion 62 are the first mesa portions 61. All the mesa portions 60 in the non-adjustment region 202 may be the second mesa portions 62. Among the mesa portions 60 in the adjustment region 201, one or more mesa portions 60 closest to the non-adjustment region 202 may be the second mesa portion 62. Fig.12 In the example of FIG. 1 , in the adjustment area 201, one mesa portion 60 closest to the non-adjustment area 202 is the second mesa portion 62. In other examples, in the adjustment area 201, two or more mesa portions 60 closest to the non-adjustment area 202 may be the second mesa portion 62. In addition, the second mesa portion 62 may be located on the boundary between the adjustment area 201 and the non-adjustment area 202.

[0194] Fig.13 2 is a diagram showing another example of the ee cross section. The semiconductor device 100 of this example is different from the semiconductor device 100 described in this specification in that it does not have the lifetime adjustment region 206, the adjustment region 201, and the non-adjustment region 202. The other structures are the same as those of any semiconductor device 100 described in this specification. Fig.13 In the figure, it is shown that Figure 3The illustrated structure deletes the lifetime adjustment area 206 , the adjustment area 201 , and the non-adjustment area 202 . However, in the structures illustrated in other figures, the lifetime adjustment area 206 , the adjustment area 201 , and the non-adjustment area 202 may be deleted.

[0195] Fig.14 2 is a diagram showing another example of the ee cross section. The semiconductor device 100 of this example is different from the semiconductor device 100 described in this specification in that the lifetime adjustment region 206 is provided in the entire X-axis direction of the transistor portion 70. The other structures are the same as those of any semiconductor device 100 described in this specification. Fig.14 In the Figure 3 In the illustrated structure, the lifetime adjustment region 206 is arranged in the entire transistor portion 70 . However, in the structures shown in other figures, the lifetime adjustment region 206 may be arranged in the entire transistor portion 70 .

[0196] Fig.15 is a diagram showing another example of the ee cross section. Fig. 9 Compared with the structure described in the specification, the depths of the trench contact portion 17-1 and the trench contact portion 17-2 are different. The other structures are the same as the semiconductor device 100 of any embodiment described in this specification. In this example, the trench contact portion 17-2 of at least one first mesa portion 61 is provided shallower than the trench contact portion 17-1 of the first mesa portion 61 disposed closer to the diode portion 80 than the first mesa portion 61. The trench contact portion 17 of each first mesa portion 61 can be formed shallower as it is farther from the diode portion 80. According to this example, hole injection in the transistor portion 70 near the diode portion 80 can be suppressed, and holes can be easily extracted.

[0197] Fig.16 is a diagram showing another example of the ee cross section. For the semiconductor device 100 of this example, at least one third terrace portion 63 of the diode portion 80 has a trench contact portion 17. All third terrace portions 63 of the diode portion 80 may have a trench contact portion 17. In addition, at least one fourth terrace portion 64 of the boundary region 200 may have a trench contact portion 17. All fourth terrace portions 64 of the boundary region 200 may have a trench contact portion 17. The other structures are the same as those of the semiconductor device 100 of any method described in this specification. Fig.16 In the Figure 3 In the illustrated structure, the third land portion 63 and the fourth land portion 64 have the groove contact portion 17 . However, in the structures shown in other figures, the third land portion 63 and the fourth land portion 64 may also have the groove contact portion 17 .

[0198] The trench contact portion 17 of the third mesa portion 63 may be formed shallower than the trench contact portion 17 of the transistor portion 70, may be formed deeper than the trench contact portion 17 of the transistor portion 70, or may be formed at the same depth as the trench contact portion 17 of the transistor portion 70. The trench contact portion 17 of the fourth mesa portion 64 may be formed shallower than the trench contact portion 17 of the transistor portion 70, may be formed deeper than the trench contact portion 17 of the transistor portion 70, or may be formed at the same depth as the trench contact portion 17 of the transistor portion 70.

[0199] like Fig.16 As shown in FIG. 2 , the lower end of the third contact portion 213 may be disposed at a position lower than the lower end of the second contact portion 212. Figure 3 As shown in FIGS. 1 and 14 , the lower end of the third contact portion 213 may be arranged at the same depth as the lower end of the second contact portion 212 .

[0200] Fig.17 It is an enlarged view of the vicinity of the first terrace portion 61, the second terrace portion 62, and the third terrace portion 63. The emitter electrode 52 of this example does not have a barrier metal portion 252 in the portion in contact with the semiconductor substrate 10. In addition, the first contact portion 211, the second contact portion 212, and the third contact portion 213 do not have a first plug region 221, a second plug region 222, and a third plug region 223. The other structures are the same as those of the semiconductor device 100 of any mode described in this specification. Thus, by providing the trench contact portion 17 in the first terrace portion 61 of the transistor portion 70, the reverse recovery loss can be reduced. As described above, according to this example, the hole injection in the transistor portion 70 near the diode portion 80 can be adjusted, the reduction in tolerance can be suppressed, and the trade-off between the reverse recovery loss and the forward voltage can be adjusted.

[0201] The present invention has been described above using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It can be clearly known from the description of the claims that such changes or improvements can also be included in the technical scope of the present invention.

[0202] It should be noted that the execution order of the actions, sequences, steps, stages, etc. in the devices, systems, programs, and methods shown in the claims, specifications, and drawings can be implemented in any order unless it is specifically stated that "before...", "prior to...", etc., and the output of the previous process is not used in the subsequent process. Even if the action flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, it does not mean that it must be implemented in this order.

Claims

1. A semiconductor device, characterized in that: The device comprises: a semiconductor substrate having an upper surface and a lower surface; a transistor portion provided on the semiconductor substrate; and a diode portion provided on the semiconductor substrate and arranged in parallel with the transistor portion in a first direction, The transistor section and the diode section each include: a metal electrode disposed above the upper surface of the semiconductor substrate; a plurality of groove portions provided from the upper surface of the semiconductor substrate to the inside and arranged in parallel in the first direction; as well as a plurality of mesa portions which are portions of the semiconductor substrate sandwiched by two of the groove portions in the first direction, The transistor unit has: a first contact portion for a first land portion among the plurality of land portions to contact the metal electrode; and a second contact portion for contacting the metal electrode with a second mesa portion of the plurality of mesa portions that is disposed farther from the diode portion than the first mesa portion, The lower end of the second contact portion is arranged above the lower end of the first contact portion.

2. The semiconductor device according to claim 1, wherein: The first face portion has: An emitter region of a first conductivity type exposed on the upper surface of the semiconductor substrate; a contact region of a second conductivity type, which is exposed on the upper surface of the semiconductor substrate; The first plug region of the second conductivity type is disposed in contact with the lower end of the first contact portion and has a doping concentration higher than that of the contact region.

3. The semiconductor device according to claim 2, wherein: The second face portion has: the launch area; said contact area; and a second plug region of the second conductivity type, which is connected to the lower end of the second contact portion and has a doping concentration higher than that of the contact region; The first plug area is disposed at a lower position than the second plug area.

4. The semiconductor device according to claim 3, wherein: The dose of the first plug region is the same as the dose of the second plug region.

5. The semiconductor device according to claim 2, wherein: The first terrace portion has a length in a second direction different from the first direction in a plan view, and the emission areas and the contact areas are alternately arranged along the second direction. The first plug region is disposed in any cross section that is perpendicular to the second direction and passes through the contact region.

6. The semiconductor device according to claim 5, wherein: The first plug region is not provided in any cross section which is perpendicular to the second direction and passes through the emission region.

7. The semiconductor device according to claim 3, wherein: The second terrace portion has a length in a second direction different from the first direction in a plan view, and the emission areas and the contact areas are alternately arranged along the second direction. The second plug region is disposed in any cross section that is perpendicular to the second direction and passes through the contact region.

8. The semiconductor device according to claim 7, wherein: The second plug region is not provided in any cross section which is perpendicular to the second direction and passes through the emission region.

9. The semiconductor device according to claim 1, wherein: The first contact portion includes a trench contact portion in which the metal electrode is disposed inside the semiconductor substrate.

10. The semiconductor device according to claim 1, wherein: A lower end of the second contact portion is disposed on the upper surface of the semiconductor substrate.

11. The semiconductor device according to claim 1, wherein: The diode portion includes a third contact portion for a third mesa portion among the plurality of mesa portions to contact the metal electrode. The lower end of the third contact portion is arranged above the lower end of the first contact portion.

12. The semiconductor device according to claim 1, wherein: The diode portion includes a third contact portion for a third mesa portion among the plurality of mesa portions to contact the metal electrode. The lower end of the third contact portion is arranged below the lower end of the second contact portion.

13. The semiconductor device according to claim 1, wherein: The diode portion includes a third contact portion for a third mesa portion among the plurality of mesa portions to contact the metal electrode. The lower end of the third contact portion is arranged at the same depth position as the lower end of the second contact portion.

14. The semiconductor device according to claim 13, wherein: The third surface has: An anode region of a second conductivity type, which is disposed in contact with the upper surface of the semiconductor substrate; The third plug region of the second conductivity type is connected to the lower end of the third contact portion and has a doping concentration higher than that of the anode region.

15. The semiconductor device according to claim 13, wherein: The mesa portion of the transistor portion has a base region of a second conductivity type, The third mesa portion has an anode region of a second conductivity type, the anode region of the second conductivity type is disposed in contact with the upper surface of the semiconductor substrate, and the doping concentration of the anode region of the second conductivity type is lower than the doping concentration of the base region.

16. The semiconductor device according to any one of claims 1 to 15, characterized in that The semiconductor device further includes a lifetime adjustment region in at least one of the transistor portion and the diode portion, the lifetime adjustment region being arranged on the upper surface side of the semiconductor substrate and including a lifetime suppressor for adjusting a lifetime of carriers.

17. The semiconductor device according to claim 16, wherein: The life adjustment area is arranged below the first stage portion.

18. The semiconductor device according to claim 16, wherein: The lifetime adjustment region is provided below the first mesa portion and at least one of the diode portion.

19. The semiconductor device according to claim 16, wherein: The lifetime adjustment region is provided under the first mesa portion, under the second mesa portion, and at least any one of the diode portion.

20. The semiconductor device according to claim 16, wherein: The transistor unit has: an adjustment region in which the lifetime adjustment region is provided extending from the diode portion; and a non-adjustment zone, which is arranged in parallel with the adjustment zone in the first direction and does not include the life adjustment zone, The first stage portion and the first contact portion are arranged in the adjustment area, The second terrace portion and the second contact portion are arranged in the non-adjustment region.

21. The semiconductor device according to claim 20, wherein: In a plan view, the area of ​​the non-adjustment zone is larger than the area of ​​the adjustment zone.

22. The semiconductor device according to any one of claims 1 to 15, characterized in that In the transistor portion, the number of the second mesa portions is greater than the number of the first mesa portions.

23. The semiconductor device according to any one of claims 1 to 15, characterized in that In the transistor portion, a threshold voltage of the second mesa portion is lower than a threshold voltage of the first mesa portion.

24. The semiconductor device according to claim 9, wherein: The transistor portion includes two or more first mesa portions arranged in parallel in the first direction, The trench contact portion of at least one of the first mesa portions is provided at a deeper position than the trench contact portion of the first mesa portion arranged at a position closer to the diode portion than the first mesa portion.

25. The semiconductor device according to any one of claims 1 to 15, characterized in that The metal electrodes of the first contact portion and the second contact portion include barrier metal, The barrier metal includes titanium.

26. The semiconductor device according to any one of claims 11 to 13, characterized in that The metal electrode of the third contact portion includes a barrier metal, The barrier metal includes titanium.

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