Semiconductor scribing method and semiconductor chip

Abstract

The invention provides a semiconductor scribing method and a semiconductor chip. The semiconductor scribing method is used for a single-axis scribing machine and comprises the following steps: S1, fixing a silicon wafer; s2, cutting the center of the scribing channel of the silicon wafer for the first time in a penetrating manner; s3, cutting a second knife at a first preset distance on one side of the knife edge of the first knife in a penetrating manner; s4, cutting a third knife at a second preset distance on the other side of the knife edge of the first knife in a penetrating manner; and S5, separating the cut silicon wafer to obtain a semiconductor chip. According to the invention, the size of the broken edge of the chip after cutting up can be controlled within a small range, no step exists on the side surface of the chip after cutting up, in addition, the method can be directly carried out on a single-axis scribing machine, and the equipment transformation cost can be saved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor dicing method and a semiconductor chip. Background Art

[0002] Single-axis dicing machines are widely used in silicon wafer cutting due to their simple structure. Figure 1 As shown in the figure, during the cutting process of the single-axis dicing machine, the two sides of the silicon wafer are subjected to tensile stress and compressive stress respectively, and tensile stress is the main cause of defects. The traditional single-axis dicing machine's cutting method of directly penetrating the silicon wafer cannot effectively reduce tensile stress.

[0003] To solve this problem, one improvement method is to imitate the working mode of the dual-axis dicing machine: first use a thick blade to cut a shallow groove on the silicon wafer, and then use a narrow blade to complete the cutting. Although this method can effectively reduce tensile stress and reduce back collapse defects, it requires the use of two dicing machines or the replacement of blades on the same dicing machine, which increases the complexity of the process. In addition, the narrow blade needs to be realigned when cutting the shallow groove left by the thick blade, which increases the risk of alignment deviation and affects the cutting effect.

[0004] In addition, although the dual-axis saw blade can reduce the back chip size, such as Figure 2 As shown, its cost is much higher than that of a single-axis saw. The obvious steps left by the dual-axis saw on the side of the chip also affect the overall appearance of the chip. Summary of the invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a semiconductor dicing method and a semiconductor chip for a single-axis dicing machine, which can control the chip edge collapse size within a small range after dicing and there is no step on the side of the chip after dicing. In addition, the semiconductor dicing method can be directly performed on the single-axis dicing machine, which can save the cost of equipment modification.

[0006] Specifically, the present invention is achieved through the following technical solutions: In a first aspect, the present invention provides a semiconductor dicing method for a single-axis dicing machine, the semiconductor dicing method comprising: step S1, fixing a silicon wafer; step S2, cutting through the center of a scribe line on the silicon wafer with a first knife; step S3, cutting through the center of a scribe line on the silicon wafer with a second knife at a first predetermined distance on one side of the blade of the first knife; step S4, cutting through the center of a scribe line on the other side of the blade of the first knife with a third knife; step S5, separating the cut silicon wafer to obtain semiconductor chips.

[0007] Further, the first predetermined distance is the distance between the center of the blade and the edge of the first blade on the side where the second blade is located when cutting the second blade, and the second predetermined distance is the distance between the center of the blade and the edge of the first blade on the side where the third blade is located when cutting the third blade.

[0008] Furthermore, the first predetermined distance is equal to the second predetermined distance.

[0009] Furthermore, fixing the silicon wafer in step S1 includes: fixing the silicon wafer on a workbench of the single-axis dicing machine by means of a fixing ring and a carrier film.

[0010] Furthermore, in step S2, cutting through the center of the scribe line of the silicon wafer with a first knife includes: scribing the center surface of the scribe line of the silicon wafer, and cutting through the center surface of the scribe line with the first knife according to the scribing path.

[0011] Furthermore, the step S5 of separating the cut silicon wafers includes: placing the cut silicon wafers into a debonding machine for debonding, and then separating the silicon wafers from the carrier film.

[0012] Further, the step S2 is performed before the step S3 and the step S4, and there is no sequence between the step S3 and the step S4.

[0013] Further, the first predetermined distance and the second predetermined distance are both set to be smaller than the size of the semiconductor chip and larger than the thickness of the blade.

[0014] Furthermore, the blade of the single-axis dicing machine is a hard blade with a thickness of 28 μm and an exposed edge amount of 700 μm.

[0015] In a second aspect, the present invention provides a semiconductor chip obtained by the semiconductor dicing method according to any one of the above-mentioned first aspects.

[0016] The present invention provides a semiconductor dicing method and a semiconductor chip. The method first cuts the center of a scribe line of a silicon wafer, and then cuts again near the edge of the first knife. The phenomenon that the narrow side of the material is susceptible to tensile stress is utilized to reduce the size of the chipping edge. The method can control the chipping edge size of the chip after dicing within a relatively small range and there is no step on the side of the chip after dicing. In addition, the method can be directly performed on a single-axis dicing machine, which can save the cost of equipment modification.

[0017] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a schematic diagram of dicing by a single-axis dicing machine; Figure 2 It is a schematic diagram of dicing by a dual-axis dicing machine; Figure 3 is a flow chart of a semiconductor dicing method according to an embodiment of the present invention; Figure 4 is a schematic diagram of a semiconductor dicing method according to an embodiment of the present invention; Figure 5 is a plan view of a semiconductor dicing method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] The semiconductor dicing method of the embodiment of the present invention can be applied to a single-axis dicing machine. A single-axis dicing machine is a key device used in semiconductor packaging technology, mainly used to cut silicon wafers into individual chips. The single-axis dicing machine mainly includes a spindle, a blade, a fixed ring, a carrier film, a workbench, a cutting cooling system, a visual recognition alignment system, and a motion control system. In an embodiment of the present invention, the blade of the single-axis dicing machine can be a hard blade with a thickness of 28 μm and an exposed blade amount of 700 μm. Figures 3 to 5 A semiconductor dicing method according to an embodiment of the present invention will be described.

[0022] Figure 3 is a flow chart of a semiconductor dicing method according to an embodiment of the present invention, Figure 4 Schematic diagram of a semiconductor dicing method according to an embodiment of the present invention. Figure 3 and Figure 4, a semiconductor dicing method according to an embodiment of the present invention may include: step S1, fixing the silicon wafer to be diced (ie, to be cut). Specifically, the silicon wafer to be diced can be fixed on the workbench of the single-axis dicing machine by the fixing ring and the carrying film of the single-axis dicing machine. Among them, the fixing ring of the single-axis dicing machine is mainly used to firmly fix the silicon wafer to be diced on the workbench to ensure that the wafer will not be displaced or vibrated during the cutting process. The fixing ring usually fixes the silicon wafer with tools such as a suction cup or tape. In this way, the accuracy and stability of the cutting process can be guaranteed, and inaccurate cutting or damage caused by the movement of the silicon wafer can be avoided. The role of the carrying film (also called a protective film or tape) in the silicon wafer dicing process is to protect the silicon wafer and the chip from damage. Before cutting, a layer of film will be adhered to the back of the silicon wafer, and this film can stick the chip to the film to keep the grain intact during the cutting process. The carrying film can reduce problems such as edge collapse, displacement and falling during the cutting process. After cutting is completed, the carrier film can also help remove the cut chips from the workbench, facilitating the subsequent packaging and testing process.

[0023] The semiconductor scribing method according to an embodiment of the present invention may further include: step S2, cutting the first knife through the center of the scribing path of the silicon wafer. Specifically, before cutting, the silicon wafer can be scribed first, that is, the central surface of the scribing path of the silicon wafer is scribed, and the first knife is cut through according to the scribing path, and the first knife is obtained. The intersection. For example, in an embodiment of the present invention, a diamond scribing pen can be used to scribing the silicon wafer, and during the scribing process, the diamond scribing pen contacts the surface of the silicon wafer and applies a certain pressure, scribing along a predetermined path to ensure that a sufficiently deep scratch is formed on the surface of the wafer, but not too deep to damage the wafer. In addition, during the cutting process, in order to protect the silicon wafer from external damage, a carrier film will be attached to the wafer in advance. Due to the large friction during cutting, deionized water should be sprayed continuously from all directions.

[0024] The semiconductor dicing method according to an embodiment of the present invention may further include: step S3, cutting through the second knife at a first predetermined distance d1 on one side of the blade of the first knife; and step S4, cutting through the third knife at a second predetermined distance d2 on the other side of the blade of the first knife. Here, the first predetermined distance d1 is the distance between the center of the blade and the edge of the first knife on the side of the second knife when cutting the second knife, and the second predetermined distance d2 is the distance between the center of the blade and the edge of the first knife on the side of the third knife when cutting the third knife, such as Figure 4As shown. Preferably, the first predetermined distance d1 is equal to the second predetermined distance d2, and both can be set to be smaller than the size of the semiconductor chip and larger than the thickness of the blade, for example, both can be 40 μm. In addition, it should be noted that there is no order between step S3 and step S4, and step S3 can be performed first and then step S4, or step S4 can be performed first and then step S3. However, step S2 must be performed before step S3 and step S4.

[0025] The semiconductor dicing method according to the embodiment of the present invention may further include: step S5, separating the cut silicon wafer to obtain semiconductor chips. Specifically, the cut silicon wafer may be placed in a disintegrator for disintegration, and then the silicon wafer may be separated from the carrier film to obtain semiconductor chips.

[0026] Figure 5 1 is a plan view of a semiconductor dicing method according to an embodiment of the present invention. Figure 5 A specific example of dicing a silicon wafer using the semiconductor dicing method of the present invention is described.

[0027] (1) Take a 4-inch 500 μm thick silicon wafer and fix it in the center of the fixed ring using a film mounter. Figure 5 shown.

[0028] (2) Set the starting point and stepping in the CH1 and CH2 directions respectively, and perform dicing according to the first tool trajectory obtained by scribing.

[0029] (3) Using the upper edge of the first knife as the reference point, set the starting point and stepping distance in the CH1 and CH2 directions respectively, and scribing according to the second knife trajectory obtained by scribing.

[0030] (4) Using the lower edge of the first knife as the reference point, set the starting point and stepping distance in the CH1 and CH2 directions respectively, and scribing according to the third knife trajectory obtained by scribing.

[0031] (5) The fixing ring is taken out from the dicing machine and then placed in a disintegrating machine for disintegration, thereby obtaining separated semiconductor chips.

[0032] From the above, it can be seen that the semiconductor dicing method provided by the present invention reduces the size of the chipping edge by first cutting the first knife in the center of the scribe line of the silicon wafer, and then cutting again near the edge of the first knife respectively, utilizing the phenomenon that the narrow side of the material is susceptible to tensile stress. The chipping edge size of the chip after dicing can be controlled within a smaller range (for example, 10 μm) through the present invention, and there is no step introduced by a dual-axis dicing machine or a method similar to a dual-axis dicing machine on the side of the chip after dicing. In addition, since the invention only changes the dicing method and does not involve upgrading and modification of the equipment, the method can be directly performed on a single-axis dicing machine, which greatly saves the cost of equipment modification and effectively improves the dicing quality.

[0033] In addition, the present invention also provides a semiconductor chip obtained by slicing a silicon wafer using a single-axis dicing machine through a semiconductor dicing method according to an embodiment of the present invention. The semiconductor chip can control the chipping size within a range of 10 μm, and there is no step introduced by the dual-axis dicing machine on the side of the chip.

[0034] In summary, the present invention provides an adjustable capacitor structure and a method for forming the same. By setting multiple electrode layers and multiple metal electrodes conductively connected to the multiple electrode layers in the adjustable capacitor structure, the required capacitance indicators can be integrated into a capacitor, thereby providing a capacitor structure with a small size, high reliability, and adjustable capacitance and withstand voltage. The process for forming the capacitor structure is simple, highly customizable, and highly adaptable.

[0035] In addition, in the present invention, the description with reference to the terms "embodiment", "present embodiment", "another embodiment", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0036] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor dicing method for a single-axis dicing machine, characterized in that: include: Step S1, fixing the silicon wafer; Step S2, performing a first cut through the center of the scribe line of the silicon wafer; Step S3, cutting through with a second knife at a first predetermined distance on one side of the blade of the first knife; Step S4, cutting through with a third knife at a second predetermined distance on the other side of the blade of the first knife; Step S5, separating the cut silicon wafer to obtain semiconductor chips.

2. The semiconductor dicing method according to claim 1, characterized in that: The first predetermined distance is the distance between the center of the blade and the edge of the first blade on the side where the second blade is located when cutting the second blade, and the second predetermined distance is the distance between the center of the blade and the edge of the first blade on the side where the third blade is located when cutting the third blade.

3. The semiconductor dicing method according to claim 2, characterized in that: The first predetermined distance is equal to the second predetermined distance.

4. The semiconductor dicing method according to any one of claims 1 to 3, characterized in that: Fixing the silicon wafer in step S1 includes: fixing the silicon wafer on the workbench of the single-axis dicing machine by means of a fixing ring and a carrier film.

5. The semiconductor dicing method according to claim 4, characterized in that: The step S2 of cutting through the center of the scribe line of the silicon wafer with a first knife includes: scribing the center surface of the scribe line of the silicon wafer, and cutting through the center surface of the scribe line with the first knife according to the scribing path.

6. The semiconductor dicing method according to claim 5, characterized in that: The step S5 of separating the cut silicon wafers includes: placing the cut silicon wafers into a debonding machine for debonding, and then separating the silicon wafers from the carrier film.

7. The semiconductor dicing method according to claim 1, characterized in that: The step S2 is performed before the step S3 and the step S4, and there is no sequence between the step S3 and the step S4.

8. The semiconductor dicing method according to claim 3, characterized in that: The first predetermined distance and the second predetermined distance are both set to be smaller than the size of the semiconductor chip and larger than the thickness of the blade.

9. The semiconductor dicing method according to claim 1, characterized in that: The blade of the single-axis dicing machine is a hard blade with a thickness of 28 μm and an exposed edge amount of 700 μm.

10. A semiconductor chip, characterized in that: The semiconductor chip is obtained according to the semiconductor dicing method according to any one of claims 1 to 9.

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