Method, controller, data access device and electronic device for controlling data access of a host device

Abstract

A method, a controller, a data access device and an electronic device for controlling data access of a host device are provided. The method can include receiving a plurality of host commands from the host device for data access of a medium according to the plurality of host commands, and performing a data access optimization procedure for maintaining correctness of data reception, such as receiving data of the medium to obtain at least one codeword, performing a first low density parity check (LDPC) code decoding operation for a plurality of rows, wherein a portion of the rows are exceptional rows corresponding to punctured variable nodes, finding at least one row satisfying at least one predetermined selection condition for performing at least one second LDPC code decoding operation for the at least one row, performing a plurality of third LDPC code decoding operations for the plurality of rows, and returning error-free data to the host device.

Description

Technical Field

[0001] This invention relates to memory control, and more particularly to a method and related apparatus for data access control of a host device, such as a data access device, a controller within the data access device, and an electronic device comprising the data access device. Background Technology

[0002] Memory devices may include flash memory for storing data, and access management for flash memory is quite complex. For example, a memory device can be a memory card, a solid-state drive (SSD), or an embedded storage device (such as an embedded storage device conforming to the Universal Flash Storage (UFS) specification). When manufacturers attempt to reduce overall costs by using downgraded flash memory dies, certain problems may arise. In particular, the characteristics of downgraded flash memory dies are unstable and prone to data errors, which can lead to a decrease in the overall performance of the memory device. Related technologies attempt to address this issue; however, they may introduce additional problems such as side effects. For example, in the event of an uncorrectable error, employing stronger data processing mechanisms to attempt data recovery may take a considerable amount of time. Therefore, a novel approach and related architecture are needed to address these problems without introducing side effects or in a way that is unlikely to introduce side effects. Summary of the Invention

[0003] One of the objectives of this invention is to provide a method and related equipment, such as a data access device, a controller within the data access device, and an electronic device including the data access device, for performing data access control on a host device, in order to solve the aforementioned problems.

[0004] At least one embodiment of the present invention provides a method for data access control of a host device, wherein the method can be applied to a controller of a data access device. The method may include: receiving a plurality of host commands from the host device for data access to at least one medium based on the plurality of host commands, wherein the data access includes data reception; and performing a data access optimization procedure to maintain the correctness of the data reception. For example, the data access optimization procedure may include: receiving data from the at least one medium to obtain at least one codeword, wherein the at least one codeword comprises multiple column segments; in a first decoding stage, performing multiple first low-density parity-check (LDPC) code decoding operations on the multiple column segments, wherein a portion of the multiple column segments are aberrant column segments corresponding to puncture variable nodes; in a second decoding stage, finding at least one column segment that satisfies at least one predetermined selection condition, and performing at least one second low-density parity-check code decoding operation on the at least one column segment; in a third decoding stage, performing multiple third low-density parity-check code decoding operations on the multiple column segments; and after decoding is completed, transmitting error-free data corresponding to the at least one codeword back to the host device.

[0005] In addition to the methods described above, the present invention also provides a controller for a data access device, wherein the data access device can be used to control data access for a host device. Furthermore, the controller includes a processing circuit, a transmission interface circuit, and a low-density peer-to-peer (LDP) decoding circuit. The processing circuit is used to control the controller according to multiple host commands from the host device, allowing the host device to access at least one medium through the controller. The transmission interface circuit is used to communicate with the host device, and the LDP decoding circuit is used to perform LDP decoding. Moreover, the controller receives the multiple host commands from the host device through the transmission interface circuit within the controller, for data access to the at least one medium according to the multiple host commands, wherein the data access includes data reception. The controller performs a data access optimization procedure to maintain the correctness of the data reception. For example, the data access optimization procedure includes: receiving data from the at least one medium to obtain at least one codeword, wherein the at least one codeword comprises multiple line segments; performing multiple first low-density peer check (LDP) decoding operations on the multiple line segments in a first decoding stage using the LDP decoding circuit, wherein a portion of the multiple line segments are abnormal line segments corresponding to puncture variable nodes; searching for at least one line segment that satisfies at least one predetermined selection condition in a second decoding stage using the LDP decoding circuit, and performing at least one second LDP decoding operation on the at least one line segment; performing multiple third LDP decoding operations on the multiple line segments in a third decoding stage using the LDP decoding circuit; and, after decoding is completed, sending back error-free data corresponding to the at least one codeword to the host device.

[0006] In addition to the methods described above, the present invention also provides a data access device including the controller described above, wherein the data access device includes: the controller for controlling the operation of the data access device.

[0007] In addition to the methods described above, the present invention also provides an electronic device including the aforementioned data access device, wherein the electronic device further includes a host device coupled to the data access device. The host device may include: at least one processor for controlling the operation of the host device; and a power supply circuit coupled to the at least one processor and for providing power to the at least one processor and the data access device.

[0008] The method and related apparatus of this invention ensure that the data access device can operate appropriately under different conditions, and in particular, ensure the correctness of the data. Although the characteristics of degraded flash memory die are unstable, the method and related apparatus of this invention can perform at least one read retry operation to obtain relevant information for soft decoding. For example, the method and related apparatus of this invention can identify at least one row segment that satisfies the above-mentioned at least one predetermined selection condition during the soft decoding process, and perform decoding processing on the at least one row segment with a higher priority, thereby controlling the rapid convergence of relevant decoding parameters to improve the overall decoding speed, so as to significantly improve the overall data access performance in the case of abnormal row segments corresponding to puncture variable nodes. In addition, the method and related apparatus of this invention can solve the problems of related technologies without introducing side effects or by means that are unlikely to introduce side effects. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of an electronic device according to one embodiment of the present invention.

[0010] Figure 2A This is a schematic diagram of a low-density parity check code decoding control scheme according to one embodiment of the present invention.

[0011] Figure 2B Illustration based on an embodiment of the present invention Figure 2A The low-density parity check code decoding control scheme shown involves a barrel shifter.

[0012] Figure 2C Illustration based on an embodiment of the present invention Figure 2B Some implementation details of the barrel shifter are shown.

[0013] Figure 3 Illustration based on an embodiment of the present invention Figure 2A The low-density parity check code decoding control scheme shown here involves a codeword, wherein the codeword may contain a set of channel values.

[0014] Figure 4A Illustration based on an embodiment of the present invention Figure 2A The low-density parity check code decoding control scheme shown involves multiple sign bits.

[0015] Figure 4B Illustration based on an embodiment of the present invention Figure 2A The low-density parity check code decoding control scheme shown involves one sign bit and multiple soft bits.

[0016] Figure 5AIllustration based on an embodiment of the present invention Figure 2A The low-density parity-checking code decoding control scheme shown here involves a parity-checking matrix, one of which is also plotted in the diagram. Figure 5A To facilitate better understanding.

[0017] Figure 5B Illustration based on an embodiment of the present invention Figure 5A The following are several cases of the basic matrix.

[0018] Figure 5C Illustration based on an embodiment of the present invention Figure 5A The diagram shows multiple fundamental matrices within the same position check matrix.

[0019] Figure 5D Illustration based on an embodiment of the present invention Figure 5C The example shown illustrates the case where some of the multiple fundamental matrices are zero matrices.

[0020] Figure 6A Illustration based on an embodiment of the present invention Figure 2A The low-density parity check code decoding control scheme shown refers to the message bits and parity bits within the codeword.

[0021] Figure 6B Illustration based on an embodiment of the present invention Figure 6A The example shown illustrates the case where some of the multiple parsed bits become puncture bits.

[0022] Figure 7 This is a schematic diagram of a rearrangement decoding control scheme according to an embodiment of the present invention for a method of data access control for a host device.

[0023] Figure 8A Illustration based on an embodiment of the present invention Figure 7 The diagram illustrates a workflow of the rearranged decoding control scheme.

[0024] Figure 8B Illustration based on an embodiment of the present invention Figure 8A The following are some implementation details of this workflow.

[0025] Figure 9 According to an embodiment of the present invention, the relationship between the elements in the same-position check matrix and certain rows to be processed in the method is illustrated.

[0026] Figure 10 A schematic diagram of an electronic device involved in the method is illustrated according to an embodiment of the present invention, wherein the electronic device may include a data access device.

[0027] Figure 11A A schematic diagram of an electronic device involved in the method is illustrated according to another embodiment of the present invention, wherein the electronic device may include an optical fiber transceiver.

[0028] Figure 11B A schematic diagram of an electronic device involved in the method is illustrated according to another embodiment of the present invention, wherein the electronic device may include a wired network transceiver.

[0029] Figure 11C A schematic diagram of an electronic device involved in the method is illustrated according to another embodiment of the present invention, wherein the electronic device may include a wireless network transceiver.

[0030] Figure 12 The workflow of a data access optimization procedure according to an embodiment of the present invention is illustrated.

[0031] [Symbol Explanation]

[0032] 10, 11, 11_1~11_3: Electronic devices

[0033] 50: Main unit

[0034] 52: Processor

[0035] 54: Power Supply Circuit

[0036] 58: Transmission Interface Circuit

[0037] 100: Memory device

[0038] 110: Memory controller

[0039] 112: Microprocessor

[0040] 112C: Program Code

[0041] 112M: Read-Only Memory

[0042] 114: Control Logic Circuit

[0043] 114D, 200, 700: Low-Density Parity Check (LDPC) code decoding circuit

[0044] 116: Random Access Memory

[0045] 116AM: Temporary Logic-to-Entity (L2P) Address Mapping Table

[0046] 118: Transmission Interface Circuit

[0047] 120: Non-volatile (NV) memory

[0048] 120C: Memory cells

[0049] 120AM: Global Logical-to-Entity (L2P) Address Mapping Table

[0050] 122-1~122-N E Non-volatile (NV) memory elements

[0051] 205: Channel Value (CV) Memory

[0052] 210: Variable Node Unit (VNU)

[0053] 221, 222: Barrel Shifter (BS) Circuits

[0054] 220, 221_1, 221_2~221_F, 222_1, 222_2~222_F: Barrel shifter (BS)

[0055] 220D: Decoder

[0056] 220S: Shift circuit

[0057] 230: Check Node Unit (CNU)

[0058] 710: Normal row segment processing sub-circuit

[0059] 720: Abnormal row segment processing sub-circuit

[0060] 730: Segment S processing sub-circuit

[0061] 1000: Data access device

[0062] 1000_1: Fiber optic transceiver

[0063] 1000_2: Wired network transceiver

[0064] 1000_3: Wireless network transceiver

[0065] 1010, 1010_1~1010_3: Transmission medium controller

[0066] 1014, 1014_1~1014_3: Transmission medium interface circuit

[0067] a, b: line segment

[0068] B, B 0,0 B 0,1 ~B 0,G-2 B 0,G-1 B 1,0 B 1,1 ~B1,G-2 B 1,G-1 B F-1,0 B F-1,1 ~B F-1,G-2 B F-1,G-1 B 0,0 ~B 0,6 B 1,0 ~B 1,6 B 2,0 ~B 2,6 B 3,0 ~B 3,6 Fundamental matrix

[0069] Bit0, Bit1, Bit2~Bit w-1 : bit

[0070] CH(i): Channel

[0071] CK(0), CK(1)~CK(G - 1): Data block (or "line segment")

[0072] CNT SHIFT : Shift number

[0073] CV: Channel Value

[0074] MR: Memory Region

[0075] Phase(0)~Phase(3): Stages

[0076] P1~P8: Programming Status

[0077] Sign_bit(0)~Sign_bit(2), Sign_bit(j): Sign bit

[0078] Soft_bit(j, k): Soft bit

[0079] Vth: Threshold voltage

[0080] x: Input signal

[0081] x0, x1~x Z-1 Input bits

[0082] y: Output signal

[0083] y0, y1~y Z-1 Output bits

[0084] S11, S12, S21, S211~S213, S213A, S214, S31~S33, S40~S45: Steps Detailed Implementation

[0085] Figure 1 This is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 may include a host device 50 and a memory device 100. The host device 50 may include at least one processor (e.g., one or more processors; collectively referred to as processor 52), a power supply circuit 54, and a transmission interface circuit 58, wherein the processor 52 and the transmission interface circuit 58 may be coupled to each other via a bus and may be coupled to the power supply circuit 54 to obtain power. The processor 52 may be used to control the operation of the host device 50, and the power supply circuit 54 may be used to provide power to the processor 52, the transmission interface circuit 58, and the memory device 100, and output one or more drive voltages to the memory device 100. The memory device 100 may be used to provide storage space to the host device 50, and may obtain the one or more drive voltages from the host device 50 as power for the memory device 100. Examples of the host device 50 may include, but are not limited to, multi-functional mobile phones, tablet computers, wearable devices, and personal computers, such as desktop computers and laptop computers. Examples of memory device 100 may include, but are not limited to: portable memory devices (e.g., memory cards conforming to SD / MMC, CF, MS, or XD specifications, solid-state drives (SSDs)) and different types of embedded memory devices (e.g., embedded memory devices conforming to Universal Flash Storage (UFS) or embedded multi-media card (eMMC) specifications). According to this embodiment, memory device 100 may include a controller, such as memory controller 110, and may further include a non-volatile (NV) memory 120 (referred to as "NV memory"), wherein memory controller 110 is used to access the NV memory 120, and the NV memory 120 is used to store information. The NV memory 120 may include at least one NV memory element (e.g., one or more NV memory elements), such as a plurality of non-volatile (NV) memory elements 122-1, 122-2, ..., and 122-N. E (referred to as "NV memory element"), where "N" E "Can represent a positive integer greater than 1. For example, the NV memory 120 can be a flash memory, and the plurality of NV memory elements 122-1, 122-2, ..., and 122-N E It can be multiple flash memory chips or multiple flash memory dies, but the present invention is not limited thereto.

[0086] like Figure 1As shown, the memory controller 110 may include a processing circuit, such as a microprocessor 112, a storage unit, such as a read-only memory (ROM) 112M, a control logic circuit 114, a random access memory (RAM) 116 (which may be implemented, for example, by static random access memory (SRAM)), and a transmission interface circuit 118, wherein at least some (e.g., some or all) of the above components can be coupled to each other via a bus. The random access memory 116 can be used to provide internal storage space to the memory controller 110 (e.g., to temporarily store information), but the invention is not limited thereto. In addition, the read-only memory 112M in this embodiment is used to store program code 112C, and the microprocessor 112 is used to execute program code 112C to control access to the NV memory 120. Note that program code 112C may also be stored in the random access memory 116 or any type of memory. Furthermore, control logic circuitry 114 can be used to control the NV memory 120. Transmission interface circuitry 118 may conform to one or more communication standards (e.g., Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIe), Embedded Multimedia Card (EMC), or Universal Flash Memory), and may enable memory device 100 to communicate with host device 50 (or its transmission interface circuitry 58) according to these one or more communication standards. Similarly, transmission interface circuitry 58 may conform to these one or more communication standards, and may enable host device 50 to communicate with memory device 100 (or its transmission interface circuitry 118) according to one or more of these communication standards.

[0087] In this embodiment, the host device 50 can indirectly access the NV memory 120 within the memory device 100 by transmitting multiple host commands and corresponding logical addresses to the memory controller 110. The memory controller 110 receives multiple host commands and corresponding logical addresses, and converts each host command into multiple memory operation commands (which can be simply referred to as operation commands). It then uses these operation commands to control the NV memory 120 to read, write / program, etc., memory cells or data pages corresponding to physical addresses within the NV memory 120, where physical addresses can be associated with logical addresses. For example, the memory controller 110 can generate or update at least one logical-to-physical (L2P) address mapping table to manage the relationship between physical addresses and logical addresses. The NV memory 120 can store a global logical-to-physical address mapping table 120AM for the memory controller 110 to control the memory device 100 to access data in the NV memory 120, but the invention is not limited to this.

[0088] For better understanding, the global logic-to-physical address mapping table 120AM may be located in a predetermined region (e.g., a system region) within the NV memory element 122-1, but the invention is not limited thereto. For example, the global logic-to-physical address mapping table 120AM may be divided into multiple local logic-to-physical address mapping tables, and these multiple local logic-to-physical address mapping tables may be stored in NV memory elements 122-1, 122-2, and 122-N. E In particular, the data can be stored in one or more NV memory elements, specifically in NV memory elements 122-1, 122-2 and 122-N respectively. E When needed, the memory controller 110 may load at least a portion (e.g., part or all) of the global logic-to-physical address mapping table 120AM into the random access memory 116 or other memory. For example, the memory controller 110 may load one of the plurality of local logic-to-physical address mapping tables into the random access memory 116 as a temporary logic-to-physical address mapping table 116AM, so that data in the NV memory 120 can be accessed according to the local logic-to-physical address mapping table stored as the temporary logic-to-physical address mapping table 116AM, but the present invention is not limited thereto.

[0089] Furthermore, the aforementioned at least one NV memory element (e.g., the one or more NV memory elements, such as {122-1, 122-2, …, 122-N) EThe NV memory 120 may contain multiple blocks {BLK}, wherein the smallest unit for the memory controller 110 to perform data erasure operations on the NV memory 120 is a block, and the smallest unit for the memory controller 110 to perform data write operations on the NV memory 120 is a page, but the invention is not limited thereto. For example, NV memory elements 122-1, 122-2, ... and 122-N E Any of the NV memory elements 122-n E (symbol "n) E "Can represent the interval [1, N] E The memory controller 110 can access a specific page of a block within the multiple blocks based on a block address and a page address.

[0090] According to some embodiments, the control logic circuit 114 may include a randomization circuit and an error correction code (ECC) circuit (not shown). Figure 1 The randomization circuit can randomize write data (e.g., data to be written to the NV memory 120 during a write / programming operation in response to a write command from the host device 50) and derandomize read data (e.g., data read from the NV memory 120 during a read operation in response to a read command from the host device 50). The error correction code circuit can encode error correction codes for write data and decode error correction codes for read data to protect data and / or perform error correction, but the invention is not limited thereto. For example, the plurality of NV memory elements 122-1, 122-2, ..., and 122-N E This can be implemented using degraded flash memory dies. In this case, error correction code decoding may fail, and in particular, uncorrectable error correction code (UECC) errors are prone to occur. The memory controller 110 can have a more robust read mechanism to avoid the high error rate that may result from using degraded flash memory dies.

[0091] At Figure 1In the illustrated architecture, the control logic circuit 114 may include multiple data processing sub-circuits to provide the aforementioned more robust read mechanism. These multiple data processing sub-circuits may include at least one low-density parity-check (LDPC) code decoding circuit 114D (referred to as the "LDPC code decoding circuit"), such as one or more LDPC code decoding circuits {114D}. The at least one LDPC code decoding circuit 114D can perform access operations on read data buffered in at least one memory region MR to perform related decoding operations to obtain error-free data for transmission back to the host device 50. However, the invention is not limited thereto. According to some embodiments, Figure 1 The architecture shown can be modified. For example, at least some (e.g., some or all) of the plurality of data processing sub-circuits, such as the one or more LDPC code decoding circuits {114D}, can be integrated into at least one other circuit (rather than the control logic circuit 114).

[0092] Figure 2A This is a schematic diagram of an LDPC code decoding control scheme according to one embodiment of the present invention. An LDPC code decoding circuit 200 can be used as an example of the aforementioned at least one LDPC code decoding circuit 114D, but the present invention is not limited thereto. During a read operation on the NV memory 120 in response to a read command from the host device 50, the memory controller 110 can obtain multiple channel values ​​{CV} from the NV memory 120 through at least one channel CH (e.g., one or more channels {CH}, such as multiple channels {CH(i)}), for the multiple data processing sub-circuits to perform correlation processing to obtain error-free data. For example, the memory controller 110 can perform a read optimization procedure to utilize the LDPC code decoding circuit 200 to receive the multiple channel values ​​{CV} from at least one medium, such as the NV memory 120, through channel CH(i) for correlation decoding operations to generate error-free data.

[0093] based on Figure 2AThe LDPC code decoding control scheme shown may include at least one LDPC code decoding circuit 200 corresponding to at least one channel CH, and in particular, may include multiple LDPC code decoding circuits {200} corresponding to the multiple channels {CH(i)} respectively. For example, the LDPC code decoding circuit 200 corresponding to channel CH(i) among the plurality of LDPC code decoding circuits {200} may include a volatile memory, such as a channel value (CV) memory 205, and a column-segment processing sub-circuit. This column-segment processing sub-circuit may include a variable node unit (VNU) 210, a plurality of barrel shifter (BS) circuits 221 and 222, and a check node unit (CNU) 230 (labeled "CV memory", "VNU", "BS circuit", and "CNU" respectively for brevity). Assuming "F" can represent a positive integer greater than one, the barrel shifter circuit 221 may include a set of barrel shifters {221_1, 221_2, …, 221_F} (labeled "BS_F") along the path from the variable node unit 210 to the check node unit 230. V2C (For simplicity), and the barrel shifter circuit 222 may include a set of barrel shifters {222_1, 222_2, …, 222_F} (labeled "BS_") on the path from the check node unit 230 to the variable node unit 210. C2V (In order to be concise).

[0094] To better understand, the channel value memory 205 can be implemented using at least one memory region MR (e.g., one or more memory regions {MR}). In particular, the channel value memory 205 can be implemented as the memory region MR corresponding to channel CH(i) among the plurality of memory regions {MR} in the random access memory 116 corresponding to the plurality of channels {CH(i)}, but the invention is not limited thereto. According to some embodiments, the channel value memory 205 can be implemented using dedicated memory (e.g., other random access memory).

[0095] Figure 2B Illustration based on an embodiment of the present invention Figure 2AThe LDPC code decoding control scheme shown involves a barrel shifter 220. The barrel shifter 220 can be an example of any one of the barrel shifters {221_1, 221_2, …, 221_F}, or an example of any one of the barrel shifters {222_1, 222_2, …, 222_F}. Assuming "Z" represents a positive integer greater than one, the barrel shifter 220 can be configured according to a shift number CNT. SHIFT CNT is performed on an input signal x with Z bits. SHIFT A shift operation is used to generate an output signal y with Z bits, but the invention is not limited thereto. For example, the shift number CNT SHIFT It can be an integer greater than or equal to zero. When CNT SHIFT When x = 0, the barrel shifter 220 can directly output the Z bits of the input signal x as the Z bits of the output signal y, making the output signal y equivalent to the input signal x. Furthermore, the Z bits of the input signal x may include input bits x0, x1, ... and x... Z-1 Furthermore, the Z bits of the output signal y can include output bits y0, y1, ... and y2. Z-1 .

[0096] Figure 2C Illustration based on an embodiment of the present invention Figure 2B Some implementation details of the barrel shifter 220 are shown. The barrel shifter 220 may include a decoder 220D and a shift circuit 220S. The decoder 220D can be adjusted according to the shift amount CNT. SHIFT Multiple shift control signals are generated to control multiple shift sub-circuits within the shift circuit 220S to perform corresponding shift operations. The shift circuit 220S (or the multiple shift sub-circuits within it) can adjust the input bits x0, x1, ..., x according to the multiple shift control signals. Z-1 Perform these corresponding shift operations to produce output bits y0, y1, ... and y2. Z-1 However, the present invention is not limited thereto. According to certain embodiments, Figure 2C The architecture and / or related operations shown may be changed.

[0097] Figure 3 Illustration based on an embodiment of the present invention Figure 2AThe LDPC code decoding control scheme shown here involves a codeword, wherein the codeword may contain a set of channel values ​​{CV} from the above plurality of channel values ​​{CV}. For example, suppose “G” can represent a positive integer greater than one and the total number of bits of the codeword can be equal to N. The N bits of this set of channel values ​​{CV} can be divided into G data chunks CK(0), CK(1), ... and CK(G-1) (each of which can be equal to Z bits in length, if G = (N / Z)) for LDPC code decoding. When any of the multiple LDPC code decoding operations is implemented by multiple predetermined operations (e.g., a horizontal decoding operation and a vertical decoding operation) of a Min-Sum-Algorithm-based column-layered decoding method, the G data chunks CK(0), CK(1), ... CK(G-1) can be used as G column segments, and therefore can also be called G column segments CK(0), CK(1), ... CK(G-1), but the present invention is not limited thereto. Additionally, the codeword can be configured as w bits per channel value and (Z / w) channel values ​​per column segment (denoted as "w bits per CV; (Z / w) CV per CK" for brevity). Any one of the channel values ​​{CV} in this set of channel values ​​{CV} can have w bits, and any one of the G column segments CK(0), CK(1), ..., CK(G - 1) CK(g) (e.g., "g" can represent any integer in the interval [0, (G - 1)]) can have (Z / w) channel values ​​{CV}. For example, when w = 4 and Z = 400, the codeword can be configured as 4 bits per channel value and 100 channel values ​​per column segment (denoted as "4 bits per CV; 100 CV per CK" for brevity).

[0098] Figure 4A Illustration based on an embodiment of the present invention Figure 2A The LDPC code decoding control scheme shown involves multiple sign bits Sign_bit(0), Sign_bit(1), and Sign_bit(2). A set of memory cells 120C within the NV memory 120 can be configured as J-order cells, and any one of these memory cells 120C can be in one of multiple candidate programming states {P}, such as 2. J There are programming states {P1, …, P2} JThe selected programming state P. For example, when J = 3, the group of memory cells 120C can be configured as a third-order cell, and any memory cell in the group of memory cells 120C can be in a programming state P selected from the plurality of candidate programming states {P}, such as 8 programming states {P1, …, P8}, where Figure 4A The lower half of the horizontal axis represents the threshold voltage Vth, and according to some viewpoints, the threshold voltage Vth can be referred to as the read voltage, but the invention is not limited thereto. According to certain embodiments, Figure 4A The multiple candidate programming states {P1, …, P8} shown, and / or the level count J of the group of memory cells 120C, can be varied. For example, the level count J can be equal to any value in a series of values ​​{1, 2, 3, 4, …}.

[0099] like Figure 4A As shown in the upper part, the memory controller 110 can refer to a predetermined encoding rule to encode the 2 J There are programming states {P1, …, P2} J} Such as the 8 programming states {P1, …, P8} associated with 2 J Pre-defined codes, such as the eight pre-defined codes {111, 011, 001, 101, 100, 000, 010, 110}, where the two... J Any one of the predefined codes may contain J sign bits {Sign_bit(j) | j = 0, …, (J - 1)}, such as three sign bits Sign_bit(0), Sign_bit(1), and Sign_bit(2), but the present invention is not limited thereto. According to some embodiments, the predefined encoding rule, the 2 J A reservation code such as Figure 4A The eight predefined codes {111, 011, 001, 101, 100, 000, 010, 110} and / or the order J shown can be varied.

[0100] Figure 4B Illustration based on an embodiment of the present invention Figure 2A The LDPC code decoding control scheme shown involves a sign bit (Sign_bit(j)) and (w - 1) soft bits (Soft_bit(j, k) | k = 1, …, (w - 1)). For example, the w bits of any channel value CV can include bits {Bit0, Bit1, Bit2, …, Bit}. w-1During the read optimization process, the memory controller 110 may perform a first read operation to obtain the sign bit Sign_bit(j) as bit 0, and execute a read retry procedure to perform multiple read retry operations to obtain the (w - 1) soft bits {Soft_bit(j, k) | k = 1, …, (w - 1)} as bits Bit1, Bit2, … and Bit… w-1 The (w - 1) soft bits {Soft_bit(j, k) | k = 1, …, (w - 1)} can indicate how strong or weak the sign bit Sign_bit(j) is as a bit 1 (if Sign_bit(j) = 1) or how strong or weak the sign bit Sign_bit(j) is as a bit 0 (if Sign_bit(j) = 0). According to some views, these soft bits {Soft_bit(j, k) | k = 1, …, (w - 1)} can be used to accurately indicate the position of the programming state P associated with the sign bit Sign_bit(j) on the Vth axis to improve the accuracy of detecting the position of this programming state P on the Vth axis, but the present invention is not limited thereto. For example, when k = 1, the memory controller 110 can perform the first read retry operation to obtain the first soft bit Soft_bit(j, 1); when k = 2, the memory controller 110 can perform the first read retry operation to obtain the first soft bit Soft_bit(j, 2); when k = 3, the memory controller 110 can perform the third read retry operation to obtain the third soft bit Soft_bit(j, 3); when k = 4, the memory controller 110 can perform the fourth read retry operation to obtain the fourth soft bit Soft_bit(j, 4); and so on.

[0101] To better understand, the arrows corresponding to k = 1, k = 2, k = 3, k = 4, etc., can be drawn as follows: Figure 4B The text refers to the operations related to detecting the position of this programming state P on the Vth axis, but the invention is not limited thereto. According to some embodiments, these operations, the relevant detection direction on the Vth axis (e.g., positive or negative direction), and / or the relevant detection position on the Vth axis may be varied.

[0102] Figure 5A Illustration based on an embodiment of the present invention Figure 2A The LDPC code decoding control scheme shown here involves a common alignment check matrix H, in which a fundamental matrix B is also plotted. Figure 5AFor better understanding, the parity check matrix H can contain multiple submatrices of the same size, and these multiple submatrices can be implemented as multiple fundamental matrices {B}, such as the fundamental matrix {{B}. 0,0 B 0,1 , …, B 0,G-2 B 0,G-1}, {B 1,0 B 1,1 , …, B 1,G-2 B 1,G-1}, …, {B F-1,0 B F-1,1 B F-1,G-2 B F-1,G-1 For example, when M = (F * Z) and N = (G * Z), the peer check matrix H can have a size of (M * N) (or have (M * N) elements), and any of the plurality of basis matrices {B}, such as basis matrix B, can have a size of (Z * Z) (or have (Z * Z) elements).

[0103] Figure 5B Illustration based on an embodiment of the present invention Figure 5A The diagram shows several cases of the fundamental matrix B. The fundamental matrix B can be an identity matrix of size Z. Z (For example: a matrix where all elements on the main diagonal are 1 and all other elements are 0), identity matrix I Z An X-cyclically-shifted matrix (e.g., the identity matrix I) Z The matrix is ​​either a matrix obtained by circularly shifting all its elements to the right by a displacement X, or a zero matrix. For example, in case (a), if the fundamental matrix B is equal to the identity matrix I... Z In case (b), if the fundamental matrix B is equal to the X-circularly shifted matrix, then in case (c), if the fundamental matrix B is equal to the zero matrix, then in case (d) the fundamental matrix B is marked as "X" in the pairwise check matrix H; and in case (c), if the fundamental matrix B is equal to the zero matrix, then in case (d) the fundamental matrix B is marked as "-1" in the pairwise check matrix H.

[0104] Figure 5C Illustration based on an embodiment of the present invention Figure 5A The multiple fundamental matrices {{B} within the corresponding check matrix H shown 0,0 B 0,1 B 0,2 B 0,3B 0,4 B 0,5 B 0,6}, {B 1,0 B 1,1 B 1,2 B 1,3 B 1,4 B 1,5 B 1,6},{B 2,0 B 2,1 B 2,2 B 2,3 B 2,4 B 2,5 B 2,6}, {B 3,0 B 3,1 B 3,2 B 3,3 B 3,4 B 3,5 B 3,6}}, where F = 4 and G = 7, but the present invention is not limited thereto. For the sake of simplicity, similar content in this embodiment will not be repeated here.

[0105] Figure 5D Illustration based on an embodiment of the present invention Figure 5C The multiple fundamental matrices {{B} shown 0,0 B 0,1 B 0,2 B 0,3 B 0,4 B 0,5 B 0,6}, {B 1,0 B 1,1 B 1,2 B 1,3 B 1,4 B 1,5 B 1,6}, {B 2,0 B 2,1 B 2,2 B 2,3 B 2,4 B 2,5 B 2,6}, {B 3,0 B 3,1 B 3,2 B 3,3 B 3,4 B 3,5 B 3,6This invention addresses the case where some of the fundamental matrices in the code are zero matrices (labeled "-1" for simplicity), but is not limited to this. For the sake of brevity, similar content will not be repeated in this embodiment.

[0106] Some implementation details of this row-level decoding method based on the least summation algorithm can be further explained below. According to some embodiments, let C be a binary (N, K) LDPC code specified by a parity check matrix H. In the parity check matrix H, any column in a row can be associated with a check node c, and any row in a row can be associated with a variable node v. Let N(c) = {v : H} cv = 1} represents the set of all variable nodes {v} that participate in (or are connected to via the peer check matrix H) the check node c, and let M(v) = {c: H} cv = 1} represents the set of all check nodes {c} associated with (or connected to via the peer check matrix H) the variable node v. Let I v Represents the intrinsic message used for variable node v, and R cv This represents the check-to-variable message conveyed from check node c to variable node v, and it also indicates that L... cv This represents a variable-to-check message passed from variable node v to check node c. Assume that the N bits of the codeword are divided into G groups of equal size {N0, N1, …, N}. G-1}(For example: Figure 3 The G rows shown are CK(0), CK(1), ..., CK(G-1). Therefore, the parity check matrix H can be divided into G block columns. To better understand this, taking at least one set of pseudocode as an example, this row-level decoding method based on minimum summation can include the following operations:

[0107]

[0108] In the "Iterative Decoding" section, the two layers of "For {}" can represent a For-loop, "Iter" can represent an iteration index, "Iter_maximum" can represent a predetermined maximum value of the iteration index Iter, "sgn()" can represent a positive or negative sign, and "α" can represent a scaling factor, but the invention is not limited thereto. According to certain embodiments, the above operations, the related parameters of these operations, and / or the above procedures Eq(1), Eq(2), and Eq(3) can be varied.

[0109] Figure 6A Illustration based on an embodiment of the present invention Figure 2A The LDPC code decoding control scheme shown refers to the message bits and corresponding bits within the codeword. For example, the codeword can be transmitted completely from at least one of the aforementioned media, such as the NV memory 120, so these message bits and corresponding bits can both be considered as transmitted bits, but the invention is not limited thereto. According to some embodiments, it may not be necessary for all bits within the codeword to be transmitted completely from at least one of the aforementioned media, such as the NV memory 120, and some of the operations in the above-described row-level decoding method based on minimum summation can be modified to efficiently obtain error-free data.

[0110] Figure 6B Illustration based on an embodiment of the present invention Figure 6A This illustrates the case where a portion of the multiple corresponding bits become punctured bits. For example, a portion of the bits within the codeword, such as a portion of the corresponding bits of all message bits, can be transmitted completely from at least one medium, such as the NV memory 120. Therefore, both these message bits and the portion of corresponding bits can be considered as transmitted bits. However, due to one or more reasons (e.g., at least one unexpected factor, at least one expected factor, and / or at least one predetermined transmission rule), another portion of the bits within the codeword, such as these punctured bits, is not transmitted from at least one medium, such as the NV memory 120. In this case, assuming all operations in the above-listed operations of the least-sum row-level decoding method are performed, this appears inefficient for certain time-constrained scenarios. For example, the N bits of the codeword can be divided into G groups {N0, N1, …, N G-1} For example, the G rows CK(0), CK(1), ... and CK(G-1), and the same-position check matrix H can be divided into these G blocks, such as Figure 5A The fundamental matrix {B 0,0 B 1,0 , …, B F-1,0 The 0th block row composed of} and the basic matrix {B0,1 B 1,1 , …, B F-1,1 The first block row composed of}, ... and the basic matrix {B 0,G-1 B 1,G-1 , …, B F-1,G-1 The (G-1)th block line formed by} (e.g.: Figure 5C The fundamental matrix {B 0,0 B 1,0 B 2,0 B 3,0 The 0th block row composed of} and the basic matrix {B 0,1 B 1,1 B 2,1 B 3,1 The first block row composed of}, ... and the basic matrix {B 0,6 B 1,6 B 2,6 B 3,6 The sixth block line composed of}, if F = 4 and G = 7), where as shown in the second layer of For-loop corresponding to the loop index g (e.g., g = 0, 1, …, (G - 1)), the row-level decoding method based on minimum summation can include the following for the G groups {N0, N1, …, N} G-1 The relevant LDPC code decoding operations are performed on the G line segments CK(0), CK(1), ..., CK(G-1) (or the G block lines). According to some embodiments, some of the operations in the above-listed operations of the least-sum-based row-level decoding method can be modified; in particular, they can be modified to selectively target one or more groups {N} in at least one iteration. g The corresponding LDPC code decoding operation is performed on the G groups {N0, N1, …, N} (e.g., one or more line segments {CK(g)}), instead of the G groups {N0, N1, …, N}. G-1 All groups {N} in} g Perform all LDPC code decoding operations on all rows {CK(g)} in the G rows CK(0), CK(1), ... and CK(G-1) to efficiently obtain error-free data.

[0111] Figure 7This is a schematic diagram of a rearranged decoding control scheme for a method of data access control for a host device (e.g., host device 50) according to an embodiment of the present invention. An LDPC code decoding circuit 700 can be used as an example of the aforementioned at least one LDPC code decoding circuit 114D, but the invention is not limited thereto. For better understanding, the aforementioned at least one iteration may comprise a single iteration, for example, the second iteration corresponding to Iter = 2, to achieve optimal overall performance, but the invention is not limited thereto. For example, the single iteration may be another iteration corresponding to Iter > 2. In some examples, the aforementioned at least one iteration may comprise multiple iterations.

[0112] based on Figure 7 The rearranged decoding control scheme shown may include at least one LDPC code decoding circuit 700 corresponding to at least one channel CH, and in particular, may include multiple LDPC code decoding circuits {700} corresponding to the multiple channels {CH(i)} respectively. For example, the LDPC code decoding circuit 700 corresponding to channel CH(i) among the multiple LDPC code decoding circuits {700} may include the volatile memory such as the channel value memory 205, and may include multiple row segment processing subcircuits such as a normal row segment processing subcircuit 710, an abnormal row segment processing subcircuit 720, and a row segment s processing subcircuit 730, wherein any one of the multiple row segment processing subcircuits can be used Figure 2A The row segment processing sub-circuit shown in the architecture (which includes variable node unit 210, barrel shifter circuits 221 and 222, and check node unit 230) is used to implement this.

[0113] Compared to Figure 2AThe LDPC code decoding circuit 200 shown can utilize the normal line segment processing sub-circuit 710 and the abnormal line segment processing sub-circuit 720 to perform LDPC code decoding operations on normal line segments and abnormal line segments respectively in the first iteration corresponding to Iter = 1. Furthermore, it can utilize the line segment processing sub-circuit 730 to selectively perform corresponding LDPC code decoding operations on one or more line segments {CK(g)} within the codeword in the second iteration corresponding to Iter = 2, instead of performing all LDPC code decoding operations on all line segments {CK(g)} within the codeword. Additionally, the LDPC code decoding circuit 700 can utilize the normal line segment processing sub-circuit 710 and the abnormal line segment processing sub-circuit 720 to perform LDPC code decoding operations on normal line segments and abnormal line segments respectively in at least one subsequent iteration corresponding to Iter > 2. Since the LDPC code decoding circuit 700 can perform decoding processing on the one or more line segments {CK(g)} with a higher priority in at least one iteration, for example, the second iteration corresponding to Iter = 2, the relevant decoding parameters can converge rapidly to improve the overall decoding speed.

[0114] Figure 8A Illustration based on an embodiment of the present invention Figure 7 The diagram illustrates a workflow of the rearranged decoding control scheme. The LDPC code decoding circuit 700 can, according to... Figure 8A The workflow shown is used to operate, in particular, steps S11 and S12, step S21 and steps S31 to S33 are performed in multiple decoding stages such as stages Phase (1), Phase (2) and Phase (3), wherein stage Phase (1) may correspond to Iter = 1, stage Phase (2) may correspond to Iter = 2, and stage Phase (3) may correspond to Iter > 2, but the invention is not limited thereto.

[0115] In step S11, the LDPC code decoding circuit 700 can utilize the normal row segment processing sub-circuit 710 to process variables that contain (or correspond to) normal variable nodes {v} (e.g., non-puncture variable nodes {v}, such as those corresponding to...). Figure 6B The normal line segments of the message bits and the variable nodes {v} of the corresponding bits are shown, especially the LDPC code decoding operation performed on the normal line segments in the first iteration corresponding to Iter = 1. For example, the v-axis can be plotted on... Figure 6B In the codeword, the direction of the N bits is used to indicate the normal variable node {v} in all variable nodes {v}.

[0116] In step S12, the LDPC code decoding circuit 700 can utilize the abnormal line segment processing sub-circuit 720 to process nodes {v} containing (or corresponding to) any puncture variable nodes (e.g., those corresponding to...). Figure 6B The abnormal segments of the variable nodes {v} of the puncture bits shown are particularly important in the first iteration corresponding to Iter = 1, where LDPC code decoding is performed on the abnormal segments. For example, the v-axis can be plotted on... Figure 6B In the codeword, along the direction of the N bits of the codeword, the aforementioned piercing variable node {v} in all variable nodes {v} is indicated.

[0117] In step S21, the LDPC code decoding circuit 700 can use the row segment s processing sub-circuit 730 to find at least one row segment s that satisfies at least one predetermined selection condition to process the at least one row segment s. In particular, in the second iteration corresponding to Iter = 2, the corresponding LDPC code decoding operation is selectively performed on the at least one row segment s, such as the one or more row segments CK(g)}, instead of performing all LDPC code decoding operations on all row segments {CK(g)} in the codeword.

[0118] In step S31, the LDPC code decoding circuit 700 can utilize the normal row segment processing sub-circuit 710 to process the normal variable node {v} (e.g., corresponding to the above-mentioned normal variable node) (e.g., corresponding to the normal row segment processing sub-circuit 710). Figure 6B The normal line segment of the message bits and the variable nodes {v} of the corresponding bits is shown, and in particular, LDPC code decoding operation is performed on the normal line segment in the Iter-th iteration corresponding to Iter > 2.

[0119] In step S32, the LDPC code decoding circuit 700 can utilize the abnormal line segment processing sub-circuit 720 to process nodes {v} containing (or corresponding to) any of the above-mentioned puncture variable nodes (e.g., corresponding to...). Figure 6B The abnormal line segments of the variable nodes {v} of the puncture bits shown are particularly subjected to LDPC code decoding in the Iter-th iteration corresponding to Iter > 2.

[0120] In step S33, the LDPC code decoding circuit 700 determines whether to continue to the next iteration. If yes, proceed to step S31; if no, Figure 8A The illustrated workflow is now complete. For example, the LDPC code decoding circuit 700 can, according to L... v The sign of the code is used to make the hard decision to determine whether any valid codeword has been found. If no valid codeword has been found, the LDPC code decoding circuit 700 can continue to the next iteration until a valid codeword is found or Iter = Iter_maximum.

[0121] To better understand, this method is available Figure 8A The present invention is illustrated by the workflow shown, but is not limited thereto. According to some embodiments, one or more steps may be performed... Figure 8A Add, delete, or modify within the workflow shown.

[0122] Figure 8B Illustration based on an embodiment of the present invention Figure 8A The following are some implementation details of this workflow. Figure 8A The step S21 shown may include multiple sub-steps such as Figure 8B Steps S211 to S213, S213A and S214 are shown, but the invention is not limited thereto. In addition, in the second iteration corresponding to Iter = 2, the set of line segments to be processed φ when step S211 is executed for the first time may include all line segments {CK(g)} in the codeword (e.g., the G line segments CK(0), CK(1), ... and CK(G-1)).

[0123] In step S211, the LDPC code decoding circuit 700 can use the row segment s processing sub-circuit 730 to find a row segment s (e.g., a row segment CK(g)) in the set of row segments to be processed φ that satisfies the above-mentioned at least one predetermined selection condition. The above-mentioned at least one predetermined selection condition includes: for variable node v belonging to set N(c) and variable node v belonging to row segment s, the number of variable nodes {v} with a confidence value of 0 is minimized among all variable nodes {v} except variable node v itself. For example, the above-mentioned at least one predetermined selection condition can be expressed by the following formula:

[0124] ...Eq(4)

[0125] However, the present invention is not limited thereto. According to certain embodiments, the above-described procedure Eq(4) may be varied.

[0126] In step S212, the LDPC code decoding circuit 700 can use the row segment s processing sub-circuit 730 to process the newly found row segment s (e.g., row segment CK(g)), and in particular, perform a corresponding LDPC code decoding operation for the row segment s. For example, the corresponding LDPC code decoding operation may include the horizontal decoding operation (or the horizontal step) and the vertical decoding operation (or the vertical step).

[0127] In step S213, the LDPC code decoding circuit 700 can use the line segment s processing sub-circuit 730 to remove the line segment s from the line segment set φ to update the line segment set φ.

[0128] In step S213A, the LDPC code decoding circuit 700 can use the row segment s processing sub-circuit 730 to check whether the updated set of row segments to be processed φ is an empty set. If yes, proceed to step S31; if no, proceed to step S214.

[0129] In step S214, the LDPC code decoding circuit 700 can use the line segment s processing sub-circuit 730 to check whether all confidence values ​​are not 0. If yes, proceed to step S31; if no, proceed to step S211. For example, the checking operation in step S214 can be represented by the following procedure:

[0130] …………………………Eq(5)

[0131] Where "|Lcn|" can represent the trust value corresponding to the check node c and variable n∈N(c)\v (e.g., variable n belongs to all variable nodes {v} in set N(c) except variable node v itself), but the present invention is not limited thereto. According to some embodiments, the above-described procedure Eq(5) can be varied.

[0132] For a better understanding, relevant details of this method are available. Figure 8B The present invention is illustrated by the workflow shown, but is not limited thereto. According to some embodiments, one or more steps may be performed... Figure 8B Add, delete, or modify steps in the workflow shown. For example, step S213A can be performed in... Figure 8B The process can be deleted from the workflow shown, and the relevant local processes can be modified accordingly. In particular, after executing step S213, step S214 can be directly entered. Typically, in the case of abnormal segments corresponding to puncture variable nodes, the judgment result "yes" in step S214 can be obtained after executing steps S211 and S212 a few times, or even after the first execution of steps S211 and S212. Therefore, deleting step S213A can further improve overall efficiency. For the sake of simplicity, similar content in these embodiments will not be repeated here.

[0133] According to certain embodiments, in the second iteration corresponding to Iter = 2, the second-level For-loop corresponding to the loop index g (e.g., g = 0, 1, …, (G - 1)) can be modified to first select the row segment CK(g) that satisfies at least one of the predetermined selection conditions as the row segment s that satisfies at least one of the predetermined selection conditions (as described in step S211), for the horizontal decoding operation (or the horizontal step) and the vertical decoding operation (or the vertical step) to be performed on the selected row segment CK(g) (or the newly found row segment s), wherein similar operations can be performed until the conditions defined by the square procedure Eq(5) are satisfied. For the sake of brevity, similar content in these embodiments will not be repeated here.

[0134] Figure 9 According to an embodiment of the present invention, the relationship between the elements in the peer checking matrix H and certain rows to be processed (e.g., rows a and b) in the method is illustrated. For example, assuming that "f" can represent any integer in the interval [0, (F - 1)], when Z = 3, in the plurality of basic matrices {B} in the peer checking matrix H, the basic matrix B located in the a-th block row is... f,a It can correspond to row segment a, while the fundamental matrix B located in the next block row, such as the b-th block row, is... f,b This can correspond to row segment b. Additionally, the fundamental matrix B... f,a and B f,b Each fundamental matrix in the matrix can be the identity matrix I. Z (For example: identity matrix I3, when Z = 3), and the set of row segments to be processed φ in step S211 can contain row segments a and b. Assume the number of non-piercing bits of the codeword can be equal to ((a * Z) + 2) (for example: ((3 * a) + 2), when Z = 3), in the fundamental matrix B f,a The first two elements on the main diagonal can be the elements in the same-position check matrix H that correspond to the normal variable nodes and are equal to 1, while in the fundamental matrix B... f,a The third element on the main diagonal and in the fundamental matrix B f,b The three elements on the main diagonal can be elements in the same-position check matrix H corresponding to the puncture variable node and equal to 1, where row segment b satisfies at least one of the above-mentioned predetermined selection conditions, while row segment a does not satisfy at least one of the above-mentioned predetermined selection conditions, but the present invention is not limited thereto. According to some embodiments, the same-position check matrix H, the rows to be processed such as row segments a and b, and / or the size of each row segment can be varied. For the sake of simplicity, similar content in this embodiment will not be repeated here.

[0135] According to certain embodiments, the method can be applied to any of a variety of data access devices, particularly to a controller within any of these data access devices. For example, the at least one medium may include a storage medium such as the NV memory 120, the data access device may represent a memory device 100, and the controller may represent a memory controller 110, but the invention is not limited thereto. In some examples, the at least one medium may include a transmission medium, and the data access device may include one or a combination of an optical transceiver, a wired network transceiver, and a wireless network transceiver.

[0136] Figure 10 A schematic diagram of an electronic device 11 involved in the method is illustrated according to an embodiment of the present invention, wherein the electronic device 11 may include a data access device 1000, which can be an example of any of the aforementioned data access devices. Compared to Figure 1 In the illustrated architecture, the transmission medium controller 1010 and its transmission medium interface circuit 1014 within the data access device 1000 replace the memory controller 110 and its control logic circuit 114. The transmission medium interface circuit 1014 can be used to control the data access device 1000's data access operations on the transmission medium, such as data transmission operations and data reception operations. The transmission medium interface circuit 1014 may include at least one LDPC code decoding circuit 114D as described above. For the sake of simplicity, similar content will not be repeated in this embodiment.

[0137] Figure 11A A schematic diagram of an electronic device 11_1 involved in the method is illustrated according to another embodiment of the present invention, wherein the electronic device 11_1 may include an optical fiber transceiver 1000_1, which can be used as an example of any of the above-mentioned data access devices, or as... Figure 10 The example shown is a data access device 1000. The transmission medium may include an optical fiber cable, wherein the optical fiber cable includes at least one optical fiber. A transmission medium controller 1010_1 of the optical fiber transceiver 1000_1 may include a transmission medium interface circuit 1014_1, which can be used to control the data access operations of the optical fiber transceiver 1000_1 on the optical fiber cable, such as data transmission operations and data reception operations, wherein the transmission medium interface circuit 1014_1 may include the aforementioned at least one LDPC code decoding circuit 114D. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0138] Figure 11BA schematic diagram of an electronic device 11_2 involved in the method is illustrated according to another embodiment of the present invention, wherein the electronic device 11_2 may include a wired network transceiver 1000_2, which can be used as an example of any of the above-mentioned data access devices, or as... Figure 10 The example shown is of a data access device 1000. The transmission medium may include a network cable. A transmission medium controller 1010_2 of the wired network transceiver 1000_2 may include a transmission medium interface circuit 1014_2, which can be used to control the data access operations of the wired network transceiver 1000_2 on the network cable, such as data transmission operations and data reception operations. The transmission medium interface circuit 1014_2 may include at least one LDPC code decoding circuit 114D as described above. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0139] Figure 11C A schematic diagram of an electronic device 11_3 involved in the method is illustrated according to another embodiment of the present invention, wherein the electronic device 11_3 may include a wireless network transceiver 1000_3, which can be used as an example of any of the above-mentioned data access devices, or as... Figure 10 The example shown is a data access device 1000. The transmission medium may include an air medium for transmitting radio waves. A transmission medium controller 1010_3 of the wireless network transceiver 1000_3 may include a transmission medium interface circuit 1014_3, which can be used to control the data access operations of the wireless network transceiver 1000_3 on the air medium, such as data transmission operations and data reception operations. The transmission medium interface circuit 1014_3 may include at least one LDPC code decoding circuit 114D as described above. For simplicity, similar content will not be repeated in this embodiment.

[0140] Figure 12 The flowchart of a data access optimization procedure (e.g., the read optimization procedure) according to an embodiment of the present invention is illustrated. Any of the aforementioned data access devices, such as the memory device 100 for accessing the storage medium, such as the NV memory 120, or the data access device 1000 (e.g., data access devices 1000_1, 1000_2, and 1000_3) for accessing the transmission medium, can receive the plurality of host commands from the host device 50 for data access to at least one of the aforementioned media according to the plurality of host commands, and according to... Figure 12The illustrated workflow is used to perform the data access optimization procedure to maintain the correctness of data reception, wherein the data access may include data reception. For example, when any of the above data access devices represents memory device 100, the plurality of host commands may include at least one read command, and the data reception includes data reading, but the invention is not limited thereto.

[0141] In step S40, any of the above data access devices (e.g., memory device 100 or data access device 1000) can receive data from the above at least one medium through the above at least one channel CH(i) to obtain at least one codeword, wherein the at least one codeword may contain multiple line segments {CK(g)}.

[0142] In step S41, any of the above data access devices (e.g., memory device 100 or data access device 1000) may perform multiple first LDPC code decoding operations on the multiple row segments {CK(g)} in a first decoding stage (e.g., stage Phase(1)), wherein a portion of the multiple row segments {CK(g)} are abnormal row segments corresponding to puncture variable nodes.

[0143] In step S42, any of the above data access devices (e.g., memory device 100 or data access device 1000) may, in a second decoding stage (e.g., stage Phase (2)), search for at least one row segment s (e.g., at least one row segment CK(g)) that satisfies at least one predetermined selection condition, and perform at least one second LDPC code decoding operation on the at least one row segment, without performing any LDPC code decoding operation on at least one other row segment CK(g) among the plurality of row segments {CK(g)}.

[0144] In step S43, any of the above data access devices (e.g., memory device 100 or data access device 1000) may perform multiple third LDPC code decoding operations on the multiple row segments {CK(g)} in a third decoding stage (e.g., stage Phase(3)).

[0145] In step S44, any of the aforementioned data access devices (e.g., memory device 100 or data access device 1000) may check whether decoding is complete in the third decoding stage (e.g., stage Phase (3)). If yes, proceed to step S45; if no, proceed to step S43 to continue decoding.

[0146] In step S45, after decoding is completed, any of the above data access devices (e.g., memory device 100 or data access device 1000) can send back error-free data corresponding to the above at least one codeword to the host device 50.

[0147] Any one of the plurality of first LDPC code decoding operations, the at least one second LDPC code decoding operation, and the plurality of third LDPC code decoding operations can be implemented by the horizontal decoding operation and the vertical decoding operation of the row-level decoding method based on the least sum algorithm. For example, the horizontal decoding operation and the vertical decoding operation belong to the decoding operation for a single row segment CK(g) in one of the plurality of iterations. In addition, the first decoding stage may correspond to a first iteration in the plurality of iterations, the second decoding stage may correspond to a second iteration in the plurality of iterations, and the third decoding stage may correspond to at least one third iteration in the plurality of iterations. In particular, the first iteration is the first iteration in the plurality of iterations (e.g., the first iteration corresponding to Iter = 1), the second iteration is the next iteration after the first iteration (e.g., the second iteration corresponding to Iter = 2), and the aforementioned at least one third iteration is at least one subsequent iteration of the next iteration (e.g., the at least one subsequent iteration corresponding to Iter > 2).

[0148] Any of the above-mentioned data access devices (e.g., memory device 100 or data access device 1000) operating according to this method can achieve fast decoding speed and rapid convergence, thereby significantly improving the overall data access performance in the case of abnormal rows corresponding to puncture variable nodes.

[0149] To better understand, this data access optimization procedure of the method is available. Figure 12 The present invention is illustrated by the workflow shown, but is not limited thereto. According to some embodiments, one or more steps may be performed... Figure 12 The workflow shown can be modified by adding, deleting, or altering steps. For example, step S41 may include the operations of steps S11 and S12, step S42 may include the operations of step S21, and in particular, may include the operations of at least some of the sub-steps of step S21 (e.g., steps S211, S212, S213, and S214), step S43 may include the operations of steps S31 and S32, and step S44 may include the operations of step S33. For the sake of simplicity, similar content in these embodiments will not be repeated here.

[0150] According to some embodiments, the aforementioned at least one predetermined selection condition may include: for a variable node v belonging to a predetermined set of variable nodes N(c) and the variable node v belonging to a row segment s, the number of variable nodes v with a confidence value of 0 is minimized among all variable nodes {v} other than the variable node v itself. Furthermore, any of the aforementioned data access devices (e.g., memory device 100 or data access device 1000) may selectively exit the second decoding stage based on whether a predetermined stopping condition of the second decoding stage is met. In particular, the predetermined stopping condition may include: there are no longer any variable nodes v with a confidence value of 0. For the sake of simplicity, similar content in these embodiments will not be repeated here.

[0151] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

Claims

1. A method for performing data access control for a host device, the method being applied to a controller of a data access device, the method comprising: The host device receives multiple host commands to perform data access on at least one medium according to the multiple host commands, wherein the data access includes data reception; and A data access optimization procedure is performed to maintain the correctness of data reception, wherein the data access optimization procedure includes: The data is received on the at least one medium to obtain at least one codeword, wherein the at least one codeword comprises multiple line segments; In the first decoding stage, multiple first low-density parity check code decoding operations are performed on the multiple line segments, wherein a portion of the multiple line segments are abnormal line segments corresponding to puncture variable nodes; In a second decoding stage, at least one row segment that satisfies at least one predetermined selection condition is found, and at least one second low-density parity check code decoding operation is performed on the at least one row segment. In the third decoding stage, multiple third low-density parity check code decoding operations are performed on the multiple line segments; and After decoding is completed, error-free data corresponding to the at least one codeword is sent back to the host device.

2. The method as described in claim 1, characterized in that, The at least one medium includes a storage medium; and the data access device represents a memory device, and the controller represents a memory controller, wherein the storage medium includes a non-volatile memory, and the non-volatile memory includes at least one non-volatile memory element.

3. The method as described in claim 2, characterized in that, The multiple host commands include at least one read command, and the data reception includes data reading.

4. The method as described in claim 1, characterized in that, The at least one medium includes a transmission medium; and the data access device includes one or a combination of an optical fiber transceiver, a wired network transceiver, and a wireless network transceiver.

5. The method as described in claim 1, characterized in that, The plurality of first low-density parity check code decoding operations, the at least one second low-density parity check code decoding operation, and any one of the plurality of third low-density parity check code decoding operations are implemented by a horizontal decoding operation and a vertical decoding operation of a row-level decoding method based on a minimum summation algorithm.

6. The method as described in claim 5, characterized in that, The horizontal decoding operation and the vertical decoding operation are decoding operations for a single row segment in one iteration of multiple iterations.

7. The method as described in claim 1, characterized in that, The first decoding stage corresponds to a first iteration among a plurality of iterations, the second decoding stage corresponds to a second iteration among the plurality of iterations, and the third decoding stage corresponds to at least a third iteration among the plurality of iterations.

8. The method as described in claim 7, characterized in that, The first iteration is the first iteration among the plurality of iterations, the second iteration is the next iteration after the first iteration, and the at least one third iteration is at least one subsequent iteration of the next iteration.

9. The method as described in claim 1, characterized in that, In the second decoding stage, finding at least one line segment that satisfies the at least one predetermined selection condition, and performing at least one second low-density parity check code decoding operation on the at least one line segment, further includes: In the second decoding stage, at least one row segment that satisfies the at least one predetermined selection condition is searched for, and at least one second low-density parity check code decoding operation is performed on the at least one row segment, without performing any low-density parity check code decoding operation on at least one of the remaining row segments.

10. The method as described in claim 1, characterized in that, At the beginning of the second decoding stage, a set of line segments to be processed includes the plurality of line segments; and in the second decoding stage, finding at least one line segment that satisfies the at least one predetermined selection condition, and performing at least one second low-density parity check code decoding operation on the at least one line segment, further includes: Find a line segment in the set of lines to be processed that satisfies at least one predetermined selection condition; A second low-density parity check code decoding operation is performed on the aforementioned row segment; Remove the line segment from the set of line segments to be processed to update the set of line segments to be processed; as well as Depending on whether a predetermined stopping condition of the second decoding stage is met, the system may selectively exit the second decoding stage.

11. The method as described in claim 10, characterized in that, The at least one predetermined selection condition includes: for a variable node belonging to a predetermined set of variable nodes and the variable node belonging to the row segment, the number of variable nodes with a confidence value of 0 is the smallest among all variable nodes other than the variable node itself.

12. The method as described in claim 11, characterized in that, The predetermined stopping condition includes: there are no longer any variable nodes with a trust value of 0.

13. A controller for a data access device, the data access device being used to perform data access control for a host device, the controller comprising: A processing circuit is used to control the controller according to a plurality of host commands from the host device, so as to allow the host device to access at least one medium through the controller; A transmission interface circuit for communicating with the host device; as well as A low-density parity check code decoding circuit is used to perform low-density parity check code decoding. in: The controller receives the plurality of host commands from the host device through the transmission interface circuit within the controller, for use in performing data access on the at least one medium according to the plurality of host commands, wherein the data access includes data reception; and The controller performs a data access optimization procedure to maintain the correctness of data reception, wherein the data access optimization procedure includes: The data is received on the at least one medium to obtain at least one codeword, wherein the at least one codeword comprises multiple line segments; In a first decoding stage, the low-density parity check code decoding circuit is used to perform multiple first low-density parity check code decoding operations on the multiple row segments, wherein a portion of the multiple row segments are abnormal row segments corresponding to puncture variable nodes. In a second decoding stage, the low-density parity check code decoding circuit is used to find at least one row segment that satisfies at least one predetermined selection condition, so as to perform at least one second low-density parity check code decoding operation on the at least one row segment. In a third decoding stage, the low-density parity check code decoding circuit is used to perform multiple third low-density parity check code decoding operations on the multiple row segments. as well as After decoding is completed, error-free data corresponding to the at least one codeword is sent back to the host device.

14. The controller as claimed in claim 13, characterized in that, The at least one medium includes a storage medium; and the data access device represents a memory device, and the controller represents a memory controller, wherein the storage medium includes a non-volatile memory, and the non-volatile memory includes at least one non-volatile memory element.

15. The controller as claimed in claim 13, characterized in that, The at least one medium includes a transmission medium; and the data access device includes one or a combination of an optical fiber transceiver, a wired network transceiver, and a wireless network transceiver.

16. A data access device comprising the controller of claim 13, the data access device comprising: The controller is used to control the operation of the data access device.

17. The data access apparatus as claimed in claim 16, characterized in that, The at least one medium includes a storage medium; the data access device represents a memory device, and the controller represents a memory controller, wherein the storage medium includes a non-volatile memory, and the non-volatile memory includes at least one non-volatile memory element. The memory device includes: This non-volatile memory is used to store information; as well as The memory controller is coupled to the non-volatile memory and is used to control the operation of the memory device.

18. The data access apparatus as claimed in claim 16, characterized in that, The at least one medium includes a transmission medium; and the data access device includes one or a combination of an optical fiber transceiver, a wired network transceiver, and a wireless network transceiver.

19. An electronic device comprising the data access means of claim 16, and further comprising: The host device is coupled to the data access device, wherein the host device includes: At least one processor is used to control the operation of the host device; and A power supply circuit is coupled to the at least one processor and is used to provide power to the at least one processor and the data access device.

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