HBDIMM-based command processing method and device
By adopting the HBDIMM-based command processing method in the HBDIMM system, the problem of poor system stability caused by increasing the DDR channel is solved, and a combination of high bandwidth and stability is achieved.
Patent Information
- Application Number
- CN202311233525.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-21
- Publication Date
- 2025-03-21
AI Technical Summary
The prior art increases the DIMM bandwidth by increasing the DDR channel, resulting in poor system stability.
Using the command processing method based on HBDIMM, when the clock driver is in the phase synchronization stage by commanding the host and register division, the target command is sent, and the target allocation mode is determined from the preset command allocation mode, and the target command is allocated to the target pseudo-channel according to the target mode, and transmitted to the combined data buffer.
This improves the bandwidth utilization of the system, enhances the stability of the system, and avoids the stability problems caused by increasing the DDR channel.
Smart Images
Figure CN119669117A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of memory processing technology, and in particular to a command processing method and device based on HBDIMM. Background Art
[0002] The widely used Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) standard is used for DDR4 and DDR5 memories and provides a channel that can support dual-in-line memory module (DIMM) devices on both rising and falling clock edges.
[0003] Due to the working process of synchronous dynamic random access memory (DRAM), the I / O speed gap between DRAM and host / controller is increasing, and the routing resources on software packages, DIMMs and printed circuit boards (PCB) are limited. Adding more DDR channels to increase DIMM bandwidth is not a promising solution.
[0004] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention
[0005] The embodiments of the present application provide a command processing method and device based on HBDIMM, so as to at least solve the technical problem that the relevant system increases the DIMM bandwidth by adding DDR channels, resulting in poor system stability.
[0006] According to one aspect of an embodiment of the present application, a command processing method based on HBDIMM is provided, comprising: when a command host and a register division clock driver are in a phase synchronization stage, sending a target command to a register division clock driver through the command host, wherein the target command includes at least: a command type and a command address; determining a target allocation mode corresponding to the command address of the target command from a preset command allocation mode, wherein the target command allocation mode includes at least: a fixed merge mode, a fixed interleaving mode, and a dynamic merge / interleaving mode; allocating the target command to a target pseudo channel according to the target mode, and transmitting the target command to a combined data buffer through the target pseudo channel, wherein the combined data buffer is used to perform a corresponding operation according to the command type of the target command to obtain an operation result.
[0007] Optionally, whether the command host and the register division clock driver are in the phase synchronization stage is determined in the following manner: obtaining the first phase of the first clock cycle in which the command host sends the target command and the second phase of the second clock cycle in which the register division clock driver receives the target command; when the first phase and the second phase are the same even phase or odd phase, it is determined that the command host and the register division clock driver are in the phase synchronization stage.
[0008] Optionally, after determining that the command host and the register division clock driver are in a phase synchronization stage, the method further includes: when the command host is in a state to be synchronized, performing a synchronization operation on the command host, wherein the state to be synchronized includes at least one of the following: turning off the self-refresh state, setting a flag register for maintaining asynchronous operation with the register division clock driver.
[0009] Optionally, the command host is assigned to a target pseudo-channel according to the target mode, and the target command is transmitted to a combined data buffer through the target pseudo-channel, including: when the target mode is a fixed merge mode, determining to assign a target command received by a register division clock driver when the second phase of a second clock cycle is an even number to two target pseudo-channels; transmitting the target command to the combined data buffer through the two target pseudo-channels, wherein the combined data buffer does not include preset virtual data.
[0010] Optionally, the command host is assigned to a target pseudo-channel according to the target mode, and the target command is transmitted to a combined data buffer through the target pseudo-channel, including: when the target mode is a fixed interleaved mode, the target pseudo-channel is determined based on the odd or even nature of the second phase of the second clock cycle of the target command received by the register-divided clock driver or the register-divided clock driver; and the target command is transmitted to the combined data buffer through the target pseudo-channel, wherein the combined data buffer includes valid data transmitted by the target pseudo-channel and preset virtual data.
[0011] Optionally, the command host is assigned to a target pseudo-channel according to the target mode, and the target command is transmitted to a combined data buffer through the target pseudo-channel, including: when the target mode is a dynamic merge / interleave mode, determining the number of UIs corresponding to the target command; when the number of UIs is equal to 1, determining the target pseudo-channel according to the first flag bit in the target command, or determining the target pseudo-channel according to the even-oddity of the second phase of the second clock cycle of the register division clock driver receiving the target command; when the number of UIs is equal to 2, determining the target pseudo-channel according to the first flag bit of the target command, and determining a fixed allocation mode according to the second flag bit in the target command, wherein the fixed allocation mode includes at least: a fixed merge mode and a fixed interleave mode; transmitting the target command to the combined data buffer through the target pseudo-channel, wherein the combined data buffer includes valid data transmitted by at least one target pseudo-channel and preset virtual data.
[0012] Optionally, the first flag bit is CID2, and the second flag bit is CID3.
[0013] According to another aspect of an embodiment of the present application, a command processing device based on HBDIMM is also provided, including: a command sending module, used to send a target command to a register division clock driver through a command host when the command host and the register division clock driver are in a phase synchronization stage, wherein the target command includes at least: a command type and a command address; a determination module, used to determine a target allocation mode corresponding to the command address of the target command from a preset command allocation mode, wherein the target command allocation mode includes at least: a fixed merge mode, a fixed interleaving mode, and a dynamic merge / interleaving mode; a command response module, used to allocate the target command to a target pseudo channel according to the target mode, and transmit the target command to a combined data buffer through the target pseudo channel, wherein the combined data buffer is used to perform a corresponding operation according to the command type of the target command to obtain an operation result.
[0014] According to another aspect of an embodiment of the present application, a non-volatile storage medium is further provided, the non-volatile storage medium including a stored computer program, wherein the device where the non-volatile storage medium is located executes the above-mentioned HBDIMM-based command processing method by running the computer program.
[0015] According to another aspect of an embodiment of the present application, an electronic device is further provided, comprising: a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to execute the above-mentioned HBDIMM-based command processing method through the computer program.
[0016] In an embodiment of the present application, when the command host and the register division clock driver are in the phase synchronization stage, the target command is sent to the register division clock driver through the command host, wherein the target command includes at least: command type and command address; the target allocation mode corresponding to the command address of the target command is determined from the preset command allocation mode, wherein the target command allocation mode includes at least: fixed merging mode, fixed interleaving mode, dynamic merging / interleaving mode; the target command is allocated to the target pseudo channel according to the target mode, and the target command is transmitted to the combined data buffer through the target pseudo channel, wherein the combined data buffer is used to perform the corresponding operation according to the command type of the target command to obtain the operation result. Thus, the technical problem that the relevant system increases the DIMM bandwidth by adding DDR channels, resulting in poor system stability is solved. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0018] Figure 1 This is a hardware structure block diagram of a mobile terminal for monitoring an optional smart network card according to an embodiment of the present application;
[0019] Figure 2 is a flowchart of an optional HBDIMM-based command processing method according to an embodiment of the present application;
[0020] Figure 3 is a timing diagram of an optional RDCD using a fixed merge mode to allocate commands according to an embodiment of the present application;
[0021] Figure 4 is a timing diagram of an optional RDCD using a fixed interleaving mode to allocate commands according to an embodiment of the present application;
[0022] Figure 5 is a schematic diagram of an optional command truth table according to an embodiment of the present application;
[0023] Figure 6 It is a schematic structural diagram of an optional HBDIMM-based command processing device according to an embodiment of the present application. DETAILED DESCRIPTION
[0024] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.
[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0026] In addition, the relevant information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for display, data for analysis, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. For example, an interface is set up between this system and the relevant user or organization. Before obtaining relevant information, it is necessary to send an acquisition request to the aforementioned user or organization through the interface, and obtain relevant information after receiving the consent information fed back by the aforementioned user or organization.
[0027] In order to better understand the embodiments of the present application, the technical terms involved in the embodiments of the present application are explained as follows:
[0028] Register Divider Clock Driver (RDCD): It divides the input clock signal and drives the corresponding register module to work. It can be used in the clock divider circuit in the digital system to control the working clock frequency of different modules. Usually, RDCD can set different division ratios to generate clock signals of different frequencies to meet the working requirements of different modules. It can divide the high-frequency input clock into a low-frequency clock, so that different modules in the system can work at different frequencies, realizing the system's multi-function and timing control.
[0029] Combined Data Buffer (CDB): Buffers and manages data transfer between the memory controller and the HBDIMM storage module. Its main functions include: temporarily storing data sent from the memory controller to the register module; managing the flow of data, including resolving data conflicts and rearrangement; and improving the bandwidth utilization of the HBDIMM system. By caching data and managing data flow, the combined data buffer can reduce the idle time between data transfers and make data transfer more continuous and efficient.
[0030] Example 1
[0031] The embodiment of the command processing method based on HBDIMM provided in the first embodiment of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, Figure 1 1 is a hardware structure block diagram of a mobile terminal for monitoring a smart network card according to an embodiment of the present application. Figure 1 As shown, the mobile terminal 10 may include one or more (only one is shown in the figure) processors 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory 104 for storing data, and a transmission device 106 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is for illustration only and does not limit the structure of the above electronic device. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.
[0032] The memory 104 can be used to store software programs and modules of application software, such as program instructions / modules corresponding to the monitoring of the smart network card in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, realizing the above-mentioned command processing method based on HBDIMM. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the mobile terminal 10 via a network. Examples of the above-mentioned network may include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
[0033] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the mobile terminal 10. In one example, the transmission device 106 may include a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.
[0034] In this embodiment, a command processing method based on HBDIMM is provided. Figure 2 is a flowchart of a command processing method based on HBDIMM according to an embodiment of the present application, such as Figure 2 As shown, the process includes the following steps:
[0035] Step S202, when the command host and the register division clock driver are in a phase synchronization stage, the command host sends a target command to the register division clock driver, wherein the target command includes at least: a command type and a command address.
[0036] In the scheme provided in the above step S202, the command host (Host) and the register division clock driver (RDCD) are in the phase synchronization stage, which can be understood as the command host and the RDCD send or receive the target command in the same even phase / odd phase phase, wherein the target command includes but is not limited to: read request command, write request command, precharge command, refresh command, etc.
[0037] As an optional implementation, in the technical solution provided in the above step S202, whether the command host and the register division clock driver are in the phase synchronization stage can be determined according to the following method, including: obtaining the first phase of the first clock cycle in which the command host sends the target command and the second phase of the second clock cycle in which the register division clock driver receives the target command; when the first phase and the second phase are the same even phase or odd phase, determining that the command host and the register division clock driver are in the phase synchronization stage.
[0038] In the above embodiment, the second phase can be understood as the effective instant at which the clock signal corresponds to the ideal signal, generally referring to the delay time of the rising edge or the falling edge. Usually, there is a central clock source in the system, which provides the main clock signal. Therefore, first, the frequency and phase of the main clock signal can be determined, wherein the frequency of the main clock signal is usually known and remains unchanged throughout the system; then, the clock signal path of the command host and the register division clock driver and the phase relationship of each clock signal are determined, wherein the phase relationship refers to the odd-even phase relationship or other phase relationship; then, the clock signals of the command host and the register division clock driver are detected by appropriate tools, and the phases of their clock signals are compared. If they are in the same even phase or odd phase stage, it means that their clock signals change in a similar manner, that is, the command host and the register division clock driver are in the phase synchronization stage; on the contrary, if they are in different phase stages (that is, the first phase and the second phase are different even phases or odd phases, respectively), it means that their clock signals change in different ways, that is, the command host and the register division clock driver are not in the phase synchronization stage. The above process can also be called "even / odd phase synchronization mechanism".
[0039] In addition, after completing the phase synchronization between the command host and the register division clock driver, the synchronization state of the host may be affected by some abnormal factors, such as network delay, host failure, etc. Therefore, in order to ensure the stable operation of the entire system, it is necessary to further determine whether the host needs to be synchronized.
[0040] Optionally, when the command host is in a state to be synchronized, a synchronization operation is performed on the command host, wherein the state to be synchronized includes at least one of the following: turning off the self-refresh state, setting a flag register for maintaining asynchronous operation with a register division clock driver.
[0041] Specifically, the situations where the command host needs to be synchronized include but are not limited to: initialization before entering HBDIMM mode; SRX shutdown (to make the synchronous dynamic random access memory DRAM exit the self-refresh state); the command host sets a flag register, which is particularly useful for bench verification because it is impossible to maintain synchronization with the register division clock driver in the bench board. Therefore, whenever the platform master controller wants to initiate a command to the register division clock driver, it needs to set the flag register inside the register division clock driver through the system management bus (SMBUS) and send a no operation (NOP) command to make the intentional command late by a fixed cycle.
[0042] After completing the phase synchronization of the command host and the register division clock driver through the above steps, the command host can send the target command to the HBDIMM system through the data bus, and the register division clock driver in the system will decode the command to determine the command type and the address of the target register to be accessed (i.e., the command address). Among them, the register division clock driver RDCD can generate clock signals of different frequencies, and drive the corresponding register module to work according to the clock signal, realizing the system's multi-function and timing space, so as to improve the system's work efficiency.
[0043] Step S204, determining a target allocation mode corresponding to the command address of the target command from preset command allocation modes, wherein the target command allocation modes at least include: a fixed merge mode, a fixed interleave mode, and a dynamic merge / interleave mode.
[0044] In the solution provided in the above step S204, the register division clock driver is configured to distribute the mode information of the command according to the command address, so as to control the transmission of the command and the working mode of the register division clock driver.
[0045] Step S206: assign the target command to the target pseudo channel according to the target mode, and transmit the target command to the combined data buffer through the target pseudo channel for response.
[0046] In the solution provided in the above step S206, the register division clock driver assigns the target command to the target pseudo channel PC (Pseudo Channels) according to the target mode. After receiving the target command, the target pseudo channel will forward the target command to the combined data buffer CDB, and the combined data buffer will perform operations corresponding to the target command type, such as reading, writing or modifying the value of the register. Among them, the QCA interface on the a side and the b side of the same channel is called a pseudo channel, which is controlled by the DCA (Double Channel Architecture) logic, wherein the bandwidth of DCA is twice that of QCA (QuadChannel Architecture), and the DCA / QCA bandwidth is balanced.
[0047] After the operation is completed, the combined data buffer will send the operation result to the register division clock driver through the pseudo channel, and the register division clock driver will eventually return the operation result to the command host, thereby realizing data reading, writing, refreshing and other operations. Among them, the above-mentioned combined data buffer usually interleaves data from two PCs. If only the data from one pseudo channel PC is valid, the combined data buffer will interact with the preset virtual data.
[0048] As an optional implementation, when the target mode is a fixed merge mode, it is determined that the target command received by the register division clock driver when the second phase of the second clock cycle is an even number is distributed to two target pseudo channels; the target command is transmitted to the combined data buffer through the two target pseudo channels, wherein the combined data buffer does not include preset virtual data.
[0049] That is to say, if the register division clock driver uses a fixed merge mode to distribute target commands, the command host only needs to simply send the command to the register division clock driver without making additional modifications to the command. This can reduce the processing requirements for the command host and reduce the complexity and cost of the system. In addition, when distributing commands, the command host only needs to send the target command when the first phase of the first clock cycle is an even phase stage, and the register division clock driver receives the target command when the second phase of the second clock cycle is the same even phase stage, and broadcasts the target command to the two target pseudo channels respectively, and transmits the target command to the combined data buffer through the two target pseudo channels. Figure 3 As shown, in each Big Cycle, the phase of the command sent by the HOST to the RDCD is an even phase, and the RDCD broadcasts the command to CMDPC0 and CMDPC1, so that the parallel processing of the command can be realized.
[0050] As another optional implementation, when the target mode is a fixed interleaving mode, the target pseudo channel is determined based on the odd or even nature of the first flag bit in the target command received by the register-divided clock driver or the second phase of the second clock cycle of the target command received by the register-divided clock driver; the target command is transmitted to the combined data buffer through the target pseudo channel, wherein the combined data buffer includes valid data transmitted by the target pseudo channel and preset virtual data.
[0051] That is, if the register division clock driver uses a fixed staggered mode to allocate target commands, each time a target pseudo channel is allocated, the target pseudo channel can be determined based on the channel ID of the pseudo channel or the odd-oddity of the second phase of the second clock cycle of the register division clock driver receiving the target command. In addition, the command host distributes these commands to different registers according to the command sequence and selects valid data through timing parameters. Usually, the back-to-back read / write commands of the two pseudo channels have dummy data at the beginning and end of the data stream. Figure 4 As shown, since multiple registers receive different commands at the same time and return data with different delays, there will be a certain overlap in the data returned by the combined data buffer.
[0052] As another optional implementation, when the target mode is a dynamic merge / interleave mode, the number of UIs corresponding to the target command is determined; when the number of UIs is equal to 1, the target pseudo-channel is determined based on the odd / even nature of the second phase of the second clock cycle of the register division clock driver receiving the target command; when the number of UIs is equal to 2, the target pseudo-channel is determined based on the first flag bit of the target command, and the fixed allocation mode is determined based on the second flag bit in the target command, wherein the fixed allocation mode includes at least: a fixed merge mode and a fixed interleave mode; the target command is transmitted to a combined data buffer through the target pseudo-channel, wherein the combined data buffer includes valid data transmitted by at least one target pseudo-channel and preset virtual data.
[0053] Specifically, in the dynamic merging / interleaving mode, the target pseudo channel can be determined according to the number of UIs that the target command continues. When the number of UIs is equal to 1, the target pseudo channel can be determined according to the odd and even nature of the second phase of the second clock cycle of the register division clock driver receiving the target command. When the number of UIs is equal to 2, the first flag bit in the target command can be used as an indicator of the pseudo channel, and the second flag bit can be used as an indicator of the fixed allocation mode, wherein the above-mentioned first flag bit and second flag bit are configured by the command host.
[0054] Specifically, Figure 5 is a schematic diagram of an optional command truth table according to an embodiment of the present application, such as Figure 5 As shown, it can be seen in the column corresponding to CA13 that CID2 can be used as the first flag bit and CID3 can be used as the second flag bit.
[0055] Based on the scheme defined by the above steps S202 to S206, it can be known that in the embodiment, since the frequency of the dual-channel architecture DCA is twice the frequency of the quad-channel architecture QCA, the embodiment of the present application proposes the concept of register division clock driver RDCD. At the same time, in order to emphasize the combination function of the data buffer, the embodiment of the present application also proposes the concept of combination buffer (CDB). At the same time, three different command allocation modes are proposed to adapt to different application scenarios, among which the fixed merge mode can reduce the host modification work in the merged data stream; in the fixed interleaved mode, the host can flexibly select pc as the command target, eliminating the disadvantage of the double burst length problem of the fixed merge mode; the dynamic merge / interleaved mode can maximize the performance of HBDIMM, and its scalability requirements for the host will accelerate the acceleration stage of the HBDIMM system. Thereby solving the technical problem that the relevant system increases the DIMM bandwidth by increasing the DDR channel, resulting in poor system stability.
[0056] Example 2
[0057] Based on Embodiment 1 of the present application, an embodiment of a command processing device based on HBDIMM is also provided, and when the device is running, the command processing method based on HBDIMM in the above embodiment is executed. Figure 6 is a schematic structural diagram of an optional HBDIMM-based command processing device according to an embodiment of the present application, such as Figure 6 As shown, the HBDIMM-based command processing device at least includes a command sending module 61, a determination module 63 and a command response module 65, wherein:
[0058] The command sending module 61 is used to send a target command to the register division clock driver through the command host when the command host and the register division clock driver are in a phase synchronization stage, wherein the target command includes at least: a command type and a command address;
[0059] A determination module 63, configured to determine a target allocation mode corresponding to the command address of the target command from preset command allocation modes, wherein the target command allocation mode at least includes: a fixed merge mode, a fixed interleave mode, and a dynamic merge / interleave mode;
[0060] The command response module 65 is used to assign the target command to the target pseudo channel according to the target mode, and transmit the target command to the combined data buffer through the target pseudo channel, wherein the combined data buffer is used to perform corresponding operations according to the command type of the target command to obtain the operation result.
[0061] It should be noted that the various modules in the above-mentioned HBDIMM-based command processing device can be program modules (for example, a set of program instructions that implement a certain specific function) or hardware modules. For the latter, it can be expressed in the following forms, but is not limited to this: the expression form of each of the above-mentioned modules is a processor, or the functions of each of the above-mentioned modules are implemented by a processor.
[0062] Example 3
[0063] According to an embodiment of the present application, a non-volatile storage medium is further provided, in which a program is stored, wherein when the program is running, the device where the non-volatile storage medium is located is controlled to execute the HBDIMM-based command processing method in Example 1.
[0064] Optionally, the device where the non-volatile storage medium is located implements the following steps by running the program: when the command host and the register division clock driver are in the phase synchronization stage, the target command is sent to the register division clock driver through the command host, wherein the target command includes at least: a command type and a command address; a target allocation mode corresponding to the command address of the target command is determined from a preset command allocation mode, wherein the target command allocation mode includes at least: a fixed merge mode, a fixed interleaving mode, and a dynamic merge / interleaving mode; the target command is allocated to a target pseudo channel according to the target mode, and the target command is transmitted to a combined data buffer through the target pseudo channel, wherein the combined data buffer is used to perform a corresponding operation according to the command type of the target command to obtain an operation result.
[0065] According to an embodiment of the present application, a processor is further provided, which is used to run a program, wherein the HBDIMM-based command processing method in Example 1 is executed when the program is running.
[0066] Optionally, the following steps are executed when the program is running: when the command host and the register division clock driver are in the phase synchronization stage, the target command is sent to the register division clock driver through the command host, wherein the target command includes at least: a command type and a command address; a target allocation mode corresponding to the command address of the target command is determined from preset command allocation modes, wherein the target command allocation mode includes at least: a fixed merge mode, a fixed interleaving mode, and a dynamic merge / interleaving mode; the target command is allocated to a target pseudo channel according to the target mode, and the target command is transmitted to a combined data buffer through the target pseudo channel, wherein the combined data buffer is used to perform corresponding operations according to the command type of the target command to obtain an operation result.
[0067] According to an embodiment of the present application, an electronic device is also provided, wherein the electronic device includes one or more processors; a memory for storing one or more programs, and when the one or more programs are executed by the one or more processors, the one or more processors are implemented to run the programs, wherein the program is configured to execute the HBDIMM-based command processing method in the above-mentioned embodiment 1 when running.
[0068] Optionally, the processor is configured to execute the following steps through a computer program: when the command host and the register division clock driver are in a phase synchronization stage, sending a target command to the register division clock driver through the command host, wherein the target command includes at least: a command type and a command address; determining a target allocation mode corresponding to the command address of the target command from a preset command allocation mode, wherein the target command allocation mode includes at least: a fixed merge mode, a fixed interleaving mode, and a dynamic merge / interleaving mode; allocating the target command to a target pseudo-channel according to the target mode, and transmitting the target command to a combined data buffer through the target pseudo-channel, wherein the combined data buffer is used to perform a corresponding operation according to the command type of the target command to obtain an operation result.
[0069] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.
[0070] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.
[0071] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of units can be a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.
[0072] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed over multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.
[0073] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.
[0074] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the relevant technology or all or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk, etc. Various media that can store program codes.
[0075] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.
Claims
1. A command processing method based on HBDIMM, characterized in that: include: When the command host and the register division clock driver are in a phase synchronization stage, the command host sends a target command to the register division clock driver, wherein the target command includes at least: a command type and a command address; Determine a target allocation mode corresponding to the command address of the target command from preset command allocation modes, wherein the target command allocation mode includes at least: a fixed merge mode, a fixed interleave mode, and a dynamic merge / interleave mode; The target command is assigned to a target pseudo channel according to the target mode, and the target command is transmitted to a combined data buffer through the target pseudo channel, wherein the combined data buffer is used to perform a corresponding operation according to a command type of the target command to obtain an operation result.
2. The method according to claim 1, characterized in that The command host and register division clock driver are in phase synchronization as follows: Acquire a first phase of a first clock cycle in which the command host sends the target command and a second phase of a second clock cycle in which the register-divided clock driver receives the target command; When the first phase and the second phase are both the same even phase or odd phase, it is determined that the command host and the register division clock driver are in a phase synchronization stage.
3. The method according to claim 1, characterized in that After determining that the command host and the register division clock driver are in a phase synchronization phase, the method further includes: When the command host is in a state to be synchronized, a synchronization operation is performed on the command host, wherein the state to be synchronized includes at least one of the following: turning off the self-refresh state, setting a flag register for maintaining asynchronous operation with the register division clock driver.
4. The method according to claim 2, characterized in that: Allocating the command host to the target pseudo channel according to the target mode and transmitting the target command to the combined data buffer through the target pseudo channel includes: In a case where the target mode is the fixed merge mode, determining to distribute the target command received by the register division clock driver when the second phase of the second clock cycle is an even number to the two target pseudo channels; The target command is transmitted to the combined data buffer through the two target pseudo channels, wherein the combined data buffer does not include preset dummy data.
5. The method according to claim 2, characterized in that: Allocating the command host to the target pseudo channel according to the target mode and transmitting the target command to the combined data buffer through the target pseudo channel includes: In the case where the target mode is the fixed interleaving mode, determining the target pseudo channel according to the odd or even of a second phase of a second clock cycle of the target command received by the register-divided clock driver or the register-divided clock driver; The target command is transmitted to the combined data buffer through the target pseudo channel, wherein the combined data buffer includes valid data transmitted by the target pseudo channel and preset virtual data.
6. The method according to claim 2, characterized in that Allocating the command host to the target pseudo channel according to the target mode and transmitting the target command to the combined data buffer through the target pseudo channel includes: When the target mode is the dynamic merge / interlace mode, determining the number of UIs corresponding to the target command; When the number of UIs is equal to 1, the target pseudo channel is determined according to a first flag bit in the target command, or the target pseudo channel is determined according to an even or odd number of a second phase of a second clock cycle of the target command received by the register divided clock driver; When the number of UIs is equal to 2, the target pseudo channel is determined according to the first flag bit of the target command, and the fixed allocation mode is determined according to the second flag bit in the target command, wherein the fixed allocation mode at least includes: the fixed merge mode and the fixed interleaving mode; The target command is transmitted to the combined data buffer through the target pseudo channel, wherein the combined data buffer includes at least one valid data transmitted by the target pseudo channel and preset virtual data.
7. The method according to any one of claims 5 to 6, characterized in that The first flag bit is CID2, and the second flag bit is CID3.
8. A command processing device based on HBDIMM, characterized in that: include: A command sending module, used for sending a target command to the register division clock driver through the command host when the command host and the register division clock driver are in a phase synchronization stage, wherein the target command at least includes: a command type and a command address; A determination module, configured to determine a target allocation mode corresponding to the command address of the target command from preset command allocation modes, wherein the target command allocation modes at least include: a fixed merge mode, a fixed interleave mode, and a dynamic merge / interleave mode; A command response module is used to assign the target command to a target pseudo channel according to the target mode, and transmit the target command to a combined data buffer through the target pseudo channel, wherein the combined data buffer is used to perform a corresponding operation according to a command type of the target command to obtain an operation result.
9. A non-volatile storage medium, characterized in that: The non-volatile storage medium stores a computer program, wherein the device where the non-volatile storage medium is located executes the HBDIMM-based command processing method according to any one of claims 1 to 7 by running the computer program.
10. An electronic device, characterized in that: include: A memory and a processor, wherein the processor is used to run a program stored in the memory, wherein the program executes the HBDIMM-based command processing method according to any one of claims 1 to 7 when running.