Layout structure of storage and calculation integrated array, construction method and thermal simulation method thereof

Abstract

The invention relates to a layout structure, a construction method and a thermal simulation method of a storage and calculation integrated array. The layout structure comprises a layout base and a 5T2M array unit arranged on the layout base, a second switch tube and a fourth switch tube are arranged on the leftmost side of the layout base, the second switch tube is arranged on the upper side of the fourth switch tube, a first switch tube is arranged on the layout base on the right side of the second switch tube, and a third switch tube is arranged on the layout base on the right side of the fourth switch tube. And a fifth switch tube is arranged on the layout base on the right side of the third switch tube and is positioned in the middle of the rightmost side of the layout base. The layout and wiring of the layout structure shorten a signal transmission path and reduce signal delay. According to the method, a corresponding geometric model is constructed through the layout structure of the storage and calculation integrated array for thermal simulation, temperature field distribution is obtained, the performance of the layout structure is known according to the temperature field distribution, and the practicability of the layout structure is verified.

Description

Technical Field

[0001] The present application relates to the field of storage and computing technology, and in particular to a layout structure, construction method and thermal simulation method of a storage and computing integrated array. Background Art

[0002] The rapid development of deep learning has brought about a huge demand for computing power. However, traditional silicon-based chips based on the "von Neumann architecture" with storage and computing separation are facing problems such as the "storage wall", and the computing power growth of silicon-based chips has gradually reached a bottleneck. In order to resolve this contradiction, existing technologies have been inspired by the working mode of the biological brain and proposed a storage-computing integrated architecture based on memristors. This chip with a storage-computing integrated architecture is expected to achieve several orders of magnitude improvement in energy efficiency and speed compared to the "von Neumann architecture" when processing tasks such as neural networks. It is one of the most promising technical routes for realizing ultra-low power consumption and ultra-high computing power computing chips.

[0003] As the core component of the storage-computing-in-one architecture, the performance of the storage-computing-in-one array is a key factor affecting the performance of the overall architecture. The layout design of the storage-computing-in-one array can shorten the signal transmission path, reduce latency, and improve the working speed and response performance of the chip's overall circuit architecture through reasonable layout and wiring design. At the same time, the layout design of the storage-computing-in-one array can help optimize the power consumption performance of the circuit. Summary of the invention

[0004] The present application provides a layout structure, construction method and thermal simulation method of a storage-computing integrated array, which are used to solve the technical problems of long signal transmission path and long delay time in the layout and wiring of existing storage-computing integrated architecture chips.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] On the one hand, a layout structure of a storage-computing integrated array is provided, which is applied to a 5T2M array unit based on a memristor, wherein the 5T2M array unit includes a first memristor, a second memristor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a first word line terminal, a second word line terminal, an electrode terminal, a first bit line terminal, a second bit line terminal, a third bit line terminal and a fourth bit line terminal, and the layout structure of the storage-computing integrated array includes a layout base and a 5T2M array unit arranged on the layout base;

[0007] The second switch tube and the fourth switch tube are placed on the leftmost side of the layout base, the second switch tube is located on the upper side of the fourth switch tube, the first switch tube is arranged on the layout base on the right side of the second switch tube, the third switch tube is arranged on the layout base on the right side of the fourth switch tube, the fifth switch tube is arranged on the layout base on the right side of the third switch tube, and the fifth switch tube is located in the middle of the rightmost side of the layout base;

[0008] The third end of the first switch tube is connected to the first bit line end through a connecting line, and the first bit line end is placed horizontally at the uppermost side of the layout base; the third end of the second switch tube is connected to the second bit line end through a connecting line, and the second bit line end is placed at the lower side of the first bit line end; the first end of the fifth switch tube is connected to the electrode end through a connecting line, and the electrode end is placed at the lower side of the second bit line end; the third end of the third switch tube is connected to the third bit line end through a connecting line, and the third bit line end is placed at the lower side of the electrode end; the third end of the fourth switch tube is connected to the fourth bit line end through a connecting line, and the fourth bit line end is placed at the lower side of the third bit line end; the first end of the second switch tube and the first end of the fourth switch tube are both connected to the second word line end through a connecting line, and the second word line end is placed vertically at the uppermost side of the layout base. left side; the first end of the first switch tube and the first end of the third switch tube are both connected to the first word line end through a connecting line, and the first word line end is placed on the right side of the second word line end; the second end of the first switch tube and the second end of the fifth switch tube are both connected to the positive electrode of the first memristor through a connecting line, and the first memristor is placed on the left side of the first switch tube; the second end of the second switch tube is connected to the negative electrode of the first memristor through a connecting line, and the negative electrode of the first memristor is placed on the right side of the second switch tube; the second end of the third switch tube is connected to the third end of the fifth switch tube and then to the positive electrode of the second memristor, and the positive electrode of the second memristor is placed on the left side of the third switch tube; the third end of the fourth switch tube is connected to the negative electrode of the second memristor, and the negative electrode of the second memristor is placed on the right side of the fourth switch tube.

[0009] Preferably, the spacing distance between two adjacent switch tubes on the layout base is the first distance; and / or the distance between two adjacent connecting lines on the layout base is at least the second distance.

[0010] Preferably, the connecting wire is a copper wire, a silver wire or an aluminum wire; and / or the cross-sectional area of ​​the connecting wire is 10um×10um.

[0011] Preferably, the electrode specifications of the first switch tube, the second switch tube, the third switch tube, the fourth switch tube and the fifth switch tube are all 10um×10um×10um; and / or, the substrates of the first switch tube, the second switch tube, the third switch tube, the fourth switch tube and the fifth switch tube are all P-type substrates; and / or, the doping of the first switch tube, the second switch tube, the third switch tube, the fourth switch tube and the fifth switch tube are all N-type doping; and / or, the specifications of the oxide insulation layer of the first switch tube, the second switch tube, the third switch tube, the fourth switch tube and the fifth switch tube are all 50um×50um×10um; and / or, the lower layer of the oxide insulation layer of the first switch tube, the second switch tube, the third switch tube, the fourth switch tube and the fifth switch tube is a conductive channel; and / or, the specifications of the resistive switching layer of the first memristor and the second memristor are both 10um×10um×10um.

[0012] Preferably, the specifications of the P-type substrate are 300um×400um×100um; and / or, the specifications of the N-type doping are 50um×50um×10um; and / or, the specifications of the conductive channel are 50um×50um×5um.

[0013] On the other hand, a thermal simulation method of a storage-computation integrated array is provided, which is applied to a 5T2M array unit based on a memristor, and the thermal simulation method comprises the following steps:

[0014] S1. Obtain the layout structure of the storage-computing integrated array described above, and construct a geometric model corresponding to the 5T2M array unit using the solid and fluid heat transfer physical fields of the multi-physics field simulation software according to the layout structure;

[0015] S2. Obtain thermal simulation constraints, physical parameters of the 5T2M array unit, and the occupied area of ​​the layout structure, perform thermal simulation on the geometric model according to the physical parameters, the thermal simulation constraints, and the occupied area, and obtain a first temperature field distribution before packaging;

[0016] S3. Obtain packaging materials for the 5T2M array unit, and construct a corresponding packaging layout according to the packaging materials and the layout structure; perform thermal simulation on the packaging layout using steps S2 and S3 to obtain a second temperature field distribution after packaging.

[0017] Preferably, obtaining the power consumption content in the physical parameters of the 5T2M array unit includes: obtaining electrical quantity data of each electronic component in the 5T2M array unit, and calculating the power consumption calculation data of the temperature field of the 5T2M array unit according to the electrical quantity data.

[0018] Preferably, the power consumption calculation data of the 5T2M array unit temperature field calculated according to the electrical quantity data includes:

[0019] According to the switching cycle, the memristor resistance and the memristor voltage in the electrical quantity data, the memristor power consumption when the memristor is turned on / off in the power consumption calculation data is obtained;

[0020] According to the output voltage and output current of the switch tube in the electrical quantity data, the static power consumption of the corresponding switch tube in the power consumption calculation data is obtained; according to the output voltage, output capacitance and switching frequency of the switch tube in the electrical quantity data, the dynamic power consumption of the corresponding switch tube in the power consumption calculation data is obtained;

[0021] The power consumption of the connecting line of the power consumption calculation data is obtained by calculating the switching cycle, the connecting line input voltage and the connecting line resistance in the electrical quantity data.

[0022] Preferably, the physical parameters also include material properties, thermal conductivity, density and constant-pressure heat capacity of each electronic component in the 5T2M array unit; and / or, the thermal simulation constraints include boundary conditions, initial conditions, heat sources and solver setting data; the boundary conditions include maximum allowable temperature, temperature uniformity and number of hotspot controls, the initial conditions include initial temperature distribution, the heat source includes maximum power consumption heat, and the solver setting data includes step size and convergence criteria.

[0023] On the other hand, a method for constructing a layout structure of a storage-computation-in-one array is provided, comprising the following steps:

[0024] Obtaining the memory bit width data of the chip, the layout structure of the integrated storage and computing array as claimed in any one of claims 1 to 5, and the storage bit width of the layout structure;

[0025] Determine the number of layout design rows and the number of layout structures contained in each row according to the video memory bit width data and the storage bit width;

[0026] A corresponding chip design layout is constructed according to the number of layout design rows and the number of layout structures.

[0027] The layout structure, construction method and thermal simulation method of the storage-computing integrated array, the layout structure of the storage-computing integrated array, applied to a 5T2M array unit based on a memristor, the 5T2M array unit comprising a first memristor, a second memristor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a first word line end, a second word line end, an electrode end, a first bit line end, a second bit line end, a third bit line end and a fourth bit line end, the layout structure of the storage-computing integrated array comprising a layout base and a 5T2M array unit arranged on the layout base; a second memristor is placed on the leftmost side of the layout base; a second bit line end is placed on the leftmost side of the layout base; a second bit line end is placed on the leftmost side of the layout base; a first bit line end .... The first switch tube and the fourth switch tube, the second switch tube is located on the upper side of the fourth switch tube, the first switch tube is arranged on the layout base on the right side of the second switch tube, the third switch tube is arranged on the layout base on the right side of the fourth switch tube, the fifth switch tube is arranged on the layout base on the right side of the third switch tube, and the fifth switch tube is located in the middle of the rightmost side of the layout base; the third end of the first switch tube is connected to the first bit line end through a connecting line, and the first bit line end is placed horizontally on the uppermost side of the layout base; the third end of the second switch tube is connected to the second bit line end through a connecting line, and the second bit line end is placed on the lower side of the first bit line end; the fifth switch tube The first end of the transistor is connected to the electrode end through a connecting line, and the electrode end is placed at the lower side of the second bit line end; the third end of the third switch transistor is connected to the third bit line end through a connecting line, and the third bit line end is placed at the lower side of the electrode end; the third end of the fourth switch transistor is connected to the fourth bit line end through a connecting line, and the fourth bit line end is placed at the lower side of the third bit line end; the first end of the second switch transistor and the first end of the fourth switch transistor are both connected to the second word line end through a connecting line, and the second word line end is placed vertically at the leftmost side of the layout base; the first end of the first switch transistor and the first end of the third switch transistor are both connected to the first word line end through a connecting line, and the first word line end is placed at The second end of the first switch tube and the second end of the fifth switch tube are both connected to the positive electrode of the first memristor through a connecting line, and the first memristor is placed on the left side of the first switch tube; the second end of the second switch tube is connected to the negative electrode of the first memristor through a connecting line, and the negative electrode of the first memristor is placed on the right side of the second switch tube; the second end of the third switch tube is connected to the third end of the fifth switch tube and then connected to the positive electrode of the second memristor, and the positive electrode of the second memristor is placed on the left side of the third switch tube; the third end of the fourth switch tube is connected to the negative electrode of the second memristor, and the negative electrode of the second memristor is placed on the right side of the fourth switch tube.

[0028] It can be seen from the above technical scheme that the present application has the following advantages: the layout structure of the storage-computing integrated array arranges each electronic component in the 5T2M array unit on the layout base according to specific rules, so that the layout and wiring of the layout structure of the storage-computing integrated array shorten the signal transmission path, reduce the signal delay, and solve the technical problems of long signal transmission path and long delay time in the layout and wiring of the existing storage-computing integrated architecture chip.

[0029] The thermal simulation method of the storage-computing-in-one array constructs a corresponding geometric model through the layout structure of the storage-computing-in-one array to perform thermal simulation, obtains the temperature field distribution, and knows the performance of the layout structure of the storage-computing-in-one array based on the temperature field distribution, verifies the practicality of the layout structure of the storage-computing-in-one array, and solves the technical problems of long signal transmission path and long delay time in the layout and wiring of existing storage-computing-in-one architecture chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0031] Figure 1 A schematic diagram of the three-dimensional structure of the layout structure of the storage-computation-in-one array described in an embodiment of the present application;

[0032] Figure 2 A schematic diagram of a top view of the layout structure of the storage-computation-in-one array described in an embodiment of the present application;

[0033] Figure 3 A schematic diagram of the side view of the layout structure of the storage-computation-in-one array described in an embodiment of the present application;

[0034] Figure 4 A circuit diagram of a 5T2M array unit based on a memristor according to an embodiment of the present application;

[0035] Figure 5 A flowchart of the steps of the thermal simulation method of the storage-computing integrated array described in an embodiment of the present application;

[0036] Figure 6 A first temperature field distribution diagram before packaging in the thermal simulation method for the storage-computing integrated array described in an embodiment of the present application;

[0037] Figure 7 A second temperature field distribution diagram after packaging in the thermal simulation method for the storage-computing integrated array described in an embodiment of the present application;

[0038] Figure 8 A flowchart of the steps of the method for constructing the layout structure of the storage-computation-in-one array described in an embodiment of the present application;

[0039] Fig. 9 The overall diagram of the 512-bit array in the method for constructing the layout structure of the storage-computation-in-one array described in the embodiment of the present application;

[0040] Fig.10A top view of a 512-bit array in the method for constructing the layout structure of a storage-computation-in-one array described in an embodiment of the present application;

[0041] Fig.11 This is an overall diagram of a 256-bit array in the method for constructing the layout structure of a storage-computation-in-one array described in an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the purpose, features, and advantages of the invention of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the embodiments described below are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0043] In the description of the embodiments of the present application, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0044] In the embodiments of the present application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0045] The embodiments of the present application provide a layout structure, construction method and thermal simulation method of a storage-computing integrated array, which solve the technical problems of long signal transmission paths and long delay times in the layout and wiring of existing storage-computing integrated architecture chips.

[0046] Embodiment 1:

[0047] Figure 1 Schematic diagram of the three-dimensional structure of the layout structure of the storage-computation-in-one array described in the embodiment of the present application, Figure 2 Schematic diagram of the top view of the layout structure of the storage-computation-in-one array described in the embodiment of the present application, Figure 3 Schematic diagram of the side view of the layout structure of the storage-computation-in-one array described in the embodiment of the present application, Figure 4Schematic diagram of a circuit of a 5T2M array unit based on a memristor according to an embodiment of the present application.

[0048] like Figures 1 to 4 As shown, the embodiment of the present application provides a layout structure of a storage-computation-in-one array, which is applied to a 5T2M array unit based on a memristor. Figure 4 As shown, the 5T2M array unit includes a first memristor M1, a second memristor M2, a first switch tube T1, a second switch tube T2, a third switch tube T3, a fourth switch tube T4, a fifth switch tube T5, a first word line terminal WL1.1, a second word line terminal WL1.2, an electrode terminal CL1, a first bit line terminal BL1.1, a second bit line terminal BL1.2, a third bit line terminal BL1.4 and a fourth bit line terminal BL1.4. Among them, the second end of the first switch tube T1 is connected to the first bit line terminal BL1.1, the third end of the first switch tube T1 is respectively connected to the positive electrode of the first memristor M1 and the second end of the fifth switch tube T5, the second end of the third switch tube T3 is connected to the third bit line terminal BL2.1, the third end of the third switch tube T3 is respectively connected to the positive electrode of the second memristor M2 and the third end of the fifth switch tube T5, the first end of the fifth switch tube T5 is connected to the electrode terminal CL1, the first end of the second switch tube T2 and the first end of the fourth switch tube T4 are connected in parallel to the second word line terminal WL1.2, the third end of the second switch tube T2 is connected to the negative electrode of the first memristor M1, the second end of the second switch tube T2 is connected to the second bit line terminal BL1.2, the third end of the fourth switch tube T4 is connected to the negative electrode of the second memristor M2, and the second end of the fourth switch tube T4 is connected to the fourth bit line terminal BL2.2.

[0049] It should be noted that if Figure 4 As shown, the switch tube can be preferably a MOS tube, the gate of the MOS tube serves as the first end of the switch tube, the drain of the MOS tube serves as the second end of the switch tube, and the source of the MOS tube serves as the third end of the switch tube. The 5T2M array unit based on memristor consists of 5 switch tubes and two memristors to form an array unit with two rows and two columns. In this embodiment, when the voltage difference of the positive voltage of the memristor minus the negative voltage is greater than the positive threshold voltage, the memristor has a low resistance; when the voltage difference of the positive voltage of the memristor minus the negative voltage is less than the negative threshold voltage, the memristor has a high resistance. Among them, the values ​​of the positive threshold voltage and the negative threshold voltage can be set according to requirements and are not specifically limited here. As Figure 1As shown, the gate of the first MOS transistor T1 and the gate of the third MOS transistor T3 located in the first row of the array unit are connected in parallel to the first word line terminal WL1.1, the drain of the first MOS transistor T1 is connected to the first bit line terminal BL1.1, the source of the first MOS transistor T1 is connected to the positive electrode of the first memristor M1 and to the drain of the fifth MOS transistor T5, the drain of the third MOS transistor T3 is connected to the third bit line terminal BL2.1, the source of the third MOS transistor T3 is connected to the positive electrode of the second memristor M2 and to the source of the fifth MOS transistor T5, and the gate of the fifth MOS transistor T5 is connected to the electrode terminal CL1. The gate of the second MOS transistor T2 and the gate of the fourth MOS transistor T4 located in the second row of the array unit are connected in parallel to the second word line terminal WL1.2, the source of the second MOS transistor T2 is connected to the cathode of the first memristor M1, the drain of the second MOS transistor T2 is connected to the second bit line terminal BL1.2, the source of the fourth MOS transistor T4 is connected to the cathode of the second memristor M2, and the drain of the fourth MOS transistor T4 is connected to the fourth bit line terminal BL2.2.

[0050] like Figures 1 to 3 As shown, in an embodiment of the present application, the layout structure of the storage-computing integrated array includes a layout base 10 and a 5T2M array unit arranged on the layout base 10; the second switch tube T2 and the fourth switch tube T4 are placed on the leftmost side of the layout base 10, the second switch tube T2 is located on the upper side of the fourth switch tube T4, the first switch tube T1 is arranged on the layout base 10 on the right side of the second switch tube T2, the third switch tube T3 is arranged on the layout base 10 on the right side of the fourth switch tube T4, the fifth switch tube T5 is arranged on the layout base 10 on the right side of the third switch tube T3, and the fifth switch tube T5 is located in the middle of the rightmost side of the layout base 10.

[0051] In the embodiments of the present application, Figure 2 and Figure 3As shown, the third end S1 of the first switch tube T1 is connected to the first bit line end BL1.1 through a connecting line, and the first bit line end BL1.1 is placed horizontally on the uppermost side of the layout base 10; the third end S2 of the second switch tube T2 is connected to the second bit line end BL1.2 through a connecting line, and the second bit line end BL1.2 is placed on the lower side of the first bit line end BL1.1; the first end G5 of the fifth switch tube T5 is connected to the electrode end CL1 through a connecting line, and the electrode end CL1 is placed on the lower side of the second bit line end BL1.2. The third end S3 of the third switch tube T3 is connected to the third bit line terminal BL2.1 through a connecting line, and the third bit line terminal BL2.1 is placed at the lower side of the electrode terminal CL1; the third end S4 of the fourth switch tube T4 is connected to the fourth bit line terminal BL2.2 through a connecting line, and the fourth bit line terminal BL2.2 is placed at the lower side of the third bit line terminal BL2.1; the first end G2 of the second switch tube T2 and the first end G4 of the fourth switch tube T4 are both connected to the second word line terminal WL1.2 through a connecting line, and the second word line terminal WL1.2 ...3 of the third switch tube T3 is connected to the third bit line terminal BL2.1 through a connecting line, and the third bit line terminal BL2.1 is placed at the lower side of the electrode terminal CL1; the third end S4 of the fourth switch tube T4 is connected to the fourth bit line terminal BL2.2 through a connecting line, and the fourth bit line terminal BL2.2 is placed at the lower side of the third bit line terminal BL2.1 L1.2 is placed vertically on the leftmost side of the layout base 10; the first end G1 of the first switch tube T1 and the first end G3 of the third switch tube T3 are connected to the first word line end WL1.1 through a connecting line, and the first word line end WL1.1 is placed on the right side of the second word line end WL1.2; the second end D1 of the first switch tube T1 and the second end D5 of the fifth switch tube T5 are connected to the positive electrode of the first memristor M1 through a connecting line, and the first memristor M1 is placed on the left side of the first switch tube T1; the second switch tube T The second end D2 of the third switch tube T3 is connected to the cathode of the first memristor M1 through a connecting line, and the cathode of the first memristor M1 is placed on the right side of the second switch tube T2; the second end D3 of the third switch tube T3 is connected to the third end S5 of the fifth switch tube T4 and then to the anode of the second memristor M2, and the anode of the second memristor M2 is placed on the left side of the third switch tube T3; the third end D4 of the fourth switch tube T4 is connected to the cathode of the second memristor M2, and the cathode of the second memristor M2 is placed on the right side of the fourth switch tube T4.

[0052] It should be noted that the 5T2M array unit is arranged on the layout base 10 as described above, so that the layout structure of the storage-computation-in-one array can solve the bottleneck problem of data transmission speed between storage and computing in traditional computing systems, and improve computing efficiency and energy efficiency. In this embodiment, the layout and wiring of the layout structure of the storage-computation-in-one array shortens the signal transmission path and reduces signal delay.

[0053] The layout structure of a storage-computing integrated array provided in the present application is applied to a 5T2M array unit based on a memristor, wherein the 5T2M array unit comprises a first memristor, a second memristor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a first word line terminal, a second word line terminal, an electrode terminal, a first bit line terminal, a second bit line terminal, a third bit line terminal and a fourth bit line terminal, and the layout structure of the storage-computing integrated array comprises a layout base and a 5T2M array unit arranged on the layout base; the second switch tube and the fourth switch tube are placed on the leftmost side of the layout base, and the second switch tube is placed on the leftmost side of the layout base. The gate tube is located on the upper side of the fourth switch tube, the first switch tube is arranged on the layout base on the right side of the second switch tube, the third switch tube is arranged on the layout base on the right side of the fourth switch tube, the fifth switch tube is arranged on the layout base on the right side of the third switch tube, and the fifth switch tube is located in the middle of the rightmost side of the layout base; the third end of the first switch tube is connected to the first bit line end through a connecting line, and the first bit line end is placed horizontally on the uppermost side of the layout base; the third end of the second switch tube is connected to the second bit line end through a connecting line, and the second bit line end is placed on the lower side of the first bit line end; the first end of the fifth switch tube is connected to the first bit line end through a connecting line. The first end of the second switch tube is connected to the electrode end, and the electrode end is placed at the lower side of the second bit line end; the third end of the third switch tube is connected to the third bit line end through the connecting line, and the third bit line end is placed at the lower side of the electrode end; the third end of the fourth switch tube is connected to the fourth bit line end through the connecting line, and the fourth bit line end is placed at the lower side of the third bit line end; the first end of the second switch tube and the first end of the fourth switch tube are both connected to the second word line end through the connecting line, and the second word line end is placed vertically at the leftmost side of the layout base; the first end of the first switch tube and the first end of the third switch tube are both connected to the first word line end through the connecting line, and the first word line end is placed at the second word line end The second end of the first switch tube and the second end of the fifth switch tube are both connected to the positive electrode of the first memristor through a connecting line, and the first memristor is placed on the left side of the first switch tube; the second end of the second switch tube is connected to the negative electrode of the first memristor through a connecting line, and the negative electrode of the first memristor is placed on the right side of the second switch tube; the second end of the third switch tube is connected to the third end of the fifth switch tube and then connected to the positive electrode of the second memristor, and the positive electrode of the second memristor is placed on the left side of the third switch tube; the third end of the fourth switch tube is connected to the negative electrode of the second memristor, and the negative electrode of the second memristor is placed on the right side of the fourth switch tube. The layout structure of the storage-computing integrated array arranges each electronic component in the 5T2M array unit on the layout base according to specific rules, so that the layout and wiring of the layout structure of the storage-computing integrated array shortens the signal transmission path and reduces the signal delay. It solves the technical problems of long signal transmission path and long delay time in the layout and wiring of the existing storage-computing integrated architecture chip.

[0054] In order to further shorten the signal transmission path of the 5T2M array unit and reduce the signal delay, the layout of the layout structure of the storage-computing integrated array is limited. In one embodiment of the present application, the spacing distance between two adjacent switch tubes on the layout base 10 is the first distance. The distance between two adjacent connecting lines on the layout base 10 is at least the second distance.

[0055] It should be noted that the distance between each adjacent switch tube is 50um; the connection lines on all word line ends, all bit line ends, and electrode ends are staggered to create a distance of at least 5um. In this embodiment, the first distance can be selected as 50um, and the second distance can be selected as 5um.

[0056] In one embodiment of the present application, the connection wire may be selected as a copper wire, a silver wire, an aluminum wire, etc. The cross-sectional area of ​​the connection wire may be selected as 10um×10um.

[0057] In one embodiment of the present application, the electrode specifications of the first switch tube T1, the second switch tube T2, the third switch tube T3, the fourth switch tube T4 and the fifth switch tube T5 can all be 10um×10um×10um. The substrates of the first switch tube T1, the second switch tube T2, the third switch tube T3, the fourth switch tube T4 and the fifth switch tube T5 can all be P-type substrates; the doping of the first switch tube T1, the second switch tube T2, the third switch tube T3, the fourth switch tube T4 and the fifth switch tube T5 can all be N-type doping. The specifications of the oxide insulation layer of the first switch tube T1, the second switch tube T2, the third switch tube T3, the fourth switch tube T4 and the fifth switch tube T5 can all be 50um×50um×10um. A conductive channel is set in the lower layer of the oxide insulation layer of the first switch tube T1, the second switch tube T2, the third switch tube T3, the fourth switch tube T4 and the fifth switch tube T5. The specifications of the resistive switching layers of the first memristor M1 and the second memristor M2 may both be 10um×10um×10um.

[0058] It should be noted that the specification of the P-type substrate can be 300um×400um×100um; and / or, the specification of the N-type doping can be 50um×50um×10um; the specification of the conductive channel can be 50um×50um×5um. In this embodiment, except for the height of the first end (such as the gate) of the fifth switch tube T5, the height specifications of the first end (such as the gate) of the first switch tube T1, the second switch tube T2, the third switch tube T3 and the fourth switch tube T4 can all be 10um×10um×15um. Among them, the material of the P-type substrate can be gallium phosphide GaP, and the material of the N-type doping can be gallium nitride GaN. The material of the oxide insulating layer can be silicon dioxide SiO2.

[0059] Embodiment 2:

[0060] Figure 5 This is a flow chart of the steps of the thermal simulation method of the storage-computing integrated array described in an embodiment of the present application. Figure 6 This is a first temperature field distribution diagram before packaging in the thermal simulation method for the storage-computing integrated array described in an embodiment of the present application. Figure 7 This is a second temperature field distribution diagram after packaging in the thermal simulation method of the storage and computing integrated array described in an embodiment of the present application.

[0061] like Figures 5 to 7 As shown, the layout structure of the storage-computing-in-one array includes the following steps:

[0062] S1. Obtain the layout structure of the above-mentioned storage and computing integrated array, and construct a geometric model corresponding to the 5T2M array unit using the solid and fluid heat transfer physical fields of the multi-physics field simulation software according to the layout structure.

[0063] It should be noted that the content of the layout structure of the storage and calculation integrated array in step S1 has been described in Example 1 and will not be repeated in this embodiment. In this embodiment, step S1 is to construct a geometric model corresponding to the 5T2M array unit on the solid and fluid heat transfer physical fields of the multi-physics field simulation software according to the layout structure to provide a model for subsequent thermal simulation.

[0064] S2. Obtain thermal simulation constraints, physical parameters of the 5T2M array unit, and the occupied area of ​​the layout structure, perform thermal simulation on the geometric model according to the physical parameters, thermal simulation constraints, and the occupied area, and obtain a first temperature field distribution before packaging.

[0065] It should be noted that in step S2, data for thermal simulation is obtained and thermal simulation is performed on the geometric model constructed in step S1 according to the obtained data to obtain the following: Figure 5 The first temperature field distribution before the layout structure is packaged is shown, and the data includes thermal simulation constraints, physical parameters of the 5T2M array unit, and the occupied area of ​​the layout structure. In this embodiment, the physical parameters include the material properties, thermal conductivity, density, constant pressure heat capacity, and power consumption of each electronic component in the 5T2M array unit. The thermal simulation constraints include boundary conditions, initial conditions, heat sources, and solver setting data; boundary conditions include the maximum allowable temperature, temperature uniformity, and number of hot spot controls, initial conditions include initial temperature distribution, heat sources include maximum power consumption heat, and solver setting data include step size and convergence criteria.

[0066] In the embodiments of the present application, the occupied area of ​​the layout structure can be calculated based on the width and length of the layout structure.

[0067] S3. Obtain packaging materials of the 5T2M array unit, and construct a corresponding packaging layout according to the packaging materials and the layout structure; perform thermal simulation on the packaging layout using steps S2 and S3 to obtain a second temperature field distribution after packaging.

[0068] It should be noted that in step S3, the packaging material of the 5T2M array unit is first obtained, and then the corresponding packaging layout is constructed according to the packaging material and the layout structure. Then, the layout structure is thermally simulated according to steps S1 and S2 to obtain the following: Figure 6 The second temperature field distribution after packaging is shown in FIG. 1. In this embodiment, the packaging material may be filled epoxy resin, and the specification of the packaging layout may be 300um×400um×60um.

[0069] In an embodiment of the present application, the thermal conductivity of gallium phosphide GaP is 110W / (m·K), the density of gallium phosphide GaP is 4140kg / m³, and the constant-pressure heat capacity of gallium phosphide GaP is 430J / (kg·K). The thermal conductivity of gallium nitride GaN is 130W / (m·K), the density of gallium nitride GaN is 6070kg / m³, and the constant-pressure heat capacity of gallium nitride GaN is 490J / (kg·K). The thermal conductivity of the connecting wire is 400W / (m·K). The thermal conductivity of silicon dioxide SiO2, the density of silicon dioxide SiO2 rho (T) and the constant-pressure heat capacity can be set according to requirements. The thermal conductivity and density of epoxy resin can be set according to requirements. The thermal conductivity of the resistive layer is 4W / (m·K), and the constant-pressure heat capacity of the resistive layer is 600J / (kg·K).

[0070] It should be noted that the physical parameters of each electronic component in the 5T2M array unit can be found in Table 1.

[0071] Table 1 shows the material parameters of each electronic component in the 5T2M array unit.

[0072]

[0073] In the embodiment of the present application, the thermal simulation method of the storage-computing integrated array can be known through the first temperature field distribution and the second temperature field distribution that the temperature in the layout structure before packaging has almost no effect.

[0074] It should be noted that the temperature field distribution obtained by thermal simulation based on the geometric model constructed based on the layout structure of the storage-computing integrated array has low power consumption. Adding a layer of epoxy resin film on the layout structure can effectively protect it from external impact and vibration.

[0075] The present application provides a thermal simulation method for a storage-computing integrated array, including obtaining the layout structure of the storage-computing integrated array, and constructing a geometric model corresponding to the 5T2M array unit according to the layout structure using the solid and fluid heat transfer physical fields of the multi-physics field simulation software; obtaining thermal simulation constraints, physical parameters of the 5T2M array unit, and the occupied area of ​​the layout structure, and performing thermal simulation on the geometric model according to the physical parameters, thermal simulation constraints, and occupied area to obtain a first temperature field distribution before packaging; obtaining the packaging material of the 5T2M array unit, and constructing a corresponding packaging layout according to the packaging material and the layout structure; and performing thermal simulation on the packaging layout using steps S2 and S3 to obtain a second temperature field distribution after packaging. The thermal simulation method for the storage-computing integrated array constructs a corresponding geometric model through the layout structure of the storage-computing integrated array for thermal simulation, obtains a temperature field distribution, and knows the performance of the layout structure of the storage-computing integrated array according to the temperature field distribution, verifies the practicality of the layout structure of the storage-computing integrated array, and solves the technical problems of long signal transmission paths and long delay times in the layout and wiring of the existing storage-computing integrated architecture chips.

[0076] In one embodiment of the present application, obtaining the power consumption content in the physical parameters of the 5T2M array unit includes: obtaining electrical quantity data of each electronic component in the 5T2M array unit, and calculating the power consumption calculation data of the temperature field of the 5T2M array unit according to the electrical quantity data;

[0077] The power consumption calculation data of the 5T2M array unit temperature field calculated based on the electrical quantity data include:

[0078] According to the switching cycle, memristor resistance and memristor voltage in the electrical quantity data, the memristor power consumption when the memristor is turned on / off in the power consumption calculation data is obtained;

[0079] According to the output voltage and output current of the switch tube in the electrical quantity data, the static power consumption of the corresponding switch tube in the power consumption calculation data is obtained; according to the output voltage, output capacitance and switching frequency of the switch tube in the electrical quantity data, the dynamic power consumption of the corresponding switch tube in the power consumption calculation data is obtained;

[0080] The power consumption of the connecting line of the power consumption calculation data is obtained by calculating the switching cycle, the connecting line input voltage and the connecting line resistance in the electrical quantity data.

[0081] It should be noted that the first power consumption calculation formula is used to calculate the memristor power consumption when the memristor is turned on / off in the power consumption calculation data according to the switching cycle, memristor resistance and memristor voltage in the electrical quantity data; the second power consumption calculation formula is used to calculate the static power consumption of the corresponding switch tube in the power consumption calculation data according to the output voltage and output current of the switch tube in the electrical quantity data; the second power consumption calculation formula is used to calculate the dynamic power consumption of the corresponding switch tube in the power consumption calculation data according to the output voltage, output capacitance and switching frequency of the switch tube in the electrical quantity data; the third power consumption calculation formula is used to calculate the connection line power consumption of the power consumption calculation data according to the switching cycle, connection line input voltage and connection line resistance in the electrical quantity data. The first power consumption calculation formula is:

[0082]

[0083] The second power consumption calculation formula is: ; ; ;

[0084] The third power consumption calculation formula is:

[0085]

[0086]

[0087] Wherein, Q is the memristor power consumption, V is the memristor voltage, R is the memristor resistance, T is the switching period, P1 is the static power consumption, P is the dynamic power consumption, Vds is the output voltage of the switch tube; Coss is the output capacitance of the switch tube, f is the switching frequency, Ids is the output current of the switch tube, Un is the electron mobility, Cox is the equivalent capacitance of the oxide layer at the first end of the switch tube; W / L is the width-to-length ratio of the conductive channel; Vth is the threshold voltage, V1 is the input voltage of the connecting line, R1 is the connecting line resistance, ρ is the thermal conductivity of the connecting line; L is the length of the connecting line; A is the cross-sectional area of ​​the connecting line, and Q1 is the power consumption of the connecting line.

[0088] In the embodiment of the present application, the switching period T of the memristor is set to 10 ns, the memristor voltage is 1 mV, and the memristor resistance is 100 Ω. The memristor power consumption (on power consumption) is 1×10 -16 J. Set the memristor off switching period T to 50ns, the memristor voltage to 1mV, and the memristor resistance to 10000Ω, and the memristor power consumption (off power consumption) is 5×10 -18 J. It can be seen from this that the power consumption of the memristor is very small, and the impact on the device is very small and can be ignored.

[0089] In the embodiment of the present application, the output voltage Vds of the switch tube is set to 1mV, and the electron mobility Un is , the equivalent capacitance Cox of the oxide layer at the first end of the switch tube is , the channel width-to-length ratio W / L is 1, and the threshold voltage Vth is 0.7V. The output current Ids is obtained according to the formula of the leakage current in the linear region of the switch tube, and thus the static power consumption of the switch tube is obtained. The output capacitance Coss of the switch tube is set to , the switching frequency f is , thus the dynamic power consumption of the switch tube is 8.75×10 -9 J.

[0090] In the embodiment of the present application, the thermal conductivity of copper as the connecting wire is generally about 400 W / (m\cdotpK) at room temperature (20 degrees Celsius). The cross-sectional area of ​​the connecting wire is 10um×10um×2765um. The input voltage of the connecting wire is 1mV, and the duration is 60ns. The resistance of the connecting wire is 4.83875Ω according to the resistance formula. .

[0091] Embodiment three:

[0092] Figure 8 This is a flow chart of the steps of the method for constructing the layout structure of the storage-computation-in-one array described in an embodiment of the present application. Fig. 9 This is the overall diagram of the 512-bit array in the method for constructing the layout structure of the storage-computation-in-one array described in the embodiment of the present application. Fig.10 This is a top view of a 512-bit array in the method for constructing the layout structure of the storage-computation-in-one array described in an embodiment of the present application. Fig.11 This is an overall diagram of a 256-bit array in the method for constructing the layout structure of a storage-computation-in-one array described in an embodiment of the present application.

[0093] like Figure 8 As shown, the embodiment of the present application provides a method for constructing a layout structure of a storage-computation-in-one array, comprising the following steps:

[0094] S100. Obtaining the memory bit width data of the chip, the layout structure of the above-mentioned integrated storage and computing array, and the storage bit width of the layout structure;

[0095] S200. Determine the number of layout design rows and the number of layout structures contained in each row according to the video memory bit width data and the storage bit width;

[0096] S300. Construct a corresponding chip design layout according to the number of layout design rows and the number of layout structures.

[0097] It should be noted that the content of the layout structure of the integrated storage and computing array has been described in the first embodiment, and the content of the layout structure of the integrated storage and computing array will not be repeated in this embodiment. In this embodiment, if the display memory bit width data is 512 bits, it can be known from the first embodiment that the storage bit width of the layout structure constructed by the 5T2M array unit is 2 bits. If the number of layout structures contained in each row is 8, the number of layout design rows is 32. Therefore, the constructed row has 8 5T2M array units and there are 32 rows. Fig. 9 and Fig.10 If the memory bit width data is 256 bits, it can be seen from the first embodiment that the storage bit width of the layout structure constructed by the 5T2M array unit is 2 bits. If the number of layout structures contained in each row is 8, the number of layout design rows is 16. Therefore, the construction row has 8 5T2M array units and there are 16 rows. Fig.11 The chip design layout is shown.

[0098] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0099] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0100] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0101] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0102] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0103] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A layout structure of a storage-computation integrated array, applied to a 5T2M array unit based on a memristor, wherein the 5T2M array unit comprises a first memristor, a second memristor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a first word line terminal, a second word line terminal, an electrode terminal, a first bit line terminal, a second bit line terminal, a third bit line terminal and a fourth bit line terminal, characterized in that: The layout structure of the storage-computing integrated array includes a layout base and a 5T2M array unit arranged on the layout base; The second switch tube and the fourth switch tube are placed on the leftmost side of the layout base, the second switch tube is located on the upper side of the fourth switch tube, the first switch tube is arranged on the layout base on the right side of the second switch tube, the third switch tube is arranged on the layout base on the right side of the fourth switch tube, the fifth switch tube is arranged on the layout base on the right side of the third switch tube, and the fifth switch tube is located in the middle of the rightmost side of the layout base; The third end of the first switch tube is connected to the first bit line end through a connecting line, and the first bit line end is placed horizontally at the uppermost side of the layout base; the third end of the second switch tube is connected to the second bit line end through a connecting line, and the second bit line end is placed at the lower side of the first bit line end; the first end of the fifth switch tube is connected to the electrode end through a connecting line, and the electrode end is placed at the lower side of the second bit line end; the third end of the third switch tube is connected to the third bit line end through a connecting line, and the third bit line end is placed at the lower side of the electrode end; the third end of the fourth switch tube is connected to the fourth bit line end through a connecting line, and the fourth bit line end is placed at the lower side of the third bit line end; the first end of the second switch tube and the first end of the fourth switch tube are both connected to the second word line end through a connecting line, and the second word line end is placed vertically at the uppermost side of the layout base. left side; the first end of the first switch tube and the first end of the third switch tube are both connected to the first word line end through a connecting line, and the first word line end is placed on the right side of the second word line end; the second end of the first switch tube and the second end of the fifth switch tube are both connected to the positive electrode of the first memristor through a connecting line, and the first memristor is placed on the left side of the first switch tube; the second end of the second switch tube is connected to the negative electrode of the first memristor through a connecting line, and the negative electrode of the first memristor is placed on the right side of the second switch tube; the second end of the third switch tube is connected to the third end of the fifth switch tube and then to the positive electrode of the second memristor, and the positive electrode of the second memristor is placed on the left side of the third switch tube; the third end of the fourth switch tube is connected to the negative electrode of the second memristor, and the negative electrode of the second memristor is placed on the right side of the fourth switch tube.

2. The layout structure of the storage-computation-in-one array according to claim 1, characterized in that: The spacing distance between two adjacent switch tubes on the layout base is the first distance; and / or the distance between two adjacent connection lines on the layout base is at least the second distance.

3. The layout structure of the storage-computation-in-one array according to claim 1 or 2, characterized in that: The connecting wire is a copper wire, a silver wire or an aluminum wire; and / or the cross-sectional area of ​​the connecting wire is 10um×10um.

4. The layout structure of the storage-computation-in-one array according to claim 1 or 2, characterized in that: The electrode specifications of the first switch tube, the second switch tube, the third switch tube, the fourth switch tube and the fifth switch tube are all 10um×10um×10um; and / or, the substrates of the first switch tube, the second switch tube, the third switch tube, the fourth switch tube and the fifth switch tube are all P-type substrates; and / or, the doping of the first switch tube, the second switch tube, the third switch tube, the fourth switch tube and the fifth switch tube are all N-type doping; and / or, the specifications of the oxide insulation layer of the first switch tube, the second switch tube, the third switch tube, the fourth switch tube and the fifth switch tube are all 50um×50um×10um; and / or, the lower layer of the oxide insulation layer of the first switch tube, the second switch tube, the third switch tube, the fourth switch tube and the fifth switch tube is a conductive channel; and / or, the specifications of the resistive switching layer of the first memristor and the second memristor are all 10um×10um×10um.

5. The layout structure of the storage-computation-in-one array according to claim 4 is characterized in that: The specifications of the P-type substrate are 300um×400um×100um; and / or, the specifications of the N-type doping are 50um×50um×10um; and / or, the specifications of the conductive channel are 50um×50um×5um.

6. A thermal simulation method for a storage-computation integrated array, applied to a 5T2M array unit based on a memristor, characterized in that: The thermal simulation method comprises the following steps: S1. Obtaining the layout structure of the storage-computation integrated array according to any one of claims 1 to 5, and constructing a geometric model corresponding to the 5T2M array unit using the solid and fluid heat transfer physical fields of the multi-physics field simulation software according to the layout structure; S2. Obtain thermal simulation constraints, physical parameters of the 5T2M array unit, and the occupied area of ​​the layout structure, perform thermal simulation on the geometric model according to the physical parameters, the thermal simulation constraints, and the occupied area, and obtain a first temperature field distribution before packaging; S3. Obtain packaging materials for the 5T2M array unit, and construct a corresponding packaging layout according to the packaging materials and the layout structure; perform thermal simulation on the packaging layout using steps S2 and S3 to obtain a second temperature field distribution after packaging.

7. The thermal simulation method of the storage-computation-in-one array according to claim 6, characterized in that: Acquiring the power consumption content in the physical parameters of the 5T2M array unit includes: acquiring electrical quantity data of each electronic component in the 5T2M array unit, and calculating power consumption calculation data of the temperature field of the 5T2M array unit according to the electrical quantity data.

8. The thermal simulation method of the storage-computation-in-one array according to claim 7, characterized in that: The power consumption calculation data of the 5T2M array unit temperature field calculated according to the electrical quantity data includes: According to the switching cycle, the memristor resistance and the memristor voltage in the electrical quantity data, the memristor power consumption when the memristor is turned on / off in the power consumption calculation data is obtained; According to the output voltage and output current of the switch tube in the electrical quantity data, the static power consumption of the corresponding switch tube in the power consumption calculation data is obtained; according to the output voltage, output capacitance and switching frequency of the switch tube in the electrical quantity data, the dynamic power consumption of the corresponding switch tube in the power consumption calculation data is obtained; The power consumption of the connecting line of the power consumption calculation data is obtained by calculating the switching cycle, the connecting line input voltage and the connecting line resistance in the electrical quantity data.

9. The thermal simulation method of the storage-computation-in-one array according to claim 6, characterized in that: The physical parameters also include material properties, thermal conductivity, density and constant-pressure heat capacity of each electronic component in the 5T2M array unit; and / or, the thermal simulation constraints include boundary conditions, initial conditions, heat sources and solver setting data; the boundary conditions include maximum allowable temperature, temperature uniformity and number of hot spot controls, the initial conditions include initial temperature distribution, the heat source includes maximum power consumption heat, and the solver setting data includes step size and convergence criteria.

10. A method for constructing a layout structure of a storage-computation integrated array, characterized in that: The following steps are involved: Obtaining the memory bit width data of the chip, the layout structure of the integrated storage and computing array as claimed in any one of claims 1 to 5, and the storage bit width of the layout structure; Determine the number of layout design rows and the number of layout structures contained in each row according to the video memory bit width data and the storage bit width; A corresponding chip design layout is constructed according to the number of layout design rows and the number of layout structures.

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