Memory and its operating methods, memory systems and electronic devices

Abstract

This disclosure presents a memory, its operation method, a memory system, and an electronic device. The memory includes peripheral circuitry; the peripheral circuitry includes: a first register circuit configured to store a plurality of initial refresh rates; the plurality of initial refresh rates correspond one-to-one with a plurality of initial temperature segments; a temperature sensing circuit configured to generate a temperature signal based on the sensed temperature; and a control logic circuit configured to determine a target configured refresh rate based on the temperature signal and a configuration mapping table, adjusting the target initial refresh rate from the plurality of initial refresh rates to the target configured refresh rate; the configuration mapping table includes a plurality of configured temperature segments and a plurality of configured refresh rates, with each configured temperature segment corresponding one-to-one with the plurality of configured refresh rates.

Description

Technical Field

[0001] This disclosure relates to semiconductor technology, and includes, but is not limited to, a memory and its operation method, a memory system, and an electronic device. Background Technology

[0002] Semiconductor memories are classified into volatile memories and non-volatile memories based on whether they retain stored data when power is off. Volatile memories, which lose data when power is off, can include Static Random-Access Memory (SRAM) and Dynamic Random-Access Memory (DRAM).

[0003] Volatile memory requires periodic refreshes to retain the data stored in its cells. As temperature rises, the data retention characteristics of the cells deteriorate. Therefore, how to adjust the refresh frequency (also known as the refresh rate) of volatile memory based on temperature changes has become a pressing technical problem. Summary of the Invention

[0004] In view of the above, embodiments of the present disclosure provide a memory, an operation method thereof, a memory system, and an electronic device.

[0005] In a first aspect, embodiments of this disclosure provide a memory, the memory including peripheral circuitry; the peripheral circuitry includes:

[0006] A first register circuit is configured to store a plurality of initial refresh rates; wherein the plurality of initial refresh rates correspond one-to-one with a plurality of initial temperature ranges.

[0007] A temperature sensing circuit, configured to: sense the temperature of the memory and generate a temperature signal based on the sensed temperature;

[0008] A control logic circuit is configured to: determine a target configuration refresh rate based on the temperature signal and a configuration mapping table, and adjust the target initial refresh rate among the plurality of initial refresh rates to the target configuration refresh rate; wherein the configuration mapping table includes a plurality of configuration temperature segments and a plurality of configuration refresh rates, and the plurality of configuration temperature segments and the plurality of configuration refresh rates correspond one-to-one.

[0009] In some embodiments, the peripheral circuitry further includes:

[0010] A second register circuit is configured to store the configuration mapping table;

[0011] The control logic circuit is specifically configured to: read the second register circuit based on the temperature signal and determine the target configuration refresh rate.

[0012] In some embodiments, the configuration mapping table includes multiple sub-configuration mapping tables, which are used to record the correspondence between the configuration temperature range and the configuration refresh rate; the peripheral circuit further includes:

[0013] An address decoding circuit is configured to: decode and generate a target address based on the temperature signal; wherein the target address is used to indicate the physical address of the target sub-configuration mapping table in the plurality of sub-configuration mapping tables;

[0014] The control logic circuit is specifically configured to: obtain the target sub-configuration mapping table based on the target address, and determine the target configuration refresh rate.

[0015] In some embodiments, the first register circuit is further configured to:

[0016] Update the target initial refresh rate to the target configured refresh rate;

[0017] Send the target configuration refresh rate to the memory controller.

[0018] In some embodiments, the peripheral circuitry further includes:

[0019] An electric fuse circuit, the electric fuse circuit being configured to store the configuration mapping table;

[0020] The control logic circuit is specifically configured to: read the configuration mapping table in the electric fuse circuit and save the read configuration mapping table to the second register circuit.

[0021] In some embodiments, the initial refresh rate includes a base refresh rate and an initial multiplier, and the initial multipliers of any two of the plurality of initial refresh rates are different; the configured refresh rate includes the base refresh rate and a configured multiplier, and the configured multipliers of any two of the plurality of configured refresh rates are different.

[0022] The control logic circuit is specifically configured to: determine the configuration multiple of the target configuration refresh rate based on the temperature signal and the configuration mapping table;

[0023] The first register circuit is further configured to update the initial multiple of the target initial refresh rate to the configuration multiple of the target configured refresh rate.

[0024] In some embodiments, the plurality of initial temperature segments include N initial temperature segments, where N is an integer greater than 1; the configuration mapping table includes N configuration temperature segments; wherein the minimum temperature of the i-th initial temperature segment is different from the minimum temperature of the i-th configuration temperature segment; and / or, the maximum temperature of the i-th initial temperature segment is different from the maximum temperature of the i-th configuration temperature segment; i is an integer greater than or equal to 1 and less than or equal to N.

[0025] In some embodiments, the control logic circuit is further configured to:

[0026] Enter refresh mode based on the current refresh command sent by the memory controller;

[0027] The system enters the refresh mode based on the next refresh command sent by the memory controller; wherein the target configured refresh rate is used to indicate the time interval between the next refresh command and the current refresh command.

[0028] In some embodiments, the memory is further configured to:

[0029] After the memory usage time is greater than or equal to a preset time, at least one of the configuration temperature segments in the configuration mapping table is updated.

[0030] Secondly, embodiments of this disclosure also provide an operation method for a memory, wherein the memory has peripheral circuitry; the peripheral circuitry includes a first register circuit configured to store a plurality of initial refresh rates; wherein the plurality of initial refresh rates correspond one-to-one with a plurality of initial temperature ranges; the operation method includes:

[0031] The temperature of the memory is sensed, and a temperature signal is generated based on the sensed temperature;

[0032] The target configuration refresh rate is determined based on the temperature signal and the configuration mapping table; wherein, the configuration mapping table includes multiple configuration temperature segments and multiple configuration refresh rates, and the multiple configuration temperature segments and the multiple configuration refresh rates correspond one-to-one;

[0033] Adjust the target initial refresh rate among the plurality of initial refresh rates to the target configured refresh rate.

[0034] In some embodiments, the peripheral circuitry further includes a second register circuit configured to store the configuration mapping table;

[0035] The step of determining the target configuration refresh rate based on the temperature signal and the configuration mapping table includes:

[0036] Based on the temperature signal, the second register circuit is read to determine the target configuration refresh rate.

[0037] In some embodiments, the configuration mapping table includes multiple sub-configuration mapping tables, which are used to record the correspondence between the configuration temperature range and the configuration refresh rate;

[0038] The step of reading the second register circuit based on the temperature signal to determine the target configuration refresh rate includes:

[0039] Based on the temperature signal, a target address is generated by decoding; wherein, the target address is used to indicate the physical address of the target sub-configuration mapping table in the plurality of sub-configuration mapping tables;

[0040] Based on the target address, obtain the target sub-configuration mapping table and determine the target configuration refresh rate.

[0041] In some embodiments, the operating method further includes:

[0042] Update the target initial refresh rate to the target configured refresh rate;

[0043] Send the target configuration refresh rate to the memory controller.

[0044] In some embodiments, the peripheral circuit further includes an electric fuse circuit configured to store the configuration mapping table; the operation method further includes:

[0045] The configuration mapping table in the electric fuse circuit is read, and the read configuration mapping table is saved to the second register circuit.

[0046] In some embodiments, the initial refresh rate includes a base refresh rate and an initial multiplier, and the initial multipliers of any two of the plurality of initial refresh rates are different; the configured refresh rate includes the base refresh rate and a configured multiplier, and the configured multipliers of any two of the plurality of configured refresh rates are different.

[0047] The step of determining the target configuration refresh rate based on the temperature signal and the configuration mapping table includes:

[0048] The configuration multiple of the target configuration refresh rate is determined based on the temperature signal and the configuration mapping table;

[0049] The step of adjusting the target initial refresh rate to the target configured refresh rate includes:

[0050] Update the initial multiple of the target initial refresh rate to the configuration multiple of the target configured refresh rate.

[0051] In some embodiments, the plurality of initial temperature segments include N initial temperature segments, where N is an integer greater than 1; the configuration mapping table includes N configuration temperature segments; wherein the minimum temperature of the i-th initial temperature segment is different from the minimum temperature of the i-th configuration temperature segment; and / or, the maximum temperature of the i-th initial temperature segment is different from the maximum temperature of the i-th configuration temperature segment; i is an integer greater than or equal to 1 and less than or equal to N.

[0052] In some embodiments, the operating method further includes:

[0053] Enter refresh mode based on the current refresh command sent by the memory controller;

[0054] The system enters the refresh mode based on the next refresh command sent by the memory controller; wherein the target configured refresh rate is used to indicate the time interval between the next refresh command and the current refresh command.

[0055] In some embodiments, the operating method further includes:

[0056] After the memory usage time is greater than or equal to a preset time, at least one of the configuration temperature segments in the configuration mapping table is updated.

[0057] Thirdly, embodiments of this disclosure also provide a memory system, the memory system comprising:

[0058] One or more memories as described in any of the embodiments of the first aspect of this disclosure;

[0059] A memory controller is coupled to the memory and configured to control the memory.

[0060] Fourthly, embodiments of this disclosure also provide an electronic device, including a memory system as described in the above embodiments.

[0061] In this embodiment, a temperature sensing circuit senses the temperature of the memory and generates a temperature signal based on the sensed temperature. A control logic circuit then determines the target configuration refresh rate based on the temperature signal and a configuration mapping table, and adjusts the initial target refresh rate to the target configuration refresh rate. This achieves the following: First, it generates the expected refresh rate based on the memory's data retention characteristics, preventing data loss and ensuring data reliability. Second, the refresh rate can be flexibly adjusted based on the memory's data retention characteristics, avoiding frequent refresh operations, thereby reducing power consumption and increasing the memory's lifespan. Third, without changing the circuit design, the temperature range can be flexibly configured, and a custom configuration mapping table can be created to meet the memory's data retention requirements. Attached Figure Description

[0062] Figure 1 This is a schematic diagram of a system according to an embodiment of the present disclosure;

[0063] Figure 2 This is a schematic diagram of a dynamic random access memory according to an embodiment of the present disclosure;

[0064] Figure 3 This is a schematic diagram illustrating the change of leakage current with temperature according to an embodiment of the present disclosure;

[0065] Figure 4 This is a schematic diagram illustrating the change of data retention time with temperature according to embodiments of the present disclosure;

[0066] Figure 5 This is a schematic diagram illustrating the change of the initial refresh rate with the initial temperature range according to an embodiment of this disclosure;

[0067] Figure 6 This is a schematic diagram of a mode register according to an embodiment of the present disclosure;

[0068] Figure 7a and Figure 7b This is a schematic diagram of a memory according to an embodiment of the present disclosure;

[0069] Figure 8 This is a schematic diagram illustrating the variation of the configuration refresh rate with the configuration temperature range according to an embodiment of this disclosure;

[0070] Figure 9 This is a flowchart illustrating a method of operating a memory according to an embodiment of the present disclosure;

[0071] Figure 10 This is a schematic diagram illustrating an adjustment of the refresh rate according to an embodiment of this disclosure;

[0072] Figure 11 This is a flowchart illustrating an algorithm for generating a configuration mapping table according to an embodiment of the present disclosure. Detailed Implementation

[0073] To facilitate understanding of this disclosure, exemplary embodiments of the disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

[0074] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of the actual embodiments, nor well-known functions and structures, may be described herein.

[0075] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0076] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0077] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0078] Figure 1 This is a schematic diagram illustrating a system 1 according to an embodiment of the present disclosure. System 1 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0079] like Figure 1As shown, system 1 may include a host and a memory system 30, the memory system 30 having one or more memories 20 and a memory controller 10. The host may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host may be configured to send data to or receive data from the memory 20. The memory controller 10 is coupled to the memory 20 and the host and is configured to control the memory 20. The memory controller 10 may manage the data stored in the memory 20 and communicate with the host.

[0080] The memory controller 10 can be configured to control the operation of the memory 20, such as read, erase, write, and refresh operations. In some embodiments, the memory controller 10 is also configured to process error correction codes (ECCs) regarding data read from or written to the memory 20. The memory controller 10 can also perform any other suitable functions, such as formatting the memory 20.

[0081] In some specific embodiments, the memory controller 10 and one or more memories 20 can be integrated into various types of storage devices. For example, the memory controller 10 can be integrated into the northbridge of a computer motherboard or directly into the computer CPU, and multiple memories 20 can be integrated into a memory module. In other words, the memory system 30 can be implemented and packaged into different types of terminal electronic products.

[0082] The memory controller 10 can send data to or receive data from the host, and can send commands (CMD) and addresses (ADDR) to the memory 20. The memory controller 10 may include a command generator 110, an address generator 120, a device interface 130, and a host interface 140. The host interface 140 can receive commands (CMD) and addresses (ADDR) from the host. The command generator 110 can generate access commands, refresh commands, etc., by decoding the commands (CMD) received from the host, and can provide access commands and refresh commands to the memory 20 through the device interface 130. An access command may be a signal instructing the memory 20 to write or read data by accessing a row of the memory cell array 220 corresponding to the address ADDR. A refresh command may be a signal instructing the memory 20 to read and rewrite data by accessing a row of the memory cell array 220 corresponding to the refresh address ADDR.

[0083] The address generator 120 in the memory controller 10 can generate the row and column addresses to be accessed in the memory cell array 220 by decoding the address ADDR received from the host interface 140. Furthermore, the memory 20 can generate addresses of the memory banks to be accessed when the memory cell array 220 comprises multiple banks.

[0084] Furthermore, the memory controller 10 can control memory operations such as writing and reading by providing various signals to the memory 20 via the device interface 130. For example, the memory controller 10 can provide a write command to the memory 20. The write command is used to instruct the memory 20 to perform a write operation to store data in the memory 20. In some embodiments, the memory 20 includes a memory cell array 220 and peripheral circuitry 210; wherein the memory cell array 220 includes a plurality of memory banks, each memory bank includes a plurality of memory blocks, each memory block includes a plurality of memory cell rows and a plurality of memory cell columns, each memory cell row is coupled to a corresponding word line, and each memory cell column is coupled to a corresponding bit line. The peripheral circuitry 210 can write data to or read data from the memory cell array 220 based on the command CMD and address ADDR received from the memory controller 10, or it can provide the row decoder and column decoder with the control signal CTRL for refreshing the memory cells included in the memory cell array 220. In other words, the peripheral circuitry 210 can perform all operations to process the data in the memory cell array 220. The peripheral circuit 210 may include: control circuits corresponding to each memory block, such as a sensing amplifier (SA) and a word-line driver (WLD); control circuits corresponding to each memory bank, such as a row decoder and a column decoder; and control circuits corresponding to all memory banks, such as a command buffer, a command decoder, an address buffer, a data input / output buffer, and a mode register.

[0085] The memory 20 can be random access memory (RAM), such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), double data rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), etc. The following explanation uses DRAM as an example only.

[0086] Figure 2This is a schematic diagram illustrating a dynamic random access memory according to an embodiment of the present disclosure. (Refer to...) Figure 2 As shown, the Dynamic Random Access Memory (DRAM) includes at least one DRAM chip, each DRAM chip including a memory cell array. The memory cell array includes multiple memory cells 201 arranged in an array. Each memory cell 201 includes a transistor T and a capacitor C. The main working principle of the memory cell is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The memory cells are arranged in an array, which can be considered a typical mesh structure. For details on this mesh structure, please refer to the following text. Figure 7b The memory cell array uses rows and columns to specify addresses. By specifying the intersection of rows and columns (by specifying the row address and column address of the DRAM), the memory controller can independently access each memory cell in the DRAM chip and perform read, write, or refresh operations on the data stored therein.

[0087] The leakage current of DRAM memory cells is directly proportional to temperature; that is, the leakage current increases as the temperature rises. Figure 3 As shown. Because the charge stored in a memory cell is limited, the data retention time of the memory cell is inversely proportional to temperature. For example, the data retention time at 40℃ is t1, and at 80℃ it is t2, where t2 is less than t1. Figure 4 As shown. To ensure data reliability, DRAM requires periodic refresh operations to maintain the data stored in the memory cells.

[0088] There are two methods for periodic refresh operations: one is where the memory controller periodically issues refresh commands, and the memory controller is responsible for maintaining the data (also known as automatic refresh); the other is where the memory internally generates refresh signals (also known as self-refresh). In automatic refresh operations, the time interval between two refresh commands issued by the memory controller is usually temperature-dependent to ensure that the data remains unchanged. If the time interval between two refresh commands is too short, the refresh command will take too much time, thus reducing the time for normal read and write operations. Therefore, the time interval should be updated according to the temperature, which not only preserves the data but also provides more time for normal read and write operations. In addition, it also reduces the refresh frequency by adjusting for temperature changes (e.g., a decrease in temperature) to reduce power consumption.

[0089] The memory controller updates the time interval between two refresh commands based on the refresh rate registered in the mode register in the memory. Specifically, the memory updates the refresh rate according to temperature changes, the mode register sends the updated refresh rate to the memory controller, and the memory controller sends refresh commands to the memory based on the updated refresh rate. In essence, the time interval between two refresh commands is communicated to the memory controller by the mode register.

[0090] The mode register stores multiple initial refresh rates, each corresponding to a different initial temperature range. For example, if the memory's operating temperature range is -25℃ ≤ T ≤ 80℃, this range can be divided into multiple initial temperature ranges based on these initial temperature values. Each initial temperature range corresponds to an initial refresh rate, and different initial temperature ranges correspond to different initial refresh rates. For example, refer to... Figure 5 As shown, 16 initial temperature values ​​are selected based on the operating temperature range of the memory. For example, the initial temperature value T... e1 T e2 ... T e16 It can be divided into 17 initial temperature zones.

[0091] According to the JEDEC (Joint Electron Device Engineering Council) protocol, the mode register stores 17 initial refresh rates, such as low temperature limit, refresh rate 8x, ..., high temperature limit, etc. Figure 6 As shown, each initial refresh rate corresponds to a refresh rate code, and different initial refresh rates correspond to different refresh rate codes. For example, when the memory temperature changes to the second initial temperature range, the mode register sends the refresh rate code 5'b00001 corresponding to the initial refresh rate of 8x to the memory controller, and the memory controller will perform an automatic refresh operation on the memory at an initial refresh rate of 8x.

[0092] Since multiple initial temperature ranges are fixed, it is difficult to adjust the range of the initial temperature ranges. Therefore, the initial refresh rate corresponding to all temperatures within the same initial temperature range is also fixed. However, for different memories, the data retention characteristics of their memory cells at a certain temperature may vary, and using a fixed initial temperature range will make it difficult to produce the expected refresh rate.

[0093] Figure 7a and Figure 7b This is a schematic diagram illustrating a memory 300 according to an embodiment of the present disclosure. (Refer to...) Figure 7a and Figure 7bAs shown, the memory 300 includes peripheral circuitry 310; peripheral circuitry 310 includes:

[0094] The first register circuit 350 is configured to store multiple initial refresh rates; wherein the multiple initial refresh rates correspond one-to-one with multiple initial temperature ranges.

[0095] Temperature sensing circuit 330 is configured to: sense the temperature of memory 300 and generate a temperature signal based on the sensed temperature;

[0096] The control logic circuit 340 is configured to: determine the target configuration refresh rate based on the temperature signal and the configuration mapping table, and adjust the target initial refresh rate among multiple initial refresh rates to the target configuration refresh rate; wherein, the configuration mapping table includes multiple configuration temperature segments and multiple configuration refresh rates, and the multiple configuration temperature segments and multiple configuration refresh rates correspond one-to-one.

[0097] In this embodiment of the disclosure, the memory 300 includes, but is not limited to, DRAM, Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), Graphics Double Data Rate (GDDR), and High Bandwidth Memory (HBM).

[0098] Reference Figure 7b As shown, the memory 300 includes multiple word lines 322 and multiple bit lines 323. The peripheral circuitry 310 is coupled to the memory cell array 320 via the word lines 322 and bit lines 323. The memory cell array 320 includes multiple memory cells 321 arranged in an array. Each memory cell 321 includes a transistor 324 and an energy storage element 325 coupled to the transistor 324. The transistor 324 includes a semiconductor pillar 326, a gate dielectric layer 327, and a gate 328. The semiconductor pillar includes a source, a drain, and a channel between the source and drain. The gate dielectric layer 327 covers the sidewalls of the channel. The gate 328 is in contact with at least one sidewall of the gate dielectric layer 327. Word lines 322 are coupled to the gates of memory cells 321 located in the same row, and bit lines 323 are coupled to the semiconductor pillars (e.g., the drains of the semiconductor pillars) of memory cells 321 located in the same column.

[0099] In one specific embodiment, the storage cell 321 can be a volatile storage cell, such as a DRAM storage cell, and the energy storage element 325 can be a capacitor. Of course, in other embodiments, the storage cell 321 can be a phase-change storage cell, and the energy storage element 325 can be a phase-change storage layer; or, the storage cell 321 can also be a ferroelectric storage cell, and the energy storage element 325 can be a ferroelectric storage layer; this disclosure does not limit this.

[0100] The first register circuit 350 may store multiple initial refresh rates, which correspond to multiple initial temperature segments. These multiple initial temperature segments are divided based on at least one initial temperature value. Each initial temperature segment corresponds to an initial refresh rate, and different initial temperature segments correspond to different initial refresh rates. The first register circuit 350 includes, but is not limited to, a mode register.

[0101] For example, the first register circuit 350 stores 17 initial refresh rates, such as low temperature limit, refresh rate 8x, ..., high temperature limit, etc. Figure 6 As shown. The 17 initial refresh rates correspond to 17 initial temperature segments, which are divided based on 16 initial temperature values. For example, the initial temperature value T... e1 T e2 ... T e16 Each initial refresh rate corresponds to a refresh rate code, and different initial refresh rates correspond to different refresh rate codes.

[0102] The refresh rate refers to the frequency at which data stored in memory is read out and rewritten. Periodically reading and rewriting data in memory keeps the leakage current in the energy storage components (e.g., capacitors) used to store data low, thus preventing problems caused by excessive leakage current that cannot distinguish between logic values ​​"0" and "1," and ensuring the reliability of the data stored in memory. Generally speaking, the higher the operating temperature of the memory, the faster the leakage current in the energy storage components used to store data; therefore, the higher the memory temperature, the higher the corresponding refresh rate.

[0103] It should be noted that the multiple initial refresh rates stored in the first register circuit 350 are based on the JEDEC protocol and are typically written into each die (ultimately packaged as a memory) during packaging. These multiple initial refresh rates and their corresponding initial temperature ranges are fixed, making it difficult to adapt to the data retention characteristics of different memories. Therefore, the configuration mapping table set in this embodiment can generate the expected refresh rate based on the memory's data retention characteristics to meet the memory's data retention requirements. The configuration mapping table will be described in detail below; for brevity, it will not be repeated here.

[0104] The temperature sensing circuit 330 can sense the temperature of the memory 300 and output a temperature signal based on the sensed temperature. In one embodiment, the temperature sensing circuit 330 includes a temperature sensor that can convert an analog temperature signal into a digital temperature signal and send the digital temperature signal to the control logic circuit 340. The temperature signal output by the temperature sensor can be a voltage signal corresponding to the sensed temperature, and there can be one or more temperature sensors. Although this embodiment describes the case where the temperature sensing circuit 330 is located inside the memory 300, the temperature sensing circuit 330 can also be located outside the memory 300 and sense the temperature of the memory 300.

[0105] It should be noted that the operating temperature range of the memory can be divided into multiple temperature segments, and the temperature signals corresponding to different temperatures can be the same or different. For example, if the first temperature and the second temperature belong to the same temperature segment, then the temperature signals corresponding to the first temperature and the second temperature can be the same; conversely, if the first temperature and the second temperature belong to different temperature segments, then the temperature signals corresponding to the first temperature and the second temperature can be different.

[0106] In practical applications, at least one configuration temperature value can be selected based on the operating temperature range of the memory. Multiple configuration temperature segments can then be defined based on these values, each corresponding to a different configuration refresh rate. The selection of the configuration temperature value can be based on the memory's own data retention characteristics. When multiple configuration temperature values ​​are selected, at least one of these values ​​can differ from the initial temperature value mentioned above.

[0107] For example, selecting 16 configuration temperature values ​​can divide the temperature into 17 configuration temperature ranges, such as the configuration temperature range T in Table 1. c1 T c2 ... T c9 ... T c16 and T c17 The 17 configured temperature ranges correspond to 17 configured refresh rates, for example, the configured refresh rates RM1, RM2, ..., RM9, ..., RM in Table 1. 16 and RM 17 .

[0108] In a specific example, the 16 configuration temperature values ​​are 25℃, 30℃, 35℃, 40℃, 42℃, 45℃, 48℃, 50℃, 52℃, 55℃, 60℃, 65℃, 70℃, 75℃, 80℃, and 85℃. It should be noted that the selection of configuration temperature values ​​can be determined based on the characteristics of the memory's leakage current changing with temperature. For example, if the memory's leakage current changes drastically at a certain temperature, that temperature can be determined as the configuration temperature value. The above values ​​are merely examples to convey this disclosure to those skilled in the art, and the selection of configuration temperature values ​​is not limited to these.

[0109] The control logic circuit 340 can receive a temperature signal, determine the target configuration refresh rate based on the received temperature signal and the configuration mapping table, and adjust the initial refresh rate corresponding to the temperature signal (i.e., the target initial refresh rate) to the target configuration refresh rate. The mode register sends the refresh rate code corresponding to the target configuration refresh rate to the memory controller, and the memory controller performs an automatic refresh operation on the memory at the target configuration refresh rate. Here, the target configuration refresh rate and the target initial refresh rate can be the same or different.

[0110] For example, refer to Figure 6 and Figure 8 As shown, when the temperature sensing circuit 330 senses that the temperature of the memory 300 is greater than the configured temperature value T... e2x And less than or equal to the initial temperature value T e2 When the temperature is in the second initial temperature range (i.e., if no configuration mapping table is set), the control logic circuit 340 determines the target initial refresh rate to be 8x based on this temperature. The first register circuit 350 sends the refresh rate code 5'b00001 corresponding to the refresh rate of 8x to the memory controller. The memory controller will then perform an automatic refresh operation on the memory 300 at a refresh rate of 8x. However, the refresh rate of 8x corresponding to this temperature may be insufficient to retain the data stored in the memory 300, leading to data loss and reduced reliability of the memory 300.

[0111] For example, refer to Figure 6 and Figure 8 As shown, when the temperature sensing circuit 330 senses that the temperature of the memory 300 is greater than the configured temperature value T... e2x And less than or equal to the configured temperature value T e3xWhen the temperature is in the third configuration temperature range, if a configuration mapping table is set, the control logic circuit 340 determines the configuration refresh rate to be RM3 based on the temperature and the configuration mapping table. For example, RM3 can be a refresh rate of 6x. The first register circuit 350 sends the refresh rate code 5'b00010 corresponding to the refresh rate of 6x to the memory controller. The memory controller will perform an automatic refresh operation on the memory 300 at a refresh rate of 6x. In this example, the target configuration refresh rate is different from the target initial refresh rate, which can avoid data loss and improve the reliability of the memory 300.

[0112] For example, when the temperature sensing circuit 330 senses that the temperature of the memory 300 is greater than the initial temperature value T e1 And less than or equal to the configured temperature value T e2x If a configuration mapping table is set, the control logic circuit 340 determines the configuration refresh rate as RM2 based on the temperature and the configuration mapping table. For example, RM2 can be a refresh rate of 8x. The first register circuit 350 sends the refresh rate code 5'b00001 corresponding to the refresh rate of 8x to the memory controller. The memory controller will perform an automatic refresh operation on the memory 300 at the configuration refresh rate of 8x. In this example, the target configuration refresh rate and the target initial refresh rate can be the same.

[0113] It is understandable that the temperature value T is configured in the example above. e2x Compared to the initial temperature value T e2 Shift left (e.g., T) e1 <T e2x <T e2 When the temperature change of memory 300 is greater than the configured temperature value T, e2x And less than or equal to the initial temperature value T e2 At this time, based on the configuration mapping table, automatic refresh operations can be performed at an increased refresh rate, avoiding data loss and improving the reliability of the memory 300. In other examples, the configuration temperature value T... e2x Compared to the initial temperature value T e2 Shift right (e.g., T) e2 <T e2x <T e3 When the temperature change of memory 300 is greater than the initial temperature value T e2 And less than or equal to the configured temperature value T e2x At the same time, based on the configuration mapping table, automatic refresh operation can be performed at a reduced refresh rate, which can not only avoid data loss, but also provide more time for normal read and write operations, and avoid the increase in power consumption caused by frequent refresh, that is, reduce power consumption. The selection of the configuration temperature value can be determined based on the data retention characteristics of the memory itself to produce the expected refresh rate, thereby meeting the data retention requirements of the memory. This disclosure does not limit this.

[0114] Table 1 Configuration Mapping Table

[0115]

[0116] It should be noted that the peripheral circuit 310 in this embodiment may also include other circuits known in the art, such as a sensing amplifier circuit, a word line driver circuit, a row decoder, a column decoder, a data input / output buffer, etc. For the sake of brevity, Figure 7a Not shown in the image.

[0117] In practical applications, different configuration mapping tables can be customized for different types of memory, increasing the flexibility of refresh rate adjustment. For example, before the memory leaves the factory, R&D personnel develop and design different configuration mapping tables for different types of memory and write (also known as programming) these configuration mapping tables into the memory.

[0118] In this embodiment, a temperature sensing circuit senses the temperature of the memory and generates a temperature signal based on the sensed temperature. A control logic circuit then determines the target configuration refresh rate based on the temperature signal and a configuration mapping table, and adjusts the initial target refresh rate to the target configuration refresh rate. This achieves the following: First, it generates the expected refresh rate based on the memory's data retention characteristics, preventing data loss and ensuring data reliability. Second, the refresh rate can be flexibly adjusted based on the memory's data retention characteristics, avoiding frequent refresh operations, thereby reducing power consumption and increasing the memory's lifespan. Third, without changing the circuit design, the temperature range can be flexibly configured, and a custom configuration mapping table can be created to meet the memory's data retention requirements.

[0119] In some embodiments, the peripheral circuit 310 further includes a second register circuit 360, which is configured to store a configuration mapping table;

[0120] The control logic circuit 340 is specifically configured to: read the second register circuit 360 based on the temperature signal and determine the target configuration refresh rate.

[0121] In this embodiment, the configuration mapping table can be stored in the second register circuit 360. The control logic circuit 340 reads the second register circuit 360 based on the received temperature signal to determine the target configuration refresh rate. The second register circuit 360 includes, but is not limited to, a mode register. The mode register can store various operating parameters and control parameters of the operation memory 300. The mode register can be programmed to set multiple operating parameters and control parameters, and can store parameter codes. For example, the mode register can store parameter codes (i.e., a configuration mapping table) for multiple temperature-related configuration refresh rates. The mode register can be read to determine the target configuration refresh rate. In one specific embodiment, the mode register can store data temporarily or permanently.

[0122] In some embodiments, the configuration mapping table includes multiple sub-configuration mapping tables, which are used to record the correspondence between configuration temperature ranges and configuration refresh rates; the peripheral circuit 310 also includes:

[0123] Address decoding circuit 370 is configured to: decode and generate a target address based on a temperature signal; wherein the target address is used to indicate the physical address of a target sub-configuration mapping table in a plurality of sub-configuration mapping tables;

[0124] The control logic circuit 340 is specifically configured to: obtain the target sub-configuration mapping table based on the target address and determine the target configuration refresh rate.

[0125] In this embodiment of the disclosure, the configuration mapping table includes multiple sub-configuration mapping tables, and different sub-configuration mapping tables record the correspondence between different configuration temperature ranges and configuration refresh rates. For example, referring to Table 1, the configuration mapping table includes 17 sub-configuration mapping tables, and the first sub-configuration mapping table records the configuration temperature range T. c1 The mapping relationship between the configuration refresh rate RM1 and the second sub-configuration mapping table records the configuration temperature range T. c2 The mapping relationship between the configuration refresh rate RM2, ..., the 17th sub-configuration mapping table records the configuration temperature range T. c17 and configure refresh rate RM 17 The mapping relationship between them, the number of sub-configuration mapping tables in the configuration mapping table is not limited to 17, the number of sub-configuration mapping tables can be less than or greater than 17.

[0126] The address decoding circuit 370 receives the temperature signal, decodes the temperature signal to generate a target address, and sends the target address to the control logic circuit 340. The control logic circuit 340 reads the sub-configuration mapping table in the second register circuit 360 based on the target address to determine the target configuration refresh rate. It can be understood that multiple sub-configuration mapping tables are stored in different locations in the second register circuit 360, corresponding to multiple different physical addresses. The target sub-configuration mapping table is one of these multiple sub-configuration mapping tables, and the target address is the physical address corresponding to that sub-configuration mapping table.

[0127] For example, at the first moment, the temperature sensing circuit 330 senses that the temperature of the memory 300 is 25°C and outputs a first temperature signal; the address decoding circuit 370 receives the first temperature signal and decodes it to generate a first target address; the control logic circuit 340 reads the first sub-configuration mapping table in the second register circuit 360 based on the first target address, determines the target configuration refresh rate RM1, and the memory controller will perform an automatic refresh operation on the memory 300 at the refresh rate RM1. In this example, the target sub-configuration mapping table is the first sub-configuration mapping table, and the target address is the physical address of the first sub-configuration mapping table, i.e., the first target address.

[0128] For example, at the second moment, the temperature sensing circuit 330 senses that the temperature of the memory 300 is 30°C and outputs a second temperature signal. The address decoding circuit 370 receives the second temperature signal and decodes it to generate a second target address. The control logic circuit 340 reads the second sub-configuration mapping table in the second register circuit 360 based on the second target address to determine the target configuration refresh rate RM2. The memory controller will then perform an automatic refresh operation on the memory 300 at a refresh rate of RM2. In this example, the target sub-configuration mapping table is the second sub-configuration mapping table, and the target address is the physical address of the second sub-configuration mapping table, i.e., the second target address. The second moment can be before or after the first moment, thus allowing for timely adjustment of the memory refresh rate when the temperature changes.

[0129] In some embodiments, the first register circuit 350 is further configured to: update the target initial refresh rate to the target configured refresh rate; and send the target configured refresh rate to the memory controller.

[0130] For example, when the sensed temperature is greater than the configured temperature value T e2x And less than or equal to the initial temperature value T e2At that time, the control logic circuit 340 determines the configuration refresh rate as RM3 based on the temperature and configuration mapping table. For example, RM3 can be a refresh rate of 6x. The first register circuit 350 updates the target initial refresh rate of 8x corresponding to the temperature to the target configuration refresh rate of 6x, and sends the refresh rate code 5'b00010 corresponding to the refresh rate of 6x to the memory controller. The memory controller will perform an automatic refresh operation on the memory 300 with a configuration refresh rate of 6x.

[0131] In some embodiments, the peripheral circuit 310 further includes: an electric fuse circuit 380, which is configured to store a configuration mapping table; the control logic circuit 340 is specifically configured to: read the configuration mapping table in the electric fuse circuit 380 and save the read configuration mapping table to the second register circuit 360.

[0132] The electric fuse circuit 380 is used to store the configuration mapping table. The electric fuse circuit 380 includes programmable logic devices, such as one-time programmable (OTP) registers, several-time programmable (FTP) registers, or multi-time programmable (MTP) registers. OTP includes fuse OTP or anti-fuse OTP. The configuration mapping table can be written into the electric fuse circuit 380 before the memory 300 leaves the factory. Because OTP, FTP, MTP, etc., are non-volatile, the configuration mapping table can still be saved when the memory 300 is powered off, avoiding the loss of the configuration mapping table.

[0133] The control logic circuit 340 can first read the configuration mapping table in the electric fuse circuit 380 and cache the read configuration mapping table in the second register circuit 360. Thus, when the temperature changes (e.g., rises or falls), the target configuration refresh rate is determined based on the temperature signal output by the temperature sensing circuit 330 and the configuration mapping table cached in the second register circuit 360, and the refresh rate of the memory 300 is adjusted to the target configuration refresh rate in a timely manner.

[0134] In this embodiment of the disclosure, a configuration mapping table is stored by setting an electric fuse circuit. Due to the non-volatility of the electric fuse circuit, the configuration mapping table can still be saved when the memory is powered off, thus avoiding the loss of the configuration mapping table.

[0135] In some embodiments, the initial refresh rate includes a base refresh rate and an initial multiplier, and the initial multipliers of any two initial refresh rates are different; the configured refresh rate includes a base refresh rate and a configured multiplier, and the configured multipliers of any two configured refresh rates are different.

[0136] The control logic circuit 340 is specifically configured to: determine the configuration multiple of the target configuration refresh rate based on the temperature signal and the configuration mapping table;

[0137] The first register circuit 350 is also configured to update the initial multiple of the target initial refresh rate to the configuration multiple of the target configured refresh rate.

[0138] For example, refer to Figure 6 As shown, the 17 initial refresh rates can be represented as multiples of the base refresh rate x. The initial multiples of any two initial refresh rates are different. For example, the initial multiple of refresh rate 8x is 8, and the initial multiple of refresh rate 6x is 6. The representation of multiple configured refresh rates is similar to that of multiple initial refresh rates, and will not be repeated here.

[0139] For example, control logic circuit 340 determines the configuration multiple 6 of the target configuration refresh rate 6x based on the temperature signal and the configuration mapping table; first register circuit 350 updates the initial multiple 8 of the target initial refresh rate 8x to the configuration multiple 6, thereby updating the target initial refresh rate 8x to the target configuration refresh rate 6x. It can be understood that in this example, the target initial refresh rate can be updated to the target configuration refresh rate by updating the multiple of the base refresh rate.

[0140] In some embodiments, the plurality of initial temperature segments include N initial temperature segments, where N is an integer greater than 1; the configuration mapping table includes N configuration temperature segments; wherein the minimum temperature of the i-th initial temperature segment is different from the minimum temperature of the i-th configuration temperature segment; and / or, the maximum temperature of the i-th initial temperature segment is different from the maximum temperature of the i-th configuration temperature segment; i is an integer greater than or equal to 1 and less than or equal to N.

[0141] For example, refer to Figure 8 As shown, the minimum temperature of the second initial temperature zone and the minimum temperature of the second configured temperature zone are both T. e1 The maximum temperature in the second initial temperature range is T. e2 The maximum temperature of the second configured temperature zone is T. e2x , among which, T e1 <T e2x <T e2 In this example, the minimum temperature of the second initial temperature segment is the same as the minimum temperature of the second configured temperature segment, while the maximum temperature of the second initial temperature segment is different from the maximum temperature of the second configured temperature segment. Of course, in other embodiments, the minimum temperature of the second initial temperature segment and the minimum temperature of the second configured temperature segment can be different; for example, the minimum temperature of the second initial temperature segment may be T. e1 The minimum temperature for the second temperature zone is T. e1x Te1x It can be less than or greater than T e1 .

[0142] In practical applications, the range of each configured temperature range can be flexibly adjusted according to the characteristics of the memory's leakage current changing with temperature. For example, if the leakage current changes drastically, the configured temperature range can be adjusted to a shorter range; if the leakage current changes less, the configured temperature range can be adjusted to a wider range to adapt to the memory's data retention characteristics, thereby generating the expected refresh rate at a specific temperature.

[0143] It is understandable that by shifting the minimum and / or maximum temperature of at least one of the multiple initial temperature ranges, a configuration temperature range different from the initial temperature range can be obtained, thereby meeting the data retention requirements of the memory.

[0144] In some embodiments, the control logic circuit 340 is further configured to:

[0145] Enter refresh mode based on the current refresh command sent by the memory controller;

[0146] The system enters refresh mode based on the next refresh command sent by the memory controller; the target refresh rate is used to indicate the time interval between the next refresh command and the current refresh command.

[0147] The memory controller is coupled to the memory 300 and is used to control the logical operations of the memory 300, such as writing, reading, or refreshing. The memory controller refreshes the memory cells by periodically sending refresh commands to the memory 300. Write, read, and other operations are typically performed after the automatic refresh operation is completed.

[0148] For example, the first register circuit 350 sends the refresh rate code 5'b00010 to the memory controller, which then performs an automatic refresh operation on the memory 300 at a refresh rate of 6x. The refresh rate of 6x indicates the time interval between the next refresh command and the current refresh command. It is understood that when the refresh rate changes, the time interval between the next refresh command and the current refresh command also changes. For example, a higher refresh rate shortens the time interval; conversely, a lower refresh rate lengthens the time interval.

[0149] In some embodiments, the memory 300 is further configured to update at least one configuration temperature segment in the configuration mapping table after the usage duration of the memory 300 is greater than or equal to a preset duration.

[0150] Compared to when it was first manufactured, the performance of memory may degrade after a period of use. For example, the data retention time of memory cells may decrease at a certain temperature. Therefore, after the memory has been used for a period of time greater than or equal to a preset duration, the minimum and / or maximum temperature of the configuration temperature range can be adjusted to a larger value, thereby reducing the time interval between refresh commands. The preset duration can include one month, six months, one year, or other longer periods. It should be noted that after the memory has been used for a period of time greater than or equal to the preset duration, the configuration refresh rate corresponding to one or more configuration temperature ranges in the configuration mapping table can be updated, and this disclosure does not impose any special restrictions on this.

[0151] In practical applications, multiple configuration temperature values ​​can be written after chip testing, or more specifically, written into the second register circuit 360. Based on these multiple configuration temperature values, multiple configuration temperature segments can be defined. These multiple configuration temperature values ​​can also be updated after chip packaging, thereby updating at least one configuration temperature segment in the configuration mapping table.

[0152] In this embodiment, by updating at least one configuration temperature segment in the configuration mapping table after the memory usage time is greater than or equal to a preset duration, the configuration refresh rate corresponding to that configuration temperature segment is updated. This allows for timely adjustment of the memory refresh rate based on memory usage time, further preventing data loss and increasing the memory's lifespan.

[0153] Based on the above-described memory, this disclosure also provides a method for operating the memory.

[0154] Figure 9 This is a flowchart illustrating an operation method of a memory according to an embodiment of the present disclosure. The memory includes peripheral circuitry; the peripheral circuitry includes a first register circuit configured to store a plurality of initial refresh rates; wherein the plurality of initial refresh rates correspond one-to-one with a plurality of initial temperature ranges. (Refer to...) Figure 9 As shown, this operation method includes at least the following steps:

[0155] Step S410: Sensing the temperature of the memory and generating a temperature signal based on the sensed temperature;

[0156] Step S420: Determine the target configuration refresh rate based on the temperature signal and the configuration mapping table; wherein, the configuration mapping table includes multiple configuration temperature segments and multiple configuration refresh rates, and the multiple configuration temperature segments and multiple configuration refresh rates correspond one-to-one;

[0157] Step S430: Adjust the target initial refresh rate from the multiple initial refresh rates to the target configured refresh rate.

[0158] In some embodiments, the peripheral circuitry further includes a second register circuit configured to store a configuration mapping table; step S420 includes: reading the second register circuit based on a temperature signal to determine a target configuration refresh rate.

[0159] In some embodiments, the configuration mapping table includes multiple sub-configuration mapping tables, which are used to record the correspondence between configuration temperature ranges and configuration refresh rates; the above-mentioned determination of the target configuration refresh rate based on the temperature signal by reading the second register circuit includes:

[0160] Based on the temperature signal, a target address is generated through decoding; the target address is used to indicate the physical address of the target sub-configuration mapping table in multiple sub-configuration mapping tables.

[0161] Based on the target address, obtain the target sub-configuration mapping table and determine the target configuration refresh rate.

[0162] In some embodiments, the above-described operation method further includes:

[0163] Update the target initial refresh rate to the target configured refresh rate;

[0164] Send the target configuration refresh rate to the memory controller.

[0165] In some embodiments, the peripheral circuitry further includes an electric fuse circuit configured to store a configuration mapping table; the above-described operation method further includes:

[0166] Read the configuration mapping table in the electric fuse circuit and save the read configuration mapping table to the second register circuit.

[0167] In some embodiments, the initial refresh rate includes a base refresh rate and an initial multiplier, and the initial multipliers of any two initial refresh rates are different; the configured refresh rate includes a base refresh rate and a configured multiplier, and the configured multipliers of any two configured refresh rates are different.

[0168] The above step S420 includes: determining the configuration multiple of the target configuration refresh rate based on the temperature signal and the configuration mapping table;

[0169] Step S430 above includes: updating the initial multiple of the target initial refresh rate to the configuration multiple of the target configured refresh rate.

[0170] In some embodiments, the plurality of initial temperature segments include N initial temperature segments, where N is an integer greater than 1; the configuration mapping table includes N configuration temperature segments; wherein the minimum temperature of the i-th initial temperature segment is different from the minimum temperature of the i-th configuration temperature segment; and / or, the maximum temperature of the i-th initial temperature segment is different from the maximum temperature of the i-th configuration temperature segment; i is an integer greater than or equal to 1 and less than or equal to N.

[0171] In some embodiments, the above-described operation method further includes:

[0172] Enter refresh mode based on the current refresh command sent by the memory controller;

[0173] The system enters refresh mode based on the next refresh command sent by the memory controller; the target refresh rate is used to indicate the time interval between the next refresh command and the current refresh command.

[0174] In some embodiments, the above-described operation method further includes:

[0175] After the memory usage time is greater than or equal to the preset time, update at least one configuration temperature segment in the configuration mapping table.

[0176] The above operation method has been described in detail on the memory side, and will not be repeated here for the sake of brevity.

[0177] Figure 10 This is a schematic diagram illustrating an embodiment of the present disclosure of adjusting the refresh rate. (Refer to...) Figure 10 As shown, the temperature sensing circuit senses the temperature of the memory and generates a temperature signal based on the sensed temperature. The control logic circuit receives the temperature signal, determines the target configuration refresh rate based on the temperature signal and the configuration mapping table, and adjusts the target initial refresh rate to the target configuration refresh rate. Here, the configuration mapping table is used to store the results of the computer algorithm, which can be developed in parallel with the memory circuit design and written after chip testing. Of course, during other circuit design and chip testing processes, the algorithm can be optimized based on the circuit design and test results.

[0178] In one specific embodiment, reference is made to Figure 10 As shown, the address decoding circuit receives the temperature signal, decodes the temperature signal to generate the target address; the control logic circuit reads the target sub-configuration mapping table in the second register circuit based on the target address, and outputs the read result (i.e., the read value). The output read result is used to indicate the target configuration refresh rate.

[0179] Figure 11 This is a schematic diagram illustrating a process for generating a configuration mapping table using an algorithm, according to an embodiment of this disclosure. The following will be combined with... Figure 11 The process of generating a configuration mapping table according to the embodiments of this disclosure is described above.

[0180] Execution step S510: Set initial multiplier values. For example, the products of multiple initial multipliers specified by the JEDEC protocol and the basic refresh rate x are written into the first register circuit, so that the first register circuit stores multiple initial refresh rates, each initial refresh rate corresponds to an initial temperature range, and different initial refresh rates correspond to different initial temperature ranges.

[0181] Step S520: Calculate the configuration temperature values. For example, calculate multiple temperature-related configuration temperature values ​​based on the data retention characteristics of the memory. For example, 16 configuration temperature values ​​are calculated, namely 25℃, 30℃, 35℃, 40℃, 42℃, 45℃, 48℃, 50℃, 52℃, 55℃, 60℃, 65℃, 70℃, 75℃, 80℃, and 85℃.

[0182] Execution step S530: Save the configuration temperature values. Based on multiple configuration temperature values, multiple configuration temperature segments can be divided, and a correspondence between multiple configuration temperature segments and multiple configuration refresh rates is established, i.e., a configuration mapping table; the configuration mapping table is saved to the second register circuit.

[0183] Perform step S540: Test the configured temperature value. For example, provide a test temperature to test the memory.

[0184] Step S550: Based on the test results, determine whether the configuration temperature value meets the requirements; if yes, complete; if no, return to step S520, recalculate the configuration temperature value by adjusting the algorithm, generate a new configuration temperature range based on the newly calculated configuration temperature value, and write the new configuration temperature range into the second register circuit until the requirements are met. Here, at the test temperature, when the refresh rate is the configuration refresh rate corresponding to the test temperature, the memory is sufficient to hold the data, and it can be determined that the configuration temperature value meets the requirements.

[0185] This disclosure also provides a memory system, such as... Figure 1 As shown, the memory system 30 includes:

[0186] One or more memory 300 as described in any of the above embodiments;

[0187] The memory controller 10 is coupled to the memory 300 and configured to control the memory 300.

[0188] Memory 300 can be referenced accordingly Figure 1 The memory 20 in the illustrated embodiment will not be described in detail here, nor will the functions, applications, and interactions between the memory 300 and the memory controller 10 be further elaborated.

[0189] This disclosure also provides an electronic device, including a memory system as described in the above embodiments.

[0190] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0191] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0192] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, The memory includes peripheral circuitry; the peripheral circuitry includes: A first register circuit is configured to store a plurality of initial refresh rates; wherein the plurality of initial refresh rates correspond one-to-one with a plurality of initial temperature ranges. A temperature sensing circuit, configured to: sense the temperature of the memory and generate a temperature signal based on the sensed temperature; A control logic circuit is configured to: determine a target configuration refresh rate based on the temperature signal and a configuration mapping table, and adjust the target initial refresh rate among the plurality of initial refresh rates to the target configuration refresh rate; wherein the configuration mapping table includes a plurality of configuration temperature segments and a plurality of configuration refresh rates, and the plurality of configuration temperature segments and the plurality of configuration refresh rates correspond one-to-one.

2. The memory according to claim 1, characterized in that, The peripheral circuit also includes: A second register circuit is configured to store the configuration mapping table; The control logic circuit is specifically configured to: read the second register circuit based on the temperature signal and determine the target configuration refresh rate.

3. The memory according to claim 2, characterized in that, The configuration mapping table includes multiple sub-configuration mapping tables, which are used to record the correspondence between the configuration temperature range and the configuration refresh rate; the peripheral circuit also includes: An address decoding circuit is configured to: decode and generate a target address based on the temperature signal; wherein the target address is used to indicate the physical address of the target sub-configuration mapping table in the plurality of sub-configuration mapping tables; The control logic circuit is specifically configured to: obtain the target sub-configuration mapping table based on the target address, and determine the target configuration refresh rate.

4. The memory according to claim 2, characterized in that, The first register circuit is also configured to: Update the target initial refresh rate to the target configured refresh rate; Send the target configuration refresh rate to the memory controller.

5. The memory according to claim 2, characterized in that, The peripheral circuit also includes: An electric fuse circuit, the electric fuse circuit being configured to store the configuration mapping table; The control logic circuit is specifically configured to: read the configuration mapping table in the electric fuse circuit and save the read configuration mapping table to the second register circuit.

6. The memory according to claim 1, characterized in that, The initial refresh rate includes a base refresh rate and an initial multiplier, and the initial multipliers of any two of the plurality of initial refresh rates are different; the configured refresh rate includes the base refresh rate and a configured multiplier, and the configured multipliers of any two of the plurality of configured refresh rates are different. The control logic circuit is specifically configured to: determine the configuration multiple of the target configuration refresh rate based on the temperature signal and the configuration mapping table; The first register circuit is further configured to update the initial multiple of the target initial refresh rate to the configuration multiple of the target configured refresh rate.

7. The memory according to claim 1, characterized in that, The plurality of initial temperature segments includes N initial temperature segments, where N is an integer greater than 1; the configuration mapping table includes N configuration temperature segments; wherein, the minimum temperature of the i-th initial temperature segment is different from the minimum temperature of the i-th configuration temperature segment; and / or, the maximum temperature of the i-th initial temperature segment is different from the maximum temperature of the i-th configuration temperature segment; i is an integer greater than or equal to 1 and less than or equal to N.

8. The memory according to claim 1, characterized in that, The control logic circuit is further configured to: Enter refresh mode based on the current refresh command sent by the memory controller; The system enters the refresh mode based on the next refresh command sent by the memory controller; wherein the target configured refresh rate is used to indicate the time interval between the next refresh command and the current refresh command.

9. The memory according to claim 1, characterized in that, The memory is also configured to: After the memory usage time is greater than or equal to a preset time, at least one of the configuration temperature segments in the configuration mapping table is updated.

10. A method for operating a memory, characterized in that, The memory includes peripheral circuitry; the peripheral circuitry includes a first register circuit configured to store multiple initial refresh rates; wherein the multiple initial refresh rates correspond one-to-one with multiple initial temperature ranges; the operation method includes: The temperature of the memory is sensed, and a temperature signal is generated based on the sensed temperature; The target configuration refresh rate is determined based on the temperature signal and the configuration mapping table; wherein, the configuration mapping table includes multiple configuration temperature segments and multiple configuration refresh rates, and the multiple configuration temperature segments and the multiple configuration refresh rates correspond one-to-one; Adjust the target initial refresh rate among the plurality of initial refresh rates to the target configured refresh rate.

11. The operating method according to claim 10, characterized in that, The peripheral circuit also includes a second register circuit, which is configured to store the configuration mapping table; The step of determining the target configuration refresh rate based on the temperature signal and the configuration mapping table includes: Based on the temperature signal, the second register circuit is read to determine the target configuration refresh rate.

12. The operating method according to claim 11, characterized in that, The configuration mapping table includes multiple sub-configuration mapping tables, which are used to record the correspondence between the configuration temperature range and the configuration refresh rate. The step of reading the second register circuit based on the temperature signal to determine the target configuration refresh rate includes: Based on the temperature signal, a target address is generated by decoding; wherein, the target address is used to indicate the physical address of the target sub-configuration mapping table in the plurality of sub-configuration mapping tables; Based on the target address, obtain the target sub-configuration mapping table and determine the target configuration refresh rate.

13. The operating method according to claim 11, characterized in that, The operation method further includes: Update the target initial refresh rate to the target configured refresh rate; Send the target configuration refresh rate to the memory controller.

14. The operating method according to claim 11, characterized in that, The peripheral circuit also includes an electric fuse circuit, which is configured to store the configuration mapping table; the operation method further includes: The configuration mapping table in the electric fuse circuit is read, and the read configuration mapping table is saved to the second register circuit.

15. The operating method according to claim 10, characterized in that, The initial refresh rate includes a base refresh rate and an initial multiplier, and the initial multipliers of any two of the plurality of initial refresh rates are different; the configured refresh rate includes the base refresh rate and a configured multiplier, and the configured multipliers of any two of the plurality of configured refresh rates are different. The step of determining the target configuration refresh rate based on the temperature signal and the configuration mapping table includes: The configuration multiple of the target configuration refresh rate is determined based on the temperature signal and the configuration mapping table; The step of adjusting the target initial refresh rate to the target configured refresh rate includes: Update the initial multiple of the target initial refresh rate to the configuration multiple of the target configured refresh rate.

16. The operating method according to claim 10, characterized in that, The plurality of initial temperature segments includes N initial temperature segments, where N is an integer greater than 1; the configuration mapping table includes N configuration temperature segments; wherein, the minimum temperature of the i-th initial temperature segment is different from the minimum temperature of the i-th configuration temperature segment; and / or, the maximum temperature of the i-th initial temperature segment is different from the maximum temperature of the i-th configuration temperature segment; i is an integer greater than or equal to 1 and less than or equal to N.

17. The operating method according to claim 10, characterized in that, The operation method further includes: Enter refresh mode based on the current refresh command sent by the memory controller; The system enters the refresh mode based on the next refresh command sent by the memory controller; wherein the target configured refresh rate is used to indicate the time interval between the next refresh command and the current refresh command.

18. The operating method according to claim 10, characterized in that, The operation method further includes: After the memory usage time is greater than or equal to a preset time, at least one of the configuration temperature segments in the configuration mapping table is updated.

19. A memory system, characterized in that, include: One or more memories as described in any one of claims 1 to 9; A memory controller, coupled to the memory and configured to control the memory.

20. An electronic device, characterized in that, include: The memory system as described in claim 19.

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