Integrated circuit including tri-state content addressable memory cells

Abstract

An example integrated circuit includes a ternary content addressable memory (TCAM) cell on a front side of a substrate, a back via extending through the substrate in a vertical direction relative to the substrate, a back routing layer on a back side of the substrate, and a front routing layer over the TCAM cell in the vertical direction. The TCAM unit includes a first unit storing a first value, a second unit storing a second value, and a comparison circuit connected to the first unit and the second unit. The backside wiring layer includes at least one backside power rail configured to send a supply voltage to the TCAM cell through the backside path. The front wiring layer includes a bit line connected to the first cell and the second cell, a complementary bit line connected to the first cell and the second cell, and a match line connected to the comparison circuit.

Description

Technical Field

[0001] The present disclosure relates to integrated circuits including ternary content addressable memory cells. Background Art

[0002] Due to the requirements for high integration of semiconductor processes and the development of semiconductor processes, the width, spacing and / or height of the wiring included in the integrated circuit may be reduced, and the influence of the parasitic components of the wiring may increase. In addition, in order to reduce power consumption, high operating speed, etc., the power supply voltage of the integrated circuit may be reduced, and accordingly, the influence of the parasitic components of the wiring on the integrated circuit may be greater. Therefore, there are higher requirements for the design method of the integrated circuit for effective wiring lines and paths. Summary of the invention

[0003] The present disclosure relates to an integrated circuit capable of improving power performance area (PPA) by implementing an integrated circuit including a ternary content addressable memory (TCAM) cell using backside wiring.

[0004] In some implementations, an integrated circuit includes: a ternary content addressable memory (TCAM) cell, the TCAM cell being arranged on a front side of a substrate and including a first cell storing a first value, a second cell storing a second value, and a comparison circuit connected to the first cell and the second cell; a back side via, the back side via penetrating the substrate in a vertical direction relative to the substrate; a back side wiring layer, the back side wiring layer being arranged on a back side of the substrate and including at least one back side power rail configured to transmit a supply voltage to the TCAM cell through the back side via; and a front side wiring layer, the front side wiring layer being arranged above the TCAM cell in the vertical direction and including a bit line connected to the first cell and the second cell, a complementary bit line connected to the first cell and the second cell, and a match line connected to the comparison circuit.

[0005] In some implementations, an integrated circuit includes: a ternary content addressable memory (TCAM) cell, the TCAM cell being arranged on a front side of a substrate and including a first cell storing a first value, a second cell storing a second value, and a comparison circuit connected to the first cell and the second cell; a back side via, the back side via penetrating the substrate in a vertical direction relative to the substrate; a back side wiring layer, the back side wiring layer being arranged on a back side of the substrate and including a matching line connected to the comparison circuit through the back side via; and a front side wiring layer, the front side wiring layer being arranged above the TCAM cell in the vertical direction and including a bit line connected to the first cell and the second cell, a complementary bit line connected to the first cell and the second cell, and at least one front side power rail configured to transmit a supply voltage to the TCAM cell.

[0006] In some implementations, an integrated circuit includes: a ternary content addressable memory (TCAM) cell, the TCAM cell being arranged on a front side of a substrate and including a first cell storing a first value, a second cell storing a second value, and a comparison circuit connected to the first cell and the second cell; a back side via, the back side via penetrating the substrate in a vertical direction relative to the substrate; a back side wiring layer, the back side wiring layer being arranged on a back side of the substrate and including at least one word line connected to the first cell and the second cell through the back side via; and a front side wiring layer, the front side wiring layer being arranged above the TCAM cell in the vertical direction and including a bit line connected to the first cell and the second cell, a complementary bit line connected to the first cell and the second cell, and at least one front side power rail configured to transmit a supply voltage to the TCAM cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The implementation of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0008] Figure 1 is a circuit diagram showing an example of a memory cell.

[0009] Figure 2 It is shown that Figure 1 A schematic diagram of an example layout of an integrated circuit of a memory cell.

[0010] Figure 3A It is shown Figure 2 A top view of an example of a backside wiring layer of an integrated circuit, Figure 3B It is shown Figure 2 A top view of an example of a first front wiring layer of an integrated circuit, and Figure 3C It is shown Figure 2FIG. 1 is a top view of an example of a second front-side wiring layer of an integrated circuit.

[0011] Figure 4A It is along Figure 2 An example cross-sectional view taken along line II' of Figure 4B It is along Figure 2 An example cross-sectional view taken along line II-II';

[0012] Figure 5 It is shown that Figure 1 A schematic diagram of an example layout of an integrated circuit of a memory cell.

[0013] Fig. 6A It is shown Figure 5 A top view of an example of a backside wiring layer of an integrated circuit, Figure 6B It is shown Figure 5 A top view of an example of a first front wiring layer of an integrated circuit, and Figure 6C It is shown Figure 5 FIG. 1 is a top view of an example of a second front-side wiring layer of an integrated circuit.

[0014] Fig. 7A It is along Figure 5 An example cross-sectional view taken along line III-III', Figure 7B It is along Figure 5 An example cross-sectional view taken along line IV-IV' of Figure 7C It is along Figure 5 An example cross-sectional view taken along line V-V'.

[0015] Figure 8 It is shown that Figure 1 A schematic diagram of an example layout of an integrated circuit of a memory cell.

[0016] Fig.9A It is shown Figure 8 A top view of an example of a backside wiring layer of an integrated circuit, Fig. 9B It is shown Figure 8 A top view of an example of a first front wiring layer of an integrated circuit, and Fig. 9C It is shown Figure 8 FIG. 1 is a top view of an example of a second front-side wiring layer of an integrated circuit.

[0017] Fig. 10A It is along Figure 8 An example cross-sectional view taken along line VI-VI' of Fig. 10B It is along Figure 8 An example cross-sectional view taken along line VII-VII'.

[0018] Fig.11 is a block diagram illustrating an example of a memory device.

[0019] FIG. 12A to FIG. 12D is a diagram illustrating an example of an element.

[0020] Fig.13 is a flow chart illustrating an example of a method of manufacturing an integrated circuit.

[0021] Fig.14 is a block diagram illustrating an example of a system on a chip.

[0022] Fig.15 is a block diagram illustrating an example of a computing system including a memory for storing programs. DETAILED DESCRIPTION

[0023] Hereinafter, the implementation of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the accompanying drawings, and redundant descriptions thereof will be omitted.

[0024] In this specification, the X-axis direction may be referred to as a first horizontal direction or a first direction, the Y-axis direction may be referred to as a second horizontal direction or a second direction, and the Z-axis direction may be referred to as a vertical direction. A plane formed by the X-axis and the Y-axis may be referred to as a horizontal plane, a component arranged in the +Z-axis direction relative to another component may be referred to as being located above the other component, and a component arranged in the -Z-direction relative to the other component may be referred to as being located below the other component.

[0025] An integrated circuit can be designed by arranging multiple standard cells. A standard cell can be referred to as a unit of an integrated circuit layout, and can be referred to as a cell. A standard cell can be designed to include multiple transistors to perform a predefined function. The standard cell method is a method of preparing standard cells with multiple functions in advance and combining standard cells to design a dedicated large-scale integrated circuit customized to customer or user specifications. Standard cells are pre-designed and verified and registered in a standard cell library, and integrated circuits can be designed by performing logic design, layout and wiring of the combined standard cells using computer-aided design (CAD). When designing these integrated circuits, the performance of the integrated circuit can be further improved by reducing the length and wiring complexity of the wiring and / or paths.

[0026] Figure 1 is a circuit diagram showing an example of a memory cell MC.

[0027] Reference Figure 1, the memory cell MC may be connected to a word line WL, a bit line BL, and a complementary bit line BLB, and may also be connected to a match line ML, a search line SL, and a complementary search line SLB. In some implementations, the memory cell MC may correspond to a ternary content addressable memory (TCAM) cell. TCAM cells are widely used in applications such as networking, imaging, and speech recognition that require very fast database searches. Hereinafter, the memory cell MC will be referred to as a TCAM cell.

[0028] The memory cell MC may include a first cell C1, a second cell C2, and a comparison circuit CP. Since the first cell C1 stores a first value and the second cell C2 stores a second value, the first cell C1 and the second cell C2 may constitute a memory circuit for storing three values ​​"0", "1", and "x" (irrelevant). For example, when the first value is 1 and the second value is 0, the memory cell MC may be considered to store "0". For example, when the first value is 0 and the second value is 1, the memory cell MC may be considered to store "1". For example, when the first value is 1 and the second value is 1, the memory cell MC may be considered to store "x".

[0029] In some implementations, the first cell C1 may be referred to as a mask cell, and the second cell C2 may be referred to as a content cell or a key cell. For example, the first cell C1 and the second cell C2 may be implemented as static random access memory (SRAM) cells. The comparison circuit CP may be connected to the first cell C1 and the second cell C2, and may be cascaded with the storage circuit. Hereinafter, the configuration of the storage cell MC will be described in more detail.

[0030] The first unit C1 may include a cross-coupled inverter pair between a node to which a positive power supply voltage, such as a power supply voltage VDD, is applied and a node to which a negative power supply voltage, such as a ground voltage VSS, is applied. For example, a first inverter in the cross-coupled inverter pair may include a pull-up transistor PU1 and a pull-down transistor PD1, and a second inverter in the cross-coupled inverter pair may include a pull-up transistor PU2 and a pull-down transistor PD2.

[0031] In this case, a first storage node M between the pull-up transistor PU1 and the pull-down transistor PD1 may be connected to the gate of the pull-up transistor PU2 and the gate of the pull-down transistor PD2, and a first complementary storage node M_B between the pull-up transistor PU2 and the pull-down transistor PD2 may be connected to the gate of the pull-up transistor PU1 and the gate of the pull-down transistor PD1. In this case, a voltage level of the first storage node M may correspond to a first value.

[0032] In addition, the first cell C1 may further include transmission transistors PG1 and PG2 configured to connect the first inverter and the second inverter to the bit line BL and the complementary bit line BLB, respectively, through an activated (e.g., high-level voltage) word line WL. In this case, the first storage node M may be connected to the bit line BL through the transmission transistor PG1, and the first complementary storage node M_B may be connected to the complementary bit line BLB through the transmission transistor PG2. For example, the pull-up transistors PU1 and PU2 may both be P-type transistors, and the pull-down transistors PD1 and PD2 and the transmission transistors PG1 and PG2 may both be N-type transistors.

[0033] The second unit C2 may include a cross-coupled inverter pair between a node to which a positive power supply voltage, such as a power supply voltage VDD, is applied and a node to which a negative power supply voltage, such as a ground voltage VSS, is applied. For example, a third inverter in the cross-coupled inverter pair may include a pull-up transistor PU3 and a pull-down transistor PD3, and a fourth inverter in the cross-coupled inverter pair may include a pull-up transistor PU4 and a pull-down transistor PD4.

[0034] In this case, a second storage node C between the pull-up transistor PU3 and the pull-down transistor PD3 may be connected to the gate of the pull-up transistor PU4 and the gate of the pull-down transistor PD4, and a second complementary storage node C_B between the pull-up transistor PU4 and the pull-down transistor PD4 may be connected to the gate of the pull-up transistor PU3 and the gate of the pull-down transistor PD3. In this case, the voltage level of the second storage node C may correspond to the second value.

[0035] In addition, the second cell C2 may further include transmission transistors PG3 and PG4 configured to connect the third inverter and the fourth inverter to the bit line BL and the complementary bit line BLB, respectively, through the activated (e.g., high-level voltage) word line WL. In this case, the second storage node C may be connected to the bit line BL through the transmission transistor PG3, and the first complementary storage node C_B may be connected to the complementary bit line BLB through the transmission transistor PG4. For example, the pull-up transistors PU3 and PU4 may each be a P-type transistor, and each of the pull-down transistors PD3 and PD4 and the transmission transistors PG3 and PG4 may be an N-type transistor.

[0036] The comparison circuit CP may include data transistors DG1 and DG2 and search transistors SG1 and SG2. The data transistor DG1 may include a gate connected to the first storage node M and a source to which a ground voltage VSS is applied. The data transistor DG2 may include a gate connected to the second storage node C and a source to which a ground voltage VSS is applied. The search transistor SG1 may include a gate connected to a complementary search line SLB and a source connected to the data transistor DG1. The search transistor SG2 may include a gate connected to the search line SL and a source connected to the data transistor DG2. The search transistor SG1 may be configured to connect the data transistor DG1 to the match line ML through the complementary search line SLB, and the search transistor SG2 may be configured to connect the data transistor DG2 to the match line ML through the search line SL. The drain of the search transistor SG1 and the drain of SG2 may correspond to the output node of the memory cell MC.

[0037] The comparison circuit CP may compare the search value input through the search line SL and the complementary search line SLB with the first value and the second value stored in the first cell C1 and the second cell C2, and output the comparison result through the match line ML. In this case, the search value input through the search line SL and the complementary search line SLB may be referred to as search data, and the first value and the second value stored in the first cell C1 and the second cell C2 may be referred to as storage data. When the result of the comparison is that the storage data matches the search data, a match may occur, and when the result of the comparison is that the storage data does not match the search data, a mismatch may occur. For example, during the comparison operation, the match line ML is precharged to a logic high level. When the comparison result is a match, the match line ML may be discharged to a logic low level, and when the comparison result is a mismatch, the match line ML may maintain a logic high level.

[0038] For example, when the memory cell MC stores "0", that is, when the first value is 1 and the second value is 0, and when 0 is input to the search line SL and 1 is input to the complementary search line SLB, the data transistor DG1 and the search transistor SG1 may be turned on. In this case, since a match occurs, that is, the stored data is consistent with the search data, the match line ML may be discharged. In addition, for example, when the memory cell MC stores "0", that is, when the first value is 1 and the second value is 0, and when 1 is input to the search line SL and 0 is input to the complementary search line SLB, the data transistor DG2 and the search transistor SG1 may be turned off. In this case, the match line ML may maintain a logic high level. For example, when the memory cell MC stores "x", that is, when the first value is 1 and the second value is 1, the data transistors DG1 and DG2 may be turned on. Therefore, regardless of the search value input to the search line SL and the complementary search line SLB, the match line ML may be discharged.

[0039] Figure 2 It is shown that Figure 1 FIG. 1 is a schematic diagram of an example layout of a memory cell integrated circuit 10 . Figure 3A It is shown Figure 2 FIG. 1 is a top view of an example of a backside wiring layer BM of the integrated circuit 10 . Figure 3B It is shown Figure 2 FIG. 1 is a top view of an example of a first front-side wiring layer M1 of an integrated circuit 10 . Figure 3C It is shown Figure 2 FIG. 1 is a top view of an example of a second front-side wiring layer M2 of the integrated circuit 10 .

[0040] Refer to Figures 1 to 3C , the integrated circuit 10 may include a gate line GT, a gate contact CB, a first via VA, a second via V1, a first front wiring layer M1, a second front wiring layer M2, a back wiring layer BM, and a back via BVA. In some implementations, the first front wiring layer M1 and the second front wiring layer M2 may be collectively referred to as a front wiring layer. For example, the gate line GT, the gate contact CB, and the back via BVA may constitute a memory cell MC, for example, a TCAM cell, and the memory cell MC may be implemented as a standard cell defined by a cell boundary BD.

[0041] The integrated circuit 10 may include a first front wiring layer M1, a second front wiring layer M2, and a back wiring layer BM, and a power distribution network (PDN) may be implemented using the first front wiring layer M1, the second front wiring layer M2, and the back wiring layer BM. In this case, the first front wiring layer M1 and the second front wiring layer M2 may be arranged above the standard cell, i.e., the memory cell MC, in the vertical direction Z, and the back wiring layer BM may be arranged below the standard cell, i.e., the memory cell MC, in the vertical direction Z.

[0042] Therefore, some of the signals and / or power applied to the integrated circuit 10 can be transmitted through the first front wiring layer M1 and the second front wiring layer M2, and the rest can be transmitted through the back wiring layer BM. Therefore, compared with a structure in which wiring is laid out only on the front side of the substrate, the wiring complexity can be greatly reduced, and the length of each line or each path can be reduced, thereby improving the performance of the integrated circuit 10.

[0043] The integrated circuit 10 may be implemented as a semiconductor device, and a substrate on which the semiconductor device is formed may have a first surface and a second surface. The first surface may be, for example, a surface on which circuit elements such as transistors are arranged, and in this specification, the first surface may be referred to as a "front surface". The second surface may be a surface facing the first surface, and in this specification, the second surface may be referred to as a "back surface".

[0044] The gate lines GT may include a plurality of gate lines GT1 to GT10 extending in the first direction X. For example, the gate lines GT1 to GT3 may be arranged in a row along the first direction X, the gate lines GT4 and GT5 may be arranged in a row along the first direction X, the gate lines GT6 and GT7 may be arranged in a row along the first direction X, and the gate lines GT8 to GT10 may be arranged in a row along the first direction X. The gate contacts CB may be disposed on the gate lines GT1 to GT10, respectively.

[0045] In some implementations, the first front wiring layer M1 and the second front wiring layer M2 may be used as signal wiring for transmitting signals to the integrated circuit 10 and power wiring for transmitting power to the integrated circuit 10, and the back wiring layer BM may be used as power wiring for transmitting power to the integrated circuit 10. For example, the first front wiring layer M1 and the second front wiring layer M2 may transmit a search line SL signal, a complementary search line SLB signal, and a word line WL signal to the memory cell MC, may transmit a bit line BL signal and a complementary bit line BLB signal to the memory cell MC, may receive a bit line BL signal and a complementary bit line BLB signal from the memory cell MC, and may receive a match line ML signal from the memory cell MC. In addition, the first front wiring layer M1 and the second front wiring layer M2 may provide power such as a positive power supply voltage, such as a power supply voltage VDD, to the memory cell MC. For example, the back wiring layer BM may provide power such as a negative power supply voltage, such as a ground voltage VSS, to the memory cell MC.

[0046] The back wiring layer BM may include back wiring lines 11a, 11b, and 11c each extending in the first direction X and spaced apart from each other in the second direction Y. For example, the back wiring lines 11a, 11b, and 11c may be used as a "back power rail" for providing a power supply voltage to the memory cell. For example, the back wiring lines 11a, 11b, and 11c may be a back power rail for providing a negative power supply voltage, such as a ground voltage VSS, to the memory cell.

[0047] The backside vias BVA may be arranged on the backside wiring lines 11a, 11b, and 11c, respectively. Each of the backside wiring lines 11a, 11b, and 11c may be connected to the source / drain region of the transistor through the corresponding backside vias BVA. For example, through the backside wiring lines 11a, 11b, and 11c, the ground voltage VSS may be provided to the source of each N-type transistor (e.g., each of PD1 to PD4, PG1 to PG4, SG1 and SG2, and DG1 and DG2).

[0048] In this way, the backside via BVA can connect the layers and elements on the back side to the substrate, such as elements in the diffusion region. Specifically, the backside via BVA can be connected to the source / drain regions of the active region, respectively. Here, the backside via BVA can be a "backside source / drain contact". In this way, the structure that connects the contact to the lower part of the epitaxial region (such as the source / drain region) can be called a direct backside contact (DBC). In some implementations, the DBC can include a backside contact and / or a backside via.

[0049] The first front wiring layer M1 may include a plurality of front wiring patterns each extending in the second direction Y. The front wiring patterns 12a, 12b, 12f, 12g, 12h, and 12i may be connected to the gate lines GT4, GT6, GT2, GT9, GT3, and GT10 through the gate contacts CB, respectively, and the front wiring patterns 12c, 12d, 12e, and 12j may be connected to the gate lines GT4, GT6, GT2, GT9, GT3, and GT10 through the first vias VA and the source / drain contacts (e.g., Figure 4B CA) is connected to the source / drain region.

[0050] The front wiring pattern 12c may correspond to a complementary bit line BLB and may be connected to, for example, the source / drain of pass transistors PG2 and PG4. The front wiring pattern 12d may correspond to a front power rail and may, for example, transmit a power supply voltage VDD to the sources of pull-up transistors PU1 to PU4. For example, the front wiring pattern 12e may correspond to a bit line BL and may be connected to, for example, the source / drain regions of pass transistors PG1 and PG3.

[0051] The front wiring pattern 12h may correspond to a complementary search line SLB and may transmit a complementary search line (SLB) signal to the gate line GT3. For example, the gate line GT3 may correspond to the gate of the search transistor SG1. The front wiring pattern 12i may correspond to a search line SL and may transmit a search line SL signal to the gate line GT10. For example, the gate line GT10 may correspond to the gate of the search transistor SG2.

[0052] The second front wiring layer M2 may include a first front wiring line 13a, a second front wiring line 13b, and a third front wiring line 13c extending in the first direction X, respectively. For example, the first front wiring line 13a and the third front wiring line 13c may correspond to the word line WL, and the second front wiring line 13b may correspond to the match line ML. The first front wiring line 13a may be connected to the front wiring patterns 12a and 12f through the second via V1, and the front wiring patterns 12a and 12f may transmit the word line WL signal to the gate lines GT4 and GT2, respectively, through the gate contact CB. The third front wiring line 13c may be connected to the front wiring patterns 12b and 12g through the second via V1, and the front wiring patterns 12b and 12g may transmit the word line WL signal to the gate lines GT6 and GT9, respectively, through the gate contact CB. The second front wiring line 13b may be connected to the front wiring pattern 12j through the second via V1, and the front wiring pattern 12j may be connected to the source / drain region through the first via VA and the source / drain contact CA.

[0053] In this implementation, the back power rail included in the back wiring layer BM, such as the back wiring lines 11a, 11b, and 11c, can be used to supply the ground voltage VSS to the memory cell MC. In this case, since the wiring width of the back power rail can be arranged to be larger than the wiring width of the front power rail, the wiring width of each of the back wiring lines 11a, 11b, and 11c can be increased, thereby smoothly supplying the ground voltage VSS to the memory cell MC.

[0054] In addition, the wiring width of the front wiring lines included in the front wiring layer can be increased by arranging the power rails conventionally arranged on the front wiring layer on the back wiring layer BM. For example, the wiring width of each word line (e.g., the first front wiring line 13a and the third front wiring line 13c) included in the second front wiring layer M2 can be increased, thereby further improving the performance of the integrated circuit 10 by reducing the word line resistance.

[0055] Figure 4A It is along Figure 2 An example cross-sectional view taken along line II' of Figure 4B It is along Figure 2 An example cross-sectional view taken along line II-II'.

[0056] Refer to Figure 4A and Figure 4B , the first layer L1 may include a substrate or a semiconductor substrate. For example, the semiconductor substrate may include any one of silicon, silicon on insulator, silicon on sapphire, germanium, silicon germanium, and gallium arsenide. For example, the upper region of the first layer L1 may correspond to the active region. An interlayer insulating layer may be arranged above the first layer L1.

[0057] In some implementations, the first layer L1 may correspond to a bulkless substrate. During the manufacturing process of the integrated circuit 10, a device wafer may be formed by forming gate lines, source / drain regions, contacts, vias, and / or wiring layers on the entire surface of the substrate. Subsequently, at least a portion of the substrate may be removed by temporarily bonding the device wafer to a carrier wafer and performing a back grinding process on the device wafer. In this manner, a wafer that has been back ground so that the height of the substrate is lower than a reference height may be referred to as a bulkless wafer or a bulkless substrate.

[0058] The gate line GT and the source / drain region SD may be arranged on the first layer L1. The gate line GT may be defined as a conductive segment including a conductive material such as polysilicon and one or more metals. The source / drain region SD may include an epitaxial region of a semiconductor material such as silicon, boron, phosphorus, germanium, carbon, SiGe, and / or SiC. The gate line GT and the source / drain region SD may constitute a transistor.

[0059] The back wiring lines 11a, 11b, and 11c may be arranged on the back side of the first layer L1. The back wiring lines 11a, 11b, and 11c may extend in the first direction X and may be spaced apart from each other in the second direction Y. For example, the back wiring lines 11a, 11b, and 11c may receive a ground voltage VSS. The back vias BVA1 and BVA2 may be arranged on the back wiring lines 11a and 11c, respectively, and may extend through the first layer L1 in a vertical direction Z. The back via BVA1 may electrically connect the back wiring line 11a to the source / drain region SD1, and the back via BVA2 may electrically connect the back wiring line 11c to the source / drain region SD2.

[0060] The gate line GT4 can be connected to the front wiring pattern 12a through the gate contact CB, and the front wiring pattern 12a can be connected to the first front wiring line 13a through the second path V1. The gate line GT6 can be connected to the front wiring pattern 12b through the gate contact CB, and the front wiring pattern 12b can be connected to the third front wiring line 13c through the second path V1. The first front wiring line 13a and the third front wiring line 13c can receive the word line WL signal, so the gate lines GT4 and GT6 can receive the word line WL signal.

[0061] The source / drain region SD3 may be connected to the front wiring pattern 12j through the source / drain contact CA and the first via VA, and the front wiring pattern 12j may be connected to the second front wiring line 13b through the second via V1. For example, the source / drain region SD3 may correspond to the drains of the search transistors SG1 and SG2, and may be electrically connected to the second front wiring line 13b corresponding to the match line ML.

[0062] Figure 5 It is shown that Figure 1 FIG. 2 is a schematic diagram of an example layout of an integrated circuit 20 of a memory cell. Fig. 6A It is shown Figure 5 FIG. 2 is a top view of an example of a backside wiring layer BM of an integrated circuit 20 . Figure 6B It is shown Figure 5 FIG. 1 is a top view of an example of a first front-side wiring layer M1 of an integrated circuit 20 . Figure 6C It is shown Figure 5 FIG. 1 is a top view of an example of a second front-side wiring layer M2 of an integrated circuit 20 .

[0063] Refer to Figure 1 and Figures 5 to 6C , the integrated circuit 20 may include a gate line GT, a gate contact CB, a first via VA, a second via V1, a first front wiring layer M1, a second front wiring layer M2, a back wiring layer BM, and a back via BVA. For example, the gate line GT, the gate contact CB, and the back via BVA may constitute a memory cell MC, for example, a TCAM cell, and the memory cell MC may be implemented as a standard cell defined by a cell boundary BD. The integrated circuit 20 corresponds to Figure 2 A modified example of the integrated circuit 10 in FIG. Figures 2 to 4B The details described may apply to this implementation.

[0064] The gate lines GT may include a plurality of gate lines GT1 to GT10 extending in the first direction X. Gate contacts CB may be disposed on the gate lines GT1 to GT10 , respectively, and may be electrically connected to the gate lines GT1 to GT10 , respectively.

[0065] In some implementations, the first front wiring layer M1 and the second front wiring layer M2 may be used as signal wiring for transmitting signals to the integrated circuit 20 and power wiring for transmitting power to the integrated circuit 20, and the back wiring layer BM may be used as signal wiring for transmitting signals to the integrated circuit 20. For example, the first front wiring layer M1 and the second front wiring layer M2 may transmit a search line SL signal, a complementary search line SLB signal, and a word line WL signal to the memory cell MC, and may send a bit line BL signal and a complementary bit line BLB signal to the memory cell MC and receive a bit line BL signal and a complementary bit line BLB signal from the memory cell MC. In addition, through the first front wiring layer M1 and the second front wiring layer M2, power such as a positive power supply voltage such as a power supply voltage VDD and a negative power supply voltage such as a ground voltage VSS may be provided to the memory cell MC. For example, the back wiring layer BM may receive a match line ML signal from the memory cell MC.

[0066] The back wiring layer BM may include a back wiring line 21 extending in the first direction X. For example, the back wiring line 21 may correspond to the matching line ML. The back wiring line 21 may be connected to the source / drain region of the transistor through a back via BVA. Here, the back via BVA may be a “back source / drain contact”. For example, the back wiring line 21 may be connected to Figure 1 The back contact may be arranged between the back via BVA and the source / drain region or between the back wiring line 21 and the back via BVA.

[0067] The first front wiring layer M1 may include a plurality of front wiring patterns 22a to 22m each extending in the second direction Y. The front wiring patterns 22b, 22c, 22h, 22j, 22k, and 22m may be connected to the gate lines GT4, GT6, GT2, GT9, GT3, and GT10 through the gate contacts CB, respectively. The front wiring patterns 22a, 22d, 22e, 22f, 22g, 22i, and 22l may be connected to the gate lines GT4, GT6, GT2, GT9, GT3, and GT10 through the first vias VA and the source / drain contacts (e.g., 7A to 7C CA) is connected to the source / drain region.

[0068] The front wiring pattern 22e may correspond to a complementary bit line BLB and may be connected to, for example, source / drain regions of pass transistors PG2 and PG4. The front wiring pattern 22f may correspond to a front power rail and may transmit a power supply voltage VDD to, for example, sources of pull-up transistors PU1 to PU4. For example, the front wiring pattern 22g may correspond to a bit line BL and may be connected to, for example, source / drain regions of pass transistors PG1 and PG3.

[0069] The front wiring pattern 22k may correspond to a complementary search line SLB and may transmit a complementary search line (SLB) signal to the gate line GT3. For example, the gate line GT3 may correspond to the gate of the search transistor SG1. The front wiring pattern 22m may correspond to a search line SL and may transmit a search line SL signal to the gate line GT10. For example, the gate line GT10 may correspond to the gate of the search transistor SG2.

[0070] The second front wiring layer M2 may include first to fifth front wiring lines 23a to 23e, each extending in the first direction X. For example, the first front wiring line 23a, the third front wiring line 23c, and the fifth front wiring line 23e may correspond to a power rail that provides a ground voltage VSS. The first front wiring line 23a may be connected to the front wiring patterns 22a and 22l through the second via V1, and the front wiring patterns 22a and 22l may transmit the ground voltage VSS to the source / drain region through the first via VA and the source / drain contact CA. The third front wiring line 23c may be connected to the front wiring pattern 22i through the second via V1, and the front wiring pattern 22i may transmit the ground voltage VSS to the source / drain region through the first via VA and the source / drain contact CA. The fifth front-side wiring line 23e may be connected to the front-side wiring patterns 22d and 22l through the second via V1, and the front-side wiring patterns 22d and 22h may transmit the ground voltage VSS to the source / drain regions through the first via VA and the source / drain contacts CA.

[0071] For example, the second front wiring line 23b and the fourth front wiring line 23d may correspond to the word line WL. The second front wiring line 23b may be connected to the front wiring patterns 22b and 22h through the second via V1, and the front wiring patterns 22b and 22h may transmit the word line WL signal to the gate lines GT4 and GT2 through the gate contact CB, respectively. The fourth wiring line 23d may be connected to the front wiring patterns 22c and 22j through the second via V1, and the front wiring patterns 22c and 22j may transmit the word line WL signal to the gate lines GT6 and GT9, respectively, through the gate contact CB.

[0072] According to the present implementation, the match line ML can be implemented using the back signal line included in the back wiring layer BM, such as the back wiring line 21. In this case, since the wiring width of the back signal line can be laid out to be larger than the wiring width of the front signal line, the wiring width of the back wiring line 21 can be increased, thereby smoothly outputting the match line ML signal from the memory cell MC to improve the performance of the integrated circuit 20.

[0073] In addition, since the match line ML previously laid out on the front wiring layer is deleted, the width of the memory cell MC in the first direction X can be reduced, thereby reducing the area of ​​the integrated circuit 20. For example, the first front wiring layer M1 of the integrated circuit 20 may not include Fig. 9B Therefore, the width of the memory cell MC1 in the first direction X can be reduced according to the size of the active region, for example, the nanosheet, in which the comparison circuit CP is implemented.

[0074] Fig. 7A It is along Figure 5 An example cross-sectional view taken along line III-III′. Figure 7B It is along Figure 5 An example cross-sectional view taken along line IV-IV'. Figure 7C It is along Figure 5 Example cross-sectional view taken along line V-V'. Figure 4A and Figure 4B The description can be applied to this implementation.

[0075] Reference Fig. 7A , the gate line GT4 can be connected to the front wiring pattern 22b through the gate contact CB, and the front wiring pattern 22b can be connected to the second front wiring line 23b through the second via V1. The gate line GT6 can be connected to the front wiring pattern 22c through the gate contact CB, and the front wiring pattern 22c can be connected to the fourth front wiring line 23d through the second via V1. The second front wiring line 23b and the fourth front wiring line 23d can receive the word line WL signal, so the gate lines GT4 and GT6 can receive the word line WL signal.

[0076] The source / drain region SD4 may be connected to the front wiring pattern 22a through the source / drain contact CA and the first via VA, and the front wiring pattern 22a may be connected to the first front wiring line 23a through the second via V1. The source / drain region SD5 may be connected to the front wiring pattern 22d through the source / drain contact CA and the first via VA, and the front wiring pattern 22d may be connected to the fifth front wiring line 23e through the second via V1. Therefore, the source / drain regions SD4 and SG5 may receive the ground voltage VSS from the first front wiring line 23a and the fifth front wiring line 23e, respectively.

[0077] Reference Figure 7B, the gate line GT2 can be connected to the front wiring pattern 22h through the gate contact CB, and the front wiring pattern 22h can be connected to the second front wiring line 23b through the second via V1. The gate line GT9 can be connected to the front wiring pattern 22j through the gate contact CB, and the front wiring pattern 22j can be connected to the fourth front wiring line 23d through the second via V1. The second front wiring line 23b and the fourth front wiring line 23d can receive the word line WL signal, so the gate lines GT2 and GT9 can receive the word line WL signal.

[0078] The source / drain region SD6 may be connected to the front wiring pattern 22i through the source / drain contact CA and the first via VA, and the front wiring pattern 22i may be connected to the third front wiring line 23c through the second via V1. Accordingly, the source / drain region SD6 may receive the ground voltage VSS from the third front wiring line 23c.

[0079] Reference Figure 7C , the back wiring line 21 may be arranged on the back side of the first layer L1 and may extend in the first direction X. For example, the back wiring line 21 may correspond to the matching line ML. The back via BVA may be arranged on the back wiring line 21 and extend in the vertical direction Z by penetrating the first layer L1. The back wiring line 21 may be electrically connected to the source / drain region SD7 through the back via BVA. As a result, the output of the memory cell MC indicating a match or mismatch may be sent from the source / drain region SD7 to the back wiring line 21. Here, the back via BVA may correspond to DBC. In some implementations, the back contact may also be arranged between the back via BVA and the source / drain region SD7 or between the back wiring line 21 and the back via BVA.

[0080] Figure 8 It is shown that Figure 1 FIG. 1 is a schematic diagram of an example layout of an integrated circuit 30 of a memory cell. Fig.9A It is shown Figure 8 FIG. 1 is a top view of an example of a backside wiring layer BM of an integrated circuit 30 . Fig. 9B It is shown Figure 8 FIG. 1 is a top view of an example of a first front-side wiring layer M1 of an integrated circuit 30 . Fig. 9C It is shown Figure 8 FIG. 1 is a top view of an example of a second front-side wiring layer M2 of an integrated circuit 30 .

[0081] Refer to Figure 1 and Figures 8 to 9C, the integrated circuit 30 may include a gate line GT, a gate contact CB, a first via VA, a second via V1, a first front wiring layer M1, a second front wiring layer M2, a back wiring layer BM, and a back via BVA. For example, the gate line GT, the gate contact CB, and the back via BVA may constitute Figure 1 The integrated circuit 20 corresponds to a memory cell MC, for example, a TCAM cell, and the memory cell MC may be implemented as a standard cell defined by a cell boundary BD. Figure 2 A modified example of the integrated circuit 10 in FIG. Figures 2 to 4B The details described may apply to this implementation.

[0082] The gate line GT may include a plurality of gate lines GT1 to GT10 extending in the first direction X. The backside path BVA may be arranged below each of the gate lines GT2, GT4, GT6, and GT9, and may be electrically connected to each of the gate lines GT2, GT4, GT6, and GT9. The gate contact CB may be arranged on the gate lines GT1, GT3, GT5, GT7, GT8, and GT10, respectively, and may be electrically connected to the gate lines GT1, GT3, GT5, GT7, GT8, and GT10.

[0083] In some implementations, the first front wiring layer M1 and the second front wiring layer M2 may be used as signal wiring for transmitting signals to the integrated circuit 30 and power wiring for transmitting power to the integrated circuit 30, and the back wiring layer BM may be used as signal wiring for transmitting signals to the integrated circuit 30. For example, the bit line BL signal and the complementary bit line BLB signal may be transmitted to the memory cell MC through the first front wiring layer M1 and the second front wiring layer M2, and the bit line BL signal and the complementary bit line BLB signal may be received from the memory cell MC, the search line SL signal and the complementary search line SLB signal may be transmitted to the memory cell MC through the first front wiring layer M1 and the second front wiring layer M2, and the match line ML signal may be received from the memory cell MC through the first front wiring layer M1 and the second front wiring layer M2. In addition, power such as a positive power supply voltage such as a power supply voltage VDD and a negative power supply voltage such as a ground voltage VSS may be provided to the memory cell MC through the first front wiring layer M1 and the second front wiring layer M2. For example, the back wiring layer BM may transmit a word line WL signal to the memory cell MC.

[0084] The back wiring layer BM may include back wiring lines 31a and 31b extending in the first direction X. For example, the back wiring lines 31a and 31b may correspond to word lines WL. The back wiring line 31a may transmit word line WL signals to the gate lines GT2 and GT4 through the back via BVA, and the back wiring line 31b may transmit word line WL signals to the gate lines GT6 and GT9 through the back via BVA. Here, the back via BVA may be a "back gate contact".

[0085] The first front wiring layer M1 may include a plurality of front wiring patterns 32a to 32j each extending in the second direction Y. The front wiring patterns 32a, 32b, 32c, 32d, 32e, 32f, 32h, and 32j may be connected to the source / drain contacts (e.g., Fig. 10A and Fig. 10B The front wiring patterns 32g and 32i may be connected to the gate lines GT3 and GT10 through the gate contacts CB, respectively.

[0086] The front wiring pattern 32c may correspond to a complementary bit line BLB and may be connected to, for example, source / drain regions of pass transistors PG2 and PG4. The front wiring pattern 32d may correspond to a front power rail and may transmit, for example, a power supply voltage VDD to the sources of pull-up transistors PU1 to PU4. For example, the front wiring pattern 32e may correspond to a bit line BL and may be connected to, for example, source / drain regions of pass transistors PG1 and PG3.

[0087] The front wiring pattern 32g may correspond to a complementary search line SLB and may transmit a complementary search line (SLB) signal to the gate line GT3. For example, the gate line GT3 may correspond to the gate of the search transistor SG1. The front wiring pattern 32i may correspond to a search line SL and may transmit a search line SL signal to the gate line GT10. For example, the gate line GT10 may correspond to the gate of the search transistor SG2.

[0088] The second front wiring layer M2 may include first to fifth front wiring lines 33a to 33e, each extending in the first direction X. For example, the first front wiring line 33a, the third front wiring line 33c, and the fifth front wiring line 33e may correspond to a power rail that provides a ground voltage VSS. The first front wiring line 33a may be connected to the front wiring patterns 32a and 32h through the second via V1, and the front wiring patterns 32a and 32h may transmit the ground voltage VSS to the source / drain region through the first via VA and the source / drain contact CA. The third front wiring line 33c may be connected to the front wiring pattern 32f through the second via V1, and the front wiring pattern 32f may transmit the ground voltage VSS to the source / drain region through the first via VA and the source / drain contact CA. The fifth front-side wiring line 33e may be connected to the front-side wiring patterns 32b and 32h through the second via V1, and the front-side wiring patterns 32b and 32h may transmit the ground voltage VSS to the source / drain regions through the first via VA and the source / drain contacts CA.

[0089] For example, the second front wiring line 33b and the fourth front wiring line 33d may correspond to the matching line ML. The second front wiring line 33b and the fourth front wiring line 33d may be connected to the front wiring pattern 32j through the second via V1, and the front wiring pattern 32j may be connected to the source / drain region through the first via VA and the source / drain contact CA.

[0090] According to the present implementation, the word line WL can be implemented by using the back signal line such as the back wiring lines 31a and 31b included in the back wiring layer BM. In this case, since the wiring width of the back signal line can be arranged to be larger than the wiring width of the front signal line, the wiring width of each of the back wiring lines 21a and 21b can be increased. As a result, the word line resistance can be reduced and the word line WL signal can be smoothly supplied to the memory cell MC to improve the performance of the integrated circuit 30.

[0091] In addition, the wiring width of the front wiring line included in the front wiring layer can be increased by arranging the word line conventionally arranged on the front wiring layer on the back wiring layer BM. For example, the wiring width of each of the power rails such as the first front wiring line 33a, the third front wiring line 33c, and the fifth front wiring line 33e included in the second front wiring layer M2 can be increased, so as to smoothly supply the ground voltage VSS to the memory cell MC. In addition, for example, the wiring width of each of the match lines ML such as the second front wiring line 33b and the fourth front wiring line 33d included in the second front wiring layer M2 can be increased, so as to smoothly output the match line ML signal from the memory cell MC to improve the performance of the integrated circuit 30.

[0092] Fig. 10A It is along Figure 8 An example cross-sectional view taken along line VI-VI' of Fig. 10B It is along Figure 8 Example cross-sectional view taken along line VII-VII'. Figure 4A and Figure 4B The description can be applied to this implementation.

[0093] Reference Fig. 10A , back wiring lines 31a and 31b may be arranged on the back side of the first layer L1. The back wiring lines 31a and 31b may extend in the first direction X and may be spaced apart from each other in the second direction Y. For example, the back wiring lines 31a and 31b may correspond to the word line WL. The back vias BVA3 and BVA4 may be arranged on the back wiring lines 31a and 31b, respectively, and may extend through the first layer L1 in the vertical direction Z. The back wiring line 31a may be electrically connected to the gate line GT4 through the back via BVA3. The back wiring line 31b may be electrically connected to the gate line GT6 through the back via BVA4. Accordingly, the gate lines GT4 and GT6 may receive the word line WL signal.

[0094] The source / drain region SD8 may be connected to the front wiring pattern 32a through the source / drain contact CA and the first via VA, and the front wiring pattern 32a may be connected to the first front wiring line 33a through the second via V1. The source / drain region SD9 may be connected to the front wiring pattern 32b through the source / drain contact CA and the first via VA, and the front wiring pattern 32b may be connected to the fifth front wiring line 33e through the second via V1. Therefore, the source / drain regions SD8 and SD9 may receive the ground voltage VSS.

[0095] Reference Fig. 10B , the source / drain region SD10 can be connected to the front wiring pattern 32j through the source / drain contact CA and the first via VA, and the front wiring pattern 32j can be connected to the second front wiring line 33b and the fourth front wiring line 33d through the second via V1. Therefore, the source / drain region SD10 can be electrically connected to the match line ML.

[0096] Fig.11 is a block diagram illustrating an example of the memory device 40 .

[0097] Reference Fig.11, the memory device 40 may include a cell array 41, a row decoder 42, a search driver 43, a read / write circuit 44, and a matching circuit 45. Here, the row decoder 42, the search driver 43, the read / write circuit 44, and the matching circuit 45 may be collectively referred to as a peripheral circuit. In some implementations, the peripheral circuit may also include a control circuit, a command buffer, an address buffer, a voltage generator, and / or a data input / output circuit.

[0098] The cell array 41 may include a plurality of memory cells, and each memory cell may correspond to Figure 1 The memory cell MC is, for example, a TCAM cell. Accordingly, the cell array 41 may be implemented as described above with reference to Figures 2 to 10B The row decoder 42 may be connected to the cell array 41 through a plurality of word lines WL, and may activate a selected word line among the plurality of word lines WL in response to a command and an address. Accordingly, a memory cell connected to the activated selected word line may be selected from among the memory cells included in the cell array 41.

[0099] The search driver 43 may be connected to the cell array 41 through a plurality of search lines SL, and may provide a search word for searching a memory address to the cell array 41. Accordingly, search data or a search word may be input to the cell array 41 through the search line. The read / write circuit 44 may be connected to the cell array 41 through a plurality of bit lines BL, and may latch write data and read data. During a write operation, the read / write circuit 44 may function as a write driver that provides write data to the cell array 41 through a plurality of bit lines BL. During a read operation, the read / write circuit 44 may function as a sense amplifier that receives read data from the cell array 41 through a plurality of bit lines BL.

[0100] The matching circuit 45 may be connected to the cell array 41 through a plurality of match lines ML. The matching circuit 45 may function as an encoder that outputs an address corresponding to currently input search data in response to a logic state of the plurality of match lines ML. For example, the matching circuit 45 may output an address of a memory cell storing data matching the search data based on a voltage received through the match line ML.

[0101] In some implementations, a back wiring layer including a back power rail may be arranged below the cell array 41. For example, each memory cell MC may receive a ground voltage VSS from the back power rail via a back path or DBC. In some implementations, a back wiring layer including a match line ML may be arranged below the cell array 41. For example, the output node of each memory cell MC may be connected to the match line ML via a back path or DBC. In some implementations, a back wiring layer including a word line WL may be arranged below the cell array 41. For example, each memory cell MC may be connected to the word line WL via a back path.

[0102] In some implementations, a back wiring layer including a back power rail and a match line ML may be arranged below the cell array 41, and each memory cell MC may receive a supply voltage from the back power rail and output a comparison result through the match line ML. In some implementations, a back wiring layer including a back power rail and a word line WL may be arranged below the cell array 41, and each memory cell MC may receive a supply voltage from the back power rail and receive a word line signal through the word line WL. In some implementations, a back wiring layer including a match line ML and a word line WL may be arranged below the cell array 41, and each memory cell MC may output a comparison result through the match line ML and receive a word line signal through the word line WL. In some implementations, a back wiring layer including a back power rail, a match line ML and a word line WL may be arranged below the cell array 41, and each memory cell MC may receive a supply voltage from the back power rail, output a comparison result through the match line ML, and receive a word line signal through the word line WL.

[0103] FIG. 12A to FIG. 12D is a diagram showing an example of an element. For example, Fig. 12A FinFET 50a is shown, Fig. 12B A gate-all-around field effect transistor (GAAFET) 50b is shown, Fig. 12C A multi-bridge channel field effect transistor (MBCFET) 50c is shown, and Fig.12D A dummy field effect transistor (VFET) 50d is shown. For ease of illustration, FIG. 12A to FIG. 12C shows a state where one of the two source / drain regions is removed, and Fig.12D The VFET 50 d is shown as a cross section cut into a plane parallel to a plane formed along the second direction Y and the vertical direction Z and passing through the channel CH of the VFET 50 d.

[0104] Reference Fig. 12A, the FinFET 50a may be formed of a fin-shaped active pattern extending in a first direction X between shallow trench isolators (STI) and a gate G extending in a second direction Y. Source / drain S / D may be formed on both sides of the gate G, and accordingly, the source and the drain may be spaced apart from each other in the first direction X. An insulating layer may be formed between the channel CH and the gate G. In some implementations, the FinFET 50a may be formed of a gate G and a plurality of active patterns spaced apart from each other in the second direction Y.

[0105] Reference Fig. 12B , the GAAFET 50b may be formed of active patterns, i.e., nanowires, which are spaced apart from each other in the vertical direction Z and extend in the first direction X, and a gate G which extends in the second direction Y. The source / drain S / D may be formed on both sides of the gate G, and accordingly, the source and the drain may be spaced apart from each other in the first direction X. An insulating layer may be formed between the channel CH and the gate G. Note that the number of nanowires included in the GAAFET 50b is not limited to Fig. 12B The quantity shown in .

[0106] Reference Fig. 12C , the MBCFET 50c may be formed of active patterns, i.e., nanosheets, which are spaced apart from each other in the vertical direction Z and extend in the first direction X, and a gate G which extends in the second direction Y. The source / drain S / D may be formed on both sides of the gate G, and accordingly, the source and the drain may be spaced apart from each other in the first direction X. An insulating layer may be formed between the channel CH and the gate G. Note that the number of nanosheets included in the MBCFET 50c is not limited to Fig. 12C The quantity shown in .

[0107] Reference Fig.12D , the VFET 50d may include a top source / drain T_S / D and a bottom source / drain B_S / D spaced apart from each other in the vertical direction Z and a channel CH located between the top source / drain T_S / D and the bottom source / drain B_S / D. The VFET 50d may include a gate G surrounding the periphery of the channel CH between the top source / drain T_S / D and the bottom source / drain B_S / D. An insulating layer may be formed between the channel CH and the gate G.

[0108] However, the transistor is not limited to the above structure. For example, the integrated circuit may include a ForkFET in which a nanosheet for a P-type transistor is separated from a nanosheet for an N-type transistor by a dielectric wall so that an N-type transistor and a P-type transistor are closer to each other. In addition, the integrated circuit may include a bipolar junction transistor and a FET such as a CFET, a NCFET, a CNTFET, etc.

[0109] Fig.13is a flow chart illustrating an example of a method of manufacturing an integrated circuit.

[0110] Reference Fig.13 , the method is a method for manufacturing an integrated circuit IC including a standard cell, and may include a plurality of operations S10, S30, S50, S70, and S90. The cell library (or standard cell library) D12 may include information about the standard cell, for example, information about functions, characteristics, layouts, and the like. In some configurations, the cell library D12 may define a tap cell and a dummy cell and a functional cell that generates an output signal according to an input signal. In some implementations, the cell library D12 may define a storage cell and a dummy cell with the same footprint. The design rule D14 may include requirements that the layout of the integrated circuit IC must comply with. For example, the design rule D14 may include requirements for the space between patterns in the same layer, the minimum width of the pattern, the wiring direction of the wiring layer, and the like. In some implementations, the design rule D14 may define the minimum separation distance within the same track of the wiring layer.

[0111] In operation S10, a logic synthesis operation of generating netlist data D13 from RTL data D11 may be performed. For example, a semiconductor design tool (e.g., a logic synthesis tool) may perform logic synthesis from RTL data D11 written in a hardware description language (HDL) such as VHSIC hardware description language (VHDL) and Verilog by referring to a cell library D12, and may generate netlist data D13 including a bitstream or a netlist. Netlist data D13 may correspond to an input of a layout and routing to be described later.

[0112] In operation S30, the standard cells may be arranged. For example, a semiconductor design tool (e.g., a P&R tool) may arrange the standard cells used in the netlist data D13 by referring to the cell library D12. In some implementations, the semiconductor design tool may arrange the standard cells into a row extending in the X-axis direction or the Y-axis direction, and the arranged standard cells may receive power from a power rail extending along a boundary of the row.

[0113] In operation S50, the pins of the standard cells can be wired. For example, the semiconductor design tool can generate interconnections that electrically connect the output pins and input pins of the arranged standard cells, and can generate layout data D15 that defines the arranged standard cells and the generated interconnections. The interconnections may include a path in a path layer and / or a pattern in a wiring layer. The wiring layer may include a front wiring layer arranged above the front side of the substrate and a back wiring layer arranged on the back side of the substrate. The layout data D15 may, for example, have a format such as GDSII, and may include geometric information of the cells and the interconnections. The semiconductor design tool may refer to the design rule D14 when wiring the pins of the cells. The layout data D15 may correspond to the output of the layout and wiring. Only operation S50 or operations S30 and S50 may be collectively referred to as a method for designing an integrated circuit.

[0114] In some implementations, such as Figures 2 to 10B As shown in , an integrated circuit may include a backside wiring layer, the backside wiring layer including at least one backside power rail and / or at least one backside signal line. Specifically, a memory cell implemented as a standard cell, such as a TCAM cell, may receive power such as a power supply voltage or a ground voltage through the backside power rail. In addition, a memory cell implemented as a standard cell, such as a TCAM cell, may receive an input signal or transmit an output signal via at least one backside signal line. Accordingly, the performance of the integrated circuit may be improved, and the wiring freedom of the frontside wiring layer may be improved.

[0115] In some implementations, each memory cell MC may receive a supply voltage, such as a ground voltage, from a back power rail disposed on a back wiring layer through a back path or DBC. In some implementations, the output node of each memory cell may be connected to a match line ML disposed on a back wiring layer through a back path or DBC. In some implementations, each memory cell MC may be connected to a word line WL disposed on a back wiring layer through a back path. However, the implementation is not limited thereto, and at least one of the signal lines connected to each memory cell MC, such as a bit line BL, a complementary bit line BLB, a search line SL, a complementary search line SLB, a match line ML, a word line WL, a power supply voltage VDD power rail, and a ground voltage VSS power rail, may be disposed on the back wiring layer.

[0116] In some implementations, each memory cell MC may receive a supply voltage from a back power rail disposed on a back wiring layer, and output a comparison result through a match line ML disposed on the back wiring layer. In some implementations, each memory cell MC may receive a supply voltage from a back power rail disposed on a back wiring layer, and receive a word line signal through a word line WL disposed on the back wiring layer. In some implementations, each memory cell MC may output a comparison result through a match line ML disposed on a back wiring layer, and receive a word line signal through a word line WL disposed on the back wiring layer. In some implementations, each memory cell MC may receive a supply voltage from a back power rail included in a back wiring layer, output a comparison result through a match line ML disposed in the back wiring layer, and receive a word line signal through a word line WL disposed in the back wiring layer.

[0117] In operation S70, an operation of manufacturing a mask may be performed. For example, optical proximity correction (OPC) for correcting distortion phenomena such as refraction due to light characteristics in photolithography may be applied to the layout data D15. A pattern on the mask may be defined to form patterns arranged on a plurality of layers based on the data to which OPC is applied, and at least one mask (or photomask) for forming a pattern in each of the plurality of layers may be manufactured. In some implementations, the layout of the integrated circuit IC may be limitedly modified in operation S70, and the limited modification of the integrated circuit IC in operation S70 may refer to design polishing as post-processing for optimizing the structure of the integrated circuit IC.

[0118] In operation S90, an operation of manufacturing an integrated circuit IC may be performed. For example, an integrated circuit IC may be manufactured by patterning a plurality of layers using at least one mask manufactured in operation S70. The front end process (FEOL) may include, for example, planarizing and cleaning the wafer, forming a groove, forming a well, forming a gate line, and forming a source and a drain. Through the FEOL, independent devices such as transistors, capacitors, resistors, etc. may be formed on the substrate. In addition, the back end process (BEOL) may include operations such as silicided gates, source and drain regions, adding dielectrics, planarizing, forming holes, adding metal layers, forming paths, forming passivation layers, etc. Through the BEOL, independent devices such as transistors, capacitors, resistors, etc. may be interconnected. In some implementations, a middle process (MOL) may be performed between the FEOL and the BEOL, and contacts may be formed on independent devices. Then, the integrated circuit IC may be packaged in a semiconductor package and used as a component for various applications.

[0119] Fig.14 is a block diagram illustrating an example of a system on chip 210 .

[0120] Reference Fig.14 , a system on chip (SoC) 210 may refer to an integrated circuit in which components of a computing system or other electronic system are integrated. For example, as an example of SoC 210, an application processor (AP) may include components for a processor and other functions. SoC 210 may include a core 211, a digital signal processor (DSP) 212, a graphics processing unit (GPU) 213, an embedded memory 214, a communication interface 215, and a memory interface 216. The components of SoC 210 may communicate with each other through a bus 217.

[0121] The core 211 may process instructions and control operations of the components included in the SoC 210. For example, the core 211 may drive an operating system by processing a series of instructions and execute an application on the operating system. The DSP 212 may generate useful data by processing digital signals such as digital signals provided from the communication interface 215. The GPU 213 may generate data of an image output by a display device based on image data provided from the embedded memory 214 or the memory interface 216, or may encode the image data. In some implementations, the integrated circuit described above with reference to the accompanying drawings may be included in the core 211, the DSP 212, the GPU 213, and / or the embedded memory 214.

[0122] The embedded memory 214 may store data required for the operation of the core 211, the DSP 212, and the GPU 213. The communication interface 215 may provide an interface for a communication network or one-to-one communication. The memory interface 216 may provide an interface for an external memory (e.g., dynamic random access memory (DRAM), flash memory, etc.) of the SoC 210.

[0123] Fig.15 is a block diagram illustrating an example of a computing system 220 including a memory for storing programs.

[0124] Reference Fig.15 , the method of designing an integrated circuit, such as at least some of the operations in the above flowchart, may be performed in a computing system (or computer) 220. The computing system 220 may include a processor 221, an input / output device 222, a network interface 223, a random access memory (RAM) 224, a read-only memory (ROM) 225, and a storage device 226. The processor 221, the input / output device 222, the network interface 223, the RAM 224, the ROM 225, and the storage device 226 may be connected to a bus 227 and may communicate with each other through the bus 227.

[0125] The processor 221 may be referred to as a processing component and may include at least one core such as a microprocessor, an AP, a DSP, and a GPU that can execute any instruction set (e.g., Intel Architecture-32 (IA-32), 64-bit extensions to IA-32, x86-64, PowerPC, Spark, MIPS, ARM, IA-64, etc.). For example, the processor 221 may access a memory, i.e., a RAM 224 or a ROM 225, through a bus 227 and execute instructions stored in the RAM 224 or the ROM 225.

[0126] The RAM 224 may store a program 224_1 for a method of designing an integrated circuit or at least a portion thereof, and the program 224_1 may enable the processor 221 to execute the method of designing an integrated circuit, for example, Fig.13 That is, the program 224_1 may include a plurality of instructions executable by the processor 221, and the plurality of instructions included in the program 224_1 may enable the processor 221 to perform at least some of the operations included in the above-mentioned flowchart, for example.

[0127] If the power supplied to the computing system 220 is cut off, the storage device 226 will not lose the stored data. The storage device 226 can store the program 224_1, and the program 224_1 or at least a part thereof can be loaded from the storage device 226 to the RAM 224 before the program 224_1 is executed by the processor 221. Alternatively, the storage device 226 can store a file written in a program language, and the program 224_1 or at least a part thereof generated by a compiler or the like can be loaded from the file to the RAM 224. In addition, the storage device 226 can store a database 226_1, and the database 226_1 can include information such as information about Fig.13 The information of the designed blocks, the cell library D12 and / or the design rules D14 is information required for designing an integrated circuit.

[0128] The storage device 226 may store data to be processed by the processor 221 or data that has been processed by the processor 221. That is, the processor 221 may generate data by processing the data stored in the storage device 226 according to the program 224_1, and may store the generated data in the storage device 226. For example, the storage device 226 may store Fig.13 RTL data D11, netlist data D13 and / or layout data D15.

[0129] The input / output device 222 may include input devices such as a keyboard, a pointing device, etc., and may include output devices such as a display device, a printer, etc. For example, a user may trigger the processor 221 to execute the program 224_1 through the input / output device 222. Fig.13 The RTL data D11 and / or netlist data D13, or check Fig.13 The network interface 223 may provide access to a network external to the computing system 220. For example, the network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other type of links.

[0130] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any invention or on the scope that can be claimed, but rather as descriptions of features that can be specific to a specific implementation of a particular invention. Certain features described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation can also be implemented individually in multiple implementations or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, in some cases, one or more features in a combination may be deleted from the combination, and a combination may involve a sub-combination or a variation of a sub-combination.

[0131] While the present disclosure has been particularly shown and described with reference to implementations thereof, various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit, comprising: A TCAM unit, the TCAM unit is located on the front side of the substrate, the TCAM unit includes a first unit storing a first value, a second unit storing a second value, and a comparison circuit connected to the first unit and the second unit, the TCAM unit is a ternary content addressable memory unit; a backside via extending through the substrate in a perpendicular direction relative to the substrate; a backside wiring layer located on a backside of the substrate, the backside wiring layer comprising at least one backside power rail configured to send a supply voltage to the TCAM cell through the backside via; and A front wiring layer, the front wiring layer is located above the TCAM unit in the vertical direction, the front wiring layer includes a bit line connected to the first unit and the second unit, a complementary bit line connected to the first unit and the second unit, and a match line connected to the comparison circuit.

2. The integrated circuit according to claim 1, wherein: The supply voltage corresponds to the ground voltage, and The at least one backside power rail is configured to transmit the ground voltage to the TCAM cell through the backside via.

3. The integrated circuit according to claim 2, wherein: The at least one back power rail includes a plurality of back power rails extending in a first direction and spaced apart from each other in a second direction intersecting the first direction.

4. The integrated circuit according to claim 2, wherein: The front-side wiring layer includes a front-side power rail configured to deliver a supply voltage to the TCAM cells.

5. The integrated circuit according to claim 1, wherein: The front wiring layer comprises: A search line connected to the comparison circuit; and a complementary search line connected to the comparison circuit, and Wherein, the comparison circuit is configured as: comparing a search value with the first value and the second value, the search value being input to the search line and the complementary search line; and The comparison result of the search value with the first value and the second value is output through the match line.

6. The integrated circuit of claim 1, wherein: The front-side wiring layer includes a word line connected to the first cell and the second cell.

7. The integrated circuit according to claim 1, wherein: The at least one rear power rail extends in a first direction, and The front wiring layer comprises: a first front-side wiring layer, the first front-side wiring layer including the bit line and the complementary bit line, the first front-side wiring layer extending in a second direction intersecting the first direction; and A second front-side wiring layer is located above the first front-side wiring layer in the vertical direction, and includes a plurality of word lines extending in the first direction and the matching line.

8. An integrated circuit, comprising: A TCAM unit, the TCAM unit is located on the front side of the substrate, the TCAM unit includes a first unit storing a first value, a second unit storing a second value, and a comparison circuit connected to the first unit and the second unit, the TCAM unit is a ternary content addressable memory unit; a backside via extending through the substrate in a perpendicular direction relative to the substrate; a backside wiring layer, the backside wiring layer being located on the backside of the substrate, the backside wiring layer comprising a matching line connected to the comparison circuit through the backside via; and A front side wiring layer is located above the TCAM cell in the vertical direction, the front side wiring layer comprising a bit line connected to the first cell and the second cell, a complementary bit line connected to the first cell and the second cell, and at least one front side power rail configured to send a supply voltage to the TCAM cell.

9. The integrated circuit of claim 8, wherein: The comparison circuit includes a source / drain region corresponding to an output node of the TCAM cell, and The matching line is connected to the source / drain region through the backside via.

10. The integrated circuit of claim 8, wherein: The supply voltage corresponds to the ground voltage, and The at least one front side power rail is configured to transmit the ground voltage to the TCAM cell through a via.

11. The integrated circuit of claim 8, wherein: The supply voltage corresponds to the power supply voltage, and The at least one front side power rail is configured to deliver the supply voltage to the TCAM cell through a via.

12. The integrated circuit of claim 8, wherein: The front wiring layer comprises: A search line connected to the comparison circuit; and a complementary search line connected to the comparison circuit, and Wherein, the comparison circuit is configured as: comparing a search value with the first value and the second value, the search value being input to the search line and the complementary search line; and The comparison result of the search value with the first value and the second value is output through the match line.

13. The integrated circuit of claim 8, wherein: The front-side wiring layer includes a word line connected to the first cell and the second cell.

14. An integrated circuit, comprising: A TCAM unit, the TCAM unit is located on the front side of the substrate, the TCAM unit includes a first unit storing a first value, a second unit storing a second value, and a comparison circuit connected to the first unit and the second unit, the TCAM unit is a ternary content addressable memory unit; a backside via extending through the substrate in a perpendicular direction relative to the substrate; a backside wiring layer, the backside wiring layer being located on the backside of the substrate, the backside wiring layer comprising at least one word line connected to the first unit and the second unit through the backside via; and A front side wiring layer is located above the TCAM cell in the vertical direction, the front side wiring layer comprising a bit line connected to the first cell and the second cell, a complementary bit line connected to the first cell and the second cell, and at least one front side power rail configured to send a supply voltage to the TCAM cell.

15. The integrated circuit of claim 14, wherein: The at least one word line is configured to transmit a word line signal to a gate of a transistor through the back side via, the transistor being included in the first cell or the second cell.

16. The integrated circuit of claim 14, wherein: The at least one word line comprises: a first word line and a second word line, the first word line and the second word line extending in a first direction and spaced apart from each other in a second direction, the second direction intersecting the first direction, and Wherein, the back passage comprises: a first backside via, the first backside via being located on the first wordline; and a second backside via, the second backside via being located on the second word line, wherein The first word line is configured to transmit a first word line signal to a gate of a first transistor through the first back via, the first transistor being included in the first cell, and The second word line is configured to transmit a second word line signal to a gate of a second transistor included in the second cell through the second back via.

17. The integrated circuit of claim 14, wherein: The supply voltage corresponds to the ground voltage, and The at least one front side power rail is configured to transmit the ground voltage to the TCAM cell through a via.

18. The integrated circuit of claim 14, wherein: The supply voltage corresponds to the power supply voltage, and The at least one front side power rail is configured to transmit the supply voltage to the TCAM cells through a via.

19. The integrated circuit of claim 14, wherein: The front wiring layer comprises: A search line connected to the comparison circuit; and a complementary search line connected to the comparison circuit, and The comparison circuit is configured to compare a search value with the first value and the second value, the search value being input to the search line and the complementary search line.

20. The integrated circuit of claim 19, wherein: The front wiring layer comprises: a match line connected to the comparison circuit; and The comparison circuit is configured to output a comparison result between the search value and the first value and the second value through the match line.

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