Memory device and operating method thereof, memory system

Abstract

This application provides a memory device and its operation method, and a memory system. The memory device includes: a memory cell array, including a first memory stack and a second memory stack stacked and adjacent to each other; and peripheral circuitry coupled to the memory cell array and configured to: when programming a selected memory cell layer in the first memory stack, apply a programming voltage to the word line layer corresponding to the selected memory cell layer, and apply a first pass voltage to the word line layer corresponding to an unselected memory cell layer in the first memory stack; apply a second pass voltage to the word line layers corresponding to multiple memory cell layers in the second memory stack; and apply a third pass voltage to the dummy word line layer corresponding to at least one dummy memory cell layer at the junction of the first and second memory stacks; wherein the third pass voltage is less than the second pass voltage, and the second pass voltage is less than the first pass voltage.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a memory device and its operation method, and a memory system. Background Technology

[0002] As the number of stacked layers in three-dimensional storage devices (such as 3D NAND flash memory) increases, the channel length becomes longer, leading to increased programming voltage disturbance (Vpgm disturb) and pass voltage disturbance (Vpass disturb) during Program Erase Read (PER) operations. Therefore, reducing programming voltage disturbance and pass voltage disturbance in 3D NAND flash memory has become a pressing technical problem. Summary of the Invention

[0003] In a first aspect, embodiments of this application provide a memory device, comprising: a memory cell array, including a first memory stack and a second memory stack stacked and adjacent to each other; both the first memory stack and the second memory stack include multiple memory cell layers and word line layers corresponding to each memory cell layer, and at least one dummy memory cell layer and a dummy word line layer corresponding to each dummy memory cell layer are disposed at the junction of the first memory stack and the second memory stack; peripheral circuitry, coupled to the memory cell array, and configured to: when performing a programming operation on a selected memory cell layer in the first memory stack, apply a programming voltage to the word line layer corresponding to the selected memory cell layer, and apply a first pass voltage to the word line layer corresponding to an unselected memory cell layer in the first memory stack; apply a second pass voltage to the word line layers corresponding to multiple memory cell layers in the second memory stack; and apply a third pass voltage to the dummy word line layer corresponding to at least one dummy memory cell layer at the junction of the first memory stack and the second memory stack; wherein the third pass voltage is less than the second pass voltage, and the second pass voltage is less than the first pass voltage.

[0004] In some embodiments, the first through voltage and the second through voltage have a first difference; the second through voltage and the third through voltage have a second difference; the first difference and the second difference are different.

[0005] In some embodiments, the second difference is greater than the first difference.

[0006] In some embodiments, multiple storage cell layers in the second storage stack are all in a programmed state.

[0007] In some embodiments, the unselected memory cell layer in the first memory stack includes a memory cell layer in a programmed state and a memory cell layer in an erased state; the first through voltage includes a first sub-through voltage and a second sub-through voltage; the peripheral circuit is configured to apply the first sub-through voltage to the word line layer corresponding to the memory cell layer in the programmed state and apply the second sub-through voltage to the word line layer corresponding to the memory cell layer in the erased state; the first sub-through voltage and the second sub-through voltage are different.

[0008] In some embodiments, the memory cell array further includes a third memory stack stacked with both the first memory stack and the second memory stack; the third memory stack is disposed adjacent to the first memory stack, and at least one dummy memory cell layer and a dummy word line layer corresponding to each dummy memory cell layer are disposed at the junction of the third memory stack and the first memory stack; the peripheral circuitry is configured to apply a third pass voltage to the dummy word line layer corresponding to at least one dummy memory cell layer at the junction of the first memory stack and the third memory stack; or, the third memory stack is disposed adjacent to the second memory stack, and at least one dummy memory cell layer and a dummy word line layer corresponding to each dummy memory cell layer are disposed at the junction of the third memory stack and the second memory stack; the peripheral circuitry is configured to apply a second pass voltage to the dummy word line layer corresponding to at least one dummy memory cell layer at the junction of the second memory stack and the third memory stack.

[0009] In some embodiments, at least one dummy storage cell layer and a dummy word line layer corresponding to each dummy storage cell layer at the junction of the first storage stack and the second storage stack belong to the first storage stack and / or the second storage stack.

[0010] In some embodiments, at least one dummy word line layer at the junction of the first memory stack and the second memory stack includes a first dummy word line layer located in the first memory stack and a second dummy word line layer located in the second memory stack; the third pass voltage includes a third sub-pass voltage and a fourth sub-pass voltage; the peripheral circuitry is configured to apply a third sub-pass voltage to the first dummy word line layer and apply a fourth sub-pass voltage to the second dummy word line layer; the third sub-pass voltage and the fourth sub-pass voltage are different.

[0011] In some embodiments, the peripheral circuitry is configured to perform sequential programming operations or reverse programming operations on the multiple memory cell layers in the first memory stack when programming operations are performed on the multiple memory cell layers in the first memory stack.

[0012] Secondly, embodiments of this application provide a memory system, including: one or more memory devices according to any of the above embodiments; and a memory controller coupled to the memory and controlling the memory devices.

[0013] Thirdly, embodiments of this application provide an operation method for a memory device, comprising: when programming a selected memory cell layer in a first memory stack of a memory cell array of the memory device, applying a programming voltage to a word line layer corresponding to the selected memory cell layer, and applying a first pass voltage to a word line layer corresponding to an unselected memory cell layer in the first memory stack; applying a second pass voltage to word line layers corresponding to multiple memory cell layers in a second memory stack stacked and adjacent to the first memory stack; and applying a third pass voltage to a dummy word line layer corresponding to at least one dummy memory cell layer at the junction of the first memory stack and the second memory stack; wherein the third pass voltage is less than the second pass voltage, and the second pass voltage is less than the first pass voltage.

[0014] In some embodiments, the unselected memory cell layer in the first memory stack includes a memory cell layer in a programmed state and a memory cell layer in an erased state; the first through voltage includes a first sub-through voltage and a second sub-through voltage; applying the first through voltage to the word line layer corresponding to the unselected memory cell layer in the first memory stack includes applying the first sub-through voltage to the word line layer corresponding to the memory cell layer in a programmed state and applying the second sub-through voltage to the word line layer corresponding to the memory cell layer in an erased state; the first sub-through voltage and the second sub-through voltage are different.

[0015] In some embodiments, the memory cell array includes a third memory stack stacked with both the first memory stack and the second memory stack; when the third memory stack is adjacent to the first memory stack, at least one dummy memory cell layer and a dummy word line layer corresponding to each dummy memory cell layer are provided at the junction of the third memory stack and the first memory stack; the method further includes: applying a third through voltage to the dummy word line layer corresponding to at least one dummy memory cell layer at the junction between the first memory stack and the third memory stack; or, when the third memory stack is adjacent to the second memory stack, at least one dummy memory cell layer and a dummy word line layer corresponding to each dummy memory cell layer are provided at the junction between the third memory stack and the second memory stack; the method further includes: applying a second through voltage to the dummy word line layers corresponding to at least one dummy memory cell layer at the junction between the second memory stack and the third memory stack.

[0016] In some embodiments, at least one dummy word line layer at the junction of the first memory stack and the second memory stack includes a first dummy word line layer located in the first memory stack and a second dummy word line layer located in the second memory stack; the third pass voltage includes a third sub-pass voltage and a fourth sub-pass voltage; applying the third pass voltage to the dummy word line layer corresponding to at least one dummy memory cell layer at the junction of the first memory stack and the second memory stack includes: applying a third sub-pass voltage to the first dummy word line layer and applying a fourth sub-pass voltage to the second dummy word line layer; the third sub-pass voltage and the fourth sub-pass voltage are different.

[0017] In some embodiments, the method further includes: when programming multiple storage cell layers in the first storage stack, performing sequential programming operations or reverse programming operations on the multiple storage cell layers in the first storage stack.

[0018] In various embodiments of this application, the memory device includes a first memory stack and a second memory stack arranged adjacent to each other. During independent encoding, erasing, and reading operations on the selected memory stack (first memory stack), the non-selection word line layer of the selected memory stack needs to maintain a high pass voltage (first pass voltage) to increase the boost potential of the selected word line layer and suppress programming voltage interference. The non-selection word line layer of the non-selection memory stack (second memory stack) needs to maintain a low pass voltage (second pass voltage, and the second pass voltage is less than the first pass voltage) to reduce the pass voltage of the non-selection word line layer of the non-selection memory stack. To reduce voltage interference, the through voltage (a third through voltage, which is lower than the second through voltage) of the dummy memory layer group at the junction adjacent to the selected memory stack is further reduced. This creates a soft cutoff voltage between the memory layer group of the selected memory stack and the memory layer group of the non-selected memory stack adjacent to the selected memory stack, forming a potential barrier for residual electrons in the channel. This suppresses the migration of residual electrons in the channel to the channel position corresponding to the select word line layer of the selected memory stack, ensuring that the channel corresponding to the select word line layer of the selected memory stack maintains a high boost potential and suppresses programming voltage interference. In other words, in the embodiments of this application, during independent encoding, erasing, and reading operations on each memory stack, the through voltage interference of the non-selected memory stack is reduced, while the programming voltage interference of the selected memory stack is suppressed. Attached Figure Description

[0019] Figure 1 This is a schematic circuit diagram of an exemplary memory device including peripheral circuitry and a memory cell array according to some embodiments of this application;

[0020] Figure 2 This is a schematic circuit diagram of an exemplary memory cell array according to some embodiments of this application;

[0021] Figure 3AThis is a schematic cross-sectional view of an exemplary first type of storage cell array according to some embodiments of this application;

[0022] Figure 3B This is a cross-sectional schematic diagram of an exemplary second type of memory cell array according to some embodiments of this application;

[0023] Figure 4A This is a first exemplary programming scheme for a multi-memory stack memory device according to some embodiments of this application;

[0024] Figure 4B for Figure 4A A schematic diagram of the signal waveform of the first exemplary programming scheme;

[0025] Figure 4C for Figure 4A A schematic diagram of the channel potential of the first exemplary programming scheme;

[0026] Figure 5A This is a second exemplary programming scheme for a multi-memory stack memory device according to some embodiments of this application;

[0027] Figure 5B for Figure 5A A schematic diagram of the signal waveform of the first exemplary programming scheme;

[0028] Figure 5C for Figure 5A A schematic diagram of the channel potential of the first exemplary programming scheme;

[0029] Figure 6A This is a third exemplary programming scheme for a multi-memory stack memory device according to some embodiments of this application;

[0030] Figure 6B for Figure 6A A schematic diagram of the signal waveform of the first exemplary programming scheme;

[0031] Figure 6C for Figure 6A A schematic diagram of the channel potential of the first exemplary programming scheme;

[0032] Figure 7A This is a fourth exemplary programming scheme for a multi-memory stack memory device according to some embodiments of this application;

[0033] Figure 7B for Figure 7A A schematic diagram of the signal waveform of the first exemplary programming scheme;

[0034] Figure 7C for Figure 7A A schematic diagram of the channel potential of the first exemplary programming scheme;

[0035] Figure 8 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of this application;

[0036] Figure 9 This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of this application;

[0037] Figure 10 This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of this application. Detailed Implementation

[0038] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0039] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0040] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0041] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion. When discussing a second element, component, region, layer, or portion, it does not imply that the application necessarily contains a first element, component, region, layer, or portion.

[0042] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0044] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0045] Figure 1 This is a schematic circuit diagram of an exemplary memory device including peripheral circuitry and a memory cell array according to some embodiments of this application. Figure 2 This is a schematic circuit diagram of an exemplary memory cell array according to some implementations of this application. Figure 1 and Figure 2 Some exemplary peripheral circuits 102 and memory cell array 101 are shown below in conjunction with Figure 1 and Figure 2 To understand.

[0046] refer to Figure 1 and Figure 2 The peripheral circuitry 102 may include a page buffer / sensor amplifier 104, a column decoder / bit line driver 106, a row decoder / word line driver 108, a voltage generator 110, a control logic unit 112, a register 114, an interface 116, and a data bus 118. It should be understood that in some examples, it may also include... Figure 1 Additional peripheral circuitry not shown.

[0047] Page buffer / sensor amplifier 104 can be configured to read data from and program (write) data to memory cell array 101 according to control signals from control logic unit 112. In one example, page buffer / sensor amplifier 104 can store a page of programming data (write data) to be programmed into a page of memory cell array 101. In another example, page buffer / sensor amplifier 104 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 206 coupled to selected word line (WL) 218. In yet another example, page buffer / sensor amplifier 104 can also sense a low-power signal from bit line (BL) 216 representing a data bit stored in memory cell 206 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 106 can be configured to be controlled by control logic unit 112 and select one or more NAND memory strings 208 by applying a bit line voltage generated from voltage generator 110.

[0048] The row decoder / word line driver 108 can be configured to be controlled by the control logic unit 112 and to select / deselect memory blocks 204 of the memory cell array 101 and to select / deselect word lines 218 of the memory blocks 204. The row decoder / word line driver 108 can also be configured to drive word lines 218 using word line voltages generated from the voltage generator 110. In some embodiments, the row decoder / word line driver 108 can also select / deselect and drive BSG lines 215 and TSG lines 213. As described in detail below, the row decoder / word line driver 108 is configured to perform programming operations on memory cells 206 coupled to one or more selected word lines 218. The voltage generator 110 can be configured to be controlled by the control logic unit 112 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 101.

[0049] In some specific embodiments, the programming operation may include multiple steps. For example, the programming operation may include a bit line setting step, a programming execution step, and a programming recovery step. After the programming operation, a programming verification operation is also required; after the programming verification operation, a programming verification recovery operation is also required.

[0050] During the bitline setting step of the programming operation, the voltage of unselected word lines can be maintained at ground (GND). During the programming execution step of the programming operation, a pass voltage Vpass can be applied to the unselected word lines (hereinafter also called unselected word lines / non-selected word lines), and a programming voltage Vpgm can be applied to the selected word lines (hereinafter also called selected word lines / selected word lines). Therefore, the memory cells connected to the selected word lines can be programmed. During the programming recovery step of the programming operation, the voltage applied to all word lines can be reduced to ground (GND). During the programming verification operation, a verification voltage Vvrf can be applied to the selected word lines, and a pass voltage Vpass can be applied to the unselected word lines. During the programming verification recovery operation, a recovery operation can be performed to reduce the voltage to ground (GND) for both the unselected and selected word lines.

[0051] Control logic unit 112 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 114 can be coupled to control logic unit 112 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 116 can be coupled to control logic unit 112 and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic unit 112, and to buffer status information received from control logic unit 112 and relay them to the host. Interface 116 can also be coupled to column decoder / bitline driver 106 via data bus 118 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 101.

[0052] refer to Figure 2 The memory device may include a memory cell array 101 and peripheral circuitry 102 coupled to the memory cell array 101. Taking a three-dimensional NAND-type memory cell array as an example, the memory cells 206 are provided in the form of an array of NAND memory strings 208, each NAND memory string 208 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 208 includes a plurality of memory cells 206 coupled in series and stacked vertically. Each memory cell 206 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 206. Each memory cell 206 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0053] In some implementations, each memory cell 206 is a single-level cell (SLC) with two possible memory states and thus capable of storing one bit of data, i.e., one memory cell stores 1 bit of data, in which case each memory cell has two states, specifically 0 and 1. For example, the first memory state "0" may correspond to a first voltage range, and the second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 206 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, a multi-level cell (MLC) can store two bits of data per cell, three bits per cell (also known as a three-level cell (TLC), or four bits per cell (also known as a four-level cell (QLC)). In SLC mode, the memory cell stores 1 bit and has two logical states ("states"), namely states ER and P1. In MLC mode, the memory cell stores 2 bits and has four states, namely states ER, P1, P2, and P3. In TLC mode, the memory cell stores 3 bits and has eight states, namely states ER and states P1-P7. In QLC mode, the storage unit stores 4 bits and has 16 states.

[0054] like Figure 2 As shown, each NAND memory string 208 may include a lower select gate (BSG) 210 at its source end and an upper select gate (TSG) 212 at its drain end. The BSG 210 and TSG 212 can be configured to activate the selected NAND memory string 208 during read and program operations. In some embodiments, the sources of the NAND memory strings 208 in the same memory block 204 are coupled via a common source line (SL) 214 (e.g., a common source line). In other words, according to some embodiments, all NAND memory strings 208 in the same memory block 204 have an array common source (ACS). According to some embodiments, the TSG 212 of each NAND memory string 208 is coupled to a corresponding bit line 216, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 208 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 212) or a deselection voltage (e.g., 0V) to the corresponding TSG 212 via one or more TSG lines 213 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 210) or a deselection voltage (e.g., 0V) to the corresponding BSG 210 via one or more BSG lines 215.

[0055] like Figure 2As shown, NAND memory strings 208 can be organized into multiple memory blocks 204, each of which can have a common source line 214 (e.g., coupled to ground). In some implementations, each memory block 204 is a basic data unit for an erase operation, i.e., all memory cells 206 on the same memory block 204 are erased simultaneously. To erase memory cells 206 in a selected memory block 204, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 214 of the selected memory block 204 and the unselected memory blocks on the same plane as the selected memory block 204. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 206 of adjacent NAND memory strings 208 can be coupled via word lines 218, which can be coupled with read and programmable voltages V. WL (For example, read voltage (e.g., 0.3V) and programming voltage (e.g., 3V)) biases are coupled to the selected word line, selecting which row of memory cell 206 is affected by read and programming operations.

[0056] refer to Figure 1 and Figure 2 In some embodiments, peripheral circuitry 102 may be coupled to memory array 201 via bit line 216, word line 218, source line 214, BSG line 215, and TSG line 213. Peripheral circuitry 102 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory array 201 by applying voltage and / or current signals to each target memory cell 206 and sensing voltage and / or current signals from each target memory cell 206 via bit line 216, word line 218, source line 214, BSG line 215, and TSG line 213.

[0057] In some embodiments, the peripheral circuit 102 can apply a word line bias voltage V through the line decoder / word line driver 108. WL The waveform of the programming scheme is provided to each target memory cell 206 in the form of a waveform. In some specific embodiments, the word line bias voltage V applied to the word line 218 is... WL This may include programming voltage Vpgm, pass voltage Vpass, cutoff voltage Vcut, etc. In some specific embodiments, the column decoder / bit line driver 106 can select or deselect the NAND memory string 208 (and its memory cells 206) by applying a selection voltage or deselect voltage to the corresponding drain selection transistor 212 via the corresponding bit line 216 for various memory operations, such as programming the selected memory cell 206.

[0058] Figure 3A This is a cross-sectional schematic diagram of an exemplary first type of storage cell array according to some embodiments of this application. Figure 3B This is a cross-sectional schematic diagram of an exemplary second type of memory cell array according to some embodiments of this application.

[0059] refer to Figure 3A and Figure 3B The memory cell array includes NAND memory strings 310 extending vertically above the substrate 314 (e.g., Figure 2 The NAND memory string 208 in the memory. The substrate 314 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0060] In this document and hereinafter, for ease of description, the first and second directions in the embodiments of this application are represented as two orthogonal directions parallel to the top surface of the substrate; the third direction is a direction perpendicular to the top surface of the substrate or a third direction parallel to the substrate thickness direction. For example, the first direction can be represented as the X direction in the figures; the second direction can be represented as the Y direction in the figures; and the third direction can be represented as the Z direction in the figures. It should be noted that in... Figure 3A and Figure 3B The X, Y, and Z directions are included to further illustrate the spatial relationships between components in a memory cell array. The substrate includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally along the X direction (i.e., the lateral direction). As used herein, when the substrate is located in the lowest plane of the semiconductor structure (e.g., the vertical or depth direction), whether a component of the semiconductor structure is "above," "on top of," or "below" another component is determined in the Z direction relative to the substrate of the semiconductor structure. The same concepts will be applied throughout this application to describe spatial relationships.

[0061] like Figure 3A and Figure 3B As shown, the NAND memory string 310 extends vertically above the substrate 314 through the memory stack layer 304, which has alternating gate layer 309 (also referred to herein as "word line layer 309") and insulating layer 308.

[0062] The number of pairs of gate layers 309 and insulating layers 308 in the memory stack 304 (e.g., 32, 64, 96, or 128) determines the number of memory cells in the memory cell array. Each gate layer 309 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 309 includes a metal layer, such as a tungsten layer. In embodiments, each gate layer 309 includes a doped polysilicon layer. Each gate layer 309 may include memory cells surrounding the NAND memory string 310 (e.g., Figure 2 The storage unit 206 in the middle) and can be used as a word line (e.g., Figure 2 The control grid extends laterally (218) of the character line.

[0063] refer to Figure 3A and Figure 3B The NAND memory string 310 includes a channel structure 312 extending vertically through the memory stack layer 304. The NAND memory can be transmitted via BSG lines (e.g., Figure 2 BSG line 215) and TSG line (e.g., Figure 2 (TSG line 213) Select / deselect NAND memory string 310 (e.g., Figure 2 In the NAND memory string 310 (208), the TSG line is coupled to the gate of the drain select transistor of the NAND memory string 310, and the BSG line is coupled to the gate of the source select transistor of the NAND memory string 310. In some embodiments, the drain select transistor of each NAND memory string 310 is coupled to a corresponding bit line BL, and data can be read or written from the bit line BL via an output bus (not shown). In some embodiments, the source select transistors of the NAND memory strings 310 in the same memory block are coupled to the same source line (e.g., ...). Figure 2 The source line 214 in the middle is coupled.

[0064] In some embodiments, the channel structure 312 may include a semiconductor material (e.g., as a semiconductor channel, Figure 3A and Figure 3B (not shown) and dielectric materials (e.g., as storage films, Figure 3A and Figure 3B(Not shown) A channel hole filled with silicon. In some embodiments, the semiconductor channel material includes silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some embodiments, the storage film is a composite dielectric layer including a tunnel layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure 312 may have a cylindrical shape (e.g., a columnar shape). According to some embodiments, the semiconductor channel, tunnel layer, storage layer, and barrier layer are arranged radially from the center of the column to the outer surface of the column in this order. The material of the tunnel layer may include silicon oxide, silicon oxynitride, or any combination thereof. The material of the storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The material of the barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the storage film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0065] In some embodiments, the NAND memory string 310 further includes a semiconductor plug located in the lower portion of the NAND memory string 310 (e.g., at its lower end). Figure 3A and Figure 3B (Not shown). The semiconductor plug may comprise a semiconductor material, such as single-crystal silicon, epitaxially grown from the substrate in any suitable orientation. The semiconductor plug is coupled to the source selection transistor of the NAND memory string 310 (e.g., Figure 2 The source selection transistor 210 is a portion of the channel of the NAND memory string 310. In some embodiments, the NAND memory string 310 also includes a channel plug located in the upper portion of the NAND memory string 310 (e.g., at its upper end). In some embodiments, the channel plug is coupled to the drain selection transistor of the NAND memory string 310 (e.g., the source selection transistor 210). Figure 2 The channel of the drain selection transistor 212. As used herein, when the substrate is placed in the lowest plane of the memory cell array, the “upper end” of the component (e.g., channel structure 312) is the end farther from the substrate in the Z direction, and the “lower end” of the component (e.g., channel structure 312) is the end closer to the substrate in the Z direction.

[0066] In some embodiments, the NAND memory string 310 includes a plurality of control gates for memory cells of the NAND memory string 310 (each being a portion of gate layer 309). Gate layer 309 may include a plurality of control gates for the plurality of NAND memory strings 310 and may serve as laterally extending word lines terminating at the edge of memory stack layer 304, the word lines receiving word line bias voltages for controlling the operation of memory cells via, for example, read, erase, and program operations. It should be understood that, although Figure 3A and Figure 3BAdditional components, not shown, that can form a memory cell array, include, but are not limited to, gate gap / source contacts, local contacts, interconnect layers, etc.

[0067] exist Figure 3A and Figure 3B In this embodiment, the NAND memory string 310 includes a single-channel structure, also known as a single-cell formation structure. It should be understood that in other embodiments, the NAND memory string 310 may include inter-stack plugs (…). Figure 3A and Figure 3B (Not shown) Two-channel structures electrically connected, also known as dual-unit forming structures.

[0068] refer to Figure 3A and Figure 3B In some embodiments, the write-erase-read operation can be performed at the half-block level, the third-block level, or any other suitable fraction of the storage block. In some embodiments, the storage stack layer 304 may have a multi-stack architecture, and the storage stack layer 304 may include multiple storage decks. For example, as... Figure 3A As shown, the memory stack layer 304 may have dual memory stacks, including a lower memory stack 304L located above the substrate 314 and an upper memory stack 304U located above the lower memory stack 304L. For example, as... Figure 3B As shown, the storage stack layer 304 may also have three storage stacks, including a lower storage stack 304L located above the substrate 314, a middle storage stack 304M located above the lower storage stack 304L, and an upper storage stack 304U located above the middle storage stack 304M.

[0069] In some specific embodiments, each storage stack includes multiple storage cell layers and word line layers 309 corresponding to each storage cell layer, and at least one dummy storage cell layer and a dummy word line layer 307 corresponding to each dummy storage cell layer are provided at the junction of adjacent storage stacks.

[0070] In some embodiments, the number of gate layers in each memory stack can be the same or different. (See reference) Figure 3B In some specific embodiments, the number of gate layers 309 in each of the lower storage stack 304L, middle storage stack 304M, and upper storage stack 304U may be the same or different. (See reference...) Figure 3B In some specific embodiments, the number of dummy word line layers 307 in each of the lower storage stack 304L, the middle storage stack 304M, and the upper storage stack 304U may be the same or different.

[0071] In some embodiments, a dummy storage layer group is provided at the intersection of adjacent storage stacks in the vertical direction. For example, as shown... Figure 3A The dummy storage layer group 305 shown is located at the junction of the lower storage stack 304L and the upper storage stack 304U in the vertical direction. For example, as... Figure 3B The lower dummy storage layer group 305L is shown at the junction of the lower storage stack 304L and the upper storage stack 304U in the vertical direction, and the upper dummy storage layer group 305U is shown at the junction of the middle storage stack 304M and the upper storage stack 304U.

[0072] refer to Figure 3A and Figure 3B The storage stack layer 304 includes multiple storage stacks, each storage stack including multiple storage cell layers and word line layers corresponding to each storage cell layer (hereinafter referred to as "storage layer group"). At the junction of two adjacent storage stacks, at least one dummy storage cell layer and a dummy word line layer corresponding to each dummy storage cell layer are provided (hereinafter referred to as "dummy storage layer group"). That is, the storage stack layer 304 includes multiple storage layer groups and dummy storage layer groups between two adjacent storage layer groups. A storage layer group may include multiple storage layers, each storage layer may include one storage cell layer and a word line layer 309 corresponding to one storage cell layer; a dummy storage layer group may include at least one dummy storage layer, each dummy storage layer may include one dummy storage cell layer and a dummy word line layer 307 corresponding to one dummy storage cell layer. For example, as... Figure 3A As shown, the storage stack layer 304 includes an upper storage layer group 306U, a dummy storage layer group 305, and a lower storage layer group 306L. For example, as... Figure 3B As shown, the storage stack layer 304 includes an upper storage layer group 306U, an upper dummy storage layer group 305U, a middle storage layer group 306M, a lower dummy storage layer group 305L, and a lower storage layer group 306L.

[0073] In some embodiments, the dummy storage layer may have the same physical structure as the storage layer, but with a different electrical configuration, and the storage cells coupled through the dummy storage layer are not used for data storage (i.e., as dummy storage cells).

[0074] Due to the demand for high-capacity, low-cost storage media, the number of stacked layers in three-dimensional storage devices (such as 3D NAND flash memory) is constantly increasing to improve the storage density of storage blocks. 3D NAND flash memory uses storage blocks as the smallest unit for erase operations; larger storage block capacities undoubtedly increase the system burden of data management and affect product performance. Therefore, it is necessary to consider dividing storage blocks into multiple storage stacks, with each storage stack performing separate encoder, erase, and read operations.

[0075] When dividing a 3D NAND flash memory block into multiple memory stacks and performing individual write-erase-read operations on each stack, such as when programming a selected memory stack, reducing the pass voltage Vpass of the non-selected word line of the non-selected memory stack can reduce its pass voltage interference. When programming a selected memory stack, reducing the pass voltage of the non-selected memory stack creates a potential difference in the channel, driving residual electrons in the channel to migrate to the channel location corresponding to the selected word line where the programming voltage Vpgm is applied. This reduces the boosting potential of the channel corresponding to the selected word line, resulting in new programming voltage interference.

[0076] Figure 4A This is a first exemplary programming scheme for a multi-memory stack memory device according to some embodiments of this application; Figure 4B for Figure 4A A schematic diagram of the signal waveform of the first exemplary programming scheme; Figure 4C for Figure 4A A schematic diagram of the channel potential of the first exemplary programming scheme.

[0077] refer to Figure 4A , Figure 4B , Figure 4C and in conjunction with references Figure 1 , Figure 2 , Figure 3A , Figure 3B In some embodiments, the memory device includes: a memory cell array, including a first memory stack and a second memory stack stacked and adjacent to each other; both the first memory stack and the second memory stack include a plurality of memory cell layers and a word line layer corresponding to each memory cell layer, and at least one dummy memory cell layer and a dummy word line layer corresponding to each dummy memory cell layer are disposed at the junction of the first memory stack and the second memory stack; peripheral circuitry, coupled to the memory cell array, and configured to: when programming a selected memory cell layer in the first memory stack, apply a programming voltage to the word line layer corresponding to the selected memory cell layer, and apply a first pass voltage to the word line layer corresponding to an unselected memory cell layer in the first memory stack; apply voltages Vpass2 to Vpass1 between the first pass voltage and the second pass voltage to the word line layers corresponding to the plurality of memory cell layers in the second memory stack; and apply a second pass voltage to the dummy word line layer corresponding to at least one dummy memory cell layer at the junction of the first memory stack and the second memory stack; wherein the second pass voltage is less than the first pass voltage.

[0078] It should be noted that for details not mentioned in the embodiments of this application, other specific details regarding the structure or components of the memory device, and the operation method of the memory device, please refer to the references. Figure 5A , Figure 5B , Figure 5C and in conjunction with references Figure 1 , Figure 2 , Figure 3A , Figure 3B The relevant embodiments shown are for understanding purposes and will not be described in detail here.

[0079] It should be noted that, here and below, "first storage stack" refers to the selected storage stack (also called the chosen storage stack / selected storage stack), such as the storage stack being programmed; "second storage stack" refers to the non-selected storage stack (also called the unselected storage stack / unselected storage stack) adjacent to the first storage stack in the vertical direction, such as the non-selected storage stack that has already been programmed and is adjacent to the first storage stack. Reference Figure 4A In this embodiment of the application, the first storage stack 410 is the upper storage stack 304U, which includes an upper storage layer group 306U; the second storage stack 420 is the middle storage stack 304M, which includes a middle storage layer group 306M; and the upper storage layer group 306U and the middle storage layer group 306M are separated by an upper virtual storage layer group 305U.

[0080] refer to Figure 4B When programming the upper storage stack 304U separately, a programming voltage Vpgm is applied to the upper storage layer group selected word line layer 306U_Sel WL of the upper storage layer group of the upper storage stack 304U, a first pass voltage Vpass1 is applied to the upper storage layer group unselected word line layer 306U_unsel WL of the upper storage layer group of the upper storage stack 304U, a second pass voltage Vpass2 is applied to the middle storage layer group unselected word line layer 306M_unsel WL of the middle storage stack 304M, and a voltage Vpass2 to Vpass1 between the first pass voltage and the second pass voltage is applied to the upper dummy storage layer group dummy word line layer 305U_IDPDMY, wherein the second pass voltage Vpass2 is less than the first pass voltage Vpass1.

[0081] refer to Figure 4C When programming the upper memory stack 304U separately, the through voltage (second through voltage Vpass2) of the middle memory layer group of the middle memory stack 304M is reduced to decrease through voltage interference. When programming the upper memory stack 304U separately, the through voltage of the middle memory layer group of the middle memory stack 304M is reduced. The second through voltage Vpass2 is less than the first through voltage Vpass1, which creates a potential difference in the channel, driving the residual electrons RE in the channel to migrate to the channel position corresponding to the selected word line layer 306U_SelWL of the upper memory layer group of the upper memory stack 304U. Figure 4C(In the direction indicated by the arrow), the boost potential of the channel corresponding to the upper memory layer group select word line layer 306U_Sel WL of the upper memory stack 304U is reduced, causing programming voltage interference.

[0082] In this embodiment, the non-selection word line layer of the selected memory stack (first memory stack) being programmed needs to maintain a high pass voltage (first pass voltage Vpass1) to increase the boost potential of the selection word line layer of the selected memory stack, thereby suppressing programming voltage interference. The non-selection word line layer of the non-selection memory stack adjacent to the selected memory stack (second memory stack) needs to maintain a low pass voltage (second pass voltage Vpass2) to reduce the pass voltage interference of the non-selection word line layer of the non-selection memory stack. When the selected memory stack is programmed individually, reducing the pass voltage of the memory layer group of the selected memory stack (second pass voltage Vpass2, and second pass voltage Vpass2 is less than first pass voltage Vpass1) will create a potential difference in the channel, driving residual electrons in the channel to migrate to the channel position corresponding to the selection word line layer of the memory layer group of the selected memory stack, reducing the boost potential of the channel corresponding to the selection word line layer of the memory layer group of the selected memory stack, and causing new programming voltage interference.

[0083] Figure 5A This is a second exemplary programming scheme for a multi-memory stack memory device according to some embodiments of this application; Figure 5B for Figure 5A A schematic diagram of the signal waveform of the first exemplary programming scheme; Figure 5C for Figure 5A A schematic diagram of the channel potential of the first exemplary programming scheme.

[0084] refer to Figure 5A , Figure 5B , Figure 5C and in conjunction with references Figure 1 , Figure 2 , Figure 3A , Figure 3BThis application provides a memory device 100, including: a memory cell array 101, including a first memory stack and a second memory stack stacked and adjacent to each other; both the first memory stack and the second memory stack include multiple memory cell layers and word line layers 309 corresponding to each memory cell layer; at least one dummy memory cell layer and a dummy word line layer 307 corresponding to each dummy memory cell layer are provided at the junction of the first memory stack and the second memory stack; and peripheral circuitry 102, coupled to the memory cell array 101, and configured to: when performing a programming operation on a selected memory cell layer in the first memory stack, send a message to the selected memory cell layer... A programming voltage Vpgm is applied to the word line layer corresponding to the memory cell layer, and a first pass voltage Vpass1 is applied to the word line layer corresponding to the unselected memory cell layer in the first memory stack; a second pass voltage Vpass2 is applied to the word line layers corresponding to multiple memory cell layers in the second memory stack; and a third pass voltage Vcut is applied to the dummy word line layer corresponding to at least one dummy memory cell layer at the junction of the first and second memory stacks; wherein the third pass voltage Vcut is less than the second pass voltage Vpass2, and the second pass voltage Vpass2 is less than the first pass voltage Vpass1.

[0085] As mentioned earlier, see reference. Figure 1 and Figure 2 The memory device 100 may include a memory cell array 101 and peripheral circuitry 102 coupled to the memory cell array 101.

[0086] In some embodiments, the page buffer / sensor amplifier 104 of the peripheral circuitry 102 can be configured to read data from the memory cell array 101 and program (write) data to the memory cell array 101 according to control signals from the control logic unit 112. The row decoder / word line driver 108 of the peripheral circuitry 102 can be configured to be controlled by the control logic unit 112 and to select / deselect memory blocks 204 of the memory cell array 101 and select / deselect word lines 218 of memory blocks 204. The row decoder / word line driver 108 of the peripheral circuitry 102 can also be configured to drive word lines 218 using word line voltages generated from the voltage generator 110, providing signal waveforms for the programming scheme. In some embodiments, the row decoder / word line driver 108 can also select / deselect and drive BSG lines 215 and TSG lines 213.

[0087] In some specific embodiments, the storage cell array 101 is described as a three-dimensional NAND type storage cell array, wherein the storage cells are provided in the form of an array of NAND memory strings 208, each NAND memory string 208 including a plurality of storage cells 206 that are coupled in series and stacked vertically.

[0088] As mentioned earlier, see reference. Figure 3A , Figure 3B In some specific embodiments, each NAND memory string 310 (see corresponding reference) Figure 2 The NAND memory strings 310 extend vertically above the substrate 314, and each NAND memory string 310 includes a plurality of vertically stacked word line layers 309. In some embodiments, each NAND memory string 310 may include a lower select gate at its source end and an upper select gate at its drain end, with a BSG line coupled to the lower select gate and a TSG line coupled to the upper select gate. The BSG and TSG lines may be configured to activate a selected NAND memory string 310 during read and program operations.

[0089] refer to Figure 5A , Figure 5B , Figure 5C In some specific embodiments, the word line bias voltage applied to the word line layer 309 may include a programming voltage Vpgm, a pass voltage Vpass, and a third pass voltage Vcut. In some specific embodiments, during the programming execution step of performing a programming operation, the pass voltage Vpass may be applied to an unselected word line layer, and the programming voltage Vpgm may be applied to a selected word line layer, and the third pass voltage Vcut may be applied to a dummy word line layer.

[0090] In various embodiments of this application, the third through voltage Vcut can also be referred to as soft cut voltage Vcut or cutoff voltage Vcut.

[0091] In some embodiments, the third through voltage Vcut is less than the second through voltage Vpass2 and less than the first through voltage Vpass1, and the third through voltage Vcut is greater than or equal to a first threshold, which must satisfy the condition of not inducing significant hot electron injection. The third through voltage Vcut can reduce the migration of residual electrons in the channel to a certain extent. If the third through voltage Vcut is too low, a large potential difference will exist in the channel, inducing hot electron injection, which will lead to new interference. Therefore, the minimum value of the third through voltage Vcut must satisfy the condition of not inducing significant hot electron injection.

[0092] In some embodiments, the storage cell array may include multiple storage stacks. Exemplarily, in conjunction with reference to... Figure 5A and Figure 3B The memory cell array includes three memory stacks: a lower memory stack 304L located above the substrate 314, a middle memory stack 304M located above the lower memory stack 304L, and an upper memory stack 304U located above the middle memory stack 304M.

[0093] refer to Figure 5A In this embodiment of the application, the first storage stack 410 is the upper storage stack 304U, which includes an upper storage layer group 306U; the second storage stack 420 is the middle storage stack 304M, which includes a middle storage layer group 306M; and an upper dummy storage layer group 305U is located between the upper storage layer group 306U and the middle storage layer group 306M. Figure 3B As shown, the upper dummy storage layer group 305U is located at the junction of the upper storage stack 304U and the middle storage stack 304M. The upper storage stack 304U includes an upper storage layer group 306U adjacent to the upper dummy storage layer group 305U, and the middle storage stack 304M includes a middle storage layer group 306M adjacent to the upper dummy storage layer group 305U. The upper dummy storage layer group 305U is located between the upper storage layer group 306U and the middle storage layer group 306M.

[0094] refer to Figure 5B The peripheral circuit 102 is configured to, when programming the upper memory stack 304U separately, apply a programming voltage Vpgm to the upper memory layer group select word line layer 306U_Sel WL of the upper memory layer group of the upper memory stack 304U, apply a first pass voltage Vpass1 to the upper memory layer group unselect word line layer 306U_unsel WL of the upper memory layer group of the upper memory stack 304U, apply a second pass voltage Vpass2 to the middle memory layer group unselect word line layer 306M_unsel WL of the middle memory stack 304M, and apply a third pass voltage Vcut to the upper dummy memory layer group dummy word line layer 305U_IDPDMY, wherein the third pass voltage Vcut is less than the second pass voltage Vpass2, and the second pass voltage Vpass2 is less than the first pass voltage Vpass1.

[0095] refer to Figure 5C The peripheral circuit 102 is configured to reduce the through voltage interference by lowering the through voltage (second through voltage Vpass2) of the middle storage layer group of the middle storage stack 304M when the upper storage stack 304U is programmed separately. The second through voltage Vpass2 is less than the first through voltage Vpass1. At the same time, the through voltage of the dummy word line layer 305U_IDPDMY of the upper dummy storage layer group is reduced even further. The third through voltage Vcut is less than the second through voltage Vpass2. This can form a soft cutoff voltage between the upper storage layer group 306U and the middle storage layer group 306M, forming a barrier to the residual electron RE and suppressing the migration of the channel residual electron RE to the channel position corresponding to the upper storage layer group selected word line layer 306U_SelWL of the upper storage stack 304U. Figure 5C(As indicated by the cross-shaped mark), this ensures that the channel corresponding to the upper memory layer group selection word line layer 306U_Sel WL of the upper memory stack 304U maintains a high boost potential, suppressing programming voltage interference.

[0096] Figure 6A This is a third exemplary programming scheme for a multi-memory stack memory device according to some embodiments of this application; Figure 6B for Figure 6A A schematic diagram of the signal waveform of the first exemplary programming scheme; Figure 6C for Figure 6A A schematic diagram of the channel potential of the first exemplary programming scheme.

[0097] refer to Figure 6A In this embodiment, the first storage stack 410 is a middle storage stack 304M, which includes a middle storage layer group 306M; the second storage stack 420 is a lower storage stack 304L, which includes a lower storage layer group 306L, and a lower dummy storage layer group 305L is located between the middle storage layer group 306M and the lower storage layer group 306L. As previously mentioned, ... Figure 3B As shown, the lower dummy storage layer group 305L is located at the junction of the middle storage stack 304M and the lower storage stack 304L. The middle storage stack 304M includes a middle storage layer group 306M adjacent to the upper dummy storage layer group 305U, and the lower storage stack 304L includes an upper storage layer group 306L adjacent to the lower dummy storage layer group 305L. The lower dummy storage layer group 305L is located between the middle storage layer group 306M and the lower storage layer group 306L.

[0098] refer to Figure 6B The peripheral circuit 102 is configured to, when programming the middle memory stack 304M separately, apply a programming voltage Vpgm to the middle memory layer group select word line layer 306M_Sel WL of the middle memory stack 304M, apply a first pass voltage Vpass1 to the middle memory layer group unselect word line layer 306M_unsel WL of the middle memory stack 304M, apply a second pass voltage Vpass2 to the lower memory layer group unselect word line layer 306L_unsel WL of the lower memory stack 304L, and apply a third pass voltage Vcut to the lower dummy memory layer group dummy word line layer 305L_IDPDMY, wherein the third pass voltage Vcut is less than the second pass voltage Vpass2, and the second pass voltage Vpass2 is less than the first pass voltage Vpass1.

[0099] refer to Figure 6CThe peripheral circuit 102 is configured to reduce the through voltage interference by lowering the through voltage (second through voltage Vpass2) of the lower memory layer group of the lower memory stack 304L when the middle memory stack 304M is programmed separately. The second through voltage Vpass2 is less than the first through voltage Vpass1. At the same time, the through voltage of the dummy word line layer 305L_IDPDMY of the lower dummy memory layer group is reduced even further. The third through voltage Vcut is less than the second through voltage Vpass2. This can form a soft cutoff voltage between the middle memory layer group 306M and the lower memory layer group 306L, forming a barrier to residual electrons RE and suppressing the migration of channel residual electrons RE to the channel position corresponding to the middle memory layer group select word line layer 306M_SelWL of the middle memory stack 304M. Figure 6C (As indicated by the cross-shaped mark), this ensures that the channel corresponding to the middle memory layer group selection word line layer 306M_Sel WL in the middle memory stack 304M maintains a high boost potential, suppressing programming voltage interference.

[0100] Figure 7A This is a fourth exemplary programming scheme for a multi-memory stack memory device according to some embodiments of this application; Figure 7B for Figure 7A A schematic diagram of the signal waveform of the first exemplary programming scheme; Figure 7C for Figure 7A A schematic diagram of the channel potential of the first exemplary programming scheme.

[0101] refer to Figure 7A In this embodiment of the application, the first storage stack 410 is the lower storage stack 304L, which includes a lower storage layer group 306L; the second storage stack 420 is the middle storage stack 304M, which includes a middle storage layer group 306M; and the lower storage layer group 306L and the middle storage layer group 306M are separated by a lower dummy storage layer group 305L.

[0102] refer to Figure 7B The peripheral circuit 102 is configured to, when programming the lower memory stack 304L separately, apply a programming voltage Vpgm to the lower memory layer group selected word line layer 306L_Sel WL of the lower memory stack 304L, apply a first pass voltage Vpass1 to the lower memory layer group unselected word line layer 306L_unsel WL of the lower memory stack 304L, apply a second pass voltage Vpass2 to the middle memory layer group unselected word line layer 306M_unsel WL of the middle memory stack 304M, and apply a third pass voltage Vcut to the lower dummy memory layer group dummy word line layer 305L_IDPDMY, wherein the third pass voltage Vcut is less than the second pass voltage Vpass2, and the second pass voltage Vpass2 is less than the first pass voltage Vpass1.

[0103] refer to Figure 7C The peripheral circuit 102 is configured to reduce the through voltage interference by lowering the through voltage (second through voltage Vpass2) of the middle storage layer group of the middle storage stack 304M when the lower storage stack 304L is programmed separately. The second through voltage Vpass2 is less than the first through voltage Vpass1. At the same time, the through voltage of the dummy word line layer 305L_IDPDMY of the lower dummy storage layer group is reduced even further. The third through voltage Vcut is less than the second through voltage Vpass2. This can form a soft cutoff voltage between the lower storage layer group 306L and the middle storage layer group 306M, forming a barrier to the residual electron RE and suppressing the migration of the channel residual electron RE to the channel position corresponding to the lower storage layer group selected word line layer 306L_SelWL of the lower storage stack 304L. Figure 7C (As indicated by the cross-shaped mark), this ensures that the channel corresponding to the lower memory layer group selection word line layer 306L_Sel WL in the lower memory stack 304L maintains a high boost potential, suppressing programming voltage interference.

[0104] refer to Figure 6A , Figure 6B , Figure 6C and in conjunction with references Figure 1 , Figure 2 , Figure 3A , Figure 3B In some embodiments, the memory cell array further includes a third memory stack 430 stacked with both the first memory stack 410 and the second memory stack 420; the third memory stack 430 is disposed adjacent to the first memory stack 410, and at least one dummy memory cell layer and a dummy word line layer corresponding to each dummy memory cell layer are disposed at the junction of the third memory stack 430 and the first memory stack 410; the peripheral circuit is configured to apply a third pass voltage Vcut to the dummy word line layer corresponding to at least one dummy memory cell layer at the junction between the first memory stack 410 and the third memory stack 430.

[0105] refer to Figure 6A In this embodiment of the application, the first storage stack 410 is a middle storage stack 304M, which includes a middle storage layer group 306M; the second storage stack 420 is a lower storage stack 304L, which includes a lower storage layer group 306L; the third storage stack 430 is an upper storage stack 304U, which includes an upper storage layer group 306U; there is an upper dummy storage layer group 305U between the upper storage layer group 306U and the middle storage layer group 306M; and there is a lower dummy storage layer group 305L between the middle storage layer group 306M and the lower storage layer group 306L.

[0106] refer to Figure 6B The peripheral circuit 102 is configured to, when programming the middle memory stack 304M individually, apply a programming voltage Vpgm to the middle memory layer group select word line layer 306M_Sel WL of the middle memory layer group of the middle memory stack 304M, apply a first pass voltage Vpass1 to the middle memory layer group unselect word line layer 306M_unsel WL of the middle memory layer group of the middle memory stack 304M, apply a second pass voltage Vpass2 to the lower memory layer group unselect word line layer 306L_unsel WL of the lower memory stack 304L, and apply a third pass voltage Vcut to the lower dummy memory layer group dummy word line layer 305L_IDPDMY, and apply a third pass voltage Vcut to the upper memory layer group unselect word line layer 306U_unsel WL of the upper memory stack 304U. WL applies a second pass voltage Vpass2 and applies a third pass voltage Vcut to the dummy word line layer 305U_IDPDMY of the upper dummy memory layer group, wherein the third pass voltage Vcut is less than the second pass voltage Vpass2, and the second pass voltage Vpass2 is less than the first pass voltage Vpass1.

[0107] In other embodiments, the first storage stack is a middle storage stack 304M, which includes a middle storage layer group 306M; the second storage stack is an upper storage stack 304U, which includes an upper storage layer group 306U; the third storage stack 420 is a lower storage stack 304L, which includes a lower storage layer group 306L; an upper dummy storage layer group 305U is located between the upper storage layer group 306U and the middle storage layer group 306M, and a lower dummy storage layer group 305L is located between the middle storage layer group 306M and the lower storage layer group 306L. In this case, the signal waveform of the exemplary programming scheme can be referred to... Figure 6B For understanding, and to illustrate the channel potential of the exemplary programming scheme, please refer to Figure 6C The details are not elaborated here.

[0108] refer to Figure 7A , Figure 7B , Figure 7C and in conjunction with references Figure 1 , Figure 2 , Figure 3A , Figure 3BIn some embodiments, the memory cell array further includes a third memory stack 430 stacked with both the first memory stack 410 and the second memory stack 420; the third memory stack 430 is disposed adjacent to the second memory stack 420, and at least one dummy memory cell layer and a dummy word line layer corresponding to each dummy memory cell layer are disposed at the junction of the third memory stack 430 and the second memory stack 420; the peripheral circuit is configured to apply a second pass voltage Vpass2 to the dummy word line layer corresponding to at least one dummy memory cell layer at the junction between the second memory stack 420 and the third memory stack 430.

[0109] refer to Figure 7A In this embodiment of the application, the first storage stack 410 is the lower storage stack 304L, which includes the lower storage layer group 306L; the second storage stack 420 is the middle storage stack 304M, which includes the middle storage layer group 306M; the third storage stack 430 is the upper storage stack 304U, which includes the upper storage layer group 306U; there is an upper dummy storage layer group 305U between the upper storage layer group 306U and the middle storage layer group 306M; and there is a lower dummy storage layer group 305L between the middle storage layer group 306M and the lower storage layer group 306L.

[0110] refer to Figure 7B The peripheral circuit 102 is configured to, when programming the lower memory stack 304L separately, apply a programming voltage Vpgm to the lower memory layer group select word line layer 306L_Sel WL of the lower memory stack 304L, apply a first pass voltage Vpass1 to the lower memory layer group unselect word line layer 306L_unsel WL of the lower memory stack 304L, apply a second pass voltage Vpass2 to the middle memory layer group unselect word line layer 306M_unsel WL of the middle memory stack 304M, and apply a third pass voltage Vcut to the lower dummy memory layer group dummy word line layer 305L_IDPDMY, and apply a third pass voltage Vcut to the upper memory layer group unselect word line layer 306U_unsel WL of the upper memory stack 304U. WL applies a second pass voltage Vpass2, and applies a second pass voltage Vpass2 to the dummy word line layer 305U_IDPDMY of the upper dummy memory layer group, wherein the third pass voltage Vcut is less than the second pass voltage Vpass2, and the second pass voltage Vpass2 is less than the first pass voltage Vpass1.

[0111] In other embodiments, the first storage stack is a lower storage stack 304L, which includes a lower storage layer group 306L; the second storage stack is an upper storage stack 304U, which includes an upper storage layer group 306U; the third storage stack is a middle storage stack 304M, which includes a middle storage layer group 306M; an upper dummy storage layer group 305U is located between the upper storage layer group 306U and the middle storage layer group 306M; and a lower dummy storage layer group 305L is located between the middle storage layer group 306M and the lower storage layer group 306L. In this case, the signal waveform of the exemplary programming scheme can be referred to... Figure 7B For understanding, and to illustrate the channel potential of the exemplary programming scheme, please refer to Figure 7C The details are not elaborated here.

[0112] In some embodiments, the first through voltage and the second through voltage have a first difference; the second through voltage and the third through voltage have a second difference; the first difference and the second difference are different.

[0113] In some embodiments, when the second difference is greater than the first difference, a larger potential barrier can be formed for the channel residual electrons corresponding to the non-selected word line layer of the memory layer group of the non-selected memory stack.

[0114] like Figure 5A , Figure 6A and Figure 7A As shown, in some embodiments, multiple memory cell layers in the second memory stack 420 are all in a programmed state 402. For example... Figure 6A As shown, in some embodiments, multiple storage cell layers in the second storage stack 420 are all in a programmed state 402, and multiple storage cell layers in the third storage stack 430 are all in a programmed state 402.

[0115] In this embodiment, the residual electrons that are downcoupled in the channel corresponding to the non-selection word line layer of the non-selection memory stack (the memory stack that has been programmed) will migrate to the channel corresponding to the selection word line layer of the memory layer group of the selection memory stack (the memory stack that is being programmed), so that the channel corresponding to the selection word line layer of the memory layer group of the selection memory stack still maintains a high boost potential and suppresses programming voltage interference.

[0116] like Figure 5A , Figure 6A and Figure 7AAs shown, in some embodiments, the unselected memory cell layer in the first memory stack 410 includes a memory cell layer in a programming state 402 and a memory cell layer in an erasure state 401; the first pass voltage includes a first sub-pass voltage and a second sub-pass voltage; the peripheral circuit is configured to apply the first sub-pass voltage to the word line layer corresponding to the memory cell layer in the programming state and apply the second sub-pass voltage to the word line layer corresponding to the memory cell layer in the erasure state; the first sub-pass voltage and the second sub-pass voltage are different.

[0117] In some embodiments, the first sub-pass voltage is greater than the second sub-pass voltage.

[0118] In this embodiment, the threshold voltage of the memory cell layer in the programming state 402 is higher than the threshold voltage of the memory cell layer in the erasure state 401. The pass voltage applied to the word line layer corresponding to the memory cell layer in the erasure state can be greater than the pass voltage applied to the word line layer corresponding to the memory cell layer in the erasure state. That is, the first sub-pass voltage is greater than the second sub-pass voltage, which can keep the channel corresponding to the selected word line layer of the memory layer group of the selected memory stack at a higher boost potential and suppress programming voltage interference.

[0119] Instructions are required, such as Figure 4A , Figure 5A , Figure 6A and Figure 7A The number of storage cell layers (or word line layers) in each storage stack shown is for illustrative purposes only and is not intended to limit the number of storage cell layers (or word line layers) in each storage stack in the embodiments of this application to 6. Figure 4A , Figure 5A , Figure 6A and Figure 7A The number of dummy storage cell layers (or dummy word line layers) in each storage stack shown is for illustration only and is not intended to limit the number of storage cell layers (or dummy word line layers) in each storage stack in the embodiments of this application to one.

[0120] In some embodiments, at least one dummy storage cell layer and a dummy word line layer corresponding to each dummy storage cell layer at the junction of the first storage stack and the second storage stack belong to the first storage stack and / or the second storage stack.

[0121] In this embodiment of the application, the virtual storage layer group may include at least one virtual storage cell layer and a virtual word line layer corresponding to each virtual storage cell layer, and the virtual storage layer group may be located in at least one of adjacent storage stacks.

[0122] In some specific embodiments, a dummy memory layer group may include multiple memory cell layers and word line layers corresponding to each memory cell layer. A portion of the dummy memory layer group is located in one memory stack, and another portion of the dummy memory layer group is located in another memory stack. For example, as... Figure 3A The lower virtual memory layer group 305L shown may include a virtual memory cell layer and a virtual word line layer 307 corresponding to a virtual memory cell layer located in the lower memory stack 304L, and a virtual memory cell layer and a virtual word line layer 307 corresponding to a virtual memory cell layer located in the upper memory stack 304U. For example, refer to... Figure 3B and in conjunction with references Figure 4A , Figure 5A , Figure 6A and Figure 7A The lower virtual storage layer group 305L may include a storage cell layer and a word line layer 309 corresponding to each storage cell layer located in the lower storage stack 304L, and a storage cell layer and a word line layer 309 corresponding to each storage cell layer located in the middle storage stack 304M. Alternatively, refer to... Figure 3B and in conjunction with references Figure 4A , Figure 5A , Figure 6A and Figure 7A The upper virtual storage layer group 305U may include a storage cell layer and a word line layer 309 corresponding to each storage cell layer located in the middle storage stack 304M, as well as a storage cell layer and a word line layer 309 corresponding to each storage cell layer located in the upper storage stack 304U.

[0123] In some embodiments, at least one dummy word line layer at the junction of the first memory stack and the second memory stack includes a first dummy word line layer located in the first memory stack and a second dummy word line layer located in the second memory stack; the third pass voltage includes a third sub-pass voltage and a fourth sub-pass voltage; the peripheral circuitry is configured to apply a third sub-pass voltage to the first dummy word line layer and apply a fourth sub-pass voltage to the second dummy word line layer; the third sub-pass voltage and the fourth sub-pass voltage are different.

[0124] In some embodiments, the voltage through the third sub-sub is greater than the voltage through the fourth sub-sub-sub.

[0125] In this embodiment, to increase the potential barrier between the second dummy word line layer located in the second memory stack and the word line layer in the second memory stack to which the second pass voltage Vpass2 is applied, the difference between the second pass voltage Vpass2 applied to the word line layer of the second memory stack and the fourth sub-pass voltage applied to the second dummy word line layer is maximized. At the same time, to avoid the potential barrier between the first dummy word line layer located in the first memory stack and the word line layer in the first memory stack to which the first pass voltage Vpass1 is applied, the difference between the first pass voltage Vpass1 applied to the word line layer of the first memory stack and the third sub-pass voltage applied to the first dummy word line layer is minimized. The third sub-pass voltage applied to the first dummy word line layer can be set to be greater than the fourth sub-pass voltage applied to the second dummy word line layer; both the third sub-pass voltage and the fourth sub-pass voltage are less than the second pass voltage Vpass2. In this embodiment, the residual electrons coupled downward in the channel corresponding to the non-select word line layer of the blocked memory stack will migrate to the channel corresponding to the select word line layer of the memory layer group of the selected memory stack, so that the channel corresponding to the select word line layer of the memory layer group of the selected memory stack still maintains a high boost potential and suppresses programming voltage interference.

[0126] In some embodiments, the peripheral circuitry is configured to perform sequential programming operations or reverse programming operations on the plurality of memory cell layers in the first memory stack when programming operations are performed on the plurality of memory cell layers in the first memory stack. For example, as... Figure 5A , Figure 6A and Figure 7A As shown, the peripheral circuit is configured to perform sequential programming operations on multiple memory cell layers in the first memory stack, that is, to perform programming operations on each memory cell layer in the first memory stack in a direction from the memory cell layer closest to the drain selection transistor of the NAND memory string 310 to the memory cell layer furthest from the drain selection transistor of the NAND memory string 310.

[0127] In various embodiments of this application, the memory device includes a first memory stack and a second memory stack arranged adjacent to each other. During independent encoding, erasing, and reading operations on the selected memory stack (first memory stack), the non-selection word line layer of the selected memory stack needs to maintain a high pass voltage (first pass voltage Vpass1) to increase the boost potential of the selected word line layer and suppress programming voltage interference. The non-selection word line layer of the non-selection memory stack (second memory stack) needs to maintain a low pass voltage (second pass voltage Vpass2, and the second pass voltage Vpass2 is less than the first pass voltage Vpass1) to reduce the voltage drop of the non-selection word line layer of the non-selection memory stack. By mitigating voltage interference, and simultaneously reducing the through voltage (the third through voltage Vcut, which is less than the second through voltage Vpass2) of the dummy memory layer group at the junction adjacent to the selected memory stack, a soft cutoff voltage can be formed between the memory layer group of the selected memory stack and the memory layer group of the non-selected memory stack adjacent to the selected memory stack. This forms a barrier to the channel residual electrons RE, suppressing the migration of the channel residual electrons RE to the channel position corresponding to the select word line layer of the selected memory stack, thus maintaining a higher boost potential in the channel corresponding to the select word line layer of the selected memory stack and suppressing programming voltage interference. In other words, in the embodiments of this application, when performing independent write, erase, and read operations on each memory stack of the memory device, the through voltage interference of the non-selected memory stack is reduced, while the programming voltage interference of the selected memory stack is suppressed.

[0128] This application provides an operation method for a memory device, comprising: when programming a selected memory cell layer in a first memory stack of a memory cell array of the memory device, applying a programming voltage to a word line layer corresponding to the selected memory cell layer, and applying a first pass voltage to a word line layer corresponding to an unselected memory cell layer in the first memory stack; applying a second pass voltage to word line layers corresponding to multiple memory cell layers in a second memory stack stacked and adjacent to the first memory stack; and applying a third pass voltage to a dummy word line layer corresponding to at least one dummy memory cell layer at the junction of the first and second memory stacks; wherein the third pass voltage is less than the second pass voltage, and the second pass voltage is less than the first pass voltage.

[0129] In some embodiments, the unselected memory cell layer in the first memory stack includes a memory cell layer in a programmed state and a memory cell layer in an erased state; the first through voltage includes a first sub-through voltage and a second sub-through voltage; applying the first through voltage to the word line layer corresponding to the unselected memory cell layer in the first memory stack includes applying the first sub-through voltage to the word line layer corresponding to the memory cell layer in a programmed state and applying the second sub-through voltage to the word line layer corresponding to the memory cell layer in an erased state; the first sub-through voltage and the second sub-through voltage are different.

[0130] In some embodiments, the memory cell array includes a third memory stack stacked with both the first memory stack and the second memory stack; when the third memory stack is adjacent to the first memory stack, at least one dummy memory cell layer and a corresponding dummy word line layer are provided at the junction of the third memory stack and the first memory stack; applying a third through voltage to the dummy word line layer corresponding to at least one dummy memory cell layer at the junction of the first memory stack and the second memory stack includes: applying a third through voltage to the dummy word line layer corresponding to at least one dummy memory cell layer at the junction between the first memory stack and the third memory stack; or, when the third memory stack is adjacent to the second memory stack, at least one dummy memory cell layer and a corresponding dummy word line layer are provided at the junction of the third memory stack and the second memory stack; applying a third through voltage to the dummy word line layer corresponding to at least one dummy memory cell layer at the junction of the first memory stack and the second memory stack includes: applying a second through voltage to the dummy word line layers corresponding to at least one dummy memory cell layer at the junction between the second memory stack and the third memory stack.

[0131] In some embodiments, at least one dummy word line layer at the junction of the first memory stack and the second memory stack includes a first dummy word line layer located in the first memory stack and a second dummy word line layer located in the second memory stack; the third pass voltage includes a third sub-pass voltage and a fourth sub-pass voltage; applying the third pass voltage to the dummy word line layer corresponding to at least one dummy memory cell layer at the junction of the first memory stack and the second memory stack includes: applying a third sub-pass voltage to the first dummy word line layer and applying a fourth sub-pass voltage to the second dummy word line layer; the third sub-pass voltage and the fourth sub-pass voltage are different.

[0132] In some embodiments, the method further includes: when programming multiple storage cell layers in the first storage stack, performing sequential programming operations or reverse programming operations on the multiple storage cell layers in the first storage stack.

[0133] The memory device required for the operation method of the memory device provided in this application embodiment is similar to the memory device in the above embodiments. For technical features not disclosed in detail in this application embodiment, please refer to the various embodiments on the memory device side for understanding, and will not be repeated here.

[0134] Figure 8 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of this application. Figure 9 This is a schematic diagram of an exemplary memory card with a memory system according to an embodiment of this application. Figure 10 This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of this application.

[0135] refer to Figure 8 , Figure 9 , Figure 10 This application provides a memory system, including: one or more memory devices 100 according to any of the above embodiments; and a memory controller coupled to the memory and controlling the memory devices 100.

[0136] In such Figure 8 In one example shown, system 500 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 8 As shown, system 500 may include host 508 and memory system 502, the memory system 502 having one or more memory devices 100 and memory controller 506. Host 508 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). Host 508 may be configured to send data to or receive data from memory device 100.

[0137] Memory device 100 can be any memory claimed in this application. As detailed below, memory device 100 (e.g., NAND flash memory (e.g., three-dimensional (3D) NAND flash memory)) can have reduced leakage current from drive transistors (e.g., string drivers) coupled to unselected word lines during erase operations, which allows for further reduction in the size of the drive transistors.

[0138] According to some embodiments, a memory controller 506 is coupled to the memory device 100 and the host 508 and is configured to control the memory device 100. The memory controller 506 can manage data stored in the memory device 100 and communicate with the host 508. In some embodiments, the memory controller 506 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 506 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0139] The memory controller 506 can be configured to control the operation of the memory device 100, such as read, erase, and program operations. The memory controller 506 can also be configured to manage various functions relating to data stored or to be stored in the memory device 100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 506 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 100. The memory controller 506 can also perform any other suitable functions, such as formatting the memory device 100. The memory controller 506 can communicate with external devices (e.g., host 508) according to specific communication protocols. For example, the memory controller 506 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0140] The memory controller 506 and one or more memory devices 100 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 502 can be implemented and packaged into different types of end electronic products.

[0141] In such Figure 9In one example shown, the memory controller 506 and a single memory device 100 may be integrated into a memory card 602. The memory card 602 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 602 may also include a connection between the memory card 602 and a host computer (e.g., Figure 8 The memory card connector 604 is coupled to the host 508.

[0142] In such Figure 10 In another example shown, the memory controller 506 and multiple memory devices 100 may be integrated into the SSD 606. The SSD 606 may also include components for connecting the SSD 606 to a host computer (e.g., Figure 8 The SSD connector 608 is coupled to the host 508 in the memory card 602. In some embodiments, the storage capacity and / or operating speed of the SSD 606 is greater than that of the memory card 602 (e.g., ...). Figure 9 The storage capacity and / or operating speed shown in the figure.

[0143] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0144] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application. In practical applications, various changes in form and detail can be made without departing from the spirit and scope of this application. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A memory device, characterized in that, include: A storage cell array, comprising a first storage stack and a second storage stack that are stacked and arranged adjacent to each other; Both the first storage stack and the second storage stack include multiple storage cell layers and word line layers corresponding to each storage cell layer. At the junction of the first storage stack and the second storage stack, at least one dummy storage cell layer and a dummy word line layer corresponding to each dummy storage cell layer are provided. The peripheral circuitry, coupled to the memory cell array, is configured as follows: When programming a selected memory cell layer in the first memory stack, a programming voltage is applied to the word line layer corresponding to the selected memory cell layer, and a first pass voltage is applied to the word line layer corresponding to the unselected memory cell layer in the first memory stack. A second pass voltage is applied to the word line layer corresponding to multiple memory cell layers in the second memory stack; as well as A third pass voltage is applied to the dummy word line layer corresponding to at least one dummy memory cell layer at the junction of the first memory stack and the second memory stack; Wherein, the third through voltage is less than the second through voltage, and the second through voltage is less than the first through voltage.

2. The memory device according to claim 1, characterized in that, The first through voltage and the second through voltage have a first difference; the second through voltage and the third through voltage have a second difference; the first difference and the second difference are different.

3. The memory device according to claim 2, characterized in that, The second difference is greater than the first difference.

4. The memory device according to claim 1, characterized in that, Multiple storage cell layers in the second storage stack are in a programmed state.

5. The memory device according to claim 1, characterized in that, The unselected storage cell layer in the first storage stack includes storage cell layers in the programming state and storage cell layers in the erasure state; the first through voltage includes: a first sub-through voltage and a second sub-through voltage; The peripheral circuit is configured to apply a first sub-pass voltage to the word line layer corresponding to the memory cell layer in the programming state, and to apply a second sub-pass voltage to the word line layer corresponding to the memory cell layer in the erasure state; the first sub-pass voltage and the second sub-pass voltage are different.

6. The memory device according to claim 1, characterized in that, The storage cell array further includes a third storage stack that is stacked with both the first storage stack and the second storage stack; The third storage stack is arranged adjacent to the first storage stack, and at the junction of the third storage stack and the first storage stack, at least one dummy storage cell layer and a dummy word line layer corresponding to each dummy storage cell layer are provided. The peripheral circuit is configured to apply the third pass voltage to at least one dummy word line layer corresponding to a dummy memory cell layer at the junction between the first memory stack and the third memory stack; or, The third storage stack is arranged adjacent to the second storage stack, and at the junction of the third storage stack and the second storage stack, at least one virtual storage cell layer and a virtual word line layer corresponding to each virtual storage cell layer are provided. The peripheral circuit is configured to apply the second pass voltage to at least one dummy word line layer corresponding to a dummy memory cell layer at the junction between the second and third memory stacks.

7. The memory device according to claim 1, characterized in that, At least one dummy memory cell layer and the corresponding dummy word line layer at the junction of the first memory stack and the second memory stack belong to the first memory stack and / or the second memory stack.

8. The memory device according to claim 7, characterized in that, At least one dummy word line layer at the junction of the first memory stack and the second memory stack includes a first dummy word line layer located in the first memory stack and a second dummy word line layer located in the second memory stack; the third pass voltage includes a third sub-pass voltage and a fourth sub-pass voltage; The peripheral circuit is configured to apply the third sub-pass voltage to the first dummy word line layer and the fourth sub-pass voltage to the second dummy word line layer; the third sub-pass voltage and the fourth sub-pass voltage are different.

9. The memory device according to claim 1, characterized in that, The peripheral circuit is configured as follows: When programming multiple storage cell layers in the first storage stack, sequential programming operations or reverse programming operations are performed on the multiple storage cell layers in the first storage stack.

10. A memory system, characterized in that, include: One or more memory devices as described in any one of claims 1 to 9; as well as A memory controller, coupled to the memory and controlling the memory device.

11. A method of operating a memory device, characterized in that, include: When programming a selected memory cell layer in the first memory stack of the memory cell array of the memory device, a programming voltage is applied to the word line layer corresponding to the selected memory cell layer, and a first pass voltage is applied to the word line layer corresponding to the unselected memory cell layer in the first memory stack. A second pass voltage is applied to the word line layer corresponding to a plurality of memory cell layers in a second memory stack that is stacked and adjacent to the first memory stack; as well as A third pass voltage is applied to the dummy word line layer corresponding to at least one dummy memory cell layer at the junction of the first memory stack and the second memory stack; Wherein, the third through voltage is less than the second through voltage, and the second through voltage is less than the first through voltage.

12. The operating method according to claim 11, characterized in that, The unselected storage cell layer in the first storage stack includes storage cell layers in the programming state and storage cell layers in the erasure state; the first through voltage includes: a first sub-through voltage and a second sub-through voltage; Applying a first pass voltage to the word line layer corresponding to the unselected memory cell layer in the first memory stack includes: A first sub-pass voltage is applied to the word line layer corresponding to the memory cell layer in the programming state, and a second sub-pass voltage is applied to the word line layer corresponding to the memory cell layer in the erasure state; the first sub-pass voltage and the second sub-pass voltage are different.

13. The operating method according to claim 11, characterized in that, The storage cell array includes a third storage stack that is stacked with both the first storage stack and the second storage stack; When the third storage stack is arranged adjacent to the first storage stack, at least one virtual storage cell layer and a virtual word line layer corresponding to each virtual storage cell layer are provided at the junction of the third storage stack and the first storage stack. The method further includes: applying the third pass voltage to a virtual word line layer corresponding to at least one virtual memory cell layer at the junction between the first storage stack and the third storage stack; or, When the third storage stack is arranged adjacent to the second storage stack, at least one dummy storage cell layer and a dummy word line layer corresponding to each dummy storage cell layer are provided at the junction of the third storage stack and the second storage stack; the method further includes: applying the second through voltage to the dummy word line layers corresponding to at least one dummy storage cell layer at the junction between the second storage stack and the third storage stack.

14. The operating method according to claim 11, characterized in that, At least one dummy word line layer at the junction of the first storage stack and the second storage stack includes a first dummy word line layer located in the first storage stack and a second dummy word line layer located in the second storage stack; The third through voltage includes a third sub-through voltage and a fourth sub-through voltage; Applying a third pass voltage to at least one dummy word line layer corresponding to a dummy memory cell layer at the junction of the first memory stack and the second memory stack includes: The third sub-pass voltage is applied to the first dummy word line layer, and the fourth sub-pass voltage is applied to the second dummy word line layer; The voltage through the third sub-sub is different from the voltage through the fourth sub-sub ...

15. The operating method according to claim 11, characterized in that, The method further includes: When programming multiple storage cell layers in the first storage stack, sequential programming operations or reverse programming operations are performed on the multiple storage cell layers in the first storage stack.

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