Methods, apparatuses for improving epitaxial wafer quality, and epitaxial wafers and methods of manufacturing the same

Abstract

The present disclosure provides a method and device for improving the quality of an epitaxial wafer, an epitaxial wafer and a manufacturing method thereof. The method for improving the quality of the epitaxial wafer comprises: matching the position of a surface defect of an epitaxial wafer with the contact position of a contact component in an epitaxial process equipment, obtaining a first surface defect matched with the contact position of the contact component; acquiring the topography and type of the first surface defect; and determining the improvement means of the contact component to reduce the number of the first surface defects according to the topography and type of the first surface defect and the thickness of the epitaxial layer of the epitaxial wafer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method and device for improving the quality of an epitaxial wafer, an epitaxial wafer, and a method for manufacturing the same. Background Art

[0002] Silicon wafers, composed of semiconductors, are widely used as substrates in the manufacturing process of semiconductor devices. Common types include polished wafers and epitaxial wafers. Polished wafers are produced by slicing a single crystal ingot, mirror polishing, and cleaning. Epitaxial wafers are produced by forming a single crystal silicon epitaxial layer on the surface of the polished wafer using methods such as chemical vapor deposition.

[0003] With the continuous development of semiconductor technology, the quality requirements for silicon wafers are becoming increasingly stringent. For epitaxial wafers, surface defects in the epitaxial layer are a key factor affecting epitaxial wafer quality. Among the surface defects in the epitaxial layer, some surface defects originate from the epitaxial process. Therefore, reducing the surface defects in the epitaxial layer generated during the epitaxial process can improve the quality of epitaxial wafers. Summary of the Invention

[0004] The present disclosure provides a method and device for improving the quality of epitaxial wafers, as well as an epitaxial wafer and a method for manufacturing the same; the method can reduce surface defects generated by contact components during the epitaxial process and improve the quality of the epitaxial wafers.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] In a first aspect, the present disclosure provides a method for improving the quality of an epitaxial wafer, the method comprising:

[0007] Matching the position of the surface defect of the epitaxial wafer with the contact position of a contact component in the epitaxial process equipment to obtain a first surface defect that matches the contact position of the contact component;

[0008] Acquiring the morphology and type of the first surface defect;

[0009] According to the morphology and type of the first surface defects and the thickness of the epitaxial layer of the epitaxial wafer, a means of improving the contact component is determined to reduce the number of the first surface defects.

[0010] In a second aspect, the present disclosure provides a device for improving the quality of epitaxial wafers, the device comprising: a matching unit, an acquisition unit, and a determination unit; wherein,

[0011] The matching unit is configured to match the position of the surface defect of the epitaxial wafer with the contact position of the contact component in the epitaxial process equipment to obtain a first surface defect that matches the contact position of the contact component;

[0012] The acquiring unit is configured to acquire the morphology and type of the first surface defect;

[0013] The determining unit is configured to determine, based on the morphology and type of the first surface defects and the thickness of the epitaxial layer of the epitaxial wafer, an improvement measure for the contact component to reduce the number of the first surface defects.

[0014] In a third aspect, the present disclosure provides a device for improving the quality of epitaxial wafers, the device comprising: a processor and a memory; the processor is used to execute instructions stored in the memory to implement the method for improving the quality of epitaxial wafers as described in the first aspect.

[0015] In a fourth aspect, the present disclosure provides a method for manufacturing an epitaxial wafer, the manufacturing method comprising:

[0016] Determining means for improving contact components in epitaxial process equipment according to the method for improving epitaxial wafer quality as described in the first aspect;

[0017] After adjusting the contact component according to the improvement means, an epitaxial process is performed on the polished wafer substrate.

[0018] In a fifth aspect, the present disclosure provides an epitaxial wafer, which is obtained by the method for manufacturing an epitaxial wafer described in the fourth aspect, and the number of defects with a size less than 200 nm on the surface of the epitaxial wafer is less than 2.

[0019] The present disclosure provides a method and apparatus for improving the quality of epitaxial wafers, as well as an epitaxial wafer and a method for manufacturing the same. After obtaining a first surface defect among the surface defects of the epitaxial wafer that matches the contact position of a contact component of an epitaxial process equipment, a method for improving the contact component is determined based on the morphology and type of the first surface defect and the thickness of the epitaxial layer of the epitaxial wafer. After the contact component is adjusted using the above-mentioned improvement method, abnormal contact between the contact component and the substrate wafer is avoided during the transmission process within the epitaxial process equipment, reducing surface defects on the epitaxial wafer surface caused by the contact component, and improving the quality of the epitaxial wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic top view of the epitaxial growth apparatus provided for the present disclosure.

[0021] Figure 2 A schematic structural diagram of a processing chamber for performing an epitaxial deposition process provided by the present disclosure.

[0022] Figure 3 A schematic flow chart of a method for improving epitaxial wafer quality provided by the present disclosure.

[0023] Figure 4 (A) Schematic diagram of the contact position between the contact component of the robot provided at the factory interface and the edge of the wafer.

[0024] Figure 4 (B) Schematic diagram of the contact position between the contact component of the robot and the edge of the wafer in the load lock chamber provided by the present disclosure.

[0025] Figure 4 (C) is a schematic diagram of the contact position between the contact component of the buffer area robot and the edge of the wafer in the transfer chamber provided by the present disclosure.

[0026] Figure 5 An exemplary wafer defect map provided by the present disclosure.

[0027] Figure 6 Schematic diagram of the ESF defect morphology provided in the present disclosure.

[0028] Figure 7 Schematic diagram of forming first surface defects of an epitaxial wafer from second surface defects of a substrate wafer provided by the present disclosure.

[0029] Figure 8 Another method for improving the quality of epitaxial wafers provided by the present disclosure.

[0030] Figure 9 A schematic diagram of the composition of a device for improving the quality of epitaxial wafers provided by the present disclosure.

[0031] Figure 10 A schematic diagram of another device for improving epitaxial wafer quality provided by the present disclosure.

[0032] Figure 11 A schematic diagram of the structure of a computing device provided by the present disclosure. DETAILED DESCRIPTION

[0033] The technical solutions in the present disclosure will be described clearly and completely below with reference to the accompanying drawings in the present disclosure.

[0034] See also Figure 1 , which shows a schematic top view of an epitaxial growth device 100 applicable to the technical solution of the embodiment of the present disclosure. The epitaxial growth device 100 generally includes: a factory interface (Factory Interface) 102, load lock (Loadlock) chambers 104, 106, a transfer chamber (Transfer chamber) 108, and process chambers (Process chamber) 120, 122. Figure 1As shown, wafers in the epitaxial growth apparatus 100 (shown as gray circles in the figure) can be processed in various chambers and transferred between the various chambers (shown as solid arrows and dashed arrows in the figure) without being exposed to the surrounding environment outside the epitaxial growth apparatus 100. For example, wafers can be processed in various chambers under low pressure (e.g., less than or equal to about 300 Torr) or vacuum environments or transferred between these various chambers without destroying the low pressure or vacuum environment between various processes performed on the wafers in the epitaxial growth apparatus 100. Figure 1 As shown, the epitaxial growth equipment 100 has more than one processing chamber, which can perform the epitaxial deposition process of multiple wafers in one batch, thereby improving the production efficiency of epitaxial wafers.

[0035] exist Figure 1 In the example shown, the factory interface 102 includes a docking station 140. The epitaxial growth apparatus 100 also includes a plurality of front opening unit (FOUP) 144 adapted to the docking station 140. In some examples, the epitaxial growth apparatus 100 can be operated by a robot ( Figure 1 ), the wafers can be transferred from the front-opening standard cabin 144 to the docking station 140, and then transferred from the docking station 140 to the load lock chambers 104 and 106.

[0036] The load lock chambers 104, 106 have respective ports coupled to the factory interface 102 and respective ports coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports coupled to the process chambers 120, 122. In some examples, the ports may be slit openings with slit valves that can be connected to the process chambers 120, 122 by a robot ( Figure 1 (not shown) allows wafers to pass through these ports and is used to provide a seal between the corresponding chambers to prevent gas from passing between the corresponding chambers. Generally speaking, in order to transfer a wafer through any port, the port is open; otherwise, the port is closed.

[0037] The load lock chambers 104, 106, the transfer chamber 108, and the processing chambers 120, 122 may be fluidly coupled to a gas and pressure control system ( Figure 1106). The gas and pressure control system may include one or more gas pumps (e.g., turbo pumps, cryopumps, roughing pumps, etc.), gas sources, various valves, and conduits fluidly coupled to various chambers. In operation, a robot of the factory interface 102 transfers wafers from the FOUP 144 through a port to the load lock chamber 104 or 106. The gas and pressure control system then evacuates (pumps down) the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chamber 108 at an internal low-pressure or vacuum environment (which may include an inert gas). Thus, evacuating the load lock chamber 104 or 106 facilitates the passage of substrates between, for example, the atmospheric environment of the factory interface 102 and the low-pressure or vacuum environment of the transfer chamber 108.

[0038] When the wafer is in the evacuated load lock chamber 104 or 106, the robot transfers the wafer from the load lock chamber 104 or 106 through the port into the transfer chamber 108. The robot can then transfer the wafer to a processing chamber 120, 122 for processing.

[0039] The processing chamber 120 may be any suitable chamber for processing wafers. In some examples, the processing chamber 120 may be used to perform a cleaning process, or to perform an etching process, or to perform a respective epitaxial deposition process.

[0040] For some examples, see Figure 2 The processing chamber 120 for performing an epitaxial deposition process includes a susceptor 10 and a susceptor support frame 20A. The susceptor 10 is capable of horizontally supporting a wafer W. The susceptor support frame 20A is capable of driving the susceptor 10 to rotate at a certain speed about a central axis X during vapor deposition. During the rotation of the susceptor 10, the wafer W rotates along with the susceptor 10 about the central axis X. Specifically, the wafer W remains stationary relative to the susceptor 10, and a small gap G is formed between the radial edge of the susceptor 10 and an adjacent component 10A (e.g., a preheat ring).

[0041] Chamber RC is enclosed by an upper bell jar 30A and a lower bell jar 30B, and houses a susceptor 10 and a susceptor support frame 20A. The upper bell jar 30A and the lower bell jar 30B can be made of, for example, transparent quartz. The susceptor 10 divides chamber RC into an upper reaction chamber RC1 and a lower reaction chamber RC2. Wafers W are housed in the upper reaction chamber RC1. The pressure in the upper reaction chamber RC1 is slightly greater than that in the lower reaction chamber RC2, allowing gas in the upper reaction chamber RC1 to enter the lower reaction chamber RC2 through a gap G.

[0042] An air inlet 40 and an exhaust port 50 are formed on the left and right sides of the chamber RC, respectively. Specifically, the air inlet 40 is used to transport reaction gases, such as silicon source gas, carrier gas, and dopant gas, into the upper reaction chamber RC1. Silicon atoms are generated by the reaction of the silicon source gas and the carrier gas and deposited on the wafer W to form an epitaxial layer on the surface of the wafer W by vapor deposition. The epitaxial layer of the wafer W is doped with a dopant gas to obtain the required resistivity. For example, chlorosilane-based gases such as trichlorosilane SiHCl3 or dichlorosilane SiH2Cl2 are used as silicon source gases. Hydrogen H2 is used as a carrier gas. Gases containing doping elements such as diborane B2H6 or phosphine PH3 are used as dopant gases. The exhaust port 50 is used to discharge the reaction exhaust gas out of the chamber RC.

[0043] In order to grow the epitaxial layer on the wafer W, the reaction gas (silicon source gas and carrier gas) is driven to flow along the upper surface of the wafer W, and the wafer W supported by the susceptor 10 is heated to about 1000°C to 1200°C. To this end, heat sources are provided above and below the chamber RC to provide a high temperature reaction environment. Figure 1 As shown, the heat source may be a plurality of heating bulbs 60, such as infrared lamps or far-infrared lamps. The plurality of heating bulbs 60 are disposed around the upper bell jar 30A and the lower bell jar 30B to heat the susceptor 10 and the wafer W by radiant heat from above and below the chamber 2 through the upper bell jar 30A and the lower bell jar 30B.

[0044] exist Figure 2 The processing chamber 120 shown is also provided with a wafer support rod 80A and a wafer support rod carrier 90 arranged directly below the wafer support rod 80A. Before vapor deposition, the upper bell jar 30A is opened. The wafer W is transferred from the transfer chamber 108 to be placed on the wafer support rod 80A by a robot manipulator (not shown in the figure). Then, the wafer support rod 80A is driven down by the descent of the wafer support rod carrier 90, so that the wafer W is loaded into the base 10. Finally, the upper bell jar 30A is closed, thereby completing the process of moving the wafer to the inside of the chamber RC. After completing the process of moving the wafer to the inside of the chamber RC, vapor deposition is performed. After the vapor deposition is completed, the upper bell jar 30A is opened. The wafer support rod 80A is driven up by the rise of the wafer support rod carrier 90, and the epitaxial wafer is lifted from the base 10. Finally, the epitaxial wafer is moved from the inside of the chamber RC to the transfer chamber 108 by the robot manipulator. In addition, in Figure 2 The illustrated processing chamber 120 further includes a mounting member 70 for assembling various components of the processing chamber 120 .

[0045] In conjunction with the above-described epitaxial growth apparatus 100 and processing chamber 120, during epitaxial processes, such as vapor deposition, and during transfers between chambers of the epitaxial growth apparatus 100, the robot adjusts the extension and extension dimensions and positioning angles of its manipulators to grip wafers and control the transfer of the gripped wafers between chambers. These manipulators for gripping wafers are the components of the epitaxial growth apparatus 100 that directly contact the wafer edge and are referred to herein as contact components.

[0046] During the epitaxial growth process, if these contact components are not properly configured for their extension and contraction dimensions and angles, they can create defects on the edge of the substrate wafer surface during transfer. As the epitaxial deposition process continues to overlay the single crystal epitaxial layer on the defect, the resulting epitaxial wafer surface will develop surface defects at the same locations as the defects on the substrate wafer edge.

[0047] In order to avoid the above-mentioned surface defects caused by contact components on epitaxial wafers, the present disclosure provides a solution to improve the quality of epitaxial wafers, reduce the surface defects caused by contact components on the surface of epitaxial wafers, and improve the quality of epitaxial wafers. Figure 3 , which shows a method for improving the quality of epitaxial wafers provided by the present disclosure, which may include steps S301 to S303.

[0048] In step S301 , the position of a surface defect of the epitaxial wafer is matched with the contact position of a contact component in an epitaxial process device to obtain a first surface defect that matches the contact position of the contact component.

[0049] In some examples, the contact component is a component in the epitaxial process equipment 100 that can directly contact the edge of the wafer. Figure 1 Taking the epitaxial processing equipment 100 shown as an example, during the wafer transfer process, the contact components may be robot arms. For example, these robots may be robots located at the docking station 140 of the factory interface 102, robots in the load lock chambers 104 or 106, or robots that transfer wafers from the transfer chamber 108 to the processing chambers 120 or 122.

[0050] In some examples, the position where the contact component contacts the wafer edge on the wafer surface is the contact position. Figure 4 (A) Figure 4 (B) and Figure 4(C) shows the contact positions of the contact parts of the robot (FI Robot, Factory Interface) provided at the docking station 140 of the factory interface 102, the robot (Loadlock Robot) in the load lock chamber 104 or 106, and the buffer robot (Buffer Robot) in the transfer chamber with the wafer edge, respectively. Figure 4 (A) Figure 4 (B) and Figure 4 As shown by the circled box in (C).

[0051] In some examples, surface defects on an epitaxial wafer can be distributed anywhere on the surface of the epitaxial wafer. In the present disclosure, a wafer defect map (MAP) can be generated based on the locations of surface defects on the epitaxial wafer. It can be found that, among all surface defects on the epitaxial wafer, those caused by contact components tend to cluster at locations on the epitaxial wafer surface corresponding to the contact locations.

[0052] Based on the above findings, in some examples, matching the position of the surface defect of the epitaxial wafer with the contact position of a contact component in an epitaxial process device to obtain a first surface defect that matches the contact position of the contact component includes:

[0053] Matching, at the surface edge of the epitaxial wafer, a location where surface defects are concentrated with a contact position of the contact component;

[0054] When the location where the surface defects gather matches the contact position of the contact component, the defect at the location where the surface defects gather is determined as the first surface defect.

[0055] In the above example, combined with Figure 5 The example of wafer defect map shown in the figure shows that: Figure 5 Below the wafer surface shown, the surface defects indicated by triangular points, circular points, and diamond points are more "dense" and appear to be clustered. The present disclosure uses the number of defects that appear within a set area on the wafer surface to evaluate whether there is "clustering." For example, the set area is 2μm×2μm. If there is an area on the epitaxial wafer surface that meets the area of ​​the area, and the number of defects that appear in the area is greater than or equal to a set threshold, such as 3-5, it means that the surface defects of the epitaxial wafer are clustered in the area.

[0056] According to the above example, at the surface edge of the epitaxial wafer, the present disclosure matches the location of the area where surface defects are concentrated with the contact position of the aforementioned contact component. If the location of the area where surface defects are concentrated matches the contact position of the contact component, then it can be considered that the surface defects in the area are caused by the contact component that matches it. The present disclosure determines the defects at the location where surface defects are concentrated as the first surface defects. For example, continue to refer to Figure 5 The surface defects shown in the circled box are clustered at the same location as Figure 4 If the contact position matches the one shown in (A), the surface defect within the circled box is the first surface defect.

[0057] In some examples, among the surface defects of the epitaxial wafer, there are surface defects that do not match the contact position of the contact component. In this case, the causes of the defects can be investigated for other components in the epitaxial process equipment except the contact component to eliminate such surface defects that are not caused by the contact component.

[0058] In step S302, the morphology and type of the first surface defect are obtained.

[0059] In some examples, after obtaining the first surface defect in step S301 above, a scanning electron microscope (SEM) can be used to inspect the first surface defect to determine its morphology and type. Specifically, the SEM uses a high-energy electron beam to scan the surface of the epitaxial wafer and collects secondary electrons generated by the high-energy electron beam interacting with materials on the epitaxial wafer surface to obtain a scanned image of the epitaxial wafer. Based on this scanned image, not only the defect type can be determined, but also the defect morphology can be determined.

[0060] It should be noted that the first surface defect is a surface defect caused by the contact component in the epitaxial wafer. Specifically, after the contact component forms a second surface defect on the surface edge of the substrate wafer of the epitaxial wafer, the single crystal epitaxial layer is continuously overlaid on the second surface defect of the substrate wafer during the epitaxial deposition process. As a result, the first surface defect formed on the epitaxial wafer surface at the corresponding position of the second surface defect of the substrate wafer is an epitaxial stacking fault (ESF). Furthermore, the morphology of the first surface defect formed on the surface of the epitaxial wafer varies depending on the size of the second surface defect.

[0061] In some examples, the morphology and type of the first surface defect include at least:

[0062] The first surface defect is an ESF defect, and the morphology is a polycrystalline epitaxial stacking fault type;

[0063] The first surface defect is an ESF defect, and the morphology is a composite defect of polysilicon growth and stacking faults;

[0064] The first surface defect is an ESF defect, and the morphology is a compound epitaxial stacking fault with a broken surface;

[0065] The first surface defect is an ESF defect, and the morphology is epitaxial growth protrusion on the crystal face (100).

[0066] For the above examples, for example, as shown in Figure 6 (A), Figure 6 (B), Figure 6 (C), and Figure 6 (D), respectively, ESF defect diagrams with morphologies of polysilicon epitaxial stacking fault type, composite defect of polysilicon growth and stacking faults type, compound epitaxial stacking fault with a broken surface type, and epitaxial growth protrusion on the crystal face (100) type are shown.

[0067] It should be noted that, in Figure 6 (A), the polysilicon epitaxial stacking fault type defect is the same as or similar to the defect shown in Figure 21 in SEMI MF154, covering a larger area on the epitaxial wafer surface, and being covered or surrounded by an epitaxial layer, and from a visual perspective, the shape of the defect is close to spherical, with a certain curvature, the surface has many protrusions and depressions, and there is no obvious geometric rule, the outline is complex, and there are various abrupt parts. In Figure 6 (B), the composite defect of polysilicon growth and stacking faults type defect is the same as or similar to the defect shown in Figure 18 in SEMI MF154, and from a visual perspective, the outline of the defect is close to square, and the surface is usually rough and uneven, which is due to the mutual extrusion and collision between atoms during the accumulation process, and the mutual staggered arrangement resulting in uneven surface pits. In Figure 6 (C), the compound epitaxial stacking fault with a broken surface type defect is the same as or similar to the defect shown in Figure 19 in SEMI MF154, and from a visual perspective, the defect is usually conical, with a wide base and a sharp top, and each layer is smaller than the next layer, and the whole presents a gradually shrinking trend. Figure 6 In (D), the epitaxial growth hillock on (100) is the same or similar to the defect shown in Figure 9 in SEMIMF154. Visually, the defect is usually stepped, with the height and width of each layer being basically the same, forming layers of platforms, and the layers of these platforms are distinct and orderly.

[0068] In some examples, when the first surface defects are not ESF defects, it means that although these first surface defects match the contact position of the contact component, they are not caused by the contact component. Therefore, the cause of the defects can still be investigated for other components in the epitaxial process equipment except the contact component to eliminate such first surface defects that are not caused by the contact component.

[0069] In step S303 , based on the morphology and type of the first surface defects and the thickness of the epitaxial layer of the epitaxial wafer, improvement measures for the contact component are determined to reduce the number of the first surface defects.

[0070] In the present disclosure, for the first surface defect belonging to the ESF defect, different morphologies can be characterized by the size of the first surface defect. It can be found that the size of the first surface defect is not only related to the thickness of the epitaxial layer deposited on the substrate wafer surface during the epitaxial deposition process, but also to the size of the second surface defect. In detail, Figure 7 As shown in the following example, when a layer with a thickness of t When the epitaxial layer is formed, if there is a diameter of d Second surface defects (such as Figure 7 As shown by the black dots in the figure, the second surface defect is continuously covered with a single crystal epitaxial layer (Epi-layer) during the epitaxial deposition process. This will cause the second surface defect to expand along the crystal plane (111), and eventually the size of the first surface defect formed on the surface of the epitaxial layer, that is, the surface of the epitaxial wafer, will be s Satisfy the following formula:

[0071] .

[0072] It can be found that: since the size of the first surface defect is related to the morphology, for the above formula and the different morphologies of the aforementioned ESF defects, when d / t ≥ 1, the morphology of ESF defect is polycrystalline epitaxial stacking fault type. d / t <1, the morphology of ESF defect is a composite defect of polysilicon growth and stacking fault type or a composite epitaxial stacking fault type of surface fracture. d / tWhen ≤0.2, the morphology of the ESF defect is an epitaxial growth protrusion on the crystal plane (100).

[0073] Based on the above findings, in some examples, determining, based on the morphology and type of the first surface defects and the thickness of the epitaxial layer of the epitaxial wafer, a means of improving the contact component to reduce the number of the first surface defects includes:

[0074] determining a second surface defect size of the substrate of the epitaxial wafer at a position corresponding to the first surface defect according to the morphology and type of the first surface defect and the thickness of the epitaxial layer of the epitaxial wafer;

[0075] Improvement measures for the contact component are determined according to the size of the second surface defects to reduce the number of the first surface defects.

[0076] For the above example, specifically, based on the findings of the above inventors, when the morphology and type of the first surface defect and the thickness of the epitaxial layer of the epitaxial wafer are known, the size of the second surface defect can be roughly known. For example, on the surface of an epitaxial wafer with an epitaxial layer thickness of 3.5 μm, when the first surface defect is an ESF defect and the morphology is an epitaxial growth convex type on the crystal plane (100), based on the above findings about the morphology of the epitaxial growth convex type on the crystal plane (100), the size of the second surface defect can be roughly known. d / t It can be determined that a second surface defect with a size less than 0.6 μm exists on the surface of the substrate wafer at a position corresponding to the first surface defect.

[0077] In the present disclosure, the second surface defect is caused by the contact component. That is, if the expansion and contraction amount (or expansion and contraction size) and layout angle of the contact component are not properly set, the contact component will form a second surface defect at the contact position with the substrate wafer. The worse the expansion and contraction size and layout angle are set, the larger the size of the second surface defect. Based on this, in some examples, taking the contact component as a robot arm arranged in the epitaxial process equipment, the method of determining the improvement method of the contact component based on the size of the second surface defect to reduce the number of the first surface defects includes:

[0078] The telescopic size of the manipulator during clamping and the layout angle of the manipulator are determined according to the size of the second surface defect, so as to reduce the number of the first surface defects.

[0079] Specifically, in the above example, after the size of the second surface defect is known, the telescopic size and layout angle of the contact component (i.e., the robot arm) can be adjusted based on the size, and the contact component improvement measures described in step S303 are formed based on the adjusted values ​​of the telescopic size and layout angle of the contact component. It should be noted that after the contact component is adjusted through the above improvement measures, such as the telescopic size and layout angle of the contact component, abnormal contact between the contact component and the substrate wafer can be avoided during the transfer process within the epitaxial process equipment 100, thereby reducing the number of second surface defects generated on the substrate wafer surface, and further reducing the number of first surface defects on the epitaxial wafer.

[0080] In some examples, after adjusting the contact component through improvement measures, such as adjusting the contact component's telescopic size and layout angle, the epitaxial growth process can be continued on subsequent substrate wafers based on the adjusted telescopic size and layout angle. After obtaining the subsequent epitaxial wafers, the contact component's telescopic size and layout angle are further adjusted according to the above technical solution, and the epitaxial growth process is continued on the substrate wafer based on the telescopic size and layout angle obtained from the continued adjustment. In this way, through iterative adjustment, the number and size of the first surface defects are reduced to a set standard.

[0081] Through the above technical solution, after obtaining a first surface defect among the epitaxial wafer surface defects that matches the contact position of the contact component of the epitaxial process equipment, a method for improving the contact component is determined based on the morphology and type of the first surface defect and the thickness of the epitaxial layer of the epitaxial wafer. After the contact component is adjusted using the above improvement method, abnormal contact between the contact component and the substrate wafer is avoided during transportation within the epitaxial process equipment, reducing surface defects on the epitaxial wafer surface caused by the contact component and improving the quality of the epitaxial wafer.

[0082] Based on the same inventive concept as the above technical solution, see Figure 8 , which shows another method process for improving epitaxial wafer quality, which may include:

[0083] S801: Inspect the epitaxial wafer by optical inspection means to obtain the size and number of optical inspection defects on the surface of the epitaxial wafer.

[0084] In some examples, by Figure 1 After the epitaxial wafer is manufactured by the epitaxial process equipment 100 shown in the figure, the surface of the epitaxial wafer can be inspected by optical inspection means such as surface light scattering (LLS) scanning technology to obtain a wafer defect map of the epitaxial wafer, such as Figure 5 The following example is shown. Figure 5 When defects appear on the surface of the epitaxial wafer, Figure 5 Bright spot particles appear at the location of the defect, and the number of bright spot particles is counted to obtain the number of optical defects on the epitaxial wafer surface. Optical inspection can not only identify the bright spot particles corresponding to the defect, but also the size of the defect.

[0085] S802: Compare the size and quantity of the optically detected defect with a size threshold and a quantity threshold, respectively, to determine whether the size and quantity of the optically detected defect are greater than or equal to the size threshold and the quantity threshold, respectively.

[0086] In this disclosure, size thresholds and quantity thresholds can be used to characterize whether surface defects on epitaxial wafers meet compliance criteria. In some examples, the size threshold is exemplarily set to 200nm, and the quantity threshold is exemplarily set to 3ea. Of course, the above two thresholds can be determined based on the product's indicator requirements, and this disclosure does not elaborate on this.

[0087] When the size of the optical detection defect on the surface of the epitaxial wafer is less than the size threshold, and the number of the optical detection defects on the surface of the epitaxial wafer is less than the number threshold, it indicates that the surface defects of the epitaxial wafer are compliant, and it can also indicate that the particle level in each chamber of the epitaxial process equipment meets the required standards. In this case, step S803 is executed: no adjustment is required to the epitaxial process equipment. It can be understood that when the size of the optical detection defect on the surface of the epitaxial wafer is less than the size threshold, and the number of the optical detection defects on the surface of the epitaxial wafer is greater than or equal to the number threshold, although the number of surface defects is large, it usually does not affect the subsequent process. Therefore, in this case, the epitaxial wafer can still be considered compliant, and step S803 is executed.

[0088] When the size of the optical detection defect on the surface of the epitaxial wafer is greater than or equal to the size threshold, and the number of optical detection defects on the surface of the epitaxial wafer is greater than or equal to the number threshold, execute step S804: determine whether there is an optical detection defect on the surface of the substrate wafer of the epitaxial wafer at the corresponding position of the optical detection defect on the surface of the epitaxial wafer.

[0089] Regarding step S804 above, specifically, when the size of the optically detected defects on the surface of the epitaxial wafer is greater than or equal to the size threshold, and the number of optically detected defects on the surface of the epitaxial wafer is greater than or equal to the number threshold, the epitaxial wafer is non-compliant due to a large number of surface defects or a large size. Based on the causes of surface defects on epitaxial wafers. Some surface defects on epitaxial wafers are caused by surface defects left over from the processing of the substrate wafer (e.g., polished wafer), while other surface defects are caused by epitaxial process equipment during the epitaxial process.

[0090] When the size of an optically detected defect on the surface of an epitaxial wafer is greater than or equal to a size threshold, and the number of optically detected defects on the surface of an epitaxial wafer is less than a number threshold, the defect still needs to be removed due to its large size, but due to its small number, there is no need to improve the process equipment, and the defect can be eliminated by cleaning the epitaxial wafer.

[0091] In order to identify surface defects caused by epitaxial process equipment from surface defects of the epitaxial wafer, optical detection defects on the surface of the substrate wafer can be detected by optical detection means before the substrate wafer enters the epitaxial process equipment.

[0092] If optical inspection defects are detected at the same locations on both the substrate wafer surface and the epitaxial wafer surface, it can be confirmed that the optical inspection defects on the epitaxial wafer surface are caused by the optical inspection defects at the corresponding locations on the substrate wafer surface, rather than by the epitaxial process equipment. This indicates that the epitaxial process equipment meets the required standards. In this case, step S803 is executed: no adjustments to the epitaxial process equipment are required.

[0093] If there is no optical detection defect on the epitaxial wafer surface at the corresponding position of the optical detection defect on the substrate wafer surface, then it means that this part of the optical detection defect on the epitaxial wafer surface is not caused by the optical detection defect at the corresponding position on the substrate wafer surface, but is caused by the epitaxial process equipment during the epitaxial process. Therefore, the epitaxial process equipment needs to be adjusted.

[0094] Based on this, in the present disclosure, when there is no optical detection defect on the surface of the substrate wafer at a position corresponding to the optical detection defect on the surface of the epitaxial wafer, step S805 is performed: cleaning the epitaxial wafer.

[0095] Regarding step S805, it should be noted that cleaning the epitaxial wafer removes impurity particles adhering to the surface. A large portion of these impurity particles adhere to the epitaxial wafer surface during the process from removal from the epitaxial process equipment to transfer to optical inspection. Cleaning these impurity particles prevents detection of these impurity particles during subsequent inspections, improving inspection efficiency.

[0096] S806: Obtaining surface defects of the epitaxial wafer based on optically inspecting defects on the surface of the cleaned epitaxial wafer.

[0097] Specifically, by cleaning the impurity particles attached to the surface of the epitaxial wafer and then combining the optical detection defects of the substrate wafer surface in the aforementioned step, it is possible to screen out the surface defects caused by the epitaxial process equipment from the optical detection defects on the surface of the epitaxial wafer, that is, the surface defects of the epitaxial wafer described in step S806. In response to these surface defects of the epitaxial wafer, the contact components in the epitaxial process equipment can be adjusted through the process of steps S807 to S809 to reduce the number of these defects and improve the quality of the epitaxial wafer. In some examples, the wafer map of the particle precision alignment of the cleaned epitaxial wafer can be superimposed to identify the surface defects of the above-mentioned epitaxial wafer.

[0098] S807: Matching the position of the surface defect of the epitaxial wafer with the contact position of the contact component in the epitaxial process equipment to obtain a first surface defect that matches the contact position of the contact component.

[0099] S808: Obtain the morphology and type of the first surface defect.

[0100] S809: Determine, based on the morphology and type of the first surface defects and the thickness of the epitaxial layer of the epitaxial wafer, a means of improving the contact component to reduce the number of the first surface defects.

[0101] It should be noted that the process shown in steps S807 to S809 is the same as the above Figure 3 The method flow for improving the quality of epitaxial wafers is consistent with that shown in FIG. Figure 3 The corresponding implementation details of the method flow for improving epitaxial wafer quality are not described in detail in this disclosure.

[0102] for Figure 8 In some examples of the technical solution shown, after the adjustment of the contact component is completed by the improvement means, for example, after the adjustment of the telescopic size and layout angle of the contact component, the epitaxial process can be continued on the subsequent substrate wafer based on the adjusted telescopic size and layout angle. After the subsequent epitaxial wafer is obtained, according to the above Figure 8The technical solution shown continues to adjust the telescopic size and layout angle of the contact component, and performs an epitaxial process on the substrate wafer according to the telescopic size and layout angle obtained by the continued adjustment. In this way, the number and size of the first surface defects are reduced to the set index requirements through iterative adjustment.

[0103] Based on the same inventive concept as the above technical solution, see Figure 9 , which shows a device 90 for improving the quality of epitaxial wafers provided by the present disclosure, the device 90 includes: a matching unit 901, an acquisition unit 902 and a determination unit 903; wherein,

[0104] The matching unit 901 is configured to match the position of the surface defect of the epitaxial wafer with the contact position of the contact component in the epitaxial process equipment to obtain a first surface defect that matches the contact position of the contact component;

[0105] The acquiring unit 902 is configured to acquire the morphology and type of the first surface defect;

[0106] The determining unit 903 is configured to determine, based on the morphology and type of the first surface defects and the thickness of the epitaxial layer of the epitaxial wafer, a means of improving the contact component to reduce the number of the first surface defects.

[0107] In some examples, the determining unit 903 is configured to:

[0108] determining a second surface defect size of the substrate of the epitaxial wafer at a position corresponding to the first surface defect according to the morphology and type of the first surface defect and the thickness of the epitaxial layer of the epitaxial wafer;

[0109] Improvement measures for the contact component are determined according to the size of the second surface defects to reduce the number of the first surface defects.

[0110] In some examples, the contact component is a manipulator of a robot disposed in the epitaxial process equipment; accordingly, the determining unit 903 is configured to:

[0111] The telescopic size of the manipulator during clamping and the layout angle of the manipulator are determined according to the size of the second surface defect, so as to reduce the number of the first surface defects.

[0112] In some examples, the morphology and type of the first surface defect include at least:

[0113] The first surface defect is an ESF defect, and the morphology is a polycrystalline epitaxial stacking fault type;

[0114] The first surface defect is an ESF defect, and its morphology is a composite defect and stacking fault type of polysilicon growth;

[0115] The first surface defect is an ESF defect, and the morphology is a composite epitaxial stacking fault with surface fracture;

[0116] The first surface defect is an ESF defect, and its morphology is an epitaxial growth protrusion type on the crystal plane (100).

[0117] In some examples, the matching unit 901 is configured to:

[0118] Matching, at the surface edge of the epitaxial wafer, a location where surface defects are concentrated with a contact position of the contact component;

[0119] When the location where the surface defects gather matches the contact position of the contact component, the defect at the location where the surface defects gather is determined as the first surface defect.

[0120] In some examples, the acquiring unit 902 is configured to:

[0121] The morphology and type of the first surface defect detected by a scanning electron microscope are obtained.

[0122] For some examples, see Figure 10 The device 90 further includes a pre-processing unit 904 configured to:

[0123] Inspecting the epitaxial wafer by optical inspection means to obtain the size and number of optical inspection defects on the surface of the epitaxial wafer;

[0124] When the size of the optical detection defect on the surface of the epitaxial wafer is greater than or equal to a size threshold, and the number of the optical detection defects on the surface of the epitaxial wafer is greater than or equal to a number threshold, determining whether there is an optical detection defect on the surface of the substrate wafer of the epitaxial wafer at a position corresponding to the optical detection defect on the surface of the epitaxial wafer;

[0125] When there is no optical detection defect on the surface of the epitaxial wafer at a position corresponding to the optical detection defect on the surface of the epitaxial wafer, cleaning the epitaxial wafer;

[0126] Surface defects of the epitaxial wafer are obtained based on optically inspecting defects on the surface of the cleaned epitaxial wafer.

[0127] Please refer to Figure 11, which shows a structural block diagram of an apparatus 90 for improving the quality of epitaxial wafers provided by an exemplary embodiment of the present disclosure. In some examples, the aforementioned apparatus 90 for improving the quality of epitaxial wafers can be implemented as a computing device 110, which is at least one of a smart phone, a smart watch, a desktop computer, a laptop computer, a virtual reality terminal, an augmented reality terminal, a wireless terminal, and a laptop portable computer. The computing device 110 has a communication function and can access a wired network or a wireless network. The computing device 110 can generally refer to one of a plurality of terminals, and those skilled in the art will appreciate that the number of the above-mentioned terminals can be more or less. In some examples, the computing device 110 can receive data based on the wired network or wireless network to which it is connected. It can be understood that the computing device 110 undertakes the calculation and processing work of the technical solution of the present disclosure, and the present disclosure does not limit this.

[0128] like Figure 11 As shown, the computing device in the present disclosure may include one or more of the following components: a processor 1110 and a memory 1120 .

[0129] Optionally, processor 1110 utilizes various interfaces and circuits to connect various components within the computing device. It executes instructions, programs, code sets, or instruction sets stored in memory 1120, as well as accesses data stored in memory 1120, to perform various functions of the computing device and process data. Optionally, processor 1110 can be implemented in at least one hardware form: a digital signal processing (DSP), a field-programmable gate array (FPGA), or a programmable logic array (PLA). Processor 1110 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), and a baseband chip. The CPU primarily processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing content displayed on the touchscreen display; the NPU is used to implement artificial intelligence (AI) functions; and the baseband chip handles wireless communications. It is understandable that the above-mentioned baseband chip may not be integrated into the processor 1110, but may be implemented by a separate chip.

[0130] Memory 1120 may include random access memory (RAM) or read-only memory (ROM). Optionally, memory 1120 includes non-transitory computer-readable storage medium. Memory 1120 may be used to store instructions, programs, code, code sets, or instruction sets. Memory 1120 may include a program storage area and a data storage area. The program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), and instructions for implementing each of the above method embodiments. The data storage area may store data created based on the use of the computing device.

[0131] In addition, those skilled in the art will understand that the structures of the computing devices shown in the above figures do not constitute limitations on the computing devices. The computing devices may include more or fewer components than shown, or may combine certain components or arrange the components differently. For example, the computing devices may also include a display screen, a camera assembly, a microphone, a speaker, a radio frequency circuit, an input unit, sensors (such as an accelerometer, an angular velocity sensor, a light sensor, etc.), an audio circuit, a WiFi module, a power supply, a Bluetooth module, and other components, which will not be described in detail here.

[0132] The present disclosure also provides a computer-readable storage medium storing at least one instruction, wherein the at least one instruction is configured to be executed by a processor to implement the method for improving the quality of epitaxial wafers as described in the above embodiments.

[0133] The present disclosure also provides a computer program product, which includes computer instructions stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computing device executes to implement the method of improving the quality of epitaxial wafers described in the above-mentioned various embodiments.

[0134] In addition, the present disclosure also provides a method for manufacturing an epitaxial wafer, the method comprising:

[0135] Determining means for improving contact components in epitaxial process equipment according to the method for improving epitaxial wafer quality as described in the above embodiments;

[0136] After adjusting the contact component according to the improvement means, an epitaxial process is performed on the polished wafer substrate.

[0137] In addition, the present disclosure also provides an epitaxial wafer, which is obtained by the aforementioned epitaxial wafer manufacturing method, and the number of defects with a size less than 200 nm on the surface of the epitaxial wafer is less than 2.

[0138] Those skilled in the art will appreciate that in one or more of the above examples, the functions described in this disclosure can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0139] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily without conflict.

[0140] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for improving the quality of epitaxial wafers, characterized in that: The method comprises: Matching the position of the surface defect of the epitaxial wafer with the contact position of a contact component in the epitaxial process equipment to obtain a first surface defect that matches the contact position of the contact component; Acquiring the morphology and type of the first surface defect; Determining, based on the morphology and type of the first surface defects and the thickness of the epitaxial layer of the epitaxial wafer, a means of improving the contact component to reduce the number of the first surface defects; the contact component is a manipulator of a robot disposed in the epitaxial process equipment; Wherein, determining the means for improving the contact component to reduce the number of the first surface defects according to the morphology and type of the first surface defects and the thickness of the epitaxial layer of the epitaxial wafer includes: determining a second surface defect size of the substrate of the epitaxial wafer at a position corresponding to the first surface defect according to the morphology and type of the first surface defect and the thickness of the epitaxial layer of the epitaxial wafer; The telescopic size of the manipulator during clamping and the layout angle of the manipulator are determined according to the size of the second surface defect, so as to reduce the number of the first surface defects.

2. The method according to claim 1, characterized in that The morphology and type of the first surface defect include at least: The first surface defect is an ESF defect, and the morphology is a polycrystalline epitaxial stacking fault type; The first surface defect is an ESF defect, and its morphology is a composite defect and stacking fault type of polysilicon growth; The first surface defect is an ESF defect, and the morphology is a composite epitaxial stacking fault with surface fracture; The first surface defect is an ESF defect, and its morphology is an epitaxial growth protrusion type on the crystal plane (100).

3. The method according to claim 1, characterized in that The step of matching the position of the surface defect of the epitaxial wafer with the contact position of a contact component in the epitaxial process equipment to obtain a first surface defect that matches the contact position of the contact component includes: Matching, at the surface edge of the epitaxial wafer, a location where surface defects are concentrated with a contact position of the contact component; When the location where the surface defects gather matches the contact position of the contact component, the defect at the location where the surface defects gather is determined as the first surface defect.

4. The method according to claim 1, wherein Before matching the position of the surface defect of the epitaxial wafer with the contact position of the contact component in the epitaxial process equipment, the method further includes: Inspecting the epitaxial wafer by optical inspection means to obtain the size and number of optical inspection defects on the surface of the epitaxial wafer; When the size of the optical detection defect on the surface of the epitaxial wafer is greater than or equal to a size threshold, and the number of the optical detection defects on the surface of the epitaxial wafer is greater than or equal to a number threshold, determining whether there is an optical detection defect on the surface of the substrate wafer of the epitaxial wafer at a position corresponding to the optical detection defect on the surface of the epitaxial wafer; When there is no optical detection defect on the surface of the epitaxial wafer at a position corresponding to the optical detection defect on the surface of the epitaxial wafer, cleaning the epitaxial wafer; Surface defects of the epitaxial wafer are obtained based on optically inspecting defects on the surface of the cleaned epitaxial wafer.

5. A device for improving the quality of epitaxial wafers, characterized in that: The device includes: a matching unit, an acquisition unit and a determination unit; wherein, The matching unit is configured to match the position of the surface defect of the epitaxial wafer with the contact position of the contact component in the epitaxial process equipment to obtain a first surface defect that matches the contact position of the contact component; The acquiring unit is configured to acquire the morphology and type of the first surface defect; The determining unit is configured to determine, based on the morphology and type of the first surface defect and the thickness of the epitaxial layer of the epitaxial wafer, an improvement method for the contact component to reduce the number of the first surface defects; the contact component is a manipulator of a robot disposed in the epitaxial process equipment; The determining unit is configured to: determining a second surface defect size of the substrate of the epitaxial wafer at a position corresponding to the first surface defect according to the morphology and type of the first surface defect and the thickness of the epitaxial layer of the epitaxial wafer; The telescopic size of the manipulator during clamping and the layout angle of the manipulator are determined according to the size of the second surface defect, so as to reduce the number of the first surface defects.

6. A device for improving the quality of epitaxial wafers, characterized in that: The device includes: a processor and a memory; the processor is used to execute instructions stored in the memory to implement the method for improving epitaxial wafer quality according to any one of claims 1 to 4.

7. A method for manufacturing an epitaxial wafer, characterized in that: The manufacturing method comprises: Determining means for improving contact components in the epitaxial process equipment according to the method for improving epitaxial wafer quality according to any one of claims 1 to 4; After adjusting the contact component according to the improvement means, an epitaxial process is performed on the polished wafer substrate.

8. An epitaxial wafer, characterized in that: The epitaxial wafer is obtained by the method for manufacturing an epitaxial wafer according to claim 7, and the number of defects with a size smaller than 200 nm on the surface of the epitaxial wafer is less than 2.

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