A high aspect ratio silicon carbide pn junction structure and preparation method thereof
By performing two ICP etching and epitaxial backfilling on a silicon carbide substrate, a high-aspect-ratio silicon carbide pn junction structure is prepared, which solves the problems of limited energy and depth in the existing technology and achieves high-aspect-ratio pn junction shape control and excellent device performance.
Patent Information
- Application Number
- CN202411619336.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-13
- Publication Date
- 2025-09-30
- Estimated Expiration
- 2044-11-13
AI Technical Summary
Existing technologies make it difficult to prepare pn junctions with high aspect ratios in silicon carbide. Ion implantation methods have problems with limited energy and depth, and etching is difficult, with poor verticality of the sidewall morphology, making it difficult to achieve high aspect ratio etching.
A method of two ICP etchings and two epitaxial backfillings is used to prepare a high aspect ratio silicon carbide pn junction structure by controlling the etching line width. The method includes forming a patterned mask layer on a silicon carbide substrate, etching to form deep trenches and backfilling the epitaxial layer, and then thinning to form a pn junction.
A high aspect ratio silicon carbide pn junction structure was achieved, which solved the problem of limited ion implantation energy and depth, controlled the junction shape and area, and improved the feasibility of device design and the consistency between simulation and actual performance.
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Figure CN119673762B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a silicon carbide pn junction structure with a high aspect ratio and a preparation method thereof. Background Art
[0002] When preparing common power devices, silicon carbide (SiC) is often prepared by ion implantation to form a pn junction. However, due to the lattice characteristics of silicon carbide, silicon carbide is difficult to thermally diffuse, so a high energy is required during implantation. Therefore, many crystal defects will be generated when silicon carbide is implanted at high concentrations, and these defects cannot be eliminated even by high-temperature annealing. At the same time, because the activation range of silicon carbide is between 1600 and 1800°C, Si shedding will occur, further causing surface roughness. In summary, although ion implantation is relatively simple, its depth is limited when preparing silicon carbide pn junctions.
[0003] However, if deep etching with small line width is directly used, deep etching of silicon carbide is currently difficult, the etching rate decreases rapidly with increasing depth, and the verticality of the sidewall morphology is poor, and the electrical properties of the trench bottom morphology are poor. Therefore, it is difficult to achieve high aspect ratio etching of silicon carbide, and further epitaxial production of pn junctions is impossible. Summary of the Invention
[0004] In order to solve the above problems existing in the prior art, the present invention provides a high aspect ratio silicon carbide pn junction structure and a method for preparing the same. The technical problem to be solved by the present invention is achieved through the following technical solutions:
[0005] The present invention provides a method for preparing a silicon carbide pn junction structure with a high aspect ratio, comprising:
[0006] S1: selecting a silicon carbide substrate and forming a patterned first mask layer on the upper surface of the silicon carbide substrate;
[0007] S2: etching a first deep trench on the upper surface of the silicon carbide substrate not covered by the first mask layer and backfilling the first deep trench and the upper surface of the silicon carbide substrate with a first silicon carbide epitaxial layer;
[0008] S3: thinning the silicon carbide substrate coated with the first silicon carbide epitaxial layer, and removing the first silicon carbide epitaxial layer and the first mask layer on the upper surface of the silicon carbide substrate;
[0009] S4: etching a second deep trench in the middle of the upper surface of the first silicon carbide epitaxial layer;
[0010] S5: backfilling a second silicon carbide epitaxial layer on the upper surface of the silicon carbide substrate and inside the second deep trench;
[0011] S6: removing the second silicon carbide epitaxial layer on the upper surface of the silicon carbide substrate to form a silicon carbide pn junction structure.
[0012] In one embodiment of the present invention, the S2 includes:
[0013] removing the remaining photoresist on the upper surface of the first mask layer, and performing plasma etching on the upper surface of the silicon carbide substrate using the first mask layer as a mask to form a first deep trench in an area of the upper surface of the silicon carbide substrate not covered by the first mask layer;
[0014] Using epitaxial equipment, a first silicon carbide epitaxial layer with a predetermined doping concentration is backfilled on the upper surface of the etched silicon carbide substrate and inside the first deep trench.
[0015] In one embodiment of the present invention, if the silicon carbide substrate is an n-type silicon carbide substrate or an n-type silicon carbide epitaxial wafer, the first silicon carbide epitaxial layer is a p-type silicon carbide material; if the silicon carbide substrate is a p-type silicon carbide substrate or a p-type silicon carbide epitaxial wafer, the first silicon carbide epitaxial layer is an n-type silicon carbide material.
[0016] In one embodiment of the present invention, the S4 includes:
[0017] Depositing a second mask layer of mask material on the upper surface of the thinned silicon carbide substrate, then coating photoresist on the mask, then coating photoresist on the second mask layer, using the photoresist as a mask, and wet-etching the second mask layer using a diluted hydrofluoric acid solution until a portion of the upper surface of the first silicon carbide epitaxial layer is exposed, thereby forming a patterned second mask layer on the upper surface of the silicon carbide substrate;
[0018] The photoresist on the upper surface of the second mask layer is removed, and plasma etching is performed using the patterned second mask layer as a mask to form a second deep trench in an uncovered area of the upper surface of the first silicon carbide epitaxial layer.
[0019] In one embodiment of the present invention, the width of the second deep trench is smaller than the width of the first silicon carbide epitaxial layer, and the depth of the second deep trench is greater than the width of the first silicon carbide epitaxial layer.
[0020] In one embodiment of the present invention, the material of the first mask layer and the second mask layer is silicon dioxide or silicon nitride.
[0021] In one embodiment of the present invention, if the silicon carbide substrate is an n-type silicon carbide substrate or an n-type silicon carbide epitaxial wafer, the second silicon carbide epitaxial layer is an n-type silicon carbide material or a non-silicon carbide heterogeneous material; if the silicon carbide substrate is a p-type silicon carbide substrate or a p-type silicon carbide epitaxial wafer, the second silicon carbide epitaxial layer is a p-type silicon carbide material or a non-silicon carbide heterogeneous material.
[0022] In one embodiment of the present invention, the second silicon carbide epitaxial layer and the silicon carbide substrate have the same doping concentration.
[0023] Another aspect of the present invention provides a silicon carbide pn junction structure with a high aspect ratio, which is prepared using the preparation method described in any one of the above embodiments.
[0024] Compared with the prior art, the present invention has the following beneficial effects:
[0025] 1. The present invention provides a method for preparing a silicon carbide pn junction structure with a high aspect ratio, comprising two ICP etchings with a relatively large line width and two epitaxial backfillings. By controlling the line widths of the two etchings, the aspect ratio of the final pn junction can be controlled, thereby obtaining a silicon carbide pn junction structure with a high aspect ratio. The prepared device has excellent functions and solves the problems of limited ion implantation energy, limited implantation depth, and shallow junction depth in the preparation of silicon carbide pn junctions by ion implantation.
[0026] 2. Compared with the ion implantation method, the preparation method of the present invention can better control the junction shape and junction area. Since the etching morphology is controllable, the pn junction morphology produced after backfilling is controllable, which provides more feasibility for device design and plays a guiding role in the consistency of simulation and actual device performance.
[0027] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 This is a flow chart of a method for preparing a high aspect ratio silicon carbide pn junction structure provided by an embodiment of the present invention;
[0029] Figures 2a to 2h This is a schematic diagram of a preparation process of a high aspect ratio silicon carbide pn junction structure provided by an embodiment of the present invention.
[0030] Description of reference numerals:
[0031] 1-silicon carbide substrate; 2-first mask layer; 3-first silicon carbide epitaxial layer; 4-second mask layer; 5-second silicon carbide epitaxial layer; 6-first deep trench; 7-second deep trench. DETAILED DESCRIPTION
[0032] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following is a detailed description of a high aspect ratio silicon carbide pn junction structure and a preparation method thereof proposed in accordance with the present invention in conjunction with the accompanying drawings and specific embodiments.
[0033] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.
[0034] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the element.
[0035] See Figure 1 , Figure 1 This is a flow chart of a method for preparing a high aspect ratio silicon carbide pn junction structure provided by an embodiment of the present invention. The preparation method includes:
[0036] S1: Select a silicon carbide substrate 1 and form a patterned first mask layer 2 on the upper surface of the silicon carbide substrate 1 .
[0037] In this embodiment, an n-type silicon carbide substrate or an n-type silicon carbide epitaxial wafer is selected as the silicon carbide substrate 1, and the silicon carbide substrate 1 is cleaned in a standardized manner, specifically using a standard RCA wet chemical cleaning technique to obtain a silicon carbide substrate 1 with a clean surface.
[0038] A mask material is deposited on the upper surface of the cleaned silicon carbide substrate 1 to form a first mask layer, and then a photoresist is coated on the first mask layer. Then, based on a pre-set mask layer pattern, the photoresist is used as a mask and the first mask layer is wet-etched using a hydrofluoric acid dilution solution until a portion of the upper surface of the silicon carbide substrate 1 is exposed, thereby patterning the first mask layer, that is, forming a patterned first mask layer 2 on the upper surface of the silicon carbide substrate 1. Figure 2aAs shown. In this embodiment, the material of the first mask layer 2 is silicon dioxide SiO2 with a thickness of 4 μm, or silicon nitride with a thickness of 1.2 μm. The pattern of the first mask layer 2 is designed according to actual needs. In other embodiments, the first mask layer 2 can also be made of other appropriate materials, which is not limited here.
[0039] Furthermore, in other embodiments, a p-type silicon carbide substrate or a p-type silicon carbide epitaxial wafer may be selected as the silicon carbide substrate 1 .
[0040] S2 : etching to form a first deep trench 6 on the upper surface of the silicon carbide substrate 1 not covered by the first mask layer 2 and backfilling the first silicon carbide epitaxial layer 3 inside the first deep trench 6 and the upper surface of the silicon carbide substrate 1 .
[0041] Specifically, the remaining photoresist on the upper surface of the first mask layer 2 is removed, and the upper surface of the silicon carbide substrate 1 is subjected to plasma etching (ICP etching) using the patterned first mask layer 2 as a mask to form a first deep trench 6 in the uncovered area of the upper surface of the silicon carbide substrate 1. Figure 2b In this embodiment, the line width of the first deep trench 6 is 7 μm and the depth is 12 μm. In other embodiments, the line width and depth of the first deep trench can be adjusted according to actual needs and are not limited here.
[0042] Then, using epitaxial equipment, the upper surface of the etched silicon carbide substrate and the interior of the first deep trench are backfilled with a first silicon carbide epitaxial layer 3 having a certain doping concentration, such as Figure 2c shown.
[0043] It should be noted that if the silicon carbide substrate 1 is an n-type silicon carbide substrate or an n-type silicon carbide epitaxial wafer, the first silicon carbide epitaxial layer 3 is a p-type silicon carbide material; if the silicon carbide substrate 1 is a p-type silicon carbide substrate or a p-type silicon carbide epitaxial wafer, the first silicon carbide epitaxial layer 3 is an n-type silicon carbide material.
[0044] S3: thinning the silicon carbide substrate 1 coated with the first silicon carbide epitaxial layer 3 to remove the first silicon carbide epitaxial layer 3 and the first mask layer 2 on the upper surface of the silicon carbide substrate 1 .
[0045] In this embodiment, the silicon carbide substrate 1 after epitaxy in step S2 is thinned using a thinning device such as a polishing machine or a surface planarizer. The thinning is first performed using a coarse-grained grinding wheel at a speed of 3 μm / s, and then finely ground using a fine-grained grinding wheel at a speed of less than 1 μm / s to remove the first silicon carbide epitaxial layer and the first mask layer on the upper surface of the silicon carbide substrate until the upper surface of the silicon carbide substrate is exposed. Figure 2d shown.
[0046] S4 : etching to form a second deep trench 7 in the middle of the upper surface of the first silicon carbide epitaxial layer 3 .
[0047] Specifically, a mask material is deposited on the upper surface of the n-type silicon carbide after thinning in step S3 to form a second mask layer, and then a photoresist is coated on the second mask layer. Using the photoresist as a mask, the second mask layer is wet-etched using a hydrofluoric acid dilution solution until a portion of the upper surface of the first silicon carbide epitaxial layer 3 is exposed, that is, a patterned second mask layer 4 is formed on the upper surface of the silicon carbide substrate 1, as shown in FIG. Figure 2e As shown, the patterned second mask layer 4 exposes the middle portion of the upper surface of the first silicon carbide epitaxial layer 3. In this embodiment, the mask layer is made of silicon dioxide SiO2 with a thickness of approximately 4 μm, or silicon nitride with a thickness of approximately 1.2 μm. In other embodiments, the second mask layer 4 can also be made of other appropriate materials, which are not limited here.
[0048] Subsequently, the photoresist on the upper surface of the second mask layer 4 is removed, and plasma etching (ICP etching) is performed using the patterned second mask layer 4 as a mask to form a second deep trench 7 in the uncovered area on the upper surface of the first silicon carbide epitaxial layer 31, wherein the width of the second deep trench 7 is smaller than the width of the first silicon carbide epitaxial layer 3, and the depth of the second deep trench 7 is greater than the width of the first silicon carbide epitaxial layer 3, as shown in FIG. Figure 2b In this embodiment, the second deep trench has a line width of 5 μm and a depth of 14 μm.
[0049] S5: backfilling a second silicon carbide epitaxial layer on the upper surface of the silicon carbide substrate and inside the second deep trench.
[0050] Using epitaxial equipment, the upper surface of the silicon carbide substrate 1 and the interior of the second deep trench 7 are backfilled with a second silicon carbide epitaxial layer 5 having the same doping concentration as the silicon carbide substrate, as shown in FIG. Figure 2g As shown. In this embodiment, if the silicon carbide substrate 1 is an n-type silicon carbide substrate or an n-type silicon carbide epitaxial wafer, the second silicon carbide epitaxial layer 5 is an n-type silicon carbide material; if the silicon carbide substrate 1 is a p-type silicon carbide substrate or a p-type silicon carbide epitaxial wafer, the second silicon carbide epitaxial layer 5 is a p-type silicon carbide material. In other embodiments, the second silicon carbide epitaxial layer 5 can also be silicon carbide with different doping concentrations or other appropriate non-silicon carbide heterogeneous materials.
[0051] S6: removing the second silicon carbide epitaxial layer on the upper surface of the silicon carbide substrate to form the silicon carbide pn junction structure.
[0052] In this embodiment, thinning equipment such as a grinding and polishing machine, a surface planarizer, etc. is used to thin the silicon carbide substrate 1 after epitaxial growth in step S5. First, coarse grinding is performed using a coarse-grained grinding wheel at a speed of 3 μm / s, and then fine grinding is performed using a fine-grained grinding wheel at a speed of less than 1 μm / s to remove the second silicon carbide epitaxial layer 5 and the second mask layer 4 on the upper surface of the silicon carbide substrate until the upper surface of the silicon carbide substrate 1 is exposed.
[0053] Then, cleaning is performed to obtain a silicon carbide pn junction structure with a high aspect ratio, such as Figure 2h shown.
[0054] Based on the above embodiments, the present invention further provides a silicon carbide pn junction structure with a high aspect ratio.
[0055] The present invention provides a method for preparing a high-aspect-ratio silicon carbide pn junction structure, comprising two relatively wide ICP etchings and two epitaxial backfills. By controlling the line widths of the two etchings, the aspect ratio of the final pn junction can be controlled, resulting in a high-aspect-ratio silicon carbide pn junction structure. The resulting device exhibits excellent functionality and addresses the issues of limited ion implantation energy and depth, resulting in a shallow junction depth, encountered during ion implantation in the preparation of silicon carbide pn junctions. Compared to ion implantation methods, the present invention allows for better control of junction shape and area. Because the etching morphology is controllable, the pn junction morphology produced after backfilling is also controllable, providing greater feasibility for device design and guiding the consistency of simulation and actual device performance.
[0056] In the several embodiments provided herein, it should be understood that the apparatus and method disclosed herein can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the module division is merely a logical functional division. In actual implementation, other division methods may be used. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not implemented.
[0057] In addition, the functional modules in various embodiments of the present invention may be integrated into a single processing module, each module may exist physically separately, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or hardware plus software functional modules.
[0058] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.
Claims
1. A method for preparing a silicon carbide pn junction structure with a high aspect ratio, characterized in that: include: S1: selecting a silicon carbide substrate and forming a patterned first mask layer on the upper surface of the silicon carbide substrate; S2: etching a first deep trench on the upper surface of the silicon carbide substrate not covered by the first mask layer and backfilling the first deep trench and the upper surface of the silicon carbide substrate with a first silicon carbide epitaxial layer; S3: thinning the silicon carbide substrate coated with the first silicon carbide epitaxial layer, and removing the first silicon carbide epitaxial layer and the first mask layer on the upper surface of the silicon carbide substrate; S4: etching a second deep trench in the middle of the upper surface of the first silicon carbide epitaxial layer; S5: backfilling a second silicon carbide epitaxial layer on the upper surface of the silicon carbide substrate and inside the second deep trench; S6: removing the second silicon carbide epitaxial layer on the upper surface of the silicon carbide substrate to form a silicon carbide pn junction structure.
2. The method for preparing a silicon carbide pn junction structure with a high aspect ratio according to claim 1, wherein: The S2 includes: removing the remaining photoresist on the upper surface of the first mask layer, and performing plasma etching on the upper surface of the silicon carbide substrate using the first mask layer as a mask to form a first deep trench in an area of the upper surface of the silicon carbide substrate not covered by the first mask layer; Using epitaxial equipment, a first silicon carbide epitaxial layer with a predetermined doping concentration is backfilled on the upper surface of the etched silicon carbide substrate and inside the first deep trench.
3. The method for preparing a silicon carbide pn junction structure with a high aspect ratio according to claim 2, wherein: If the silicon carbide substrate is an n-type silicon carbide substrate or an n-type silicon carbide epitaxial wafer, the first silicon carbide epitaxial layer is a p-type silicon carbide material; if the silicon carbide substrate is a p-type silicon carbide substrate or a p-type silicon carbide epitaxial wafer, the first silicon carbide epitaxial layer is an n-type silicon carbide material.
4. The method for preparing a silicon carbide pn junction structure with a high aspect ratio according to claim 1, wherein: The S4 includes: Depositing a second mask layer of mask material on the upper surface of the thinned silicon carbide substrate, then coating the mask with photoresist, then coating the second mask layer with photoresist, using the photoresist as a mask, and wet-etching the second mask layer with a hydrofluoric acid dilution solution until a portion of the upper surface of the first silicon carbide epitaxial layer is exposed, thereby forming a patterned second mask layer on the upper surface of the silicon carbide substrate 1; The photoresist on the upper surface of the second mask layer is removed, and plasma etching is performed using the patterned second mask layer as a mask to form a second deep trench in an uncovered area of the upper surface of the first silicon carbide epitaxial layer.
5. The method for preparing a silicon carbide pn junction structure with a high aspect ratio according to claim 4, wherein: The width of the second deep trench is smaller than the width of the first silicon carbide epitaxial layer, and the depth of the second deep trench is greater than the width of the first silicon carbide epitaxial layer.
6. The method for preparing a silicon carbide pn junction structure with a high aspect ratio according to claim 4, wherein: The material of the first mask layer and the second mask layer is silicon dioxide or silicon nitride.
7. The method for preparing a silicon carbide pn junction structure with a high aspect ratio according to claim 1, wherein: If the silicon carbide substrate is an n-type silicon carbide substrate or an n-type silicon carbide epitaxial wafer, the second silicon carbide epitaxial layer is an n-type silicon carbide material or a non-silicon carbide heterogeneous material; if the silicon carbide substrate is a p-type silicon carbide substrate or a p-type silicon carbide epitaxial wafer, the second silicon carbide epitaxial layer is a p-type silicon carbide material or a non-silicon carbide heterogeneous material.
8. The method for preparing a silicon carbide pn junction structure with a high aspect ratio according to claim 7, wherein: The second silicon carbide epitaxial layer and the silicon carbide substrate have the same doping concentration.
9. A high aspect ratio silicon carbide pn junction structure, characterized in that: Prepared by the preparation method according to any one of claims 1 to 8.
Citation Information
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