Double-sided heat dissipation MOS structure and packaging process thereof

Abstract

The invention discloses a double-sided heat dissipation MOS structure and a packaging technology thereof, and the technology comprises the following steps: packaging a chip: enabling the back surface of the chip to face upwards, enabling the chip to be inversely installed on a bonding film, completely packaging the chip, and grinding a packaging surface until the back surface of the chip is exposed; electroplating outer pins: electroplating a plurality of bonding pads on the exposed back surface of the chip and the ground packaging surface, continuously electroplating the outer pins on the surface of each bonding pad, continuously packaging the bonding pads and the outer pins, grinding and exposing the bottom surfaces of the outer pins, and transmitting heat of the back surface of the chip from the bonding pads to the outer pins and then dissipating the heat; electroplating the front surface of the chip: stripping the adhesive film, electroplating a metal column A on the front surface of the chip, encapsulating and grinding an encapsulating surface until the top surface of the metal column A is exposed; according to the invention, MOS devices are formed on the back surface and the front surface of the chip through the processes of layer-by-layer encapsulation, grinding, electroplating and the like, so that a double-surface heat dissipation packaging structure is formed, the heat dissipation effect is good, and the heat dissipation efficiency is high.

Description

Technical Field

[0001] The invention belongs to the technical field of chip packaging, and in particular relates to a double-sided heat dissipation MOS structure and a packaging process thereof. Background Art

[0002] Metal-oxide-semiconductor chip, abbreviated as MOS chip, is a major component in an integrated circuit. It is composed of metal oxide-semiconductor field effect transistors (MOSFET, abbreviated as MOS transistors). In electronic circuits, MOS chips are usually used in amplification circuits or switching circuits. Each MOS chip is equipped with three electrode terminals: gate, source and drain. MOS chips need to be packaged and protected before being welded in the working area. Packaging can ensure the reliability and service life of the chip and prevent external factors from damaging the chip.

[0003] Existing MOS chips generate a lot of heat during operation, which needs to be dissipated, otherwise it will affect the normal operation of the chip and its internal connection structure. However, due to the large thermal resistance of the encapsulation material and the chip setting of the encapsulation structure, the chip's heat dissipation efficiency is low and the heat dissipation effect is poor. Summary of the invention

[0004] In order to solve the above problems in the prior art, the present invention provides a double-sided heat dissipation MOS structure and a packaging process thereof.

[0005] To achieve the above object, the present invention proposes a double-sided heat dissipation MOS structure packaging process, comprising the following steps: chip encapsulation: flip-mounting the chip on an adhesive film with the back side facing upward, completely encapsulating the chip, and grinding the encapsulation surface until the back side of the chip is exposed; External pin plating: electroplate multiple pads on the exposed back of the chip and the ground package surface, and continue to electroplate external pins on the surface of each pad, continue to encapsulate the pads and external pins, and grind to expose the bottom surface of the external pins. The heat on the back of the chip is transferred from the pads to the external pins and then dissipated; Chip front side electroplating: peel off the adhesive film, electroplate metal pillar A on the front side of the chip, and encapsulate and grind the encapsulation surface until the top surface of metal pillar A is exposed; Electroplating of the redistribution layer and metal pillar B: electroplating the redistribution layer on the encapsulation surface, the redistribution layer is electrically connected to the metal pillar A, and the metal pillar B is further electroplated on the redistribution layer to encapsulate the redistribution layer and the metal pillar B, and the top surface of the metal pillar B is exposed by grinding; Heat sink plating: A heat sink is plated on the top surface of the exposed metal pillar B. The heat sink is set outside the encapsulation material. The heat from the front of the chip is transferred from the metal pillar A, the redistribution layer, and the metal pillar B to the heat sink and then dissipated.

[0006] Furthermore, the chip encapsulation first applies a glue layer on the back of the chip, grinds the encapsulation surface until the glue layer on the back of the chip is exposed, and the pads connected to the chip are electroplated on the glue layer on the back of the chip.

[0007] Furthermore, while the front side of the chip is electroplated, a hole is drilled in the area corresponding to the pad of the package surface where the metal column A is exposed by grinding to expose the pad surface, and a hole column is electroplated in the hole.

[0008] Furthermore, the redistribution layer is electroplated on the surface of the package surface, and extends flatly along the package surface. The redistribution layer is electrically connected to the via column after electroplating.

[0009] Furthermore, an etching step is performed while the redistribution layer and the metal pillar B are electroplated, and a plurality of evenly distributed long holes are vertically etched on the upper surface of the redistribution layer and the metal pillar B, and the long holes are also filled with the encapsulation material during encapsulation.

[0010] A double-sided heat dissipation MOS structure, comprising a package body, wherein the package body encapsulates: Chip and external pins, multiple pads are plated in the package, some of the pads are plated on the back of the chip, and the external pins are plated on each pad. The bottom surface of the external pins is flush with the bottom surface of the package and exposed. The heat on the back of the chip is transferred from the pads to the external pins and then dissipated; Rewiring layer: electroplating metal pillar A on the front of the chip, electroplating the rewiring layer on the metal pillar A, and continuing to electroplating metal pillar B on the rewiring layer. The metal pillar B is flush with the top surface of the package and exposed; The heat sink is electroplated on the top surface of the package and connected to the metal column B by electroplating. The heat from the front of the chip is transferred from the metal column A, the redistribution layer, and the metal column B to the heat sink and then dissipated.

[0011] Furthermore, a glue layer is applied to the back of the chip, and a solder pad connected to the chip is electroplated on the glue layer on the back of the chip.

[0012] Furthermore, the redistribution layer is flatly plated and extended in the package body, and a via is plated in the package body, the upper end of the via is electrically connected to the redistribution layer, and the lower end of the via is electrically connected to another portion of the plated pad.

[0013] Furthermore, the package is formed by encapsulating, grinding and electroplating on both sides of the chip.

[0014] Furthermore, a plurality of evenly distributed long holes are vertically etched on the upper surfaces of the redistribution layer and the metal pillars B, and the long holes are also filled with encapsulation material during encapsulation.

[0015] The present invention: 1. The MOS device is formed through layer-by-layer encapsulation, grinding and electroplating processes on the back and front of the chip to form a double-sided heat dissipation packaging structure, which has good heat dissipation effect and high heat dissipation efficiency. The packaging process is simple and efficient, and the electroplating thickness and size of the heat sink can be flexibly adjusted; 2. The internal structure of the package is stable. Multiple evenly distributed long holes are vertically etched on the redistribution layer and the upper surface of the metal column B to increase the contact area with the encapsulation material, prevent peeling and cracking between the metal material and the encapsulation material, and ensure the performance and life of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1-Figure 2 A cross-sectional view of a chip encapsulation step of a double-sided heat dissipation MOS structure packaging process of the present invention; Figure 3-Figure 6 A cross-sectional view of an outer pin electroplating step of a double-sided heat dissipation MOS structure packaging process of the present invention; Figure 7-Figure 9 It is a cross-sectional view of a chip front electroplating step in a double-sided heat dissipation MOS structure packaging process of the present invention; Figure 10-Figure 14 It is a cross-sectional view of the electroplating of the redistribution layer and the metal pillar B in a double-sided heat dissipation MOS structure packaging process of the present invention; Fig.15 A cross-sectional view of a heat sink electroplating step in a double-sided heat dissipation MOS structure packaging process of the present invention; Fig.16 A product cross-sectional view of a double-sided heat dissipation MOS structure of the present invention; Fig.17 It is an internal perspective view of a double-sided heat dissipation MOS structure of the present invention.

[0017] In the figure: 1. Package; 2. Chip; 3. Rewiring layer; 4. Pad; 5. External pin; 6. Metal column A; 7. Metal column B; 8. Heat sink. DETAILED DESCRIPTION

[0018] The content of the present invention will be explained below in conjunction with specific embodiments, examples of which are shown in the accompanying drawings, wherein the same or similar numbers throughout represent the same or similar components or components with the same or similar functions.

[0019] The directional terms mentioned in the present invention, such as: up, down, left, right, front, back, inside, outside, front, back, side, etc., are only reference directions of the drawings. The embodiments described below with reference to the drawings and the directional terms used are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention. In addition, the various specific process and material examples provided in the present invention are all those skilled in the art who can recognize the application of other processes and / or the use of other materials.

[0020] In order to better understand the purpose, structure and function of the present invention, the following is a further detailed description of a double-sided heat dissipation MOS structure and its packaging process proposed by the present invention in conjunction with the accompanying drawings. The process includes the following steps: Chip 2 encapsulation: Chip 2 is flipped on the adhesive film with the back side facing upwards, the chip 2 is completely encapsulated, and the encapsulation surface is grinded until the back side of the chip 2 is exposed; External pin 5 electroplating: electroplating multiple pads 4 on the exposed back side of the chip 2 and the ground package surface, and continuing to electroplating external pins 5 on the surface of each pad 4, continuing to encapsulate the pads 4 and the external pins 5, and grinding to expose the bottom surface of the external pins 5, the heat on the back side of the chip 2 is transferred from the pads 4 to the external pins 5 and then dissipated; Electroplating on the front side of chip 2: peel off the adhesive film, electroplate the metal pillar A6 on the front side of chip 2, and encapsulate and grind the encapsulation surface until the top surface of the metal pillar A6 is exposed; Electroplating of the redistribution layer 3 and the metal pillar B7: electroplating the redistribution layer 3 on the encapsulation surface, the redistribution layer 3 is electrically connected to the metal pillar A6, and the metal pillar B7 is further electroplated on the redistribution layer 3 to encapsulate the redistribution layer 3 and the metal pillar B7, and the top surface of the metal pillar B7 is exposed by grinding; Heat sink 8 electroplating: Heat sink 8 is electroplated on the top surface of the exposed metal column B7. Heat sink 8 is arranged outside the encapsulation material. The heat from the front side of chip 2 is transferred from metal column A, redistribution layer 3 and metal column B7 to heat sink 8 and then dissipated.

[0021] Among them, Figure 1-Figure 2As shown, in the chip 2 encapsulation step, a layer of glue is first applied to the back of the chip 2, and then an adhesive film is provided, and the chip 2 is flipped on the adhesive film with the back facing upward, that is, the front of the chip 2 is in contact with the adhesive film. The adhesive film is a common film material commonly used in this field, such as an adhesive film of polyimide material, which firmly bonds and fixes the chip 2. According to the size of the adhesive film, multiple chips 2 can be evenly placed. In the actual process, it is further necessary to bond and fix the adhesive film on a resin substrate, and the resin substrate provides a supporting function. This application takes placing a chip 2 on the adhesive film as an example. After chip 2 is placed, it is encapsulated for the first time to completely encapsulate chip 2. After the encapsulation material is solidified, the top surface of the encapsulation is mechanically polished to horizontally grind the encapsulation surface until the glue layer on the back of chip 2 is exposed. The glue layer on the back of chip 2 plays a protective role when the back of chip 2 is exposed by grinding, preventing the back of chip 2 from being damaged due to improper grinding. For MOS, the back of chip 2 here refers to the side with a source (Source), and a gate (Gate) is also provided on the source side of this side. The front of chip 2 refers to the side with a drain (Drain).

[0022] Among them, Figure 3-Figure 6 As shown, in the electroplating step of the external pin 5, the external pin 5 is an intermediate body for welding the package body 1 after encapsulation of the chip 2 to the working area and realizing electrical connection with the circuit of the working area. After the encapsulation and grinding of the adhesive layer on the back of the chip 2 is exposed, the encapsulation surface becomes horizontal and flat due to horizontal mechanical grinding. A plurality of pads 4 with the same height are electroplated at corresponding positions on this encapsulation surface through the electroplating process. The pad 4 includes a portion electroplated on the adhesive layer on the back of the chip 2, that is, the pads 4 corresponding to the source electrode terminal on the back of the chip 2 and the gate electrode terminal on the back of the chip 2, and also includes a portion on the encapsulation surface. After the electroplating of the pad 4 is completed, the encapsulation process is continued on the encapsulation surface. Encapsulation, the pad 4 is completely encapsulated, and then mechanically grinds at the new encapsulation surface level until the surface of the pad 4 is exposed, and the external pin 5 is electroplated on the exposed surface of each pad 4. The plated external pin 5 has the same height. After electroplating, the encapsulation and grinding are continued to expose the surface of the external pin 5, that is, the surface of the external pin 5 is flush with the grinding surface of the encapsulation material and exposed; for MOS products with source end heat dissipation, the packaging process can electroplate the pad 4 and the external pin 5 at the source end respectively, and the heat at the source end of the chip 2 is transferred from the pad 4 to the external pin 5 and then dissipated to the outside of the package body 1, and the electroplating process can reasonably select the electroplating area according to the size of the source end to ensure sufficient heat dissipation area.

[0023] Among them, Figure 7-Figure 9As shown, in the electroplating step on the front side of the chip 2, after the back side of the chip 2 is encapsulated, ground and electroplated layer by layer, the chip 2 is peeled off from the adhesive film and turned over so that the external pin 5 is firmly bonded to the adhesive film, the front side of the chip 2 faces upward, and the metal column A6 is electroplated on the front side of the chip 2, that is, the metal column A6 is electroplated at the gate end of the chip 2, and the metal column A6 is encapsulated and mechanically ground horizontally on the encapsulation surface to expose the top surface of the metal column A6, and a hole is drilled on the encapsulation surface where the metal column A6 is exposed by grinding, and the encapsulation material corresponding to the part of the pad 4 electroplated on the encapsulation surface where the back side adhesive layer of the chip 2 is exposed by grinding in the electroplating step of the external pin 5 is removed, the upper surface of the pad 4 is exposed in the hole, and a hole column (not marked in the figure) connected to the pad 4 is electroplated in the hole, and the top surface of the hole column is flush with the encapsulation surface where the metal column A6 is exposed by grinding.

[0024] Among them, Figure 10-Figure 14 As shown, during the electroplating of the redistribution layer 3 and the metal pillar B7, the redistribution layer 3 is electroplated on the exposed metal pillar A6, the redistribution layer 3 is electroplated on the surface of the package surface that is polished to expose the top surface of the metal pillar A6, and is flatly extended along the package surface. After electroplating, the redistribution layer 3 is electrically connected to the hole pillar, and the metal pillar B7 is electroplated on the redistribution layer 3; the electroplated metal pillars A6 and metal pillars B7 have the same structural dimensions and are symmetrical about the redistribution layer 3. The metal pillars A6 and metal pillars B7 can be flatly spread over the front side of the chip 2 and the redistribution layer 3, respectively, or can be partially covered with the front side of the chip 2 and the redistribution layer 3, respectively. The parts are in contact with each other so that the stresses on the redistribution layer 3 offset each other and ensure structural stability. This application takes the metal pillars A6 and B7 laid flat on the front of the chip 2 and the redistribution layer 3 as an example, and continues to encapsulate the redistribution layer 3 and the metal pillar B7 completely, and mechanically grinds the encapsulation material horizontally on the encapsulation surface until the top surface of the metal pillar B7 is exposed; the electroplating step of the redistribution layer 3 and the metal pillar B7 also includes an etching step, and a plurality of evenly distributed long holes (not marked in the figure) are vertically etched on the upper surface of the redistribution layer 3 and the metal pillar B7, and the long holes are also filled with the encapsulation material during encapsulation.

[0025] The electrode terminal on the front of chip 2 is the main source of heat inside the device when it is working. At the same time, due to the different thermal expansion coefficients of the encapsulation material and the redistribution layer 3 and metal pillar B7 of the metal material, the temperature gradient and temperature change rate caused by temperature changes during the packaging process and the operation of chip 2 lead to stress between the redistribution layer 3 on the front of chip 2 and the metal pillar B7 and the encapsulation material. Stress refers to the internal force generated by the interaction between the various parts of the material when the material is deformed due to external factors such as temperature changes, in order to resist such external factors and try to restore the material itself from the position after deformation to the position before deformation. The internal force per unit area is called stress, and this stress can be It may cause peeling and cracking between the metal material and the encapsulation material, thus affecting the performance and life of the device. A plurality of evenly distributed long holes are vertically etched on the upper surface of the redistribution layer 3 and the metal column B7. On the one hand, the total amount of metal material is reduced, thereby reducing stress. On the other hand, while encapsulating the redistribution layer 3 and the metal column B7, the long holes are also filled with the encapsulation material. The long holes increase the total surface area of ​​the redistribution layer 3 and the metal column B7, and increase the contact area between the redistribution layer 3 and the metal column B7 and the encapsulation material, thereby preventing faults at the connection between the two different materials, and preventing peeling and cracking between the metal material and the encapsulation material, thereby ensuring the performance and life of the device.

[0026] Among them, Fig.15 As shown, in the step of electroplating the heat sink 8, the heat sink 8 is electroplated on the above-mentioned ground package surface, the heat sink 8 is electrically connected to the exposed top surface of the metal column B7, and the heat sink 8 is arranged outside the package body 1; the heat from the front side of the chip 2 is transferred from the metal column A6, the redistribution layer 3, and the metal column B7 to the heat sink 8 and then dissipated, and the MOS device constitutes a double-sided heat dissipation packaging structure with good heat dissipation effect and high heat dissipation efficiency. The double-sided heat dissipation structure is formed on the back and front sides of the chip 2 through layer-by-layer encapsulation, grinding and electroplating processes. The packaging process is simple and efficient, and the electroplating thickness and size of the heat sink 8 can be flexibly adjusted to reduce stress.

[0027] This application takes encapsulating one chip at a time as an example. In actual production, in order to improve production capacity, multiple chips 2 are evenly arranged and encapsulated at one time, and electroplating, grinding and encapsulation are performed simultaneously until the entire process is completed. When multiple chips 2 are encapsulated at the same time, a cutting step is required at the end to peel off the entire encapsulation body from the adhesive film and separate it into product units containing a single chip 2, namely, the package body 1, by cutting along the cutting path.

[0028] A double-sided heat dissipation MOS structure can be obtained by the above-mentioned double-sided heat dissipation MOS structure packaging process, such as Fig.16 and Fig.17 As shown, the structure includes a package body 1, and the package body 1 encapsulates: Chip 2 and external pins 5, multiple pads 4 are electroplated in package 1, some pads 4 are electroplated on the back of chip 2, and external pins 5 are electroplated on each pad 4, the bottom surface of external pins 5 is flush with the bottom surface of package 1 and exposed, and the heat on the back of chip 2 is transferred from pads to external pins 5 and then dissipated; Rewiring layer 3, electroplating metal pillar A6 on the front surface of chip 1, electroplating redistribution layer 3 on metal pillar A6, and continuing to electroplating metal pillar B7 on redistribution layer 3, metal pillar B7 is flush with the top surface of package body 1 and exposed; Heat sink 8 is electroplated on the top surface of package body 1 and connected with metal pillar B7 by electroplating. Heat from the front of chip 2 is transferred from metal pillar A6, redistribution layer 3 and metal pillar B7 to heat sink 8 and then dissipated.

[0029] A glue layer is applied on the back of the chip 2, and the pad 4 connected to the chip 2 is electroplated on the glue layer on the back of the chip 2. The redistribution layer 3 is flatly plated and extended in the package 1. A hole column is plated in the package 1, and the upper end of the hole column is electrically connected to the redistribution layer 3, and the lower end of the hole column is electrically connected to another part of the plated pad 4. The package 1 is formed by layer-by-layer encapsulation, grinding and electroplating processes on both sides of the chip 2. A plurality of evenly distributed long holes are vertically etched on the upper surface of the redistribution layer 3 and the metal column B7, and the long holes are also filled with encapsulation material during encapsulation.

[0030] The encapsulation material used in the present invention is a plastic encapsulation material, and the specific material may be epoxy resin, cyanate, polyimide, etc., which has low cost and good curing performance. The encapsulation process plays an important role in the field of semiconductor manufacturing, mainly in terms of protection, connection, support, reliability and promotion of technological progress. The protection function refers to the ability to protect the internal structure from mechanical damage, moisture, dust and other external environmental factors, ensuring the normal operation of the device in extreme environments; the connection function refers to the fact that the package provides a way to connect the device with other electronic components, so that the device can be installed and used on the circuit board; the support function refers to the fact that the encapsulation material can fix the device while supporting the device to prevent it from being damaged; reliability refers to the increasingly high reliability requirements for packaging materials and processes to ensure that the device can operate normally in various extreme environments.

[0031] All the steps of the electroplating process of the present invention are to first form electroplating protection on the surface through exposure and development photolithography technology, and then form a metal seed layer in the area to be electroplated by sputtering or copper deposition or other appropriate methods. The metal seed layer is made of copper or other metal materials. The metal seed layer is to ensure the bonding force between the subsequent electroplated metal and the encapsulation material, and at the same time provide a surface for the electroplating to attach conductive ions to ensure the electroplating effect. The entire steps in the electroplating process and the materials used are also technical common sense in this field.

[0032] The present invention forms a packaging structure with double-sided heat dissipation by forming MOS devices on the back and front sides of the chip 2 through layer-by-layer encapsulation, grinding and electroplating processes. The heat dissipation effect is good, the heat dissipation efficiency is high, the packaging process is simple and efficient, the electroplating thickness and size of the heat sink can be flexibly adjusted, the heat on the back side of the chip 2 is transferred from the pad 4 to the external pin 5 and then dissipated to the outside of the package body 1, and the heat on the front side of the chip 2 is transferred from the metal column A6, the redistribution layer 3, and the metal column B7 to the heat sink 8 and then dissipated; the internal structure of the package body 1 is stable, and a plurality of evenly distributed long holes are vertically etched on the upper surfaces of the redistribution layer 3 and the metal column B7 to increase the contact area between the redistribution layer 3 and the metal column B7 and the encapsulation material, thereby preventing peeling, cracking, etc. between the metal material and the encapsulation material, and ensuring the performance and life of the device.

[0033] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present invention are within the scope of protection of the present invention.

Claims

1. A double-sided heat dissipation MOS structure packaging process, characterized in that: The following steps are involved: Chip encapsulation: Place the chip on the adhesive film with the back side facing up, completely encapsulate the chip, and grind the encapsulation surface until the back side of the chip is exposed; External pin plating: electroplate multiple pads on the exposed back of the chip and the ground package surface, and continue to electroplate external pins on the surface of each pad, continue to encapsulate the pads and external pins, and grind to expose the bottom surface of the external pins. The heat on the back of the chip is transferred from the pads to the external pins and then dissipated; Chip front side electroplating: peel off the adhesive film, electroplate metal pillar A on the front side of the chip, and encapsulate and grind the encapsulation surface until the top surface of metal pillar A is exposed; Electroplating of the redistribution layer and metal pillar B: electroplating the redistribution layer on the encapsulation surface, the redistribution layer is electrically connected to the metal pillar A, and the metal pillar B is further electroplated on the redistribution layer to encapsulate the redistribution layer and the metal pillar B, and the top surface of the metal pillar B is exposed by grinding; Heat sink plating: A heat sink is plated on the top surface of the exposed metal pillar B. The heat sink is set outside the encapsulation material. The heat from the front of the chip is transferred from the metal pillar A, the redistribution layer, and the metal pillar B to the heat sink and then dissipated.

2. The double-sided heat dissipation MOS structure packaging process according to claim 1 is characterized in that: The chip encapsulation first applies a glue layer on the back of the chip, grinds the encapsulation surface until the glue layer on the back of the chip is exposed, and electroplates the pads connected to the chip on the glue layer on the back of the chip.

3. The double-sided heat dissipation MOS structure packaging process according to claim 1 is characterized in that: While the front side of the chip is electroplated, a hole is drilled in the area corresponding to the pad of the package surface where the metal column A is exposed by grinding to expose the pad surface, and a hole column is electroplated in the hole.

4. The double-sided heat dissipation MOS structure packaging process according to claim 1 is characterized in that: The redistribution layer is electroplated on the surface of the package surface, and extends flatly along the package surface. The redistribution layer is electrically connected to the hole column after electroplating.

5. The double-sided heat dissipation MOS structure packaging process according to claim 1 is characterized in that: While the redistribution layer and the metal pillars B are being electroplated, an etching step is also performed. A plurality of evenly distributed long holes are vertically etched on the upper surfaces of the redistribution layer and the metal pillars B. During encapsulation, the long holes are also filled with encapsulation material.

6. A double-sided heat dissipation MOS structure, comprising a package, characterized in that: The package contains: Chip and external pins, multiple pads are plated in the package, some of the pads are plated on the back of the chip, and the external pins are plated on each pad. The bottom surface of the external pins is flush with the bottom surface of the package and exposed. The heat on the back of the chip is transferred from the pads to the external pins and then dissipated; Rewiring layer: electroplating metal pillar A on the front of the chip, electroplating the rewiring layer on the metal pillar A, and continuing to electroplating metal pillar B on the rewiring layer. The metal pillar B is flush with the top surface of the package and exposed; The heat sink is electroplated on the top surface of the package and connected to the metal column B by electroplating. The heat from the front of the chip is transferred from the metal column A, the redistribution layer, and the metal column B to the heat sink and then dissipated.

7. The double-sided heat dissipation MOS structure according to claim 6, characterized in that: The back of the chip is coated with a glue layer, and the pads connected to the chip are electroplated and arranged on the glue layer on the back of the chip.

8. The double-sided heat dissipation MOS structure according to claim 6, characterized in that: The redistribution layer is flatly plated and extended in the package body, and a hole column is plated in the package body, the upper end of the hole column is electrically connected to the redistribution layer, and the lower end of the hole column is electrically connected to another part of the plated pad.

9. The double-sided heat dissipation MOS structure according to claim 8, characterized in that: The package is formed by encapsulating, grinding and electroplating on both sides of the chip.

10. The double-sided heat dissipation MOS structure according to claim 6, characterized in that: A plurality of evenly distributed long holes are vertically etched on the upper surfaces of the redistribution layer and the metal pillars B, and the long holes are also filled with encapsulation material during encapsulation.

Images