Method for manufacturing semiconductor device based on glass interposer and semiconductor device

Abstract

The present invention provides a method for manufacturing a semiconductor device based on a glass interposer and a semiconductor device. The method includes: Step S1, stacking and forming a plurality of metal pattern layers on a silicon substrate, the plurality of metal pattern layers being electrically connected to each other and having a thickness in the range of 0.05 μm to 15 μm; Step S2, bonding the side of the silicon substrate having the plurality of metal pattern layers face to face with a TGV glass sheet, the TGV glass sheet having a thickness in the range of 20 μm to 2000 μm; Step S3, removing the silicon substrate and thinning the glass layer thickness of the TGV glass sheet to 15 μm to 1900 μm. By using the present invention, it is possible to complete the manufacture of a glass interposer with high-density metal interconnection, obtain a characteristic structure of glass + silicon layer + dielectric layer, and achieve that all processes can be compatible with a silicon-based Fab, thereby completing a finer metal interconnection structure on the glass interposer.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor device manufacturing, and particularly relates to a method for manufacturing a semiconductor device based on a glass interposer and a semiconductor device. Background Art

[0002] In 2.5D CoWoS (Chip-on-Wafer-on-Substrate), the Wafer is mainly made of Si material. The Si Wafer belongs to the front-end process of the entire semiconductor and is currently widely used. Glass material is also widely regarded as a candidate material to replace silicon chips. However, at present, the processing technology of glass is not compatible with the circuit technology of silicon-based. The line width that can be finally achieved by glass-based is in the order of dozens of μm, which is too large to meet the relatively fine size requirements of the interposer. Summary of the Invention

[0003] Therefore, the present invention provides a method for manufacturing a semiconductor device based on a glass interposer. The method includes: Step S1, stacking and forming a plurality of metal pattern layers on a silicon substrate. The plurality of metal pattern layers are electrically connected to each other and have a thickness in the range of 0.05 μm to 15 μm; Step S2, bonding the side of the silicon substrate with the plurality of metal pattern layers face-to-face with a TGV glass sheet. The TGV glass sheet has a thickness in the range of 20 μm to 2000 μm; Step S3, removing the silicon substrate and thinning the glass layer thickness of the TGV glass sheet to 15 μm to 1900 μm.

[0004] In addition, preferably, in the method for manufacturing a semiconductor device of the present invention, when forming the plurality of metal pattern layers on the silicon substrate, the damascene process is adopted to form them in the order of decreasing critical dimension.

[0005] In addition, preferably, in the method for manufacturing a semiconductor device of the present invention, in the step S1, each metal pattern layer in the plurality of metal pattern layers is formed in the order of TM2, TM1, M5, M4, M3, M2, M1.

[0006] In addition, preferably, in the method for manufacturing a semiconductor device of the present invention, in the step S2, the bonding of the silicon substrate and the TGV glass sheet adopts anodic bonding or hybrid bonding method.

[0007] In addition, preferably, in the method for manufacturing a semiconductor device of the present invention, the silicon substrate is connected to the positive electrode of the power supply, the TGV glass sheet is connected to the negative electrode of the power supply, a voltage of 500V to 1000V is applied, and the heating temperature is maintained at 300°C to 500°C.

[0008] In addition, preferably, in the method for manufacturing a semiconductor device of the present invention, when a voltage is applied, Na ions in the TGV glass wafer will drift toward the negative electrode direction and form a depletion layer with a thickness of 1 μm to 10 μm on the glass surface adjacent to the silicon wafer until the current between each of the plurality of patterned circuit layers is reduced to nearly zero.

[0009] In addition, preferably, in the method for manufacturing a semiconductor device of the present invention, a silicon layer with a thickness range of 0.05 μm - 300 μm is pre-grown on the surface of the TGV glass wafer.

[0010] In addition, preferably, in the method for manufacturing a semiconductor device of the present invention, before performing the face-to-face bonding, a silicon layer is grown on the front and back surfaces of the TGV glass wafer by low-pressure chemical vapor deposition or silicon epitaxial chemical vapor deposition.

[0011] In addition, preferably, in the method for manufacturing a semiconductor device of the present invention, the electrical connection of the plurality of metal patterned layers is achieved by using a damascene copper process or a silicon-based process.

[0012] In addition, preferably, the present invention provides a semiconductor device manufactured by using the method for manufacturing a semiconductor device according to any one of the above.

[0013] By using the above process method, the present invention significantly increases the contact area between hybrid-bonded metals, thereby increasing the bonding force between metal-to-metal bonds and ultimately significantly increasing the bonding strength of the semiconductor device. Therefore, by using the present invention, it is possible to manufacture a glass interposer for high-density metal interconnection, obtain a characteristic structure of glass + silicon layer + dielectric layer, and achieve compatibility of all processes with a silicon-based Fab, thereby completing a finer metal interconnection structure on the glass interposer. Description of the Drawings

[0014] Figure 1 is a schematic diagram showing the relationship between the insertion loss and frequency of a transmission line on a glass and a standard silicon substrate according to an embodiment of the present invention.

[0015] Figure 2 is a schematic diagram showing the improved shape management effect when the glass CTE of an embodiment of the present invention is between the bottom organic material and the top silicon.

[0016] Figure 3 is a schematic diagram showing the electrical circuit Array process flow of a glass substrate according to an embodiment of the present invention.

[0017] Figure 4 is a schematic diagram showing the process flow of a glass interposer for a silicon wafer - carrier process according to an embodiment of the present invention.

[0018] Figure 5 It is a schematic diagram showing the principle of glass - silicon anodic bonding according to an embodiment of the present invention.

[0019] Figure 6 It is a schematic diagram showing the principle of glass - silicon anodic bonding according to an embodiment of the present invention.

[0020] Figure 7 It is a schematic diagram showing the process flow of glass substrate covering silicon according to an embodiment of the present invention.

[0021] Figure 8 It is a schematic diagram showing the deposition of furnace tube polysilicon according to an embodiment of the present invention.

[0022] Figure 9 It is a schematic diagram showing the silicon vapor phase epitaxy process according to an embodiment of the present invention.

[0023] Figure 10 It is a schematic diagram showing the characteristic structure of a semiconductor device according to an embodiment of the present invention. Detailed Embodiments

[0024] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Other embodiments or variant embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments in the present application all fall within the scope of protection of the present application.

[0025] In 2.5D CoWoS (Chip - on - Wafer - on - Substrate), the Wafer is mainly made of Si material. The reason is that the Si Wafer belongs to the front - end process of the entire semiconductor, with a more mature process flow, smaller line widths that can be achieved, and a higher circuit density. Therefore, it is widely used at present.

[0026] Glass material is currently also widely regarded as a candidate material to replace silicon chips. Glass has the following advantages compared to silicon:

[0027] 1. Lower electrical loss: Since glass has better insulation performance than silicon, the electrical signal loss in its high - frequency oscillation circuit is less. The relationship between signal loss and frequency is as Figure 1 shown.

[0028] 2. Adjustable CTE: The coefficient of thermal expansion of the glass can be regulated by adjusting its composition. Currently, the CTE can be adjusted within the range of 2.7 - 12.4, so it can better adapt to different organic substrates, carrier wafers and other materials. For the same reason, parameters such as TTV / warpage can also be better than those of silicon, and the shape management effect is as Figure 2 shown.

[0029] 3. Cost advantage: The cost of glass is lower than that of silicon. At the same time, its size can be made larger and its shape more diverse.

[0030] However, currently the processing technology of glass is not compatible with the silicon-based circuit process. The line width that the glass substrate can ultimately achieve is in the order of dozens of μm, which is too large to meet the relatively fine size requirements of the interposer.

[0031] Figure 3 is a schematic diagram showing the electrical circuit Array process flow of a glass substrate according to an embodiment of the present invention. The density of electrical interconnection of this solution is relatively low, and it cannot meet the requirements of high-performance interposers in terms of electrical performance.

[0032] If you want to use a glass interposer to replace a silicon interposer, you need to miniaturize the circuit size. For the commonly used silicon interposer currently, the metal interconnection above the TSV uses the copper damascene process. Therefore, we want to adopt the silicon-based damascene process and combine it with the glass TGV process to realize the production of glass interposers.

[0033] If you want to achieve the interconnection density of a silicon interposer. The prior art is to directly metallize and interconnect on the glass by imitating the silicon damascene process. The existing processes are all developed based on silicon wafers. Therefore, the entire set of process parameters is set and debugged for silicon materials. When the material is switched to glass, due to the different material properties, a large amount of Recipe debugging is involved, and the workload is huge. For example, the original lithography process determines parameters such as the mask layer, photoresist thickness, alignment, light spreading, and development according to the reflection characteristics of silicon. Now that the material is changed to glass, since the light transmittance of glass and silicon is very different, all the above parameters need to be changed accordingly. A large amount of experimental debugging work needs to be carried out to determine the final series of passing conditions.

[0034] Some aspects cannot be covered by the Recipe software and need to be achieved through hardware modification, resulting in higher costs. For example, PVD, ETCH and other machines fix the wafer by electrostatic adsorption of the ECHUCK. Due to the insulating property of the glass material, the way of gripping the wafer by the chuck needs to be changed, such as changing to vacuum adsorption and other methods.

[0035] At this time, the cooperation of multiple departments such as manufacturers, equipment engineers, process engineers, and even factory facilities is involved, and a huge amount of resources are required.

[0036] In summary, there are currently the following two main solutions:

[0037] 1. Use the common method of the original glass panel for electrical interconnection. Through the optimization of the Recipe, the line width can be reduced and the interconnection density can be increased. However, limited by the overall process flow principle, the interconnection density of this method is relatively low and cannot meet the requirements of high-performance interposer boards.

[0038] 2. On the glass material, use the damascene process for electrical interconnection. However, due to the different materials of glass and silicon, a large amount of Recipe debugging and machine hardware modification work are involved, and the workload is huge. It is not compatible with the existing silicon interposer production line and requires an additional new production line to be established.

[0039] The present invention has two process flows:

[0040] I. The process flow of the glass interposer for the silicon wafer - carrier wafer process:

[0041] (1) Use the damascene structure on a conventional silicon wafer for metal layer interconnection.

[0042] (2) Bond the completed silicon wafers face - to - face to the glass with completed TGV.

[0043] (3) Remove the silicon wafers. If necessary, continue to thin the glass interposer from the back.

[0044] The specific process flow schematic diagram is as Figure 4 shown.

[0045] In addition, it should also be noted that:

[0046] When bonding silicon to the wafer, the face - to - face method is adopted. Therefore, the order of fabricating the damascene circuit on silicon is in reverse order, such as TM2, TM1, M5, M4, … M1. That is, the order of CD from large to small.

[0047] When bonding the silicon wafer to the glass, methods such as anodic bonding or hybrid bonding can be used.

[0048] The anodic bonding technology was proposed by Wallis and Pomerantz in 1969. It can bond glass to metal, alloy, or semiconductor without any binder. This kind of bonding has a low bonding temperature, a firm bonding interface, and good long - term stability.

[0049] Using an anodic bonding device, connect the silicon wafer to be bonded to the positive electrode of the power supply and the glass to the negative electrode, with a voltage of 500 - 1000V. Heat the glass-silicon wafer to 300 - 500°C. When a voltage is applied, the Na ions in the glass will drift towards the negative electrode, forming a depletion layer on the glass surface adjacent to the silicon wafer. The width of the depletion layer is about several μm. The depletion layer carries negative charges, and the silicon wafer carries positive charges. There is a large electrostatic attraction between the silicon wafer and the glass, causing them to be in close contact. In this way, the applied voltage is mainly applied to the depletion layer. The process of anodic bonding can be reflected by the change of the current in the circuit. When the voltage is first applied, there is a large current pulse, then the current decreases, and finally it is almost zero, indicating that the bonding is completed at this time.

[0050] A chemical reaction will occur at the closely contacted silicon / glass interface, forming strong chemical bonds such as Si-O-Si bonds, etc., to form a strong bonding interface.

[0051] The principle of silicon wafer - glass anodic bonding is as Figure 5 shown.

[0052] Hybrid bonding is a conventional process: Since the dielectric layer material is on top of the silicon and the main component of the glass is also SiO2, the bonding between the silicon wafer and the glass can be achieved through conventional processes such as chemical mechanical polishing, ion activation, cleaning, bonding, and annealing, to achieve the connection of electricity and structure.

[0053] The face-to-face bonding is adopted in this solution. If the back-to-back bonding is adopted as Figure 6 shown. The disadvantage of back-to-back bonding is that it adds a TSV process and a carrier wafer bonding / delamination process. The advantage is that the damascene process on the silicon wafer is in the normal order of M1, M2…TM1, TM2.

[0054] The bonding between the glass and the silicon is an alignment bonding. While ensuring the structural connection, it is necessary to ensure the electrical connection between the TGV and the metal layer of the silicon wafer.

[0055] II. Glass substrate covering silicon process:

[0056] (1) Grow silicon on both the front and back sides of the glass interposer after completing the TGV.

[0057] (2) Perform the TSV process on the silicon on the front side of the glass interposer.

[0058] (3) Continue to perform the damascene process on the TSV.

[0059] (4) Remove the silicon on the back side of the glass substrate. If necessary, continue to thin the glass interposer from the back side.

[0060] The schematic diagram of the process flow is as Figure 7 shown;

[0061] In addition, it should be noted that:

[0062] The idea of this method is to grow a certain thickness of silicon material on both the front and back sides of the glass. At this time, the glass wafer is wrapped by silicon, so it exhibits the characteristics of a silicon wafer. All the damascene processes on the front side are equivalent to being fabricated on a silicon wafer and are fully compatible with the conventional process; the suction cup device and various sensing devices on the back side detect silicon material, which is the same as that of a conventional silicon wafer and is also compatible with the original process.

[0063] The silicon growth process of this solution can grow silicon on both the front and back sides simultaneously using a furnace tube process, or it can also adopt the method of silicon epitaxial chemical vapor deposition.

[0064] Among them, the furnace tube process is a low-pressure chemical vapor deposition (LPCVD), which is generally carried out in a vacuum furnace tube. Its characteristic is that silicon material can be covered on both the front and back sides simultaneously. The detailed schematic diagram is as Figure 8 shown.

[0065] The growth schematic diagram of silicon epitaxy is as Figure 9 shown. In order to ensure that both the front and back sides are covered by silicon, it is necessary to deposit once on the front side and then deposit once on the back side.

[0066] In addition to the damascene copper process, any metal interconnection of silicon-based processes can also be adopted in the subsequent processes of this solution, such as the metal RDL process commonly used in packaging and testing factories, etc., to achieve metal interconnection.

[0067] In addition to Figure 4 the glass carrier process of the face-to-face silicon wafer-carrier process shown, there are also characteristic structures such as Figure 10 a layer of silicon material between the glass and the circuit shown.

[0068] In summary, the existing technology mainly focuses on the electrical interconnection process for glass materials. This kind of process is mostly applied to the production of TFT LCD Array in panel factories. The line width of this kind of process is relatively large, usually dozens of μm, and it cannot meet the electrical interconnection density requirements of the carrier board. Therefore, one technical route is to achieve it by miniaturizing the line width, but it is very difficult to do so because of the glass material and the existing process flow. If a new process flow is developed, the cost is too high and the feasibility also needs to be verified.

[0069] The existing silicon carrier board process is very mature. If the silicon carrier board process (mainly the copper damascene process) is directly applied to the glass wafer, it is relatively difficult because the materials are quite different, involving a large amount of Recipe software debugging and hardware transformation, and it cannot be mixed and run with the existing silicon machines. A new production line needs to be established separately, and the cost is too high.

[0070] The advantages of the present invention are that almost all processes are completed on silicon materials, enabling the direct application of existing copper damascene processes for silicon materials and allowing for mix run with conventional silicon wafers. At the same time, both the silicon-glass bonding process and the process of growing silicon on glass (such as furnace tube, silicon epitaxy, etc.) are mature processes. Therefore, this solution can significantly reduce the R & D cost, achieve the same interconnection density as that of silicon interposer on the glass interposer, and also possess the advantages of glass materials as described above.

[0071] In addition, the present invention also has the following effects:

[0072] Solution 1: After completing the damascene metal interconnection process on silicon, bond it with a glass substrate with TGV, and then remove the silicon, thus completing the fabrication of a glass interposer with high-density metal interconnection.

[0073] Solution 2: Use processes such as furnace tube polysilicon deposition and silicon vapor epitaxy to deposit silicon on both sides of the glass sheet, disguising it as a common silicon wafer in the Fab, making it compatible with all silicon-based processes in the Fab. Subsequently, remove the silicon on the back of the wafer, thus completing the fabrication of a glass interposer with high-density metal interconnection.

[0074] Adopting Solution 2 can obtain the characteristic structure of the present invention with glass + silicon layer + dielectric layer as Figure 10 shown.

[0075] Copper is generated inside the glass vias. However, regarding how to fabricate finer circuits on glass, the processes of Fabs similar to glass processing are not fine enough at present, while the processes of silicon-based Fabs can meet the requirements. But if directly using the processes of silicon-based Fabs to process glass in a silicon-based Fab, there will be a problem of process incompatibility, resulting in failure to achieve the final goal. Therefore, silicon is grown on both sides of the glass in advance. In this way, the machines in the silicon-based Fab can determine that the object being processed is a silicon wafer, so that all processes can be compatible with the silicon-based Fab, thereby completing the finer metal interconnection structure on the glass interposer.

[0076] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0077] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments.

[0078] As described above, the above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

[0079] The above embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made on the basis of the above description. It is not necessary and impossible to enumerate all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor device based on a glass transfer plate, characterized in that: The method includes: Step S1, using a Damascus process to stack a plurality of metal pattern layers on a silicon substrate in descending order of critical dimensions, wherein the plurality of metal pattern layers are electrically connected to each other and have a thickness in a range of 0.05 μm to 15 μm; Step S2, using low pressure chemical vapor deposition or silicon epitaxial chemical vapor deposition to grow silicon layers with a thickness ranging from 0.05 μm to 300 μm on the front and back surfaces of the TGV glass sheet, respectively, and bonding the side of the silicon substrate having the plurality of metal pattern layers to the TGV glass sheet face to face, wherein the thickness of the TGV glass sheet is in the range of 20 μm to 2000 μm; Step S3, removing the silicon substrate and thinning the glass layer of the TGV glass sheet to a thickness of 15 μm to 1900 μm, wherein: In the step S1, each of the plurality of metal pattern layers is formed in the order of TM2, TM1, M5, M4, M3, M2, and M1. In step S2, the silicon substrate and the TGV glass sheet are bonded by anodic bonding or hybrid bonding. The silicon substrate is connected to the positive pole of the power supply, and the TGV glass sheet is connected to the negative pole of the power supply. A voltage of 500V to 1000V is applied, and the heating temperature is maintained at 300°C to 500°C.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: When voltage is applied, Na ions in the TGV glass sheet will drift toward the negative electrode and form a depletion layer with a thickness of 1 μm to 10 μm on the glass surface adjacent to the silicon sheet until the current between each graphic circuit in the multiple metal graphic layers is reduced to near zero.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The electrical connection of the multiple metal pattern layers is achieved by using a Damascus copper process or a silicon-based process.

4. A semiconductor device manufactured by the semiconductor device manufacturing method according to any one of claims 1 to 3.

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