Integrated circuit device with via with warded end for power delivery

Abstract

The IC device may include one or more vias for delivering power to one or more transistors in the IC device. The via may have one or more widened ends to increase capacitance and reduce resistance. The transistor may include a source electrode over a source region and a drain electrode over a drain region. The source region or the drain region may be in a support structure having one or more semiconductor materials. The via has a body section and two end sections, the body section being between the end sections. The one or both end sections are wider than the body section, e.g., from about 6 nanometers to about 12 nanometers. One end section is connected to an interconnect at the back side of the support structure. The other end section is connected to a jumper connected to the source electrode or the drain electrode.

Description

Background Art

[0001] Integrated circuit (IC) manufacturing usually includes two stages. The first stage is called the front-end of the line (FEOL). The second stage is called the back-end of the line (BEOL). In the FEOL, various semiconductor device components (e.g., transistors, capacitors, resistors, etc.) can be patterned on a wafer. In the BEOL, metal layers, vias, and insulating layers can be formed to interconnect the various components. The BEOL usually starts with forming a first metal layer on a wafer. The first metal layer is usually referred to as M0. More metal layers can be formed on top of M0, and these metal layers are usually referred to as M1, M2, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments will be readily understood from the following detailed description in conjunction with the accompanying drawings. For ease of description, the same reference numerals denote the same structural elements. In the figures of the accompanying drawings, the embodiments are illustrated by way of example and not limitation.

[0003] Figure 1 An IC device with backside power delivery according to some embodiments of the present disclosure is shown.

[0004] Figure 2 Various configurations of vias are shown according to some embodiments of the present disclosure.

[0005] Figure 3 An example via having a widened end is shown according to some embodiments of the present disclosure.

[0006] Figure 4 Another example via having widened ends according to some embodiments of the present disclosure is shown.

[0007] Figure 5 An example via having two widened ends is shown according to some embodiments of the present disclosure.

[0008] Fig. 6A and Figure 6B is a top view of a wafer and die that may include one or more IC devices with vias having widened ends according to some embodiments of the present disclosure.

[0009] Figure 7 is a side cross-sectional view of an example IC package that may include one or more IC devices with vias having widened ends according to some embodiments of the present disclosure.

[0010] Figure 8 is a cross-sectional side view of an IC device assembly that may include components having one or more IC devices with vias having widened ends according to some embodiments of the present disclosure.

[0011] Fig. 9 is a block diagram of an example computing device that may include one or more components including one or more IC devices with vias having widened ends according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] The systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein.The details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0013] Currently available technology enables scaling below 5nm (or even below 3nm) by delivering power on the back side of the die or wafer. Backside power delivery can eliminate the need to share interconnect resources between signal and power lines on the front side. Instead, the power delivery network is moved to the back side, and the signal can be carried by the front side interconnect. Backside power delivery can also achieve cost savings because it can eliminate the need for power delivery interconnects from lower metal layers at the front side. It can also facilitate optimal manufacturing of different metal layers. For example, wider metal lines can be used for VDD and VSS, while thinner metal lines can be used for signal delivery.

[0014] One of the methods for backside power delivery is to have vias transfer power from the backside power delivery network directly to the electrodes of the transistor. This approach can improve power efficiency and increase area scaling. A good power delivery network can deliver a constant, stable supply voltage to the active circuits on the IC. A key parameter that can indicate the performance of the power delivery network is the resistance of the power delivery network in the interconnect path (e.g., from the power pins of the IC to the transistors in the circuit). Another key parameter that can indicate the performance of the power delivery network is the parasitic capacitance. Minimizing the overall resistance of the vias and interconnects while maximizing the close spacing between the vias and the transistors is necessary to mitigate the increase in local capacitance and is critical to the performance of the power delivery network.

[0015] Currently available technologies for backside power delivery suffer from the problem that the width of the via is limited by the parasitic capacitance to the gate metal, as increasing the width for the benefit of reduced resistance may reduce the performance of the device due to increased parasitic capacitance. One solution to reduce contact resistance is through material engineering, such as by changing the material of the via. However, this solution often suffers from the limited physical properties of the materials available in manufacturing, thereby hindering scaling requirements. Furthermore, the solution used in metal-to-via contact engineering controlled by standard via tapering is not applicable here because the via is routed next to the active device, which requires the volume of the via to be uniformly narrowed to maximize the space for the active device, while maximizing the top contact area to reduce contact resistance.

[0016] Embodiments of the present disclosure may improve at least some of the above challenges and problems by providing an IC device having a via with a widened end for power delivery. The widened end may enlarge the contact area of ​​the via with other components of the IC device. For example, the contact area of ​​the via with a jumper connecting the via to a transistor may be enlarged. As another example, the contact area between the via and the power interconnect may be enlarged. Enlarging the contact area may reduce capacitance and resistance, which may improve the performance of the IC device.

[0017] In various embodiments of the present disclosure, an IC device may include one or more vias for delivering power to one or more transistors in the IC device. The via may have one or more widened ends to increase capacitance and reduce resistance. The transistor may include a source electrode above a source region, a drain electrode above a drain region, and a gate electrode above a channel region. The source region, the drain region, or the channel region may be in a support structure having one or more semiconductor materials. The via has a main body section and two end sections, the main body section being between the end sections. One or both end sections are wider than the main body section, for example, about 6 nanometers to about 12 nanometers wide. In an example, the width of the end section may be in a range from about 16 nanometers to about 32 nanometers, while the width of the main body section may be in a range from about 10 nanometers to about 20 nanometers. The end section may have a taper having an angle in a range from about 45 degrees to about 75 degrees. One end section is connected to an interconnect at the back of the support structure. The other end section is connected to a jumper, which is connected to a source electrode or a drain electrode.

[0018] The vias may be separated from one or more other components of the IC device (e.g., metal lines, active devices, etc.) by one or more insulating structures. The insulating structures may be self-aligned insulating spacers. The insulating structures may include one or more dielectric materials, such as silicon oxide, silicon nitride, and the like.

[0019] The present disclosure provides a method to increase the contact area between vias and source / drain interconnects without additional patterning layers while preserving space to nearby transistors to achieve scaling and minimize parasitic capacitance. This method can be applied to other vias in IC devices.

[0020] It should be noted that in some arrangements, the term "nanoribbon" is used to describe an elongated semiconductor structure having a substantially rectangular cross-section (e.g., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term "nanowire" is used to describe a similar structure, but having a substantially circular or square cross-section. In the following, the single term "nanoribbon" is used to describe an elongated semiconductor structure regardless of the shape of the cross-section. Thus, as used herein, the term "nanoribbon" is used to cover an elongated semiconductor structure having a substantially rectangular cross-section (possibly with rounded corners), an elongated semiconductor structure having a substantially square cross-section (possibly with rounded corners), an elongated semiconductor structure having a substantially circular or elliptical / oval cross-section, and an elongated semiconductor structure having any polygonal cross-section. The longitudinal axis of a structure refers to a line (e.g., an imaginary line) extending downward through the center of the structure in a direction perpendicular to the cross-section of the structure.

[0021] In the following, some descriptions may refer to a particular source or drain (S / D) region or contact being a source region / contact or a drain region / contact. However, unless otherwise specified, it is not important which region / contact of a transistor or diode is considered to be a source region / contact and which region / contact is considered to be a drain region / contact, because, as is common in the field of FETs, the designation of source and drain is generally interchangeable. Therefore, the description of some illustrative embodiments of source and drain regions / contacts provided herein may be applied to embodiments in which the designation of source and drain regions / contacts may be reversed.

[0022] As used herein, the term "metal layer" may refer to a layer above a substrate that includes a conductive interconnect structure for providing electrical connections between different IC components. The metal layers described herein may also be referred to as "interconnect layers" to clearly indicate that these layers include conductive interconnect structures, which may be, but not necessarily, metal.

[0023] The systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein.The details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0024] In the following detailed description, various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the essence of their work to other persons skilled in the art. For example, the term "connection" refers to a direct electrical or magnetic connection between objects connected without any intermediate device, while the term "coupling" refers to a direct electrical or magnetic connection between connected objects, or an indirect connection through one or more passive or active intermediate devices. The term "circuit" refers to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. If used, the terms "oxide", "carbide", "nitride", etc. refer to compounds containing oxygen, carbon, nitrogen, etc., respectively, the term "high-k dielectric" refers to a material having a higher dielectric constant (k) than silicon oxide, and the term "low-k dielectric" refers to a material having a lower k than silicon oxide. The terms "substantially", "close", "approximately", "nearby", and "approximately" generally refer to within + / -20% of a target value based on the context of a specific value as described herein or as known in the art. Similarly, terms indicating the orientation of various elements (e.g., "coplanar," "perpendicular," "orthogonal," "parallel") or any other angle between elements generally mean within + / - 5-20% of the target value based on the context of the specific value as described herein or as known in the art.

[0025] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer, or may have one or more intervening layers. Additionally, a layer disposed between two layers may be in direct contact with the two layers, or may have one or more intervening layers. Conversely, a first layer that is "above" a second layer is in direct contact with the second layer. Similarly, unless expressly stated otherwise, a feature disposed between two features may be in direct contact with the adjacent feature, or may have one or more intervening layers.

[0026] For purposes of this disclosure, the term "or" means an inclusive "or" rather than an exclusive "or". The phrase "A and / or B" or the phrase "A or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B and / or C" or the phrase "A, B or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). When used with reference to a measurement range, the term "between" includes the endpoints of the measurement range. As used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0027] The description may use the phrases "in one embodiment" or "in an embodiment," which may each refer to one or more of the same or different embodiments. In addition, the terms "including," "comprising," "having," and the like as used with respect to the embodiments of the present disclosure are synonymous. The present disclosure may use perspective-based descriptions, such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments. The drawings are not necessarily drawn to scale. Unless otherwise stated, the use of ordinal adjectives "first," "second," and "third," etc. to describe common objects merely indicates that different instances of similar objects are being referenced, and are not intended to imply that the objects so described must be in a given sequence in time, space, order, or in any other way.

[0028] In the following detailed description, reference is made to the accompanying drawings which form a part hereof and in which are shown by way of illustration embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be construed as limiting. For convenience, if there is a collection of figures named with different letters, e.g. Fig. 6A and Figure 6B , then such a set may be referred to herein without letters, for example, as "FIG. 6".

[0029] In the accompanying drawings, some schematic diagrams of example structures of various devices and components described herein may be shown with exact right angles and straight lines, but it should be understood that these schematic diagrams may not reflect real-world process limitations that may cause features to appear less than "ideal" when any structure described herein is examined, for example, using a scanning electron microscope (SEM) image or a transmission electron microscope (TEM) image. In such images of real structures, possible processing defects are also visible, such as imperfectly straight edges of material, tapered vias or other openings, unintentional rounding of corners, or thickness variations of different material layers, accidental spirals, edge or combined dislocations within crystalline regions, and / or accidental dislocation defects of single atoms or clusters of atoms. Other defects that are not listed here but are common in the field of device manufacturing may exist. Using, for example, optical microscopy, TEM or SEM to examine the layout and mask data of portions of the device and reverse engineering to reconstruct the circuit, and / or using, for example, physical failure analysis (PFA) to examine cross-sections of the device to detect the shape and position of various device elements described herein, will allow the presence of vias with widened ends as described herein to be determined.

[0030] The various operations may be described as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be order-dependent. In particular, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. In additional embodiments, various additional operations may be performed, and / or the described operations may be omitted.

[0031] Various vias with widened ends as described herein may be implemented in or associated with one or more components associated with an IC, or / and may be implemented between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, and the like. Components associated with an IC may include components mounted on the IC or connected to the IC. The IC may be analog or digital and may be used in many applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, and the like, depending on the components associated with the IC. The IC may be used as part of a chipset for performing one or more related functions in a computer.

[0032] Figure 1 An IC device 100 with backside power delivery according to some embodiments of the present disclosure is shown. IC device 100 includes support structure 110, transistor 120, electrical insulator 125, conductive structure 150, jumper 155, via 160, metal line 170 (individually "metal line 170") and metal line 180 (individually "metal line 180"), vias 190A-190C, and another electrical insulator 195. In other embodiments, IC device 100 may include fewer, more, or different components. For example, IC device 100 may include Figure 1 As another example, IC device 100 may include fewer or more metal layers.

[0033] The support structure 110 may be any suitable structure on which the transistor 120 may be built, such as a substrate, a die, a wafer, or a chip. The support structure 110 may be, for example, a Fig. 6A The wafer 2000 may be a die (e.g., discussed below). Figure 6BThe support structure 110 may be a semiconductor substrate composed of a semiconductor material system including, for example, an N-type or P-type material system, and in some embodiments, the channel region 130 described herein may be a part of the support structure 110. In some embodiments, the semiconductor substrate may be a crystalline substrate formed using bulk silicon or a silicon-on-insulator substructure. In other embodiments, the semiconductor substrate may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of III-V, II-VI, or IV materials. In some embodiments, the substrate may be non-crystalline. In some embodiments, the support structure may be a printed circuit board (PCB) substrate. One or more transistors (such as transistor 120) may be built on the support structure 110.

[0034] Although several examples of materials that can form support structure 110 are described herein, any material that can be used as a basis on which an IC can be built falls within the spirit and scope of the present disclosure. In various embodiments, support structure 110 may include any such substrate, possibly having some layers and / or devices already formed thereon, which are not specifically shown in the present figures. As used herein, the term "support" does not necessarily mean that it provides mechanical support for IC devices / structures (e.g., transistors, capacitors, interconnects, etc.) built thereon. For example, some other structure (e.g., a carrier substrate or a packaging substrate) can provide such mechanical support, and support structure 110 can provide material "support" because, for example, the IC devices / structures described herein are built based on the semiconductor material of support structure 110. However, in some embodiments, support structure 110 can provide mechanical support.

[0035] The transistor 120 may be a field effect transistor (FET), such as a metal oxide semiconductor FET (MOSFET), a tunnel FET (TFET), a fin-based transistor (e.g., FinFET), a nanoribbon-based transistor, a nanowire-based transistor, a full-ring gate (GAA) transistor, other types of FETs, or a combination of the two. The transistor 120 includes a semiconductor structure including a channel region 130, a source region 140A, and a drain region 140B. The semiconductor structure of the transistor 120 may be at least partially in the support structure 110. The support structure 110 may include a semiconductor material, and at least a portion of the semiconductor structure is formed by the semiconductor material. The semiconductor structure of the transistor 120 (or a portion of the semiconductor structure, such as the channel region 130) may be a planar structure or a non-planar structure. The non-planar structure is a three-dimensional structure, such as a fin, a nanowire, or a nanoribbon. The non-planar structure may have a longitudinal axis and a cross-section perpendicular to the longitudinal axis. In some embodiments, the size of the non-planar structure along the longitudinal axis may be greater than the size along other directions (e.g., along the direction of the axis perpendicular to the longitudinal axis).

[0036] The channel region 130 includes a channel material. The channel material may be composed of a semiconductor material system including, for example, an n-type or p-type material system. In some embodiments, the channel material may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the channel material may include a compound semiconductor having a first sub-lattice of at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sub-lattice of at least one element from Group V of the periodic table (e.g., P, As, Sb). In some embodiments, the channel material may include a compound semiconductor having a first sub-lattice of at least one element from Group II of the periodic table (e.g., Zn, Cd, Hg) and a second sub-lattice of at least one element from Group IV of the periodic table (e.g., C, Si, Ge, Sn, Pb). In some embodiments, the channel material is an epitaxial semiconductor material deposited using an epitaxial deposition process. The epitaxial semiconductor material can have a polycrystalline structure with a grain size between about 2 nanometers and 100 nanometers, including all values ​​and ranges therein.

[0037] For some example n-type transistor embodiments (i.e., for embodiments where transistor 120 is an NMOS (N-type metal oxide semiconductor) transistor or an n-type TFET), the channel material may advantageously include a III-V material with high electron mobility, such as, but not limited to, InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some In x Ga 1-x As fin embodiments, the In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In 0.7 Ga 0.3 As). In some embodiments with the highest mobility, the channel material may be an intrinsic III-V material, i.e., a III-V semiconductor material that has not been intentionally doped with any electrically active impurities. In alternative embodiments, a nominal impurity dopant level may be present in the channel material, e.g., to further fine tune the threshold voltage Vt, or to provide a HALO pocket implant, etc. However, even for impurity doped embodiments, the impurity dopant level in the channel material 304 may be relatively low, e.g., less than 10 15 dopant atoms per cubic centimeter (cm -3 ), and advantageously less than 10 13 cm -3 These materials may be amorphous or polycrystalline, for example, with a grain size between 0.5 nanometers and 100 nanometers.

[0038] For some example P-type transistor embodiments (i.e., for embodiments in which transistor 120 is a PMOS (P-type metal oxide semiconductor) transistor or a P-type TFET), the channel material may advantageously be a Group IV material having a high hole mobility, such as, but not limited to, Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel material may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7. In some embodiments having the highest mobility, the channel material may be an intrinsic Group III-V (or Group IV for P-type devices) material and is not intentionally doped with any electrically active impurities. In alternative embodiments, one or more nominal impurity dopant levels may be present within the channel material, for example to further set the threshold voltage (Vt), or to provide a HALO pocket implant, etc. However, even for impurity doped embodiments, the impurity dopant level within the channel portion is relatively low, for example, less than 10 15 cm -3 , and advantageously less than 10 13 cm -3These materials may be amorphous or polycrystalline, for example, with a grain size between 0.5 nanometers and 100 nanometers.

[0039] In some embodiments, the channel material may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, aluminum zinc oxide, or tungsten oxide. Generally speaking, for a thin film transistor (TFT), the channel material may include one or more of the following: tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, molybdenum disulfide, N-type or P-type amorphous or polycrystalline silicon, single crystal silicon, germanium, indium arsenide, indium gallium arsenide, indium selenide, indium antimonide, zinc antimonide, antimony selenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, black phosphorus, zinc sulfide, indium sulfide, gallium sulfide, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten and magnesium, etc. In some embodiments, thin film channel materials may be deposited at relatively low temperatures, which allows the channel materials to be deposited within the thermal budget imposed on back-end fabrication to avoid damaging other components, for example, front-end components such as logic devices.

[0040] As described above, the channel material may include IGZO. IGZO-based devices have several desirable electrical and manufacturing properties. IGZO has high electron mobility compared to other semiconductors, for example, in the range of 20-50 times that of amorphous silicon. In addition, amorphous IGZO (a-IGZO) transistors are generally characterized by high band gap, low temperature process compatibility, and low manufacturing cost relative to other semiconductors.

[0041] IGZO can be deposited as a uniform amorphous phase while maintaining a higher carrier mobility than oxide semiconductors such as zinc oxide. Different formulations of IGZO include different proportions of indium oxide, gallium oxide, and zinc oxide. One specific form of IGZO has the chemical formula InGaO3(ZnO)5. Another example form of IGZO has an indium:gallium:zinc ratio of 1:2:1. In various other examples, IGZO can have a gallium to indium ratio of 1:1, a gallium to indium ratio greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), and / or a gallium to indium ratio less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10). IGZO may also contain ternary dopants such as aluminum or nitrogen.

[0042] The source region 140A and the drain region 140B are connected to the channel region 130. The source region 140A and the drain region 140B each include a semiconductor material having a dopant. In some embodiments, the source region 140A and the drain region 140B have the same semiconductor material, which may be the same as the channel material of the channel region 130. The semiconductor material of the source region 140A or the drain region 140B may be a group IV material, a compound of a group IV material, a group III / V material, a compound of a group III / V material, a group II / VI material, a compound of a group II / VI material, or other semiconductor materials. Example group II materials include zinc (Zn), cadmium (Cd), etc. Example group III materials include aluminum (Al), boron (B), indium (In), gallium (Ga), etc. Example group IV materials include silicon (Si), germanium (Ge), carbon (C), etc. Example group V materials include nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), etc. Example Group VI materials include sulfur (S), selenium (Se), tellurium (Te), oxygen (O), etc. Compounds of Group IV materials may be binary compounds, such as SiC, SiGe, etc. Compounds of Group III / V materials may be binary, ternary, or quaternary compounds, such as GaN, InN, etc. Compounds of Group II / VI materials may be binary, ternary, or quaternary compounds, such as CdSe, CdS, CdTe, ZnO, ZnSe, ZnS, ZnTe, CdZnTe, CZT, HgCdTe, HgZnTe, etc.

[0043] In some embodiments, the dopants in the source region 140A and the drain region 140B are of the same type. In other embodiments, the dopants of the source region 140A and the drain region 140B may be of different (e.g., opposite) types. In an example, the source region 140A has an N-type dopant and the drain region 140B has a P-type dopant. In another example, the source region 140A has a P-type dopant and the drain region 140B has an N-type dopant. Example N-type dopants include Te, S, As, tin (Sn), Si, Ga, Se, S, In, Al, Cd, chlorine (Cl), iodine (I), fluorine (F), etc. Example P-type dopants include beryllium (Be), Zn, magnesium (Mg), Sn, P, Te, lithium (Li), sodium (Na), Ga, Cd, etc.

[0044] In some embodiments, the source region 140A and the drain region 140B may be highly doped, for example, with a doping ratio of about 1·10 21 cm -3The source and drain regions 140A and 140B may have a dopant concentration that is higher than the dopant concentration in other regions (e.g., higher than the dopant concentration in the channel region 130), and thus may be referred to as "highly doped" (HD) regions.

[0045] The channel region 130 may include one or more semiconductor materials having a doping concentration that is significantly lower than the doping concentration of the source region 140A and the drain region 140B. For example, in some embodiments, the channel material of the channel region 130 may be an intrinsic (e.g., undoped) semiconductor material or alloy that is not intentionally doped with any electrically active impurities. In alternative embodiments, a nominal impurity dopant level may be present in the channel material, such as to set a threshold voltage Vt, or to provide a HALO pocket implant, etc. However, in such an impurity-doped embodiment, the impurity dopant level in the channel material is still significantly lower than the dopant level in the source region 140A and the drain region 140B, such as less than 10 15 cm -3 or less than 10 13 cm -3 Depending on the context, the term “S / D terminal” may refer to the S / D region or the S / D contact or electrode of a transistor.

[0046] Transistor 120 also includes an electrode 145A located above source region 140A and an electrode 145B located above drain region 140B. Electrode 145A may be referred to as a source electrode or source contact. Electrode 145B may be referred to as a drain electrode or drain contact. Electrode 145A and electrode 145B are conductive and may be coupled to a source terminal and a drain terminal, respectively, for receiving power. Electrode 145A or electrode 145B include one or more conductive materials, such as metals. Examples of metals in electrode 145A and electrode 145B may include, but are not limited to, ruthenium (Ru), copper (Cu), cobalt (Co), palladium (Pd), platinum (Pt), nickel (Ni), etc.

[0047] The transistor 120 also includes a gate over or around at least a portion of the channel region 130. The gate includes a gate electrode 135 and a gate insulator 137. The gate electrode 135 can be coupled to a gate terminal that controls a gate voltage applied to the transistor 120. The gate electrode 135 can include one or more gate electrode materials, wherein the selection of the gate electrode material can depend on whether the transistor 120 is a P-type transistor or an N-type transistor. For a P-type transistor, the gate electrode materials that can be used in different parts of the gate electrode can include, but are not limited to, Ru, Pd, Pt, Co, Ni, and conductive metal oxides (e.g., ruthenium oxide). For an N-type transistor, the gate electrode materials that can be used in different parts of the gate electrode can include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode 135 may include a stack of multiple gate electrode materials, wherein zero or more materials of the stack are work function (WF) materials, and at least one material of the stack is a fill metal layer. Additional materials / layers may be included next to the gate electrode for other purposes, such as serving as a diffusion barrier layer or / and adhesion layer.

[0048] The gate insulator 137 separates at least a portion of the channel region 130 from the gate electrode 135, so that the channel region 130 is insulated from the gate electrode 135. In some embodiments, the gate insulator 137 can surround at least a portion of the channel region 130. The gate insulator 137 can also surround at least a portion of the source region 140A or the drain region 140B. At least a portion of the gate insulator 137 can be surrounded by the gate electrode. The gate insulator 137 includes an electrical insulator, such as a dielectric material, a hysteresis material, etc. Example dielectric materials include oxides (e.g., Si-based oxides, metal oxides, etc.), high-k dielectrics, etc. Example hysteresis materials include ferroelectric materials, antiferroelectric materials, etc.

[0049] exist Figure 1 In some embodiments, transistor 120 may receive power from a backside power delivery network including conductive structure 150. Conductive structure 150 may be a backside interconnect, such as a backside metal line. Conductive structure 150 may be referred to as a power interconnect. In some embodiments, conductive structure 150 may be a power plane of IC device 100. Power may be delivered from conductive structure 150 to transistor 120 through vias 160 and jumpers 155. Jumpers 155 and vias 160 are conductive and include one or more conductive materials, such as metals, including the metals described above. Vias 160 may be referred to as vias. Jumpers 155 may be referred to as power jumpers. Figure 1As shown in , via 160 is connected to conductive structure 150 and to jumper 155. Jumper 155 is connected to electrode 145B. Therefore, conductive structure 150, via 160 and jumper 155 constitute a conductive path to electrode 145B. Jumper 155 provides an electrical connection between via 160 and electrode 145B. Jumper 155 can be or include a wire or other type of conductive structure. Although in Figure 1 Middle jumper 155 is connected to electrode 145B, but jumper 155 or additional jumpers in IC device 100 may also be connected to electrode 145A so that power may be delivered to electrode 145A in other embodiments.

[0050] Conductive structure 155 may be or may be coupled to a VDD terminal. In some embodiments, conductive structure 155 may facilitate delivery of a positive supply voltage to electrode 145B, while electrode 145A may receive a negative supply voltage or may be coupled to a ground plane. Transistor 120 may be an N-type transistor, such as an NMOS. In other embodiments, conductive structure 155 may facilitate delivery of a negative supply voltage to electrode 145B or couple electrode 145B to ground. The transistor may be a P-type transistor, such as a PMOS transistor.

[0051] The via 160 includes a main body section 163 and an end section 165. The main body section 163 is connected to the conductive structure 150. The main body section 163 extends from the back side of the support structure 110 toward the front side of the support structure 110. In some embodiments, the main body section 163 has a longitudinal axis along the Z axis. The widths of the various parts of the main body section 163 along the X axis may be the same or substantially similar. In some embodiments, the width of the main body section 163 along the X axis is in the range from about 10 nanometers to about 20 nanometers. The via 160 may penetrate at least a portion of the support structure 110. In some embodiments, the via 160 may penetrate the entire support structure 110 along the Z axis. The via 160 may be a through-silicon via.

[0052] The end section 165 is connected to the jumper 155. The end section 165 is closer to the front surface of the support structure 110 than the rear surface of the support structure 110. Figure 1In some embodiments, the end segment 165 has a taper. The taper may have an angle in a range from about 45 degrees to about 75 degrees. In other embodiments, the end segment 165 may not have a taper. The end segment 165 is wider than the main segment 163, for example, from about 6 nanometers to about 12 nanometers wide. In some embodiments, the width of the end segment 165 along the X-axis (for example, the maximum width of the end segment 165) is in a range from about 16 nanometers to about 32 nanometers. The widened end of the via 160 enlarges the contact area of ​​the via 160 with the jumper 155, which can reduce the resistance in the back power delivery network. When the main segment 163 is narrower, the distance between the via 160 and one or more electrodes of the transistor (for example, electrode 145A, electrode 145B, or gate electrode 135) is larger, and therefore the capacitance is lower. The following is combined with Figure 2-5 Provides more details about vias.

[0053] Each of the electrodes 145A and 145B, the gate electrode 135, the jumper 155, and the via 160 may be at least partially surrounded by an electrical insulator to avoid undesired electrical connection or coupling. The electrical insulator 195 may include an electrical insulator such as a dielectric material, a hysteresis material, etc. Example dielectric materials include oxides (e.g., Si-based oxides, metal oxides, etc.), high-k dielectrics, etc. Example hysteresis materials include ferroelectric materials, antiferroelectric materials, etc.

[0054] Metal lines 170 and 180 are stacked above support structure 110, transistor 120, and electrical insulator 125 along the Z-axis. Metal line 170 is coupled to gate electrode 135 of transistor 120 through via 190A. In some embodiments, metal line 170 can be used to deliver a signal (e.g., a control signal) to gate electrode 135. Other metal lines 170 are coupled to metal line 180 through vias 190B and 190C, respectively. In other embodiments, the electrical connections of metal lines 170 and 180 may be different. Although in Figure 1 Although not shown, metal line 170 or 180 may also be coupled to other devices besides transistor 120, such as a diode, a power supply, a resistor, a capacitor, an inductor, a sensor, a transceiver, a receiver, an antenna.

[0055] In some embodiments, metal line 170 may constitute a metal layer disposed closest to transistor 120 and may be a first BEOL layer at the front side of support structure 110. In some embodiments, the metal layer may be referred to as M0. Metal line 180 may constitute a second metal layer at the front side, which may be referred to as M1. There may be one or more metal layers disposed on top of metal line 170, which may be referred to as M3, M4, etc. Metal line 170 is coupled to metal line 180 through vias 190B and 190C. Metal lines 170 and 180 are at least partially surrounded by electrical insulator 195. Electrical insulator 195 may include electrical insulators such as dielectric materials, hysteresis materials, and the like. Example dielectric materials include oxides (e.g., Si-based oxides, metal oxides, etc.), high-k dielectrics, and the like. Example hysteresis materials include ferroelectric materials, antiferroelectric materials, and the like.

[0056] Figure 2 Various configurations of vias 210, 220, 230, and 240 are shown according to some embodiments of the present disclosure. For illustration purposes, each of vias 210, 220, 230, and 240 is connected to conductive structure 203 and jumper 207. Jumper 207 couples each of vias 210, 220, 230, and 240 to transistor 205. An example of conductive structure 203 may be Figure 1 An example of a jumper 207 may be Figure 1 An example of transistor 205 may be Figure 1 The transistor 120 in FIG.

[0057] The vias 210, 220, 230 and 240, the conductive structure 203 and the jumper 207 can be used for backside power delivery. For backside power delivery, the lower the resistance in the power delivery path, the better. The contact resistance between two conductive structures will be inversely proportional to the overlap area of ​​the two conductive structures. A larger overlap area can result in a smaller resistance, which can improve the efficiency of power delivery. Figure 2 As shown, vias 210, 230, and 240 have a larger overlap area with corresponding jumper 207 than via 220. Therefore, the resistance between each of vias 210, 230, and 240 and jumper 207 is lower than the resistance between via 220 and jumper 207.

[0058] However, vias 210 and 230 have the disadvantage of lower scaling opportunities compared to vias 220 and 240 because vias 210 and 230 are closer to transistor 205 than vias 220 and 240. The smaller distance of vias 220 and 240 to transistor 205 may also result in higher capacitance, which is undesirable for power delivery. Although the bottom of via 230 is farther away from transistor 205 than the top of via 230, the scaling opportunities are still limited. Via 240 can promote optimal power delivery performance compared to vias 210, 220, and 230 because it can provide the best scaling opportunities and also have a larger contact area with the jumper. In some embodiments, via 240 may have a wider end at the side where it is connected to conductive structure 203, which can expand the overlap area with conductive structure 203 and reduce the resistance between via 240 and conductive structure 203.

[0059] Figure 3 An example via 300 having a widened end is shown according to some embodiments of the present disclosure. The via 300 may be Figure 1 Via 160 or Figure 2 An example of via 240 in FIG. Figure 3 As shown, via 300 includes a first section 310 and a second section 320. First section 310 includes a widened end of via 300. First section 310 has a taper. The taper has an angle 311, which can be from about 45 degrees to about 75 degrees. First section 310 has a width 312 along the X-axis, which can be from about 16 nanometers to about 32 nanometers. Width 312 can be the width of the widened end of via 300. First section 310 also has a height 313 along the Z-axis, which can be from about 5 nanometers to about 10 nanometers.

[0060] The second segment 320 is below the first segment 310. The second segment has a longitudinal axis 321, which can be parallel to the Z axis. A distance 322 from the edge of the first segment 310 to the longitudinal axis 321 of the second segment 320 can be in a range from about 3 nanometers to about 6 nanometers. In some embodiments, the longitudinal axis 321 is located at the center of the second segment 320 in the direction along the X axis.

[0061] Figure 4 Another example via 400 having a widened end according to some embodiments of the present disclosure is shown. The via 400 may be Figure 1 Via 160 or Figure 2 An example of via 240 in FIG. Figure 4 As shown, the via 400 includes a first section 410 and a second section 420. The first section 410 includes a widened end portion of the via 400. Figure 3Unlike via 300 in FIG. 4 , first segment 410 of via 400 has no taper. First segment 410 has a width 412 along the X-axis, which may be from about 16 nanometers to about 32 nanometers. Width 412 may be the width of the widened end of via 400. First segment 410 also has a height 413 along the Z-axis, which may be from about 5 nanometers to about 10 nanometers.

[0062] The second segment 420 is below the first segment 410. The second segment has a longitudinal axis 421, which can be parallel to the Z axis. A distance 422 from an edge of the first segment 410 to the longitudinal axis 421 of the second segment 420 can be in a range from about 3 nanometers to about 6 nanometers. In some embodiments, the longitudinal axis 421 is located at the center of the second segment 420 in a direction along the X axis.

[0063] Figure 5 An example via 500 having two widened ends according to some embodiments of the present disclosure is shown. The via 500 may be Figure 1 Via 160 or Figure 2 An example of via 240 in FIG. Figure 5 As shown, the via 500 includes a first section 510A, a second section 520, and a third section 510B. The first section 510A and the third section 510B may be collectively referred to as "sections 510" or "section 510", each section 510 including a widened end of the via 500. Each section 510 has a taper. The taper has an angle 511, which may be from about 45 degrees to about 75 degrees. In addition, each section 510 has a width 512 along the X-axis, which may be from about 16 nanometers to about 32 nanometers. The width 512 may be the width of the widened end of the via 500. Each section 510 has a height 513 along the Z-axis, which may be from about 5 nanometers to about 10 nanometers.

[0064] Despite Figure 5 In the embodiment of the present invention, the segments 510 have the same size, but in other embodiments, the segments 510 can have different sizes. For example, the segments 510 can have different widths, heights, etc. In addition, the segments 510 can have different shapes. In an example, one of the segments 510 can have a tapered shape while the other does not have a tapered shape. In some embodiments, both segments 510 may not have a tapered shape. For example, one or both of the segments 510 may have a tapered shape. Figure 4 The shape of the first section 410 of the via 400 in FIG. Figure 3 The vias in 300 or Figure 4 Compared to via 400 in FIG. 1 , via 500 may provide better power delivery performance due to the additional widened end.

[0065] The second segment 520 is below the first segment 510. The second segment has a longitudinal axis 521, which can be parallel to the Z axis. A distance 522 from the edge of the first segment 510 to the longitudinal axis 521 of the second segment 520 can be in a range from about 3 nanometers to about 6 nanometers. In some embodiments, the longitudinal axis 521 is located at the center of the second segment 520 in the direction along the X axis.

[0066] Fig. 6A and Figure 6B 2 is a top view of a wafer 2000 and die 2002 that may include one or more IC devices with vias having widened ends according to some embodiments of the present disclosure. In some embodiments, die 2002 may be included in an IC package according to some embodiments of the present disclosure. For example, any of die 2002 may be used as a Figure 7 2256 in the IC package 2200 shown in FIG. Wafer 2000 may be composed of semiconductor material and may include one or more dies 2002 having IC devices formed on a surface of wafer 2000. The IC devices may include one or more vias having widened ends. Examples of IC devices may include Figure 1 2002. Each of the dies 2002 can be a repeating unit of a semiconductor product including any suitable IC (e.g., an IC having vias with widened ends as described herein). After fabrication of the semiconductor product is complete (e.g., after fabrication of metal lines as described herein), the wafer 2000 can undergo a singulation process in which each of the dies 2002 is separated from one another to provide discrete "chips" of the semiconductor product. In particular, a device including vias with widened ends as disclosed herein can take the form of or include components in the form of the wafer 2000 (e.g., not singulated) or in the form of the dies 2002 (e.g., singulated). The dies 2002 can include one or more diodes, one or more transistors (e.g., one or more III-N transistors as described herein), and optionally, supporting circuitry for transmitting electrical signals to the III-N diodes and III-N transistors having n-doped wells and capping layers, as well as any other IC components. In some embodiments, wafer 2000 or die 2002 may implement an electrostatic discharge (ESD) protection device, an RF front-end device, a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple of these devices may be combined on a single die 2002.

[0067] Figure 7is a side cross-sectional view of an example IC package 2200 that may include one or more IC devices with vias having widened ends according to some embodiments of the present disclosure. In some embodiments, IC package 2200 may be a system-in-package (SiP).

[0068] like Figure 7 As shown, IC package 2200 may include package substrate 2252. Package substrate 2252 may be formed of a dielectric material (e.g., ceramic, glass, a combination of organic and inorganic materials, a built-up film, an epoxy film with filler particles therein, etc., and may have embedded portions with different materials), and may have conductive paths extending through the dielectric material between face 2272 and face 2274, or between different locations on face 2272, and / or between different locations on face 2274.

[0069] The packaging substrate 2252 may include conductive contacts 2263 coupled to conductive paths 2262 through the packaging substrate 2252, thereby allowing the circuit system within the tube core 2256 and / or the interposer 2257 to be electrically coupled to individual ones of the conductive contacts 2264 (or to other devices included in the packaging substrate 2252, not shown).

[0070] IC package 2200 may include interposer 2257 coupled to package substrate 2252 via conductive contacts 2261 of interposer 2257 , first level interconnects 2265 , and conductive contacts 2263 of package substrate 2252 . Figure 7 The first level interconnects 2265 shown in FIG. 22 are solder bumps, but any suitable first level interconnects 2265 may be used. In some embodiments, interposer 2257 may not be included in IC package 2200; instead, die 2256 may be coupled directly to conductive contacts 2263 at face 2272 via first level interconnects 2265.

[0071] IC package 2200 may include one or more dies 2256 coupled to interposer 2257 via conductive contacts 2254 of die 2256, first level interconnects 2258, and conductive contacts 2260 of interposer 2257. Conductive contacts 2260 may be coupled to conductive paths (not shown) through interposer 2257, thereby allowing circuitry within die 2256 to be electrically coupled to respective ones of conductive contacts 2261 (or to other devices included in interposer 2257, not shown). Figure 7The first level interconnect 2258 shown in the figure is a solder bump, but any suitable first level interconnect 2258 can be used. As used herein, a "conductive contact" can refer to a portion of a conductive material (e.g., a metal) that serves as an interface between different components; a conductive contact can be recessed into the surface of a component, flush with the surface of a component, or extend away from the surface of a component, and can take any suitable form (e.g., a conductive pad or a socket).

[0072] In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first level interconnect 2265, and a mold compound 2268 may be disposed around the die 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the mold compound 2268. An example material that may be used for the underfill material 2266 and the mold compound 2268 is an epoxy molding material, as appropriate. The second level interconnect 2270 may be coupled to the conductive contact 2264. Figure 7 The second level interconnects 2270 shown are solder balls (e.g., for a ball grid array arrangement), but any suitable second level interconnects 2270 may be used (e.g., pins in a pin grid array arrangement or pads in a pad grid array arrangement). The second level interconnects 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and as described below with reference to Figure 8 discussed.

[0073] Die 2256 may take the form of any embodiment of die 2002 discussed herein and may include any embodiment of an IC device with vias having widened ends. In embodiments where IC package 2200 includes multiple dies 2256, IC package 2200 may be referred to as a multi-chip package. Importantly, even in such embodiments of an MCP implementation of IC package 2200, one or more IC devices with vias having widened ends may be provided in a single chip according to any embodiment described herein. Die 2256 may include circuitry for performing any desired function. For example, one or more of die 2256 may be ESD protection die, one or more of die 2256 may be logic die (e.g., silicon-based die), one or more of die 2256 may be memory die (e.g., high bandwidth memory), and the like. In some embodiments, any of the dies 2256 may include one or more back metal layers, for example, vias with widened ends as discussed above; in some embodiments, at least some of the dies 2256 may not include any III-N diodes having an n-doped well and a capping layer.

[0074] Figure 7 The IC package 2200 shown in FIG. 2 may be a flip chip package, although other package structures may be used. For example, the IC package 2200 may be a ball grid array (BGA) package, such as an embedded wafer level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer level chip scale package (WLCSP) or a panel fan-out (FO) package. Although FIG. 2 may be a flip chip package, the IC package 2200 may be a flip chip package, although other package structures may be used. For example, the IC package 2200 may be a ball grid array (BGA) package, such as an embedded wafer level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer level chip scale package (WLCSP) or a panel fan-out (FO) package. Figure 7 Two dies 2256 are shown in the IC package 2200, but the IC package 2200 may include any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface mount resistors, capacitors, and inductors disposed on the first side 2272 or the second side 2274 of the package substrate 2252 or on either side of the interposer 2257. More generally, the IC package 2200 may include any other active or passive components known in the art.

[0075] Figure 8 is a cross-sectional side view of an IC device assembly that may include components having one or more IC devices with vias having widened ends according to some embodiments of the present disclosure. IC device assembly 2300 includes a plurality of components disposed on a circuit board 2302 (which may be, for example, a motherboard). IC device assembly 2300 includes components disposed on a first side 2340 of circuit board 2302 and an opposite second side 2342 of circuit board 2302; typically, the components may be disposed on one or both sides 2340 and 2342. In particular, any suitable component among the components of IC device assembly 2300 may include any IC device with vias having widened ends according to any embodiment disclosed herein; for example, any IC package discussed below with reference to IC device assembly 2300 may take the form described above with reference to FIG. Figure 7 Any of the embodiments of IC package 2200 discussed may include vias having widened ends in / on die 2256 , for example.

[0076] In some embodiments, circuit board 2302 may be a PCB including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more metal layers may be formed in a desired circuit pattern to transmit electrical signals between components coupled to circuit board 2302 (optionally in combination with other metal layers). In other embodiments, circuit board 2302 may be a non-PCB substrate.

[0077] Figure 8The IC device assembly 2300 shown in FIG. 2 includes a package-on-interposer structure 2336 coupled to a first side 2340 of a circuit board 2302 via a coupling component 2316. The coupling component 2316 can electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302 and can include solder balls (e.g., Figure 8 as shown), male and female portions of the socket, adhesives, bottom fill materials, and / or any other suitable electrical and / or mechanical coupling structures.

[0078] The package-on-interposer structure 2336 may include an IC package 2320 coupled to the interposer 2304 via a coupling component 2318. The coupling component 2318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling component 2316. The IC package 2320 may be or include, for example, a die ( Figure 6B 2002), IC devices (e.g., Figure 1 IC device 100), or any other suitable component. In particular, IC package 2320 may include one or more IC devices with vias having widened ends as described herein. Figure 8 A single IC package 2320 is shown in the figure, but multiple IC packages can be coupled to the interposer 2304; in fact, additional interposers can be coupled to the interposer 2304. The interposer 2304 can provide an intermediate substrate for bridging the circuit board 2302 and the IC package 2320. In general, the interposer 2304 can extend the connection to a looser pitch or reroute the connection to a different connection. For example, the interposer 2304 can couple the IC package 2320 (e.g., a die) to the BGA of the coupling component 2316 for coupling to the circuit board 2302. Figure 8 In the illustrated embodiment, IC package 2320 and circuit board 2302 are attached to opposite sides of interposer 2304; in other embodiments, IC package 2320 and circuit board 2302 can be attached to the same side of interposer 2304. In some embodiments, three or more components can be interconnected through interposer 2304.

[0079] Interposer 2304 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In some embodiments, interposer 2304 may be formed of alternating rigid or flexible materials, which may include the same materials as those described above for semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. Interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to TSVs 2306. Interposer 2304 may further include embedded devices 2314, including both passive and active devices. These devices may include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD protection devices, and memory devices. More complex devices such as additional RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on interposer 2304. In some embodiments, IC devices with vias having widened ends as described herein may also be implemented in / on interposer 2304. The package-on-interposer structure 2336 may take the form of any package-on-interposer structure known in the art.

[0080] IC device assembly 2300 may include an IC package 2324 coupled to first side 2340 of circuit board 2302 via coupling component 2322. Coupling component 2322 may take the form of any of the embodiments discussed above with reference to coupling component 2316, and IC package 2324 may take the form of any of the embodiments discussed above with reference to IC package 2320.

[0081] Figure 8 The IC device assembly 2300 shown in the figure includes a package-on-package structure 2334 coupled to the second side 2342 of the circuit board 2302 by a coupling component 2328. The package-on-package structure 2334 may include an IC package 2326 and an IC package 2332 coupled together by a coupling component, such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling components 2328 and 2330 may take the form of any embodiment of the coupling component 2316 discussed above, and the IC packages 2326 and 2332 may take the form of any embodiment of the IC package 2320 discussed above. The package-on-package structure 2334 may be configured according to any package-on-package structure known in the art.

[0082] Fig. 92400 may include one or more components including one or more IC devices with vias having widened ends, according to some embodiments of the present disclosure. For example, according to some embodiments of the present disclosure, any suitable component among the components of computing device 2400 may include a die (e.g., Figure 6B Any component of computing device 2400 may include an IC device (e.g., Figure 1 A and Figure 1 B) and / or IC packages (e.g., Figure 7 Any component of computing device 2400 may include an IC device component (e.g., Figure 8 IC device component 2300).

[0083] Multiple parts in Fig. 9 2400, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured on a single SoC (system on chip) die.

[0084] Additionally, in various embodiments, computing device 2400 may not include Fig. 9 , but computing device 2400 may include interface circuitry for coupling to one or more of the components. For example, computing device 2400 may not include display device 2406, but may include display device interface circuitry (e.g., connector and driver circuitry) to which display device 2406 may be coupled. In another set of examples, computing device 2400 may not include audio input device 2418 or audio output device 2408, but may include audio input or output device interface circuitry (e.g., connector and supporting circuitry) to which audio input device 2418 or audio output device 2408 may be coupled.

[0085] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 2402 may include one or more digital signal processors (DSPs), application specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 2404 may include a memory that shares a die with the processing device 2402. The memory may be used as a cache memory and may include, for example, eDRAM and / or spin transfer torque magnetic random access memory (STT-MRAM).

[0086] In some embodiments, computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, communication chip 2412 may be configured to manage wireless communications for transmitting data to and from computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not.

[0087] The communication chip 2412 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE802.16-2005 revision), Long Term Evolution (LTE) project and any revisions, updates and / or amendments (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband wireless access (BWA) networks compatible with IEEE 802.16 are generally referred to as WiMAX networks, which is an acronym standing for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed the conformance and interoperability testing of the IEEE 802.16 standard. The communication chip 2412 can operate according to the Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA) or LTE network. The communication chip 2412 may operate according to Enhanced Data GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and beyond. In other embodiments, the communication chip 2412 may operate according to other wireless protocols. The computing device 2400 may include an antenna 2422 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0088] In some embodiments, the communication chip 2412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2412 may include multiple communication chips. For example, the first communication chip 2412 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and the second communication chip 2412 may be dedicated to longer-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO or others. In some embodiments, the first communication chip 2412 may be dedicated to wireless communications, and the second communication chip 2412 may be dedicated to wired communications.

[0089] In various embodiments, the IC devices as described herein may be particularly advantageous for use as part of an ESD circuit to protect a power amplifier, a low noise amplifier, a filter (including filter arrays and filter banks), a switch, or other active components. In some embodiments, the IC devices as described herein may be used in a PMIC, for example, as a rectifier diode for high currents. In some embodiments, the IC devices as described herein may be used in audio devices and / or various input / output devices.

[0090] Computing device 2400 may include battery / power circuitry 2414. Battery / power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of computing device 2400 to an energy source separate from computing device 2400 (e.g., AC line power).

[0091] Computing device 2400 may include display device 2406 (or corresponding interface circuitry, as discussed above). Display device 2406 may include, for example, any visual indicator such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0092] Computing device 2400 may include audio output device 2408 (or corresponding interface circuitry, as discussed above). Audio output device 2408 may include, for example, any device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0093] Computing device 2400 may include audio input device 2418 (or corresponding interface circuitry, as discussed above). Audio input device 2418 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0094] Computing device 2400 may include GPS device 2416 (or corresponding interface circuitry, as discussed above). GPS device 2416 may communicate with a satellite-based system and may receive the location of computing device 2400, as is known in the art.

[0095] Computing device 2400 may include another output device 2410 (or corresponding interface circuitry, as discussed above). Examples of other output devices 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0096] The computing device 2400 may include another input device 2420 (or corresponding interface circuitry, as discussed above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0097] The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server device or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.

[0098] The following paragraphs provide various examples of the embodiments disclosed herein.

[0099] Example 1 provides an IC device, comprising: a support structure, the support structure comprising a semiconductor material, the support structure having a first surface and a second surface opposite to the first surface; a transistor, the transistor comprising a source region, a drain region, and an electrode above the source region or the drain region, wherein the source region or the drain region is at least partially in the support structure; a first conductive structure, the first conductive structure is above the support structure in a first direction, wherein the first conductive structure is closer to the first surface of the support structure than to the second surface of the support structure; and a second conductive structure, the second conductive structure having a first segment and a second segment, the first segment being connected to the first conductive structure, the second segment being coupled to the electrode of the transistor, and having a dimension along a second direction that is greater than a dimension of the first segment along the second direction, wherein the second direction is perpendicular to the first direction.

[0100] Example 2 provides the IC device of Example 1, wherein a dimension of the second segment is in a range from about 16 nanometers to about 32 nanometers.

[0101] Example 3 provides the IC device of Example 1 or 2, wherein a size of the first segment is in a range from about 10 nanometers to about 20 nanometers.

[0102] Example 4 provides the IC device of any of Examples 1-3, wherein a difference between a size of the first segment and a size of the second segment is in a range from about 6 nanometers to about 12 nanometers.

[0103] Example 5 provides an IC device according to any of Examples 1-4, wherein a distance from an edge of the second segment to an edge of the first segment in the second direction is in a range from about 3 nanometers to about 6 nanometers.

[0104] Example 6 provides an IC device according to any of Examples 1-5, wherein a dimension of the second segment in the first direction is in a range from about 5 nanometers to about 10 nanometers.

[0105] Example 7 provides an IC device according to any of Examples 1-6, wherein an angle between an edge of the second segment and an edge of the first segment is in a range from about 45 degrees to about 75 degrees.

[0106] Example 8 provides an IC device according to any of Examples 1-7, further comprising a third conductive structure connected to the second segment of the second conductive structure and to the electrode of the transistor.

[0107] Example 9 provides an IC device according to any of Examples 1-8, wherein the second conductive structure is at least partially in the support structure.

[0108] Example 10 provides an IC device according to any of Examples 1-9, further comprising an interconnect that is closer to the second surface of the support structure than to the first surface of the support structure, wherein the transistor further comprises a channel region and an additional electrode above the channel region, and the interconnect is coupled to the additional electrode.

[0109] Example 11 provides an IC device, comprising: a semiconductor structure having a first side and a second side; a power plane, the power plane being at the first side of the semiconductor structure; and a via, the via being coupled to a single transistor and the power plane, the via comprising a first end, the first end being closer to the first side of the semiconductor structure than the second side of the semiconductor structure, a second end, the second end being closer to the second side of the semiconductor structure than the first side of the semiconductor structure, and a body, the body being between the first end and the second end, the body extending in a first direction from the first side of the semiconductor structure to the second side of the semiconductor structure, wherein a size of the first end or the second end in the second direction is larger than a size of the body in the second direction, and the second direction is perpendicular to the first direction.

[0110] Example 12 provides the IC device of Example 11, further comprising a transistor at least partially in the semiconductor structure and comprising an electrode coupled to the via.

[0111] Example 13 provides the IC device of Example 12, wherein an electrode of the transistor is over a portion of the semiconductor structure.

[0112] Example 14 provides the IC device of Example 12 or 13, wherein the transistor further comprises an additional electrode coupled to the ground plane.

[0113] Example 15 provides an IC device according to any of Examples 11-14, wherein a difference between a dimension of the first end or the second end of the via and a dimension of the body of the via is in a range from about 6 nanometers to about 12 nanometers.

[0114] Example 16 provides an IC device according to any of Examples 11-15, wherein an angle between an edge of the first end or the second end of the via and an edge of the body of the via is in a range from about 45 degrees to about 75 degrees.

[0115] Example 17 provides an IC device, comprising a transistor, the transistor including a source region, a drain region, a channel region, a first electrode above the source region, a second electrode above the drain region, and a third electrode above the channel region; a jumper connected to the first electrode or the second electrode; a via, the via including a main body segment and an end segment, the end segment being connected to the jumper and being wider than the main body segment; and an interconnect connected to the via.

[0116] Example 18 provides the IC device of Example 17, wherein the end segment of the via is approximately 6 nanometers to approximately 12 nanometers wider than the body segment of the via.

[0117] Example 19 provides an IC device according to Example 17 or 18, wherein: the channel region of the transistor is in a semiconductor structure, the interconnect is closer to a first surface of the semiconductor structure than to a second surface of the semiconductor structure, and the first electrode, the second electrode, or the third electrode is closer to the second surface of the semiconductor structure than to the first surface of the semiconductor structure.

[0118] Example 20 provides an IC device according to any of Examples 17-19, wherein the via further comprises an additional end section connected to the interconnect and wider than the body section.

[0119] Example 21 provides an IC package, comprising an IC device according to any one of Examples 1-20; and another IC component coupled to the IC device.

[0120] Example 22 provides the IC package of Example 21, wherein the another IC component includes one of a package substrate, an interposer, or another IC die.

[0121] Example 23 provides an IC package according to Example 21 or 22, wherein the IC device may include or be a part of at least one of the following items: a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communication device.

[0122] Example 24 provides an electronic device comprising: a carrier substrate; and an IC package according to any of Examples 21-23, coupled to the carrier substrate.

[0123] Example 25 provides an electronic device according to Example 24, wherein the carrier substrate is a motherboard.

[0124] Example 26 provides an electronic device according to Example 24, wherein the carrier substrate is a PCB.

[0125] Example 27 provides an electronic device according to any one of Examples 24-26, wherein the electronic device is a wearable electronic device or a handheld electronic device.

[0126] Example 28 provides an electronic device according to any one of Examples 24-27, wherein the electronic device further includes one or more communication chips and an antenna.

[0127] Example 29 provides an electronic device according to any of Examples 24-28, wherein the electronic device is an RF transceiver.

[0128] Example 30 provides an electronic device according to any one of Examples 24-28, wherein the electronic device is one of: a switch, a power amplifier, a low noise amplifier, a filter, a filter bank, a duplexer, an upconverter, or a downconverter of an RF communication device (e.g., an RF transceiver).

[0129] Example 31 provides an electronic device according to any of Examples 24-30, wherein the electronic device is a computing device.

[0130] Example 32 provides an electronic device according to any of Examples 24-31, wherein the electronic device is included in a base station of a wireless communication system.

[0131] Example 33 provides an electronic device according to any of Examples 24-31, wherein the electronic device is included in a user equipment device of a wireless communication system.

[0132] The above description of the illustrated embodiments of the present disclosure (including the contents described in the summary) is not intended to be exhaustive or to limit the present disclosure to the disclosed precise form. Although the specific embodiments and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications within the scope of the present disclosure are possible as will be appreciated by those skilled in the relevant art. Based on the above detailed description, these modifications may be made to the present disclosure.

Claims

1. An integrated circuit (IC) device, comprising: a support structure comprising a semiconductor material, the support structure having a first surface and a second surface opposite the first surface; A transistor comprising a source region, a drain region, and an electrode over the source region or the drain region, wherein the source region or the drain region is at least partially in the support structure; a first conductive structure, the first conductive structure being above the support structure in a first direction, wherein the first conductive structure is closer to the first surface of the support structure than to the second surface of the support structure; and A second conductive structure, the second conductive structure having a first segment and a second segment, the first segment being connected to the first conductive structure, the second segment being coupled to the electrode of the transistor, and having a size along a second direction greater than a size of the first segment along the second direction, wherein the second direction is perpendicular to the first direction.

2. The IC device according to claim 1, wherein: The second segment has a size ranging from about 16 nanometers to about 32 nanometers.

3. The IC device according to claim 1 or 2, wherein: The first segment has a size ranging from about 10 nanometers to about 20 nanometers.

4. The IC device according to claim 1 or 2, wherein: A difference between a size of the first segment and a size of the second segment is in a range from about 6 nanometers to about 12 nanometers.

5. The IC device according to claim 1 or 2, wherein: A distance from an edge of the second segment to an edge of the first segment in the second direction is in a range from about 3 nanometers to about 6 nanometers.

6. The IC device according to claim 1 or 2, wherein: A dimension of the second segment in the first direction is in a range from about 5 nanometers to about 10 nanometers.

7. The IC device according to claim 1 or 2, wherein: An angle between an edge of the second segment and an edge of the first segment ranges from about 45 degrees to about 75 degrees.

8. The IC device according to claim 1 or 2, further comprising: A third conductive structure is connected to the second section of the second conductive structure and to the electrode of the transistor.

9. The IC device according to claim 1 or 2, wherein: The second conductive structure is at least partially within the support structure.

10. The IC device according to claim 1 or 2, further comprising: An interconnect is located closer to the second surface of the support structure than to the first surface of the support structure, wherein the transistor further comprises a channel region and an additional electrode over the channel region, and the interconnect is coupled to the additional electrode.

11. An integrated circuit (IC) device comprising: a semiconductor structure having a first side and a second side; a power plane at the first side of the semiconductor structure; as well as A via, the via being coupled to the power plane, the via comprising: a first end, the first end being closer to the first side of the semiconductor structure than the second side of the semiconductor structure, a second end, the second end being closer to the second side of the semiconductor structure than the first side of the semiconductor structure, and a body between the first end and the second end, the body extending in a first direction from the first side of the semiconductor structure to the second side of the semiconductor structure, The dimension of the first end or the second end in the second direction is greater than the dimension of the main body in the second direction, and the second direction is perpendicular to the first direction.

12. The IC device of claim 11, further comprising: A transistor is at least partially within the semiconductor structure and includes an electrode coupled to the via.

13. The IC device according to claim 12, wherein: An electrode of the transistor is over a portion of the semiconductor structure.

14. The IC device according to claim 12 or 13, wherein: The transistor also includes an additional electrode coupled to the ground plane.

15. The IC device according to any one of claims 11 to 13, wherein: A difference between a dimension of the first end of the via and a dimension of the body of the via is in a range from about 6 nanometers to about 12 nanometers.

16. The IC device according to any one of claims 11 to 13, wherein: A difference between a dimension of the second end of the via and a dimension of the body of the via is in a range from about 6 nanometers to about 12 nanometers.

17. The IC device according to any one of claims 11 to 13, wherein: An angle between an edge of the first end of the via and an edge of the body of the via ranges from about 45 degrees to about 75 degrees.

18. The IC device according to any one of claims 11 to 13, wherein: An angle between an edge of the second end of the via and an edge of the body of the via is in a range from about 45 degrees to about 75 degrees.

19. An integrated circuit (IC) device comprising: A transistor comprising a source region, a drain region, a channel region, a first electrode over the source region, a second electrode over the drain region, and a third electrode over the channel region; a jumper wire connected to the first electrode or the second electrode; a via, the via comprising a body section and an end section, the end section being connected to the jumper and being wider than the body section; as well as An interconnect is connected to the via.

20. The IC device of claim 19, wherein: The end section of the via is about 6 nanometers to about 12 nanometers wider than the body section of the via.

21. An IC device according to claim 19 or 20, wherein: The channel region of the transistor is in a semiconductor structure, and the interconnect is closer to a first surface of the semiconductor structure than to a second surface of the semiconductor structure.

22. The IC device of claim 21, wherein: Compared with the first surface of the semiconductor structure, the first electrode is closer to the second surface of the semiconductor structure.

23. The IC device of claim 21, wherein: Compared with the first surface of the semiconductor structure, the second electrode is closer to the second surface of the semiconductor structure.

24. The IC device of claim 21, wherein: Compared with the first surface of the semiconductor structure, the third electrode is closer to the second surface of the semiconductor structure.

25. The IC device according to claim 19 or 20, wherein: The via also includes an additional end section connected to the interconnect and wider than the body section.

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