A Space Vector Modulation Method and System for Inverters

Abstract

The present invention proposes an inverter space vector modulation method and system, belonging to the technical field of inverter modulation, including: Step 1: Exclude 9 voltage vectors with CMV amplitudes of ±udc / 3 and ±udc / 2 from the 27 voltage vectors, and construct a voltage space vector diagram based on the CMV amplitude and the influence of the key current direction for the remaining 19 voltage vectors. The voltage space vector diagram is divided into large sectors I to VI according to the angles of the α and β axes, and each large sector is divided into 4 small sectors. Among them, the medium vectors PON, OPN, NPO, NOP, ONP, and PNO are successively in the large sectors I to VI; Step 2: Based on the voltage space vector diagram, a non-nearest neighbor vector selection principle is proposed to achieve CMV suppression, ensure the continuity of the switching sequence, and control the neutral point voltage balance; Step 3: Based on the vector selection principle and the voltage space vector diagram, the CMV is suppressed by the 5-segment NNSVM modulation strategy and the 7-segment NNSVM modulation strategy, and the neutral point voltage of the NNSVM is balanced by the control algorithm.

Description

Technical Field

[0001] The present invention belongs to the technical field of inverter modulation, and particularly relates to a space vector modulation method and system for an inverter. Background Art

[0002] Three-level inverters have the advantages of low voltage stress, low harmonic content, high efficiency, etc., and are widely used in power transmission applications such as ship propulsion, rail transit, mine hoisting, wind power generation, steel rolling, water pumps, etc. The variable frequency speed regulation technology based on three-level PWM converters has become an effective way to improve the dynamic performance, steady-state accuracy, and harmonic performance of the system;

[0003] However, the existing three-level pulse width modulation (PWM) modulation will generate obvious high-frequency common-mode voltage (CMV) on the three-level inverter, generating high-frequency common-mode current on the parasitic capacitance, causing serious electromagnetic interference. At the same time, excessive CMV will damage the motor insulation, introduce common-mode current, cause the motor bearing to be eroded by the current and fail, and then cause problems such as increased motor vibration and broken motor rotor rings, greatly shortening the service life of the motor. Relevant research shows that motor damage caused by bearing failures accounts for 40% of the total damage, and 25% of bearing failures are caused by the common-mode voltage generated by the PWM converter.

[0004] In addition, the common-mode voltage has high-frequency characteristics and a large dv / dt, and the generated common-mode leakage current oscillation frequency is very high, up to several hundred kHz. When these high-frequency common-mode leakage currents flow back to the power grid through the grounding wire, strong common-mode electromagnetic interference (EMI) will be generated, affecting the normal operation of other control systems or electronic devices; if the amplitude of the common-mode leakage current is too large, it will also cause the protection circuit to malfunction, trigger the relay to trip and stop, affecting the stable operation of the system.

[0005] In order to suppress the amplitude of CMV, a large number of studies have been carried out, which can be divided into hardware-based methods and software control methods. The hardware-based methods can effectively reduce CMV, but will add additional hardware devices, increasing system cost and control complexity. In addition, the additional hardware will also bring negative effects such as higher efficiency loss and increased system failure rate.

[0006] Software control strategies can reduce the amplitude of CMV by optimizing the PWM strategy. The method based on SVM can be achieved by selecting vectors with lower common-mode voltage, such as LMZVM, LMSVM, VSVM, etc. The CMV suppression methods based on carrier modulation are all achieved by adjusting the carrier and modulation wave and injecting zero-sequence voltage. However, in the above-mentioned common-mode voltage suppression methods of carrier modulation and SVM, many redundant voltage vectors are abandoned, limiting the modulation range or increasing the switching frequency and converter losses, and at the same time losing the ability to balance the midpoint voltage of the three-level inverter, restricting the popularization and use of software CMV suppression strategies. Summary of the Invention

[0007] In view of this, the present invention provides a space vector modulation method and system for an inverter to solve the problems in the prior art that in the common-mode voltage suppression methods of carrier modulation and SVM, many redundant voltage vectors are abandoned, restricting the modulation range or increasing the switching frequency and converter losses, and at the same time losing the balancing ability of the neutral point voltage of the three-level inverter, restricting the popularization and use of the software CMV suppression strategy.

[0008] The technical solution adopted by the present invention is as follows:

[0009] A space vector modulation method for an inverter, comprising:

[0010] Step 1: Exclude 8 voltage vectors with CMV amplitudes of ±udc / 3 and ±udc / 2 from 27 voltage vectors, and construct a voltage space vector diagram based on the influence of the CMV amplitude and the direction of the key current for the remaining 19 voltage vectors. The space vector diagram is a hexagon, and the space vector diagram is divided into large sectors I to VI according to the angles of the α and β axes. Each large sector is divided into 4 small sectors. Among them, the medium vectors PON, OPN, NPO, NOP, ONP, and PNO are successively in large sectors I to VI;

[0011] Large sectors I to VI are equilateral triangles, and the angle of each large sector is 60 degrees. Set u s as the reference voltage and θ as the phase angle, and calculate u s in the α-β coordinate system, as shown in the following formula:

[0012]

[0013] Among them, the boundary conditions for small sector division satisfy the following formula:

[0014] θ>π / 6 (2)

[0015]

[0016] When the reference voltage u s does not satisfy formula (2) but satisfies formula (3), it belongs to the I1 small sector. When the reference voltage u s satisfies formula (2) but does not satisfy formula (4), it belongs to the I2 small sector. When the reference voltage u s does not satisfy formula (2) and formula (3), it belongs to the I3 small sector. When the reference voltage u s satisfies formula (2) and formula (4), it belongs to the I4 small sector.

[0017] Step 2: Based on the voltage space vector diagram, propose the principle of non - nearest - neighbor vector selection to achieve CMV suppression, ensure the continuity of the switching sequence, and control the neutral - point voltage balance;

[0018] Step 3: Based on the vector selection principle and the voltage space vector diagram, suppress CMV through the 5 - segment NNSVM modulation strategy and the 7 - segment NNSVM modulation strategy, and balance the neutral - point voltage of NNSVM through the control algorithm.

[0019] In Step 3, the principle of nearest - neighbor vector selection includes:

[0020] In each large sector, select the middle vector as the common vector for 4 small sectors. At the same time, select the middle vector as the starting vector and the ending vector within each switching period to ensure the continuity of the inverter operation during different switching periods;

[0021] To reduce switching losses, each switching device is only allowed to switch once within a single switching period;

[0022] In each switching period, a pair of voltage vectors with opposite neutral - point current directions must be included, and then the neutral - point voltage balance can be adjusted by adjusting the duty cycle T of this pair of vectors.

[0023] In Step 3, the specific method of suppressing CMV through the 5 - segment NNSVM modulation strategy includes:

[0024] Step A1: When u s is located in Sector I1, successively use u PON , u OOO and u ONO vectors to synthesize the reference voltage u s , and u s and the selected voltage vectors satisfy the following formula:

[0025]

[0026] where d 1,I , d 2,1 and d 3,I represent the duty cycles of u PON , u OOO and u ONO . Project these vectors onto the α - β axis, and Equation (2) can be transformed into:

[0027]

[0028] When the reference voltage u s is located in Sector I3, u PON , u PNN and u ONO vectors will be used for modulation, and the voltage synthesis rule is expressed as:

[0029]

[0030] Step A2: Obtain the switching sequences when the reference voltage is in Sector I1 and Sector I3 according to Equations (6) and (7);

[0031] Step A3: When the reference voltage u s is in other sectors, obtain the corresponding switching sequences based on Steps A1 - A2.

[0032] In Step 3, suppressing CMV through the 7 - segment NNSVM modulation strategy specifically includes:

[0033] Step B1: To ensure that the devices in the three - phase bridge arms are switched in sequence, one more switching state is introduced within one switching period. Specifically, in Sector I1, vector u POO is inserted between u PON and u OOO where the voltage vectors u POO , u ONO and u PON satisfy the following relational expressions:

[0034]

[0035] Step B2: Set the new voltage synthesis rule for Sector I1, expressed as:

[0036]

[0037] where d is the duty cycle of the vector, d 1,II to d 4,II are the duty cycles of u PON , u POO , u OOO , u ONO respectively, d min represents the minimum value of d 1,I and d 3,I , and k is the factor for replacing the original vector with the new vector;

[0038] Step B3: Insert vector u PNO in Sector I3 to obtain the new state sequence as PON - PNN - PNO - ONO, and the duty cycles of PON - PNN - PNO - ONO are d 1,II to d 4,II respectively. On the space vector plane, the voltage vectors u PON , u PNO , u PNN , u POO satisfy the following relational expressions:

[0039]

[0040] Step B4: Substitute Equation (8) into Equation (10) to obtain u while ensuring that the total duty cycle and norm remain unchanged. PON , u PNO , u PNN and u ONO satisfy the following relational expressions:

[0041]

[0042] Step B5: Replace some u PNN and u ONO in (7) according to Equation (11) to introduce the vector u PNO .

[0043] When d 3,I < 2d 2,I , 1 / 4d 3,I is used to synthesize the vector u PNO , and the new duty cycles of each vector in the I3 sector are:

[0044]

[0045] When d 3,I > 2d 2,I , d 2,I 's 1 / 2 is used to synthesize u PNO , and the duty cycles of each vector in the I3 sector are:

[0046]

[0047] Step B6: Obtain the switching sequences where the reference voltage is located in the I1 sector and the I3 sector according to Equation (9), Equation (12), and Equation (13).

[0048] In Step 3, balancing the midpoint voltage through the control algorithm specifically includes:

[0049] Obtain the upper capacitor voltage in the DC bus as u dc1 , the lower capacitor voltage as u dc2 , and the pressure difference Δu between the upper and lower capacitors can be expressed as:

[0050] Δu = u dc1 - u dc2 (14)

[0051] If the midpoint voltage is balanced, |Δu| < 0.01u dc , the duty cycles of each vector remain unchanged;

[0052] When the midpoint voltage is unbalanced, that is, |Δu| > 0.01u dc, the NP voltage should be controlled by adjusting the duty ratios of the starting middle vector and the intermediate small vectors within the switching period. The adjusted duty ratios are as follows:

[0053]

[0054] In the formula, d1 is the duty ratio of the starting middle vector, d n is the duty ratio of the starting middle vector, m is the neutral point voltage adjustment factor, where m is set to 0.5, i N is the neutral point current. In the I and IV large sectors, i N = i b ; in the II and V large sectors, i N = i a ; in the III and VI large sectors, i N = i c ;

[0055] Adjusting the duty ratios of a pair of middle vectors and small vectors according to Equation (15) can achieve the adjustment of the neutral point voltage.

[0056] An inverter space vector modulation system includes:

[0057] Vector diagram setting module: Exclude 8 voltage vectors with CMV amplitudes of ±udc / 3 and ±udc / 2 from the 27 voltage vectors, and construct a voltage space vector diagram based on the CMV amplitude and the influence of the key current direction for the remaining 19 voltage vectors. The voltage space vector diagram is divided into large sectors I to VI according to the angles of the α and β axes, and each large sector is divided into 4 small sectors. Among them, the middle vectors PON, OPN, NPO, NOP, ONP, and PNO are successively in the large sectors I to VI;

[0058] Principle setting module: Propose a non - nearest - neighbor vector selection principle based on the voltage space vector diagram to achieve CMV suppression, ensure the continuity of the switching sequence, and control the neutral point voltage balance;

[0059] Control module: Based on the vector selection principle and the voltage space vector diagram, suppress CMV through the 5 - segment NNSVM modulation strategy and the 7 - segment NNSVM modulation strategy, and balance the NNSVM neutral point voltage through the control algorithm.

[0060] In summary, due to the adoption of the above - mentioned technical solutions, the beneficial effects of the present invention are:

[0061] (1) Common-mode voltage amplitude suppression: The CMV amplitude of the proposed NNSVM modulation strategy is only 50% of that of the traditional SVM modulation strategy. Without adding additional hardware, the suppression of the CMV amplitude is achieved only through software control. Therefore, the use of this method is not limited by the three-level converter structure and is applicable to various types of three-level converters. The method is simple and easy to implement;

[0062] (2) Neutral-point voltage balance control: The traditional three-level modulation algorithm to achieve neutral-point voltage balance control completely depends on redundant small vectors, while the existing three-level common-mode voltage suppression modulation algorithms abandon redundant small vectors, such as LMZVM, LMSVM, VSVM. Therefore, the existing three-level SMV suppression algorithms have poor neutral-point voltage balance ability and poor applicability. In the newly proposed NNSVM, a pair of medium vectors and small vectors with opposite neutral-point current directions are used to adjust the neutral-point voltage. While suppressing the CMV amplitude, the balance of the neutral-point voltage can be ensured. Compared with the traditional SVM, the new method has a smaller amplitude of neutral-point voltage fluctuation and stronger neutral-point voltage balance ability;

[0063] (3) Small inverter losses: The CMV amplitude in the inverter is reduced, the losses caused by stray inductance parameters are reduced, and the switching frequency of the inverter is not increased. Therefore, compared with the traditional SVM modulation method, the proposed NNSVM modulation method makes the inverter have higher efficiency. Brief Description of the Drawings

[0064] The present invention will be described by way of examples and with reference to the accompanying drawings, wherein:

[0065] Figure 1 is the voltage space vector diagram of the present invention;

[0066] Figure 2 is the large sector I space vector diagram of the NNSVM-5 modulation strategy of the present invention;

[0067] Figure 3 is the switching sequence of the I sector of the NNSVM-5 modulation strategy of the present invention;

[0068] Figure 4 is the large sector I space vector diagram of the NNSVM-7 modulation strategy of the present invention;

[0069] Figure 5 is the switching sequence of the I sector of the NNSVM-5 modulation strategy of the present invention;

[0070] Figure 6 is the experimental block diagram of the present invention;

[0071] Figure 7 is the experimental effect comparison diagram of the three modulation algorithms of the present invention under different carrier ratios;

[0072] Figure 8 This is a comparison chart of the neutral point voltage balancing capabilities among three modulation algorithms of the present invention. Detailed implementation manners

[0073] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Generally, the components of the embodiments of the present invention described and illustrated herein can be arranged and designed in various different configurations.

[0074] Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0075] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0076] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0077] In the present invention, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may include direct contact between the first and second features, or may include indirect contact between the first and second features through additional features therebetween. Moreover, the first feature being "above", "over", and "on top of" the second feature includes the first feature being directly above and diagonally above the second feature, or merely indicating that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "below", and "beneath" the second feature includes the first feature being directly below and diagonally below the second feature, or merely indicating that the horizontal height of the first feature is lower than that of the second feature.

[0078] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0079] Embodiment 1

[0080] As Figures 1 - 4 shown, an inverter space vector modulation method is disclosed in an embodiment of the present invention, including:

[0081] Step 1: Each phase of a three-phase three-level inverter can output three levels, namely P, O, and N, and the corresponding output voltages are +udc / 2, 0, and -u dc / 2, where u dc is the DC bus voltage. Therefore, the three-level inverter has a total of 3 3 types, namely 27 voltage vectors u xxx (x = P, O, N). To suppress the CMV amplitude, voltage vectors with CMV amplitudes of ±udc / 3 (u PPO , u POP , u OPP , u NNO , u NON , u ONN ) and ±udc / 2 (u PPP , u NNN ) should be excluded in the modulation algorithm. In addition, neutral point voltage balance is also an important control objective of the three-level inverter. Only small vectors and medium vectors in the remaining vectors will affect the neutral point voltage. Therefore, when selecting vectors, the influence of the current directions of small and medium vectors on the neutral point voltage also needs to be considered. Considering the influence of CMV amplitude and midpoint current direction comprehensively, a voltage space vector diagram as shown in Figure 1 is reconstructed. The voltage space plane is divided into large sectors I - VI according to the angles of the α and β axes, and each large sector is further divided into small sectors 1 - 4. The 19 voltage vectors in the figure can be divided into large vectors, medium vectors, small vectors, and zero vectors according to their amplitudes. Among them, the large vectors correspond to a voltage amplitude of 2udc / 3, the medium vectors correspond to a voltage amplitude of the small vectors correspond to a voltage amplitude of udc / 3, and the zero vectors have a voltage amplitude of zero. And there is a midpoint current when medium vectors and small vectors act. Among them, the positive midpoint current is represented by a solid line when it is positive, and by a dotted line when the midpoint current is negative. Taking the medium vector PON as an example, the A-phase outputs the P voltage state, the B-phase outputs the O voltage state, the C-phase outputs the N voltage state, and the currents i a , i c do not flow through the midpoint of the inverter, and the current i b flows through the midpoint of the inverter. Similarly, the midpoint currents under the action of other vectors can be obtained. The boundary conditions for the small sector division satisfy the following formulas:

[0082] θ > π / 6 (2)

[0083]

[0084] Formula 2 represents the straight line composed of OOO and PON. If it satisfies Formula 2, it is above this line; otherwise, it is below this line. Formula 3 represents the straight line composed of POO and PON. If it satisfies Formula 3, it is to the left of this line; otherwise, it is to the right of this line. Formula 4 represents the straight line composed of OON and PON. If it satisfies Formula 4, it is above this line; otherwise, it is below this line. When the reference voltage u sWhen the condition of Equation (2) is not satisfied but the condition of Equation (3) is satisfied, it belongs to the I1 small sector; the reference voltage u s When the condition of Equation (2) is satisfied but the condition of Equation (4) is not satisfied, it belongs to the I2 small sector; the reference voltage u s When the conditions of Equation (2) and Equation (3) are not satisfied, it belongs to the I3 small sector; the reference voltage u s When the conditions of Equation (2) and Equation (4) are satisfied, it belongs to the I4 small sector.

[0085] The functional relationship between CMV and the three-phase switch is as follows:

[0086] u CMV =(S a +S b +S c )u dc / 6;

[0087] Among them, Sa, Sb, and Sc represent the three-phase switch states. Each phase has three output states: P, O, and N, where P = 1, O = 0, and N = -1. Therefore, Sa, Sb, Sc ∈ (-1, 0, 1);

[0088] Step 2: In order to achieve CMV suppression, ensure the continuity of the switching sequence, and control the neutral point voltage balance, the non-nearest neighbor vector selection principle is proposed:

[0089] In each large sector, the middle vector is selected as the common vector for the 4 small sectors. At the same time, selecting the middle vector as the starting vector and the ending vector within each switching period can ensure the continuity of the inverter actions during different switching periods.

[0090] To reduce the switching loss, each switching device is only allowed to switch once in a single switching period.

[0091] In each switching period, a pair of voltage vectors with opposite midpoint current directions must be included, and then the neutral point voltage balance can be adjusted by adjusting the duty cycle T of this pair of vectors.

[0092] Step 3: Combining the above vector selection principle with the new voltage space vector plane diagram, a new 5-segment and 7-segment NNSVM modulation strategy is proposed. Before introducing NNSVM, it is necessary to derive the traditional three-level SVM modulation strategy.

[0093] (I) Five-segment NNSVM (NNSVM-5)

[0094] Due to the symmetry of the voltage space vector plane diagram, only the voltage modulation process in the large sector I is analyzed. Figure 2 The selected voltage vectors in the large sector I are given, where u s is the reference voltage, θ is the phase angle, and u s in the α-β coordinate system can be calculated as

[0095]

[0096] When u s is located in the I1 sector, the reference voltage for vector synthesis u PON , u OOO and u ONO is used in sequence, and u s , u s and the selected voltage vectors satisfy the following formula

[0097]

[0098] where d 1,I , d 2,1 and d 3,I represent the duty cycles of u PON , u OOO and u ONO . Projecting these vectors onto the α-β axis, Equation (2) can be transformed into

[0099]

[0100] Similarly, when the reference voltage u s is located in the I3 sector, u PON , u PNN and u ONO vectors are used for modulation, and the voltage synthesis rule can be expressed as

[0101]

[0102] According to Equation (6) and Equation (7), the switching sequences of the reference voltage in the I1 sector and the I3 sector can be obtained. As shown in Figure 3 , by applying the switching sequence in Figure 3 , the CMV amplitude is suppressed to ±1 / 6u dc . However, there is a situation where two-phase devices switch simultaneously in the 5-segment NNSVM, which easily leads to a high total harmonic distortion. Therefore, a 7-segment NNSVM (NNSVM-7) is improved based on the NNSVM-5.

[0103] (II) 7-segment NNSVM (NNSVM-7)

[0104] As shown in Figure 4 , to ensure that the devices in the three-phase bridge arms switch sequentially, NNSVM-7 introduces one more switching state in a switching cycle. Specifically, compared with NNSVM-5, in the I1 sector, the vector u POO is inserted between u PON and u OOO . Among them, the voltage vector u POO , uONO and u PON satisfy the following relational expressions

[0105]

[0106] where d is the duty cycle of the vector. It can be seen from Equation (8) that, on the premise of keeping the duty cycle and norm unchanged, part of u in Equation (3) PON and u ONO can be replaced by u POO Therefore, in NNSVM-7, the new voltage synthesis rule for Sector I1 can be expressed as

[0107]

[0108] where d 1,II to d 4,II are respectively the duty cycles of u PON , u POO , u OOO , u ONO , d min represents the minimum value of d 1,I and d 3,I , and k is the factor for replacing the original vector with the new vector.

[0109] Insert the vector u PNO in Sector I3, and the new state sequence is PON-PNN-PNO-ONO, and their duty cycles are d 1,II to d 4,II . On the space vector plane, the voltage vectors u PON , u PNO , u PNN , u POO satisfy the following relational expressions

[0110]

[0111] Substitute Equation (8) into Equation (10). On the premise of ensuring that the total duty cycle and norm remain unchanged, we can obtain that u PON , u PNO , u PNN , u ONO satisfy the following relational expressions

[0112]

[0113] According to Equation (11), replace part of u PNN and u ONO in (7), and the vector u PNO can be introduced. When d 3,I < 2d 2,I , 1 / 4d 3,I is used to synthesize the vector uPNO , in the I3 sector, the new duty cycle of each vector is

[0114]

[0115] When d 3,I > 2d 2,I , d 2,I 1 / 2 of is used to synthesize u PNO , in the I3 sector, the duty cycle in each vector is

[0116]

[0117] According to Equation (9), Equation (12) and Equation (13), the switching sequences when the reference voltage is in the I1 sector and the I3 sector can be obtained. As Figure 5 shown, by applying the switching sequence in Figure 5 , the CMV amplitude is suppressed to ±1 / 6u dc , and the switching tubes of each phase act in sequence, which is beneficial to reducing the current harmonic content.

[0118] (III) NNSVM Neutral Point Voltage Balancing Control Algorithm

[0119] In each switching cycle of NNSVM, Figure 3 and Figure 5 the starting middle vector and the middle small vector in have opposite neutral point currents i N , therefore, the neutral point voltage balance can be adjusted by manipulating the duty cycles of the two vectors. The upper capacitor voltage in the DC bus is u dc1 , the lower capacitor voltage is u dc2 , and the voltage difference Δu between the upper and lower capacitors can be expressed as

[0120] Δu = u dc1 - u dc2 . (14)

[0121] If the neutral point voltage is balanced, |Δu| < 0.01u dc , the duty cycle of each vector remains unchanged. When the neutral point voltage is unbalanced, that is, |Δu| > 0.01u dc , the NP voltage should be controlled by adjusting the duty cycles of the starting middle vector and the middle small vector within the switching cycle. The adjusted duty cycles are

[0122]

[0123] where d1 is the duty cycle of the starting middle vector, d n is the duty cycle of the starting middle vector, m is the neutral point voltage adjustment factor, and m is set to 0.5 here. The relationship between the neutral point current i N and the large sector is shown in Table 1. In the I and IV large sectors, iN = i b ; in the second and fifth major sectors, i N = i a ; in the third and sixth major sectors, i N = i c .

[0124] Table 1 Midpoint current in the major sectors

[0125]

[0126] Adjusting the duty cycles of a pair of medium vectors and small vectors according to Equation (15) can achieve the regulation of the midpoint voltage.

[0127] Example 2

[0128] In order to verify the effectiveness of the NNSVM-5 and NNSVM-7 strategies, tests were carried out on the motor back-to-back test platform driven by a three-level inverter. The experimental principle block diagram is as Figure 6 shown. The motor control algorithm uses MTPA control. The d-q axis reference voltages output by the motor control algorithm are input to the NNSVM module. The NNSVM module calculates according to the reference voltage signal and outputs a PWM signal to control the three-level inverter to drive the motor.

[0129] (1) Verification of CMV amplitude suppression ability

[0130] In order to verify the effectiveness of the NNSVM-5 and NNSVM-7 strategies, a comparative study was carried out under different carrier frequencies f c under the conditions of 600 rpm and 25 N·m load torque in the electric drive system. The experimental results are as Figure 7 shown.

[0131] For the proposed NNSVM strategy, the THD is significantly affected by the carrier frequency. Although its THD is relatively high at low carrier frequencies, when the carrier frequency exceeds 5 kHz, the THD of NNSVM-7 decreases significantly. The CMV amplitude of the proposed NNSVM is suppressed to 50% of the traditional SVM. The oscillation amplitude of the midpoint voltage of the traditional SVM is 2.84 V, and the midpoint oscillation amplitudes of NNSVM-5 and NNSVM-7 are 1.59 V and 1.57 V respectively.

[0132] (2) Verification of midpoint voltage balance ability

[0133] In order to verify the effectiveness of the proposed algorithm, a comparative experiment was carried out with the traditional SVM. The experimental results are as Figure 8 shown. The motor load torque is controlled at 20 N·m and the speed is 600 rpm. In the figure, u off,x (x = 1, 2) represents the capacitor voltage and 1 / 2u dcThe offset between them. For traditional SVM, the amplitude of its CMV is ±80V (±ud c / 3). For NNSVM-5 and NNSVM-7, the amplitude of CMV is ±40V (±u dc / 6), which is 50% lower than that of traditional SVM. At the same time, the difference between the starting upper and lower capacitor voltages of the three modulation strategies is 24V (10%u dc ), activating the midpoint balance algorithm in the three modulation strategies, and their midpoint voltages quickly return to the balanced state. The measured CMV amplitude, midpoint voltage fluctuation amplitude and inverter efficiency are shown in Table 2. It can be seen from the table that the midpoint voltage fluctuation and working efficiency of the two proposed NNSVM modulation strategies are better than those of traditional SVM, and the modulation range is not reduced.

[0134] Table 2 Comparison of experimental results of different modulation strategies

[0135]

[0136] Example 3

[0137] This example proposes an inverter space vector modulation system, including:

[0138] Vector diagram setting module: Exclude 8 voltage vectors with CMV amplitudes of ±udc / 3 and ±udc / 2 from 27 voltage vectors, and construct a voltage space vector diagram based on the influence of CMV amplitude and key current direction for the remaining 19 voltage vectors. The voltage space vector diagram is divided into large sectors I to VI according to the angles of the α and β axes, and each large sector is divided into 4 small sectors. Among them, the medium vectors PON, OPN, NPO, NOP, ONP and PNO are successively in the large sectors I to VI;

[0139] Principle setting module: Propose a non-nearest neighbor vector selection principle based on the voltage space vector diagram to achieve CMV suppression, ensure the continuity of the switching sequence and control the neutral point voltage balance;

[0140] Control module: Based on the vector selection principle and the voltage space vector diagram, suppress CMV through the 5-segment NNSVM modulation strategy and the 7-segment NNSVM modulation strategy, and balance the midpoint voltage of NNSVM through the control algorithm.

[0141] The circuits, electronic components and modules involved are all existing technologies, which can be fully realized by those skilled in the art without further elaboration. The content protected by the present invention does not involve improvements to software and methods.

[0142] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same and similar parts among the embodiments can be referred to each other.

[0143] The foregoing description of the disclosed embodiments enables those skilled in the art to practice or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A space vector modulation method for an inverter, characterized in that, The method is applied to a three-level inverter and includes: Step 1: Exclude 8 voltage vectors with CMV amplitudes of ±udc / 3 and ±udc / 2 from 27 voltage vectors, and construct a voltage space vector diagram with the remaining 19 voltage vectors according to the influence of CMV amplitude and key current direction. The space vector diagram is a hexagon, and the space vector diagram is divided into large sectors I to VI according to the angles of the α and β axes. Each large sector is divided into 4 small sectors. Among them, the medium vectors PON, OPN, NPO, NOP, ONP, and PNO are successively in large sectors I to VI; Step 2: Based on the voltage space vector diagram, a non-nearest neighbor vector selection principle is proposed to achieve CMV suppression, ensure the continuity of the switching sequence, and control the neutral point voltage balance; Step 3: Based on the vector selection principle and the voltage space vector diagram, suppress CMV through a 5-segment NNSVM modulation strategy and a 7-segment NNSVM modulation strategy, and balance the neutral point voltage of NNSVM through a control algorithm; In Step 3, the nearest neighbor vector selection principle includes: In each large sector, select the medium vector as the common vector of 4 small sectors. At the same time, select the medium vector as the starting vector and the ending vector within each switching period to ensure the continuity of the inverter operation during different switching periods; To reduce switching losses, each switch is only allowed to switch once within a single switching period; In each switching period, a pair of voltage vectors with opposite neutral point current directions must be included, and then the neutral point voltage balance is adjusted by adjusting the duty cycle d of this pair of vectors; Large sectors I to VI are equilateral triangles, and the angle of each large sector is 60 degrees. In the large sector Set u in I s as the reference voltage, θ as the phase angle, and calculate u in the α-β coordinate system s , as shown in the following equation Among them, the boundary conditions for small sector division satisfy the following formula: θ>π / 6 (2) When the reference voltage u s does not satisfy Equation (2) but satisfies Equation (3), it belongs to the I1 small sector, and the reference voltage u s satisfies Equation (2) but does not satisfy Equation (4), it belongs to the I2 small sector, and the reference voltage u s does not satisfy Equation (2) and Equation (3), it belongs to the I3 small sector, and the reference voltage u s satisfies Equation (2) and Equation (4), it belongs to the I4 small sector.

2. The space vector modulation method of an inverter according to claim 1, characterized in that In Step 3, suppressing CMV through a 5-segment NNSVM modulation strategy specifically includes: Step A1: When u s is located in the I1 sector, successively use u PON , u OOO and u ONO to synthesize the reference voltage u s , u s and the selected voltage vectors satisfy the following formula: where d 1,I , d 2,1 and d 3,I represent the duty cycles of u PON , u OOO and u ONO . Project these vectors onto the α-β axis and convert Equation (2) to: When the reference voltage u s is in the I3 sector, u PON , u PNN and u ONO vectors will be used for modulation, and the voltage synthesis rule is expressed as: Step A2: Obtain the switching sequence with the reference voltage located in sectors I1 and I3 according to Equations (6) and (7); Step A3: When the reference voltage u s is in other sectors, obtain the corresponding switching sequence based on Steps A1 - A2.

3. A space vector modulation method for an inverter according to claim 1, characterized in that In Step 3, suppressing CMV through a 7-segment NNSVM modulation strategy specifically includes: Step B1: To ensure that the devices in the three-phase bridge arms are switched sequentially, one more switching state is introduced within one switching period, specifically including inserting vector u in Sector I1 POO between u PON and u OOO , where voltage vectors u POO , u ONO and u PON satisfy the following relational expressions: Step B2: Set a new voltage synthesis rule for sector I1, expressed as: where d is the duty cycle of the vector, d 1,II to d 4,II are respectively the duty cycles of u PON , u POO , u OOO , u ONO . d min represents the minimum value between d 1,I and d 3,I , and k is the factor for replacing the original vector with a new vector; Step B3: Insert the vector u into sector I3 PNO , and obtain a new state sequence as PON-PNN-PNO-ONO. The duty cycles of PON-PNN-PNO-ONO are d 1,II to d 4,II . On the space vector plane, the voltage vectors u PON , u PNO , u PNN , u POO satisfy the following relational expressions: Step B4: Substitute Equation (8) into Equation (10) to obtain u on the premise of ensuring that the total duty cycle and the norm remain unchanged PON , u PNO , u PNN and u ONO satisfy the following relational expressions: Step B5: Replace part of u in (7) according to Equation (11) PNN and u ONO to introduce vector u PNO ; When d 3,I <2d 2,I , 1 / 4d 3,I For synthesizing vector u PNO , the new duty ratios of the vectors in sector I3 are as follows: When d 3,I > 2d 2,I , d 2,I 1 / 2 of which is used to synthesize u PNO , and the duty cycle in each vector in the I3 sector is as follows: Step B6: Obtain the switching sequence with the reference voltage located in sectors I1 and I3 according to Equations (9), (12), and (13).

4. A space vector modulation method for an inverter according to claim 3, wherein In Step 3, balancing the neutral point voltage of NNSVM through a control algorithm specifically includes: Obtain the voltage of the upper capacitor in the DC bus as u dc1 , and the voltage of the lower capacitor as u dc2 . The voltage difference Δu between the upper and lower capacitors is expressed as: Δu = u dc1 -u dc2 (14) If the midpoint voltage is balanced and |Δu| < 0.01u dc , the duty cycle of each vector remains unchanged; When the midpoint voltage is unbalanced, i.e., |Δu|>0.01u dc , the NP voltage should be controlled by adjusting the duty cycles of the starting middle vector and the intermediate small vectors within the switching period. The adjusted duty cycles are as follows: where d1 is the duty cycle of the starting medium vector, d n is the duty cycle of the starting medium vector, m is the neutral point voltage regulation factor, where m is set to 0.5, i N is the neutral point current. In sectors I and IV, i N = i b ; in sectors II and V, i N = i a ; in sectors III and VI, i N = i c ; Adjust the duty cycles of a pair of medium vectors and small vectors according to Equation (15) to achieve the adjustment of the neutral point voltage.

5. An inverter space vector modulation system for implementing the inverter space vector modulation method according to any one of claims 1-4, characterized in that, It includes: Vector diagram setting module: Exclude 8 voltage vectors with CMV amplitudes of ±udc / 3 and ±udc / 2 from 27 voltage vectors, and construct a voltage space vector diagram with the remaining 19 voltage vectors according to the influence of CMV amplitude and key current direction. The voltage space vector diagram is divided into large sectors I to VI according to the angles of the α and β axes. Each large sector is divided into 4 small sectors. Among them, the medium vectors PON, OPN, NPO, NOP, ONP, and PNO are successively in large sectors I to VI; Principle setting module: Based on the voltage space vector diagram, a non-nearest neighbor vector selection principle is proposed to achieve CMV suppression, ensure the continuity of the switching sequence, and control the neutral point voltage balance; Control module: Based on the vector selection principle and the voltage space vector diagram, CMV is suppressed through the 5-segment NNSVM modulation strategy and the 7-segment NNSVM modulation strategy, and the neutral point voltage of NNSVM is balanced through the control algorithm.

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