Power-on reset detection circuit and chip

Abstract

The invention relates to the technical field of integrated circuits, and discloses a power-on reset detection circuit, comprising: a bias generation circuit comprising a bias resistor and a second MOS tube which are connected in series, the bias resistor being connected with a power supply voltage to generate a bias voltage; wherein the second MOS tube works in a sub-threshold region; the detection circuit comprises a first resistor, a first MOS tube and a second resistor which are sequentially connected in series; the grid electrode of the first MOS tube is connected with the bias voltage generated by the bias generation circuit, and the drain electrode voltage of the first MOS tube is used as the detection point voltage of the power supply voltage; and the comparison circuit is respectively connected with the bias voltage of the bias generation circuit and the detection point voltage of the detection circuit, and is used for comparing the bias voltage and the detection point voltage. The detection circuit is helpful for reducing the discrete range of power supply voltage detection by the power-on reset detection module, so that the reset voltage of the chip does not change along with the temperature. The invention also discloses a chip.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, for example, to a power-on reset detection circuit and chip. Background Art

[0002] The power-on reset detection circuit is used to provide a reset signal to the chip to prevent the chip from continuing to work in an environment where the power supply voltage is too low (undervoltage). Since the power-on reset detection circuit has a certain discrete range for detecting the power supply voltage, the highest value of its detection voltage is generally set to the lowest operating voltage of the chip. However, for NVM (Non-Volatile Memory) chips, after the reset signal of the power-on reset detection circuit is released, it enters the working mode. This means that the actual operating voltage of the internal circuit of the chip must be able to drop to the lowest value of the reset detection circuit detection voltage, otherwise it will cause the NVM chip to have functional abnormalities in certain working scenarios.

[0003] If the operating voltage of the internal circuit of the chip is lowered, it will inevitably lead to increased design difficulty and cost, and the chip's usage scenario does not support increasing the chip's minimum operating voltage. Summary of the invention

[0004] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0005] The embodiments of the present disclosure provide a power-on reset detection circuit and a chip to reduce the discrete range of power supply voltage detection by a power-on reset detection module, thereby enabling the internal circuits of the chip to operate at a higher voltage.

[0006] In some embodiments, the circuit includes: a bias generating circuit, including a bias resistor and a second MOS tube connected in series, the bias resistor is connected to a power supply voltage to generate a bias voltage; wherein the second MOS tube operates in a subthreshold region; a detection circuit, including a first resistor, a first MOS tube and a second resistor connected in series in sequence; the gate of the first MOS tube is connected to the bias voltage generated by the bias generating circuit, and the drain voltage of the first MOS tube is used as a detection point voltage of the power supply voltage; a comparison circuit, respectively connected to the bias voltage of the bias generating circuit and the detection point voltage of the detection circuit, for comparing the magnitude of the bias voltage and the detection point voltage.

[0007] In some embodiments, the chip includes: a chip body, and a power-on reset detection circuit as described above, connected to the chip body; wherein the chip body enters an operating mode when the power-on reset detection circuit outputs a reset signal; when the detection point voltage is greater than a preset voltage, the power-on reset detection circuit outputs a reset signal.

[0008] The power-on reset detection circuit and chip provided by the embodiments of the present disclosure can achieve the following technical effects:

[0009] Through the design of the bias generation circuit and the detection circuit, the detection point voltage has a temperature compensation function. That is, the detection point voltage does not change with temperature and is relatively constant to the power supply voltage. This helps to reduce the discrete range of the power supply voltage detection of the power-on reset detection module, so that the reset voltage of the chip does not change with temperature. As a result, the internal circuit of the chip works at a higher voltage.

[0010] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0012] Figure 1 is a structural schematic diagram of a power-on reset detection circuit provided by an embodiment of the present disclosure;

[0013] Figure 2 is a structural schematic diagram of another power-on reset detection circuit provided by an embodiment of the present disclosure;

[0014] Figure 3 is a structural schematic diagram of another power-on reset detection circuit provided by an embodiment of the present disclosure;

[0015] Figure 4 The embodiment of the present disclosure provides Figure 3 Schematic diagram of the equivalent circuit structure.

[0016] Reference numerals:

[0017] 10: bias generation circuit; 20: detection circuit; 30: comparison circuit; 40: trigger logic circuit; R1: first resistor; R2: second resistor; R3: third resistor; Rb: bias resistor; R1A: equivalent resistor; M1: first MOS tube; M2: second MOS tube; M3: third MOS tube; M4: fourth MOS tube; M5: fifth MOS tube; M6: sixth MOS tube. DETAILED DESCRIPTION

[0018] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0019] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0020] In the embodiments of the present disclosure, the terms "upper", "lower", "inside", "middle", "outside", "front", "back" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. These terms are mainly intended to better describe the embodiments of the present disclosure and their embodiments, and are not intended to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction. Moreover, in addition to being used to indicate directions or positional relationships, some of the above terms may also be used to indicate other meanings. For example, the term "upper" may also be used to indicate a certain dependency or connection relationship in certain circumstances. For those of ordinary skill in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0021] In addition, the terms "disposed", "connected", and "fixed" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0022] Unless otherwise stated, the term "plurality" means two or more.

[0023] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0024] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0025] It should be noted that, without conflict, the embodiments in this disclosure and the features in the embodiments may be combined with each other.

[0026] Combined Figure 1 As shown, an embodiment of the present disclosure provides a power-on reset detection circuit, including a bias generation circuit 10, a detection circuit 20, and a comparison circuit 30. The bias generation circuit 10 includes a series-connected bias resistor Rb and a second MOS transistor M2. The bias resistor Rb is connected to the power supply voltage VCC to generate a bias voltage VBIAS. The detection circuit includes a first resistor R1, a first MOS transistor M1, and a second resistor R2 connected in series in sequence; the gate of the first MOS transistor M1 is connected to the bias voltage VBIAS generated by the bias generation circuit, and the drain voltage of the first MOS transistor M1 is used as the detection point voltage VDET of the power supply voltage VCC. The comparison circuit 30 is respectively connected to the bias voltage VBIAS of the bias generation circuit 10 and the detection point voltage VDET of the detection circuit 20, and is used for comparing the magnitudes of the bias voltage and the detection point voltage.

[0027] Here, one end of the bias resistor of the bias generation circuit is connected to the power supply voltage, and the other end is connected to the drain and gate of the second MOS transistor M2, and the source of the second MOS transistor M2 is grounded. In this way, after power-on, the second MOS transistor M2 works to generate a bias voltage VBIAS. The detection circuit includes a first resistor R1, a first MOS transistor M1, and a second resistor R2 connected in series in sequence. One end of the first resistor R1 is connected to the power supply voltage, and the other end is connected to the drain of the first MOS transistor M1. The gate of the first MOS transistor M1 is connected to the bias voltage VBIAS, the source is connected to one end of the second resistor R2, and the other end of the second resistor R2 is grounded. Under the action of the bias voltage, the first MOS transistor M1 works, and the drain voltage of the first MOS transistor M1 is used as the detection point voltage VDET of the power supply voltage. The comparison circuit compares the magnitudes of the bias voltage VBIAS and the detection point voltage VDET and outputs a comparison result. As an example, when VBIAS > VDET, the comparison circuit outputs a high level. When VBIAS < VDET, the comparison circuit outputs a low level.

[0028] Among them, because the second MOS tube M2 works in the subthreshold region (when the gate-source voltage Vgs is lower than the threshold voltage Vth, the state of the MOS tube; the MOS tube is not fully turned on at this time), when the bias voltage VBIAS and the detection point voltage VDET are equal, based on the MOS tube subthreshold region current formula, it can be known that the detection point voltage is only related to the bias voltage, the thermoelectric parameter of the MOS tube (i.e., the thermovoltage), the first resistor R1, and the second resistor R2. The bias voltage is related to the threshold voltage of the second MOS tube M2, the threshold voltage has a negative temperature coefficient, and the thermoelectric parameter has a positive temperature coefficient. By adjusting the coefficient ratio of the threshold voltage and the thermoelectric parameter, the zero temperature coefficient of the detection point voltage can be achieved, that is, the detection point voltage remains constant to the power supply voltage and does not change with temperature. In this way, the discrete range of the power supply voltage detection of the power-on reset detection module can be reduced, so that the internal circuit of the chip works at a higher voltage, reducing the design difficulty and chip cost.

[0029] The power-on reset detection circuit, the bias generation circuit, and the detection circuit provided in the embodiment of the present disclosure are designed so that the detection point voltage has a temperature compensation function. That is, the detection point voltage does not change with temperature and is relatively constant to the power supply voltage. This helps to reduce the discrete range of the power supply voltage detection by the power-on reset detection module, so that the reset voltage of the chip does not change with temperature.

[0030] Optionally, the second MOS transistor M2 and the first MOS transistor M1 form a current mirror, and the ratio of the channel width to the length of the second MOS transistor M2 and the first MOS transistor M1 is 1:N; wherein N≥2.

[0031] Here, the first MOS tube M1 and the second MOS tube M2 form a current mirror structure, and the ratio of the channel width and length of the second MOS tube M2 to the first MOS tube M1 is 1:N. Therefore, the first MOS tube M1 also works in the subthreshold region. The values ​​of the first resistor R1 and the second resistor R2 can be adjusted, and when the bias voltage VBIAS is equal to the detection voltage VDET, the current of the first MOS tube M1 and the second MOS tube M2 can be made the same. Then, based on the MOS tube subthreshold region current formula, the detection point voltage can be derived.

[0032] Optionally, the comparison circuit includes a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6. The sources of the fifth MOS transistor M5 and the sixth MOS transistor M6 are both connected to the power supply voltage, and their gates are connected. The drain of the sixth MOS transistor M6 is connected to the drain of the fourth MOS transistor M4, and the drain of the sixth MOS transistor M6 serves as the output terminal of the comparison circuit. The source of the fourth MOS transistor M4 is grounded and its gate is connected to the detected point voltage. The gate and the drain of the fifth MOS transistor M5 are connected, and the drain is also connected to the drain of the third MOS transistor M3. The gate of the third MOS transistor M3 is connected to the bias voltage generated by the bias generation circuit, and the source is grounded. The fifth MOS transistor M5 and the sixth MOS transistor M6 form a current mirror.

[0033] Here, each MOS transistor of the comparison circuit operates in the conducting state. When VBIAS > VDET, the gate-source voltage of the fourth MOS transistor M4 decreases. When the fourth MOS transistor M4 operates in the constant current region, the drain-source voltage of the fourth MOS transistor M4 increases as the gate-source voltage decreases. Therefore, in this case, a high level is output. Similarly, when VBIAS < VDET, the gate-source voltage of the fourth MOS transistor M4 increases. When the fourth MOS transistor M4 operates in the constant current region, the drain-source voltage of the fourth MOS transistor M4 decreases as the gate-source voltage increases. Therefore, in this case, the comparison circuit outputs a low level.

[0034] Optionally, the ratio of the channel width to the channel length of the fifth MOS transistor M5 and the sixth MOS transistor M6 is 1:N; where N ≥ 1.

[0035] When N > 1, the ratio of the channel width to the channel length of the third MOS transistor M3 and the fourth MOS transistor M4 is the same as the ratio of the channel width to the channel length of the fifth MOS transistor M5 and the sixth MOS transistor M6.

[0036] Here, the ratio of the channel width to the channel length of the fifth MOS transistor M5 and the sixth MOS transistor M6, as well as the third MOS transistor M3 and the fourth MOS transistor M4, can be 1:1, or other ratios. When the ratio is 1:1 and there are no other influencing factors, the third MOS transistor M3 and the fourth MOS transistor M4 have the same magnitude of current, and the fifth MOS transistor M5 and the sixth MOS transistor M6 also have the same magnitude of current, enabling the output of the circuit to reflect the relative magnitudes between the input voltages (VBIAS and VDET). Furthermore, when comparing VBIAS and VDET, the 1:1 width-to-length ratio of M6 and M5 helps ensure that when VBIAS > VDET, the current of M5 is slightly greater than the current of M6. And when VBIAS < VDET, the current of M6 is slightly greater than the current of M5. This difference will cause a change in the drain voltage of M6, thereby generating a high-level or low-level output. It can be seen that when the ratio is 1:1, accurate current replication can be achieved, so when there is a difference between VBIAS and VDET, the magnitudes of the two can be accurately compared, that is, the accuracy of current comparison is higher.

[0037] When the ratio is other values, the accuracy of current comparison is slightly reduced. This is because the conduction capabilities of the two branches are different. When there is a small difference between VBIAS and VDET, the currents of the two branches may already have a significant difference, causing the comparison circuit to output the corresponding signal earlier. Or, when there is a large difference between VBIAS and VDET, the currents of the two branches may only then have a difference, and the comparison circuit will output the corresponding signal.

[0038] Optionally, the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are NMOS transistors; the fifth MOS transistor and the sixth MOS transistor are PMOS transistors.

[0039] Optionally, by adjusting the resistance values of the first resistor R1 and the second resistor R2, the detection point voltage can have a zero temperature coefficient.

[0040] Here, based on the circuit diagram and the above principle, the detection point can be deduced through calculation as:

[0041]

[0042] It can be seen from the above formula that the temperature coefficient of V T can be adjusted by the ratio of the first resistor R1 and the second resistor R2, so that the sum of the positive temperature coefficient and the negative temperature coefficient is zero or approaches zero, achieving a zero temperature coefficient. Among them, the specific derivation process of the above formula will be elaborated in detail below. As an example, in the initial state, the temperature coefficient of V T is 0.5% / °C, and the temperature coefficient of V th is -1% / °C; then adjust the resistance values of the first resistor R1 and the second resistor R2 to make VT The temperature coefficient of the detection point voltage is close to zero.

[0043] Optionally, the power-on reset detection circuit further includes: a trigger logic circuit connected to the output end of the comparison circuit, and configured to output a first level signal when the bias voltage is greater than the detection point voltage, or output a second level signal when the bias voltage is less than the detection point voltage.

[0044] Here, the first level signal is a low level, and the second level signal is a high level. Due to the limited gain of the comparison circuit, when the bias voltage VBIAS is almost the same as the detection voltage VDET, the output of the comparison circuit may become unstable, because the current difference between the two branch MOS tubes is very small at this time, causing the output level to fluctuate near the threshold. In order to ensure the accuracy of the output flip point and avoid such fluctuations, the trigger logic circuit is used to set the upper limit voltage and the lower limit voltage to achieve relative stability of the output signal. Among them, the trigger logic circuit includes a circuit structure composed of a gate circuit, a MOS tube, etc.

[0045] Optionally, the trigger logic circuit includes: a Schmitt trigger circuit, namely, an STM circuit. The Schmitt trigger is connected to the drain of the fifth MOS tube M5 of the comparison circuit, and is used to flip the signal reaching the upper limit voltage or the lower limit voltage of the Schmitt window.

[0046] Here, the Schmitt trigger circuit (i.e., STM circuit) is a special inverter circuit that relies on the hysteresis characteristics brought by the positive feedback mechanism, so that the input signal (i.e., the output signal of the comparison circuit) only flips within the SMT window it sets. Specifically, when the input signal changes from low to high and reaches the upper limit voltage, the output signal jumps; when the input signal changes from high to low and reaches the lower limit voltage, the output signal jumps again. This makes the signal flip point relatively stable, and also has the function of signal shaping for the current comparison output.

[0047] Combination Figure 2 As shown, the embodiment of the present disclosure provides another power-on reset detection circuit. Figure 1 On the basis of, the circuit further includes a third resistor R3. Among them, one end of the third resistor R3 is connected to the drain of the first MOS tube M1, and the other end is grounded. The third resistor R3 and the detection circuit constitute a detection adjustment circuit to keep the detection point voltage constant when the power supply voltage changes with temperature.

[0048] As mentioned above, Figure 2The corresponding embodiment has a temperature compensation function, that is, to achieve a zero temperature coefficient of the detection point voltage, so that the detection point voltage does not change with temperature. However, the detection point voltage cannot be adjusted. Vth in the above formula has no coefficient, so it is impossible to adjust the absolute value of the coefficient. Therefore, the detection point voltage cannot be adjusted. Here, the third resistor R3 is introduced to make V th With coefficients, thus through V T and V th The absolute values ​​of the two coefficients are adjusted to achieve voltage adjustment at the detection point.

[0049] Optionally, the resistance of the bias resistor is greater than the resistance of the first resistor R1.

[0050] Here, the ratio of the channel width and length of the second MOS tube M2 and the first MOS tube M1 is 1:M, and M≥2. Under the same conditions, the current ratio of the two is M:1. When the bias resistor is greater than the first resistor R1, the bias resistor can be used to reduce the current of the branch where the second MOS tube M2 is located. When the bias voltage VBIAS is equal to the detection voltage VDET, the current of the first MOS tube M1 and the second MOS tube M2 are the same. Then, the current formula of the two in the subthreshold region is used to calculate and derive the detection point voltage. This proves that the detection point voltage has a temperature compensation function, that is, the detection point voltage remains constant when the power supply voltage changes with temperature.

[0051] Optionally, by adjusting the resistance values ​​of the first resistor R1 , the second resistor R2 and the third resistor, the voltage at the detection point has a zero temperature coefficient.

[0052] Here, the zero temperature coefficient of the voltage at the detection point is related to the first resistor R1, the second resistor R2 and the third resistor R3. By adjusting the resistance values ​​of the three resistors, V T and V th The temperature coefficient of the detection point voltage is realized by adjusting the temperature coefficient so that the sum of the temperature coefficients is basically zero.

[0053] Optionally, the detection point voltage is adjusted by adjusting the absolute value of the ratio between the first resistor R1 and the second resistor R2 and the absolute value of the ratio between the first resistor R1 and the third resistor R3.

[0054] Specifically, combined Figure 3The equivalent circuit diagram is used for explanation. In the diagram, the first resistor R1 can be equivalent to the bias resistor Rb and the resistor R1A in parallel. By controlling the resistance values ​​of the resistors Rb, R1, R2, R3, and R1A, when the bias voltage VBIAS is equal to the detection voltage VDET, the current passing through the resistor R1A is the same as that passing through the resistor R3. Therefore, according to Kirchhoff's law, it can be concluded that the current passing through the first MOS tube M1 and the second MOS tube M2 is the same (when the bias voltage VBIAS is equal to the detection voltage VDET, the voltage across the bias resistor and the equivalent bias resistor in the equivalent circuit is the same, so the current in the branch where the two are located is the same).

[0055] Further combined, the bias generation circuit and the detection circuit are based on the MOS tube subthreshold current formula,

[0056]

[0057] Among them, I0 is the block drain current of the MOS tube, V gs is the gate-source voltage of the MOS tube, V th is the threshold voltage of the MOS tube, V T is the thermoelectric parameter of the MOS tube, and W / L is the ratio of the MOS tube channel width to length.

[0058] The current of the first MOS tube M1 is the same as that of the second MOS tube M2. The ratio of W / L of the second MOS tube M2 to the first MOS tube M1 is 1 to N. Substituting the parameters of the first MOS tube M1 and the second MOS tube M2 into formula (1), we can get:

[0059]

[0060] After formula (2) is rearranged, we can get: V R2 =lnN×V T At the same time, V R2 =I×R2; combining the two, the current of the first MOS tube M1 and the second MOS tube M2 can be obtained:

[0061]

[0062] Given the power supply voltage VCC, Kirchhoff's current formula can be listed for the detection voltage VDET: R1 =I R2 +I R3 , further based on formula (3) we can get:

[0063]

[0064] After rearranging formula (4), we can get:

[0065]

[0066] For the bias voltage VBIAS, we can get: VBIAS = V th The bias voltage is used to turn on the second MOS tube M2, so the bias voltage is greater than or equal to the threshold voltage of the second MOS tube M2. Here, the bias voltage is equal to the threshold voltage of the second MOS tube M2, that is, V th .

[0067] For the comparison circuit, when the detection voltage VDET is greater than the bias voltage VBIAS, we get:

[0068]

[0069] After sorting, we can get:

[0070]

[0071] Since V T With positive temperature coefficient, V th It has a negative temperature coefficient. By adjusting the ratio of each temperature coefficient and adding them together, a zero temperature coefficient can be achieved. And by adjusting the absolute value of each coefficient, the voltage at the detection point can be adjusted.

[0072] in, Figure 2 There is no third resistor R3 in the circuit diagram, and the third resistor R3 can be considered to have an infinite resistance value, so formula (7) becomes formula (8) in the above text.

[0073] The embodiment of the present disclosure provides a chip, including: a chip body, and the aforementioned power-on reset detection circuit, which is connected to the chip body. Wherein, the chip body enters the working mode when the power-on reset detection circuit outputs a reset signal; when the detection point voltage is greater than the preset voltage, the power-on reset detection circuit outputs a reset signal. The reset signal indicates that the power supply voltage has reached the range in which the chip can operate normally. As an example, the chip is an NVM chip. In the GSMC (Global Semiconductor Manufacturing Corporation) 90nm ULL (Ultra Low Leakage) process, after adjusting the values ​​of resistors R1, R2, and R3, the center value of the detection point of the power-on reset module is 1.0V. If only temperature discreteness is considered, its accuracy can reach ±0.01V. If temperature and process discreteness are considered, its accuracy reaches ±0.1V.

[0074] In the actual operation of the chip in the above embodiment, the specific process is as follows:

[0075] After the chip is powered on, the power-on reset detection circuit detects the detection point voltage of the power supply voltage. The initial bias voltage is less than the detection point voltage, and the STM (Schmitt Trigger) circuit outputs a low-level signal. As the power supply voltage continues to increase, the detection point voltage is greater than the bias voltage. If the detection point voltage is less than the preset voltage, the reset signal is maintained (i.e., the trigger logic circuit outputs a low-level signal). If the detection point voltage is greater than the preset voltage, the reset signal is released (i.e., the STM circuit outputs a high-level signal), and the chip is powered on and works.

[0076] In addition, the installation relationship between the chip and the power-on reset detection circuit is not limited to being placed inside the chip body, but also includes installation connections with other components of the chip, including but not limited to physical connections, electrical connections, or signal transmission connections, etc. The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A power-on reset detection circuit, characterized in that: include: The bias generating circuit comprises a bias resistor and a second MOS tube connected in series, wherein the bias resistor is connected to a power supply voltage to generate a bias voltage; wherein the second MOS tube operates in a subthreshold region; The detection circuit comprises a first resistor, a first MOS tube and a second resistor connected in series in sequence; the gate of the first MOS tube is connected to the bias voltage generated by the bias generation circuit, and the drain voltage of the first MOS tube is used as the detection point voltage of the power supply voltage; The comparison circuit is connected to the bias voltage of the bias generation circuit and the detection point voltage of the detection circuit respectively, and is used for comparing the magnitudes of the bias voltage and the detection point voltage.

2. The circuit according to claim 1, characterized in that The second MOS tube and the first MOS tube form a current mirror, and the ratio of the channel width and length of the second MOS tube to that of the first MOS tube is 1:M; Among them, M≥2.

3. The circuit according to claim 1, characterized in that The comparison circuit comprises: A fifth MOS and a sixth MOS tube constituting a current mirror; the gate and the drain of the fifth MOS tube are connected, and the drain of the sixth MOS tube serves as an output end of the comparison circuit; The third MOS tube is connected in series with the sixth MOS tube; the gate of the third MOS tube is connected to the bias voltage generated by the bias generating circuit, The fourth MOS tube is connected in series with the fifth MOS tube; the gate of the fourth MOS tube is connected to the drain of the first MOS tube.

4. The circuit according to claim 3, characterized in that The ratio of the channel width to the length of the fifth MOS transistor and the sixth MOS transistor is 1:N, wherein N≥1; When N>1, the ratio of the channel width to the length of the third MOS tube and the fourth MOS tube is the same as the ratio of the channel width to the length of the fifth MOS tube and the sixth MOS tube.

5. The circuit according to claim 1, characterized in that By adjusting the resistance values ​​of the first resistor and the second resistor, the voltage at the detection point has a zero temperature coefficient.

6. The circuit according to claim 1, characterized in that Also includes: A trigger logic circuit is connected to the output terminal of the comparison circuit and is used to output a first level signal when the bias voltage is greater than the detection point voltage; Alternatively, when the bias voltage is less than the detection point voltage, a second level signal is output.

7. The circuit according to any one of claims 1 to 6, characterized in that: Also includes: A third resistor, one end of which is connected to the drain of the first MOS tube, and the other end of which is grounded; The third resistor and the detection circuit constitute a detection point adjustment circuit to adjust the detection point voltage.

8. The circuit according to claim 7, characterized in that The resistance value of the bias resistor is greater than the resistance value of the first resistor.

9. The circuit according to claim 7, characterized in that The detection point voltage is adjusted by adjusting the absolute value of the ratio between the first resistor and the second resistor, and the absolute value of the ratio between the first resistor and the third resistor.

10. A chip, characterized in that: include: Chip body, The power-on reset detection circuit according to any one of claims 1 to 9, connected to the chip body; in, The chip body enters the working mode when the power-on reset detection circuit outputs a reset signal; when the voltage at the detection point is greater than a preset voltage, the power-on reset detection circuit outputs a reset signal.

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