Encoding device, decoding device, encoding method and decoding method

Abstract

The invention provides a coding device, a decoding device, a coding method and a decoding method. The coding device comprises a pre-interleaving module, a symbol distribution module, N RSFEC coding modules and a symbol interleaving module, the pre-interleaving module performs a first interleaving operation on an alignment sequence in a received sending data stream, so that an original bit sequence of the alignment sequence taking a symbol as granularity is changed; the symbol distribution module distributes the sending data stream after the first interleaving operation to N RSFEC coding modules; each RSFEC coding module carries out RSFEC coding on the received transmission data stream, and N RSFEC coding modules carry out coding to obtain N paths of transmission coding data streams; the symbol interleaving module performs second interleaving operation on the N paths of sending coding data streams to obtain N paths of sending channel data streams, and each path of sending channel data stream is sent to one of N physical channels; after the second interleaving operation, the disorganized original bit order of the alignment sequence is recovered.

Description

Technical Field

[0001] The present application belongs to the field of chip technology, and in particular relates to an encoding device, a decoding device, an encoding method and a decoding method. Background Art

[0002] InfiniBand (IB) protocol is a high-speed data transmission technology, mainly used in high-performance computing, data centers, storage systems and other occasions that require fast and efficient communication. The IB protocol enables fast and efficient communication between servers, storage devices and other computing systems. Its design goal is to provide low-latency, high-bandwidth and scalable data transmission services to meet the needs of large-scale computing and data transmission. Summary of the invention

[0003] The purpose of the present application is to provide an encoding device, a decoding device, an encoding method and a decoding method, aiming to solve the problems of large delay in the PCS encoding process of the IB network and the need for memory storage in the prior art.

[0004] According to a first aspect of the present application, there is provided a coding device, comprising: a pre-interleaving module, a symbol distribution module, N RSFEC coding modules and a symbol interleaving module;

[0005] The pre-interleaving module is used to perform a first interleaving operation on the alignment sequence in the received transmission data stream, so that the original bit order of the alignment sequence with the symbol as the granularity is changed;

[0006] The symbol distribution module is used to distribute the transmission data stream after the first interleaving operation to the N RSFEC encoding modules;

[0007] Each of the RSFEC encoding modules is used to perform RSFEC encoding on the received transmission data stream, and the N RSFEC encoding modules encode to obtain N transmission coded data streams;

[0008] The symbol interleaving module is used to perform a second interleaving operation on the N transmission coded data streams to obtain N transmission channel data streams, each transmission channel data stream is sent to one of the N physical channels; wherein, after the second interleaving operation, the original bit order of the alignment sequence that was disrupted is restored.

[0009] In an optional implementation, the symbol distribution module distributes the transmission data stream in sequence in turn with symbols as the granularity, so that the N transmission data streams formed after distribution enter the N RSFEC encoding modules in parallel.

[0010] In an optional implementation, the second interleaving operation enables each of the N transmission channel data streams to include data from a different RSFEC encoding module, and the number of symbols of the data from each of the RSFEC encoding modules is equal.

[0011] In an optional embodiment, the alignment sequence includes N channel identification symbols arranged in sequence, and each of the channel identification symbols identifies one of the physical channels; after a first interleaving operation, the original order of the N channel identification symbols is disrupted; after distribution by the symbol distribution module, the N channel identification symbols are distributed to N RSFEC encoding modules respectively, and after a second interleaving operation, different channel identification symbols are in different sending channel data streams, and the physical channel to which the sending channel data stream corresponding to each channel identification symbol is sent is the same as the physical channel identified by the channel identifier.

[0012] According to a second aspect of the present application, a decoding device is provided, comprising: a symbol aggregation module, N RSFEC decoding modules and a symbol deinterleaving module;

[0013] The symbol deinterleaving module is used to receive N receiving channel data streams from N physical channels, and perform a third interleaving operation on the N receiving channel data streams, and transmit the N receiving channel data streams after the third interleaving operation to the N RSFEC decoding modules respectively; the N receiving channel data streams are obtained after the second interleaving operation of the encoding device at the transmitting end, and the third interleaving operation is an inverse operation of the second interleaving operation;

[0014] The N RSFEC decoding modules are used to perform RSFEC decoding on the N receiving channel data streams after the third interleaving operation;

[0015] The symbol aggregation module is used to aggregate the decoded N receiving channel data streams into one receiving data stream.

[0016] In an optional implementation, the symbol aggregation module receives data from the N RSFEC decoding modules in sequence in turn with symbols as granularity, and aggregates the data into the received data stream.

[0017] In an optional implementation, each of the N receiving channel data streams includes data from a different physical channel, and the number of symbols of the data from each physical channel is equal.

[0018] According to a third aspect of the present application, there is provided an encoding method, comprising:

[0019] Receive and send data streams;

[0020] Performing a first interleaving operation on the alignment sequence in the transmitted data stream so that the original bit order of the alignment sequence with symbols as granularity is changed;

[0021] Distribute the transmission data stream after the first interleaving operation into N transmission data streams in parallel;

[0022] Perform RSFEC encoding on each transmission data stream in parallel to obtain N transmission encoded data streams;

[0023] A second interleaving operation is performed on the N transmission coded data streams to obtain N transmission channel data streams, each of which is sent to one of the N physical channels; wherein after the second interleaving operation, the original bit order of the alignment sequence that has been disrupted is restored.

[0024] In an optional implementation manner, distributing the transmit data stream after the first interleaving operation into N transmit data streams in parallel includes:

[0025] The transmission data stream after the first interleaving operation is distributed in sequence in turn with symbols as granularity to form N parallel transmission data streams;

[0026] Aggregating the decoded N receiving channel data streams into one receiving data stream, including:

[0027] Data are acquired from N receiving channel data in sequence in turn with symbols as granularity, and are aggregated into the receiving data stream.

[0028] In an optional implementation, each of the N transmission channel data streams includes a different one of the N transmission coded data streams, and the number of symbols of data from each transmission coded data stream is equal.

[0029] In an optional embodiment, the alignment sequence includes N channel identification symbols arranged in sequence, and each of the channel identification symbols identifies one of the physical channels; after a first interleaving operation, the original order of the N channel identification symbols is disrupted; the N channel identification symbols are distributed to the N transmitting data streams respectively, and after a second interleaving operation, different channel identification symbols are in different transmitting channel data streams, and the physical channel to which the transmitting channel data stream corresponding to each channel identification symbol is sent is the same as the physical channel identified by the channel identifier.

[0030] According to a fourth aspect of the present application, a decoding method is provided, further comprising:

[0031] receiving N receiving channel data streams from N physical channels, and performing a third interleaving operation on the N receiving channel data streams; the N receiving channel data streams are obtained after the second interleaving operation of the encoding device at the transmitting end, and the third interleaving operation is an inverse operation of the second interleaving operation;

[0032] Performing RSFEC decoding on the N receiving channel data streams after the third interleaving operation;

[0033] The decoded N receiving channel data streams are aggregated into one receiving data stream.

[0034] In an optional implementation manner, aggregating the decoded N receiving channel data streams into one receiving data stream includes:

[0035] Data are received from the N RSFEC decoding modules in turn in sequence with symbols as granularity, and are aggregated into the received data stream.

[0036] In an optional implementation, each of the N receiving channel data streams includes data from a different physical channel, and the number of symbols of the data from each physical channel is equal.

[0037] Compared with the related art, the technical solution of this application has the following advantages:

[0038] The present application adopts the structure of parallel RSFEC encoding and decoding modules, which eliminates the memory storage requirements introduced by data order preservation before and after encoding and decoding. At the same time, in order to ensure that the error correction capability and channel synchronization function on each physical channel are not affected, the processing process of the symbol interleaving module and the AS sequence pre-interleaving module is further introduced. The newly introduced processing process does not generate additional delay. Although this method disrupts the original order of the data, it can still be correctly restored after decoding. Compared with the serial encoding and decoding method in the related art, the present application has the following advantages:

[0039] 1. The delay of high-rate RSFEC encoding and decoding is greatly reduced, and memory resources are saved.

[0040] 2. The newly introduced AS pre-interleaving and symbol interleaving processing does not introduce delay, has simple logic and good scalability.

[0041] 3. After symbol interleaving, the data stream of the physical channel corresponds to different encoding and decoding modules according to the symbol granularity. Compared with the serial distribution structure, this application has stronger resistance to burst errors.

[0042] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained through the structures and processes indicated in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. It is obvious that the drawings described below are certain embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 It is a schematic diagram of the architecture of a serial encoding device in a data sending direction according to the related art.

[0045] Figure 2 is a schematic diagram of the architecture of an encoding device according to the related art.

[0046] Figure 3 It is a schematic diagram of the architecture of the encoding device in the data sending direction according to an exemplary embodiment of the present application.

[0047] Figure 4 It is a schematic diagram of the effect of the symbol interleaving process according to an exemplary embodiment of the present application.

[0048] Figure 5 It is a schematic diagram of the effect of the pre-interleaving process according to an exemplary embodiment of the present application.

[0049] Figure 6 is a schematic diagram of the architecture of a decoding device according to the related art.

[0050] Figure 7 It is a flowchart of an encoding method according to an exemplary embodiment of the present application.

[0051] Figure 8 It is a flowchart of a decoding method according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0053] Low latency is a key performance indicator in the IB network. RSFEC (forward error correction codec based on Reed-Solomon code) is a link in the physical layer signal processing of the IB network with high computational complexity and timing pressure, which will occupy more processing delays. Therefore, controlling and compressing the delay of this processing link will significantly improve the overall delay performance of the system.

[0054] like Figure 1 As shown, in the IB protocol, the data stream is scrambled, 64 / 66b encoded, and transcoded, and then enters the RSFEC codec serially. The encoded data is then distributed by lane (channel) according to symbols.

[0055] This serial processing method cannot be used in high-speed and high-throughput scenarios (such as processing traffic up to 800Gbps under x8 NDR) using a single RSFEC codec due to the timing limitations of the calculation speed and backend physical implementation. Therefore, in engineering implementation, multiple RSFEC codecs are usually considered to solve this problem, but it will inevitably incur overhead in terms of resources, area, and processing delay.

[0056] One feasible implementation method is to distribute the data stream according to the granularity of the FEC (forward error correction coding technology) block, and combine the bit width conversion to distribute the large flow into N small flows, corresponding to multiple RSFEC codecs for ping-pong processing. After the encoding and decoding, the N data streams are aggregated into a large flow output according to the order of the FEC blocks, and finally distributed to multiple physical lanes (channels) by symbol, see Figure 2 As shown, Figure 2 Only the data sending process is shown, and the receiving process is its reverse process and will not be described in detail.

[0057] This implementation method can not only meet the serial RSFEC codec processing requirements of the protocol, but also solve the RSFEC codec processing bottleneck problem in high-traffic scenarios. However, it also has the following problems:

[0058] 1. In Figure 2 As shown in point ①, when distributing FEC blocks, the ingress traffic is too fast and the traffic output to the RSFEC codec is slow, so it is necessary to use memory to temporarily store the data stream, which increases the delay.

[0059] 2. In Figure 2 As shown in ②, when the FEC blocks are aggregated, since the flow output by a single RSFEC codec is slow, while the original large flow output must be guaranteed, memory storage data is also required, which increases the delay.

[0060] The RSFEC codec has symmetric processing in the encoding and decoding directions, and the delays and memory consumption mentioned above will increase exponentially.

[0061] Therefore, in order to solve the problems of large delay and large area in the engineering implementation of high-speed serial RSFEC codec, the present application proposes a codec device for implementing a parallel RSFEC codec for the IB protocol.

[0062] The core idea of ​​the codec device is: put the symbol distribution operation in front to obtain N parallel data streams, and the corresponding RSFEC codecs work independently and in parallel. In order to ensure that the error correction capability on each physical channel lane in the receiving direction is not affected, the symbol interleaving process is introduced; at the same time, in order to ensure that the channel synchronization process in the receiving direction is not affected, the AS (Align sequence) pre-interleaving process is further introduced. In this way, the memory access requirements introduced by data order preservation before and after encoding and decoding can be omitted, thereby greatly reducing processing delays and reducing the use of memory, which can reduce the area of ​​the chip implementation.

[0063] See also Figure 3 As shown, the present application exemplarily proposes a coding device, including: a pre-interleaving module, a symbol distribution module, N RSFEC coding modules and a symbol interleaving module;

[0064] The pre-interleaving module is used to perform a first interleaving operation on the alignment sequence in the received transmission data stream, so that the original order of the N channel identification symbols in the alignment sequence is changed;

[0065] The symbol distribution module is used to distribute the transmission data stream after the first interleaving operation to N RSFEC encoding modules;

[0066] Each RSFEC encoding module is used to perform RSFEC encoding on the received transmission data stream, and N RSFEC encoding modules encode to obtain N transmission coded data streams;

[0067] The symbol interleaving module is used to perform a second interleaving operation on N transmission coded data streams to obtain N transmission channel data streams, each of which is sent to one of the N physical channels; wherein, after the second interleaving operation, each transmission channel data stream contains one of the channel identification symbols of the alignment sequence, and the channel identification symbols in the N channel data streams are arranged in the order of the corresponding N physical channels to be in the original order.

[0068] Exemplarily, from a holistic perspective, this application adopts a parallel processing structure. Figure 3 The TX process (i.e., the process in the sending direction) is shown in FIG. Figure 3For example, ② is the symbol distribution module. Compared with the related technology, it advances the symbol distribution of each physical channel lane to the front of the RSFEC encoding module, and no longer divides the FEC block before encoding, but only distributes it at the granularity of symbols. After distribution, each sending data stream enters each RSFEC encoding module in parallel and completes the encoding.

[0069] At ③ is the symbol interleaving module, which first performs symbol interleaving on each transmitted coded data stream and then sends it to each physical channel. After interleaving, the data on each physical channel will come from a different RSFEC encoding module. This can ensure that the error correction capability of each physical channel at the receiving end is not affected, and even has a stronger error correction capability for burst reception errors.

[0070] For example, after receiving the transmitted data stream, the receiving end needs to perform synchronization and rearrangement operations according to the AS (Align sequence) sequence, and the interleaving operation performed by the symbol interleaving module will disrupt the original order of the alignment sequence. In order to ensure that the AS sequence after interleaving is not affected, the present application adds a pre-interleaving module before the RSFEC encoding module (see Figure 3 ① of the method is used to perform a first interleaving operation on the AS sequence, so as to ensure that the AS sequence can restore its original order after the second interleaving operation of the symbol interleaving module. That is to say, at the pre-interleaving module, the original bit order of the alignment sequence in the transmitted data stream is disrupted, and after the second interleaving operation at the symbol interleaving module, the disrupted original bit order of the alignment sequence is restored. Here, the restoration of the original bit order can be understood as the order of the alignment sequence sent to each physical channel after the first interleaving operation and the second interleaving operation is consistent with the order of the alignment sequence directly sent to the physical channel without performing the first interleaving operation and the second interleaving operation. Since the purpose of adding the pre-interleaving module is to maintain the original bit order of the AS sequence after the second interleaving operation is performed by the symbol interleaving module, the first interleaving operation performed in the pre-interleaving module is related to the second interleaving operation, and can be designed based on the specific interleaving process of the second interleaving operation.

[0071] For example, it can be obtained from Figure 3 As can be seen from the figure, the AS sequence is inserted by the corresponding circuit module before the transmitted data stream enters the pre-interleaving module. Figure 3 The coding device shown is a circuit in the PCS (physical coding sublayer) of the IB network, and the pre-interleaving module also includes a scrambling module, a 64 / 66B coding module, a transcoding module, and an AS insertion module, etc. The details of the above modules can be found in the relevant technology, and the present disclosure does not make specific restrictions on this.

[0072] In some optional embodiments, the symbol distribution module distributes the transmission data stream in sequence in turn with symbols as the granularity, so that N transmission data streams formed after distribution enter N RSFEC encoding modules in parallel.

[0073] Exemplarily, the symbol distribution module distributes with symbols as the granularity, and after distribution, each transmission data stream enters each RSFEC encoding module in parallel and completes encoding. The symbol here can be understood as a segment of data bits with a certain length, such as 10 bits of data, and the distribution with symbols as the granularity can be understood as distributing the transmission data stream in groups of 10 bits in sequence to N physical channels line0-lineN-1, for example, the first 10 bits of the transmission data stream are distributed to the first RSFEC encoding module Rsfec enc0, the second 10 bits are distributed to the second RSFEC encoding module Rsfec enc1, and so on, the Nth 10 bits are distributed to the Nth RSFEC encoding module Rsfec encN-1, and from the N+1th 10 bits, they are sent from the first RSFEC encoding module Rsfec enc0, and so on.

[0074] In some optional embodiments, the second interleaving operation enables each of the N transmission channel data streams to include data from a different RSFEC encoding module, and the number of symbols of the data from each RSFEC encoding module is equal.

[0075] Exemplarily, the second interleaving operation is located after RSFEC encoding. Taking the RSFEC encoding module with a parallel degree of 160 bits as an example, in the x8 mode, 8 RSFEC encoding modules are used to perform parallel encoding processing. Each RSFEC encoding module outputs 16 symbols of data in a single shot (1 symbol of data corresponds to 10 bits). The interleaving result of the output data of the 8 RSFEC encoding modules is as follows: Figure 4 It should be noted that Figure 4 Only data processed in one clock cycle (ie, a single beat) is schematically shown.

[0076] Among them, E0~7 are the numbers of RSFEC encoding modules, symbols with the same number are output by the same RSFEC encoding module, s0~15 are the symbol numbers in a single beat, and s0 is the lowest bit symbol. Among them, the number of RSFEC encoding modules is the same as the number of physical channels, and the N-way transmission channel data streams obtained after the N-way transmission coded data streams after the RSFEC encoding module pass through the symbol interleaving module correspond to the physical channels one by one, that is, the first transmission channel data stream corresponds to the first physical channel and is sent out through the first physical channel, the second transmission channel data stream corresponds to the second physical channel and is sent out through the second physical channel, ..., the N-th transmission channel data stream corresponds to the N-th physical channel and is sent out through the N-th physical channel.

[0077] from Figure 4 It can be seen from the symbol box displayed in bold that after the second interleaving operation, the output data sent to the first physical channel Lane0 comes from all 8 RSFEC encoding modules, and the number of symbols provided by each RSFEC encoding module is equal. In this embodiment, the purpose of performing the second interleaving operation is to correspond the continuous data stream on each physical channel to different RSFEC encoding modules in sequence according to the symbol granularity, so that on the receiving side, when a burst error occurs in the received data on one or more physical channels, all 8 RSFEC decoders can simultaneously share the burst error, so as to achieve a strong burst error resistance capability.

[0078] for Figure 4The second interleaving operation shown is described as follows: first, the first symbol output by each RSFEC encoding module is sent to its corresponding physical channel in turn, that is, the first physical channel lane0 receives the first symbol s0 / E0 output by the first RSFEC encoding module, the second physical channel lane1 receives the first symbol s0 / E1 output by the second RSFEC encoding module, ..., the eighth physical channel lane7 receives the first symbol s0 / E7 output by the eighth RSFEC encoding module. After that, starting from the second symbol, the first channel lane0 receives the second symbol s1 / E1 output by the second RSFEC encoding module, the second physical channel lane1 receives the second symbol s1 / E2 output by the third RSFEC encoding module, ..., the eighth physical channel lane7 receives the second symbol s1 / E0 output by the first RSFEC encoding module, and starting from the third symbol, the first channel lane0 receives the third symbol s2 / E2 output by the third RSFEC encoding module, and the second physical channel lane1 receives the fourth RSFEC The third symbol s2 / E3 output by the encoding module, ..., the eighth physical channel lane7 receives the third symbol s2 / E1 output by the second RSFEC encoding module, that is, starting from the second symbol, in each round, the nth channel receives the mth symbol output by the n+m-1th RSFEC encoding module, where m is the number of the symbol received by the current channel in the current round. When the RSFEC encoding module number n+m-1 is greater than 8, the number should be returned to (n+m-1)-8; when the number n+m-1 is greater than 16, the number should be returned to (n+m-1)-16.

[0079] It can be understood that the inverse operation of the second interleaving operation performed by the symbol deinterleaving module is to Figure 4 After processing the data shown in the right figure, the data shown in the left figure is obtained. The data received by the symbol deinterleaving module is as follows Figure 4 As shown in the right figure, the first symbol received from each physical channel is sent to each RSFEC encoding module in turn in a one-to-one correspondence. Starting from the second symbol, in each round, the mth symbol received from the nth channel is sent to the n+m-1th RSFEC decoding module, where m is the number of the symbol received by the current channel in the current round. When the number n+m-1 is greater than 8, the number should be returned to (n+m-1)-8, and when the number n+m-1 is greater than 16, the number should be returned to (n+m-1)-16.

[0080] In some embodiments, the alignment sequence includes N channel identification symbols arranged in sequence, and each channel identification symbol identifies one of the physical channels; after a first interleaving operation, the original order of the N channel identification symbols is disrupted; after distribution by a symbol distribution module, the N channel identification symbols are distributed to N RSFEC encoding modules respectively, and after a second interleaving operation, different channel identification symbols are in different paths of sending channel data streams, and the physical channel to which the sending channel data stream corresponding to each channel identification symbol is sent is the same as the physical channel identified by the channel identifier.

[0081] Exemplarily, the AS pre-interleaving operation is located before the symbol distribution of the present application. Taking the x8 mode as an example, the AS sequence in this mode consists of AM s0-4, ld0-7 and several pad (blank padding) values ​​repeated 8 times per symbol. The original bit order of the alignment sequence, the order after the first interleaving operation, and the symbol bit order corresponding to the physical channel after the second interleaving operation are as follows: Figure 5 shown.

[0082] Among them, Figure 5 At ①, after the first interleaving operation, the order of ld (i.e., channel identifier) ​​in AS is temporarily disrupted; the channel identifier is 10-bit data, used to identify the physical channel. Taking the x8 mode as an example, there are 8 channel identifiers, which identify 8 channels respectively, among which ld0 identifies the first logistics channel, ..., ld7 identifies the eighth physical channel. At ②, after the AS sequence encoded by the RSFEC encoding module, the original bit order is restored after the second interleaving operation; at ③, taking the first physical channel Lane0 as an example, the AS sequence after the first and second interleaving operations is the same as the original bit order when output on Lane0, which ensures that it can be normally synchronized and the physical channel can be correctly rearranged when the data is received at the receiving end.

[0083] It should be noted that Figure 5The data stream shown by the original AS symbol bit sequence and the AS symbol bit sequence after pre-interleaving is actually a data stream. For the convenience of description, this data stream is shown in the figure as data arranged in rows and columns. The number of rows is the same as the number of physical channels and the number of RSFEC encoding modules. s0-s7 are numbers assigned to the symbols for the convenience of description, and E0-E7 are numbers of RSFEC encoding modules. Each data in this data stream is a symbol, that is, 10 bits, such as AM s0-AM s7, ld0-ld7, pad0, dat1-dat4 are all 10-bit symbols. The arrangement order of these symbols in this data stream is: from AM s0 in the 1st column and 1st row on the right to AM s0 in the 1st column and 8th row, then from AM s1 in the 2nd column and 1st row to AM s1 in the 8th row, ..., ld0 in the 6th column and 1st row to ld7 in the 8th row, Figure 5 As shown in the figure, pad0 in the 7th column, 1st row to the 3rd row is the padding bit, and dat0 in the 7th column, 4th row to dat4 in the 8th row are the service data after the AS sequence. This is just an example. In actual applications, a large amount of service data will continue to follow after the 7th column, which is not shown in the figure.

[0084] As described above, the purpose of pre-interleaving, i.e., the first interleaving operation, is to make the channel identifiers in the AS sequence consistent before pre-interleaving and after symbol interleaving, i.e., the second interleaving operation, that is, the original bit sequence of the channel identifiers in the AS sequence and after the second interleaving operation, the channel identifiers of each transmission channel data stream distributed thereto are sorted according to the actual corresponding physical channels, and the order is consistent. For example, the original bit sequence of the 8 channel identifiers in the AS sequence is ldO-ld7, and after the second interleaving operation, ldO-ld7 are respectively distributed to the transmission channel data streams corresponding to the 1st physical channel lane0 to the 8th physical channel lane7, and the order of the two is consistent.

[0085] Therefore, the pre-interleaving, i.e., the first interleaving operation, only needs to disrupt the order of ld0-ld7 in the AS sequence, and the principle of the disruption is to restore the original order after the second interleaving operation described above. Figure 5In the figure, the 6th symbol of the 1st physical channel after the second interleaving operation comes from the data output by the 6th RSFEC encoding module, which is ldO / E5 in the figure. Therefore, for the AS sequence, in order to maintain the original bit order of the channel symbol identifier in the AS sequence, the 6th symbol of the 1st physical channel after the second interleaving operation should be ldO. Therefore, in the first interleaving operation, ld0 needs to be exchanged to the position of the 6th row, and ld1 after ld0 is exchanged to the next row of the 6th row, that is, the 7th row, ld2 is exchanged to the 8th row, and the remaining channel identifier symbols starting from ld3 are exchanged to the 1st row to the 5th row respectively. It should be noted that Figure 5 This is only an example of a pre-interleaving process. The specific pre-interleaving operation depends on the symbol interleaving operation, that is, the second interleaving operation. Figure 4 The second interleaving operation shown is also only an example, as long as the data sent by each channel after the second interleaving operation contains data from all RSFEC encoding modules, and the number of symbols from each RSFEC encoding module is equal, and the AS sequence sent on each physical channel satisfies the established bit sequence. Therefore, the present application does not impose any restrictions on the specific interleaving methods of the first interleaving operation and the second interleaving operation.

[0086] The present application adopts the structure of parallel RSFEC encoding and decoding modules, which eliminates the memory storage requirements introduced by data order preservation before and after encoding and decoding. At the same time, in order to ensure that the error correction capability and channel synchronization function on each physical channel are not affected, the processing process of the symbol interleaving module and the AS sequence pre-interleaving module is further introduced. The newly introduced processing process does not generate additional delay. Although this method disrupts the original order of the data, it can still be correctly restored after decoding. Compared with the serial encoding and decoding method in the related art, the present application has the following advantages:

[0087] 1. The delay of high-rate RSFEC encoding and decoding is greatly reduced, and memory resources are saved.

[0088] 2. The newly introduced AS pre-interleaving and symbol interleaving processing does not introduce delay, has simple logic and good scalability.

[0089] 3. After symbol interleaving, the data stream of the physical channel corresponds to different encoding and decoding modules according to the symbol granularity. Compared with the serial distribution structure, this application has stronger resistance to burst errors.

[0090] Accordingly, see Figure 6 As shown, the present application exemplarily proposes a decoding device, which is Figure 3Corresponding to the encoding device shown, in actual application, the encoding device encodes data at the data sending end, and the decoding device decodes the data encoded by the encoding device and sent to the data receiving end at the data receiving end. The decoding device includes: a symbol aggregation module, N RSFEC decoding modules and a symbol deinterleaving module;

[0091] The symbol deinterleaving module is used to receive N receiving channel data streams from N physical channels, and perform a third interleaving operation on the N receiving channel data streams, and transmit the N receiving channel data streams after the third interleaving operation to N RSFEC decoding modules respectively; the N receiving channel data streams are obtained after the second interleaving operation of the encoding device at the transmitting end, and the third interleaving operation is an inverse operation of the second interleaving operation;

[0092] N RSFEC decoding modules are used to perform RSFEC decoding on the N receiving channel data streams after the third interleaving operation;

[0093] The symbol aggregation module is used to aggregate the decoded N receiving channel data streams into one receiving data stream.

[0094] Exemplarily, in the RX direction, the decoding device includes a symbol aggregation module, N RSFEC decoding modules and a symbol deinterleaving module. The operation of the symbol deinterleaving module is the inverse process of the symbol interleaving module, the operation of the symbol aggregation module is the inverse process of the symbol distribution module, and the operation of the RSFEC decoding module is the inverse process of the RSFEC encoding module. The aggregation process of the symbol aggregation module is as follows: starting from the first receiving channel data stream, data is received from N receiving channel data streams in sequence with symbols as the granularity, and the reception is performed cyclically, and the received data is combined into a receiving data stream in the order of reception. For example, the lowest 10 bits of data are received from the first receiving channel data stream, and then the lowest 10 bits of data are received from the second receiving channel data stream, and so on, the lowest 10 bits of data are received from the Nth receiving channel data stream, and if the width of each channel is greater than 10 bits, the second lowest 10 bits of data are received from the first receiving channel data stream, and so on, until all data are received. The received data stream obtained by the symbol aggregation module can be sent to subsequent circuits, such as a circuit module that deletes the AS sequence. It can be understood that the order of the AS alignment sequence in the received data stream is not the original bit order, but since the AS sequence will be deleted in the corresponding circuit module later, the circuit module that performs the inverse process of the pre-interleaving module is no longer set in the receiving direction. The third interleaving operation performed by the symbol deinterleaving module is the inverse operation of the second interleaving operation performed by the symbol interleaving module of the encoding device, so the specific details of the third interleaving operation can be found in the description of the encoding device above.

[0095] In some optional embodiments, the symbol aggregation module receives data from N RSFEC decoding modules in sequence in turn with symbols as the granularity, and aggregates the data into a received data stream.

[0096] Exemplarily, the symbol aggregation module also aggregates with symbols as the granularity. The symbol here can be understood as a segment of data bits with a certain length, such as 10 bits of data, and the aggregation with symbols as the granularity can be understood as receiving data from the RSFEC decoding module Rsfec dec0-N-1 in turn with symbols as the granularity, such as receiving a symbol (that is, 10 bits of data) from the first RSFEC decoding module Rsfecdec0, and then receiving a symbol from the second RSFEC decoding module Rsfec dec 1, ..., receiving a symbol from the Nth RSFEC decoding module Rsfec decN-1, and then receiving from the first decoding module Rsfec dec0, and so on, the received symbols are aggregated into a data stream.

[0097] In some optional embodiments, each of the N receiving channel data streams after the third interleaving operation includes data from a different physical channel, and the number of symbols of the data from each physical channel is equal.

[0098] Exemplarily, the structure and data processing flow of the decoding device are exactly opposite to those of the encoding device, so each of the N receiving channel data streams obtained after the third interleaving operation includes data from different physical channels, that is, the third interleaving operation actually exchanges data on the original N receiving channel data streams at a symbol granularity, so that after the exchange, each receiving channel data stream includes data from all physical channels, and for each receiving channel data stream that has undergone the third interleaving operation, the number of symbols of data from each physical channel is the same.

[0099] For details of the decoding device in this embodiment, please refer to the description of the encoding device above, which will not be repeated here.

[0100] Accordingly, see Figure 7 As shown, the present application exemplarily provides an encoding method, including:

[0101] In step S701, receiving a transmission data stream;

[0102] In step S702, a first interleaving operation is performed on the alignment sequence in the transmission data stream, so that the original bit order of the alignment sequence with the symbol as the granularity is changed;

[0103] In step S703, the transmission data stream after the first interleaving operation is distributed in parallel into N transmission data streams;

[0104] In step S704, RSFEC encoding is performed on each transmission data stream in parallel to obtain N transmission coded data streams;

[0105] In step S705, a second interleaving operation is performed on N transmission coded data streams to obtain N transmission channel data streams, each of which is sent to one of the N physical channels; wherein after the second interleaving operation, the original bit order of the alignment sequence that was disrupted is restored.

[0106] In some optional embodiments, distributing the transmit data stream after the first interleaving operation into N transmit data streams in parallel includes:

[0107] The transmission data stream after the first interleaving operation is distributed in sequence in turn with symbols as the granularity to form N parallel transmission data streams.

[0108] In some optional embodiments, each of the N transmit channel data streams includes data from a different one of the N transmit coded data streams, and the number of symbols of data from each transmit coded data stream is equal.

[0109] In some optional embodiments, the alignment sequence includes N channel identification symbols arranged in sequence, and each channel identification symbol identifies one of the physical channels; after a first interleaving operation, the original order of the N channel identification symbols is disrupted; the N channel identification symbols are distributed to N transmitting data streams respectively, and after a second interleaving operation, different channel identification symbols are in different transmitting channel data streams, and the physical channel to which the transmitting channel data stream corresponding to each channel identification symbol is sent is the same as the physical channel identified by the channel identifier.

[0110] The above method can be implemented by the encoding device provided in the above embodiment. The specific implementation method can refer to the description of the encoding device in the above embodiment, which will not be repeated here.

[0111] Accordingly, see Figure 8 As shown, the present application exemplarily provides a decoding method, including:

[0112] In step S801, N receiving channel data streams are received from N physical channels, and a third interleaving operation is performed on the N receiving channel data streams; the N receiving channel data streams are obtained after the second interleaving operation of the encoding device at the transmitting end, and the third interleaving operation is an inverse operation of the second interleaving operation;

[0113] In step S802, RSFEC decoding is performed on the N receiving channel data streams after the third interleaving operation;

[0114] In step S803, the decoded N receiving channel data streams are aggregated into one receiving data stream.

[0115] In some optional embodiments, aggregating the decoded N receiving channel data streams into one receiving data stream includes:

[0116] Data is received from N RSFEC decoding modules in turn in sequence with symbols as the granularity, and is aggregated into a received data stream.

[0117] In some optional embodiments, each of the N receiving channel data streams includes data from a different physical channel, and the number of symbols of the data from each physical channel is equal.

[0118] The above method can be implemented by the decoding device provided in the above embodiment. The specific implementation method can refer to the description of the decoding device in the above embodiment, which will not be repeated here.

[0119] Accordingly, the present application also exemplarily proposes a coding and decoding device, including the coding device as described above, and the decoding device as described above.

[0120] Accordingly, the present application also exemplarily proposes a coding and decoding method, including the coding method steps as described above, and the decoding method steps as described above.

[0121] The above-mentioned encoding and decoding device includes the encoding device and decoding device provided in the above-mentioned embodiment. For specific details, please refer to the description of the encoding device and decoding device in the above-mentioned embodiment, which will not be repeated here.

[0122] The above encoding and decoding method is implemented by the encoding device and decoding device provided in the above embodiments. For specific details, please refer to the description of the encoding device and decoding device in the above embodiments, which will not be repeated here.

[0123] It is understood that the circuit structures, names and parameters described in the above embodiments are only examples. Those skilled in the art can also easily combine and adjust the structural features of the above embodiments according to the use requirements, and should not limit the concept of the present application to the specific details of the above examples.

[0124] Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that he or she may still modify the technical solutions described in the aforementioned embodiments, or make equivalent substitutions for some of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A coding device, characterized in that: include: Pre-interleaving module, symbol distribution module, N RSFEC encoding modules and symbol interleaving module; The pre-interleaving module is used to perform a first interleaving operation on the alignment sequence in the received transmission data stream, so that the original bit order of the alignment sequence with the symbol as the granularity is changed; The symbol distribution module is used to distribute the transmission data stream after the first interleaving operation to the N RSFEC encoding modules; Each of the RSFEC encoding modules is used to perform RSFEC encoding on the received transmission data stream, and the N RSFEC encoding modules encode to obtain N transmission coded data streams; The symbol interleaving module is used to perform a second interleaving operation on the N transmitted coded data streams to obtain N transmitted channel data streams, each of which is sent to one of the N physical channels; wherein, after the second interleaving operation, the original bit order of the alignment sequence that was disrupted is restored.

2. The encoding device according to claim 1, characterized in that The symbol distribution module distributes the transmission data stream in sequence in turn with symbols as granularity, so that the N transmission data streams formed after distribution enter the N RSFEC encoding modules in parallel.

3. The encoding device according to claim 1 or 2, characterized in that The second interleaving operation enables each of the N transmission channel data streams to include data from a different RSFEC encoding module, and the number of symbols of the data from each RSFEC encoding module is equal.

4. The encoding device according to claim 3, characterized in that The alignment sequence includes N channel identification symbols arranged in sequence, and each of the channel identification symbols identifies one of the physical channels; After the first interleaving operation, the original order of the N channel identification symbols is disrupted; After being distributed by the symbol distribution module, the N channel identification symbols are respectively distributed to N RSFEC encoding modules, and after the second interleaving operation, different channel identification symbols are in different sending channel data streams, and the physical channel to which the sending channel data stream corresponding to each channel identification symbol is sent is the same as the physical channel identified by the channel identifier.

5. A decoding device, characterized in that: include: Symbol aggregation module, N RSFEC decoding modules and symbol deinterleaving module; The symbol deinterleaving module is used to receive N receiving channel data streams from N physical channels, and perform a third interleaving operation on the N receiving channel data streams, and transmit the N receiving channel data streams after the third interleaving operation to the N RSFEC decoding modules respectively; The N receiving channel data streams are obtained after the second interleaving operation of the encoding device at the transmitting end, and the third interleaving operation is an inverse operation of the second interleaving operation; The N RSFEC decoding modules are used to perform RSFEC decoding on the N receiving channel data streams after the third interleaving operation; The symbol aggregation module is used to aggregate the decoded N receiving channel data streams into one receiving data stream.

6. The decoding device according to claim 5, characterized in that The symbol aggregation module receives data from the N RSFEC decoding modules in turn in sequence with symbols as granularity, and aggregates them into the received data stream.

7. The decoding device according to claim 5 or 6, characterized in that: Each of the N receiving channel data streams includes data from a different physical channel, and the number of symbols of the data from each physical channel is equal.

8. A coding method, characterized in that: include: Receive and send data streams; Performing a first interleaving operation on the alignment sequence in the transmitted data stream so that the original bit order of the alignment sequence with symbols as granularity is changed; Distribute the transmission data stream after the first interleaving operation into N transmission data streams in parallel; Perform RSFEC encoding on each transmission data stream in parallel to obtain N transmission encoded data streams; A second interleaving operation is performed on the N transmission coded data streams to obtain N transmission channel data streams, each of which is sent to one of the N physical channels; wherein after the second interleaving operation, the original bit order of the alignment sequence that has been disrupted is restored.

9. The encoding method according to claim 8, characterized in that: Distributing the transmission data stream after the first interleaving operation into N transmission data streams in parallel, including: The transmission data stream after the first interleaving operation is distributed in sequence in turn with symbols as granularity to form N parallel transmission data streams; Aggregating the decoded N receiving channel data streams into one receiving data stream, including: Data are acquired from N receiving channel data in sequence in turn with symbols as granularity, and are aggregated into the receiving data stream.

10. The encoding method according to claim 8 or 9, characterized in that: Each of the N transmission channel data streams includes a different one from the N transmission coded data streams, and the number of symbols of data from each transmission coded data stream is equal.

11. The encoding method according to claim 8 or 9, characterized in that: The alignment sequence includes N channel identification symbols arranged in sequence, and each of the channel identification symbols identifies one of the physical channels; After the first interleaving operation, the original order of the N channel identification symbols is disrupted; the N channel identification symbols are distributed to the N transmission data streams respectively, and after the second interleaving operation, different channel identification symbols are in different transmission channel data streams, and the physical channel to which the transmission channel data stream corresponding to each channel identification symbol is sent is the same as the physical channel identified by the channel identifier.

12. A decoding method, characterized in that: include: receiving N receiving channel data streams from N physical channels, and performing a third interleaving operation on the N receiving channel data streams; The N receiving channel data streams are obtained after the second interleaving operation of the encoding device at the transmitting end, and the third interleaving operation is an inverse operation of the second interleaving operation; Performing RSFEC decoding on the N receiving channel data streams after the third interleaving operation; The decoded N receiving channel data streams are aggregated into one receiving data stream.

13. The decoding method according to claim 12, characterized in that: Aggregating the decoded N receiving channel data streams into one receiving data stream, including: Data are received from the N RSFEC decoding modules in turn in sequence with symbols as granularity, and are aggregated into the received data stream.

14. The decoding method according to claim 12 or 13, characterized in that: Each of the N receiving channel data streams includes data from a different physical channel, and the number of symbols of the data from each physical channel is equal.

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