A network acceleration card signal indication method and device based on state feedback

Abstract

The present invention provides a network acceleration card signal indication method and device based on state feedback in the field of network equipment signal indication technology, the method comprising: step S1, CPLD sets a first timer, a second timer, and a third timer 3; step S2, after the network acceleration card is turned on, the second timer records the power-on time t2 of the CPU at a time interval of Δt2; when a key is pressed, the first timer records the key pressing time t1 at a time interval of Δt1, and the third timer records the key pressing time t3 at a time interval of Δt3; step S3, CPLD identifies the key triggering power on / off function, reset function or clear CMOS function based on t1, t2 and t3; step S4, during the operation of the network acceleration card, the dual-color indicator light is controlled to indicate the startup state, fault state or host identification state. The advantages of the present invention are: the functionality of the buttons and indicator lights is greatly improved, thereby greatly optimizing the spatial layout of the network acceleration card.

Description

Technical Field

[0001] The present invention relates to the technical field of network device signal indication, and in particular to a network acceleration card signal indication method and device based on state feedback. Background Art

[0002] The network accelerator card is a new and growing network device used to optimize network transmission, reduce latency, and improve data transmission efficiency. One of the design schemes of the network accelerator card is built with an X86 CPU, that is, transferring the server application to a PCIE accelerator card with an integrated X86 CPU and multiple network ports. The design density of such a network accelerator card is very high, with a CPU, memory, and at least 2 network ports on board, and the interface space is also very limited. In order to meet the functional requirements of the network accelerator card, 3 SFP+, 10 optical ports, 1 USB TYPE-C interface, 1 Micro USB interface, 1 RJ45 management port, and 3 network port indicator lights are introduced on the interface, which makes the interface panel space of the network accelerator card very compact, and it is no longer possible to set the power on / off button, reset button, power indicator light, fault indicator light, etc. on the interface panel at the same time, which affects the functionality of the network accelerator card. The operation of the network accelerator card needs to rely on related buttons and indicators for signal indication.

[0003] For example, the Chinese utility model patent with application number CN201620169928.7 and classification number G08B25 / 10 discloses a new computer network security alarm device, which optimizes the spatial layout by reusing the function buttons and alarm indicator lights. The Chinese invention patent with application number CN201610925586.1 and classification number G08B5 / 36 discloses a multi-function signal indicator button, which also reuses the indicator lights and buttons to optimize the spatial layout.

[0004] Therefore, how to provide a network acceleration card signal indication method and device based on state feedback to improve the functionality of buttons and indicator lights, and then optimize the spatial layout of the network acceleration card, has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a network acceleration card signal indication method and device based on state feedback, so as to improve the functionality of buttons and indicator lights, and further optimize the spatial layout of the network acceleration card.

[0006] In a first aspect, the present invention provides a network acceleration card signal indication method based on state feedback, comprising the following steps:

[0007] Step S10, the CPLD of the network acceleration card sets a first timer for recording the duration of a key being pressed, a second timer for recording the duration of a CPU being powered on, and a third timer for recording the duration of a key being pressed, wherein the maximum count values ​​of the first timer, the second timer, and the third timer are T1, T2, and T3, respectively, and the counting time intervals are Δt1, Δt2, and Δt3, respectively, and 4*T1=2*T2=T3, and Δt1<Δt2=Δt3;

[0008] Step S20: After the network acceleration card is powered on, the second timer is used to record the power-on time t2 of the CPU at a time interval of Δt2; when a key is pressed, the first timer is used to record the key pressing time t1 at a time interval of Δt1, and the third timer is used to record the key pressing time t3 at a time interval of Δt3;

[0009] Step S30: The CPLD identifies the state feedback of the key based on t1, t2 and t3 to trigger the signal indication of the power on / off function, the reset function or the clear CMOS function;

[0010] Step S40: During the operation of the network acceleration card, the dual-color indicator light is controlled to provide a signal indication of the startup state, fault state or host recognition state.

[0011] Furthermore, in step S10, the value of T1 is 4 seconds, the value of T2 is 8 seconds, the value of T3 is 16 seconds, the value of Δt1 is 100 milliseconds, the value of Δt2 is 1 second, and the value of Δt3 is 1 second.

[0012] Furthermore, the step S20 is specifically as follows:

[0013] When the button is pressed in the shutdown state, the CPLD detects that the voltage range of the power module input is (2.4V, 3.3V] through the first voltage sensor, and detects that the CPU power signal CORE_OK is high through the second voltage sensor, and the network acceleration card is powered on;

[0014] The second timer records the CPU power-on time t2 at a time interval of Δt2; when a key is pressed, the first timer records the key pressing time t1 at a time interval of Δt1, and the third timer records the key pressing time t3 at a time interval of Δt3;

[0015] When the key is released, the counts of the first timer and the third timer are cleared; when a low level is detected in the CPU input, the count of the second timer is cleared.

[0016] Furthermore, in step S30, the power on / off function is triggered specifically as follows:

[0017] The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and sends a power-on / off signal PWRBTN to the CPU; if so, then:

[0018] Determine whether t1 recorded by the first timer exceeds 3 seconds, if yes, send a power on / off signal PWRBTN to the CPU; if no, do not send a power on / off signal PWRBTN to the CPU;

[0019] The triggering of the reset function is specifically as follows:

[0020] The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and the reset signal RSTBTN is not sent to the CPU. If yes, then:

[0021] Read t1 recorded by the first timer to determine whether 100 milliseconds ≤ t1 ≤ 1 second is satisfied. If so, send a reset signal RSTBTN to the CPU; if not, do not send a reset signal RSTBTN to the CPU.

[0022] The clear CMOS function is specifically as follows:

[0023] The CPLD reads t3 recorded by the third timer, sets the CMOS clear register when t3 is greater than 12 seconds, turns on the red light and keeps it on, and sends a clear CMOS signal CLEAR_CMOS to the RTC control circuit after detecting that the power module is powered off through the first voltage sensor.

[0024] Furthermore, the step S40 specifically includes:

[0025] Step S41, CPLD sets a control mode register. During the operation of the network acceleration card, CPLD determines the value of the control mode register. When the value is 0, it is an automatic control mode, and the process goes to step S42; when the value is 1, it is a manual control mode, and the process goes to step S43;

[0026] Step S42, dividing the 2.24-second indication cycle time of the dual-color indicator light into 7 320-millisecond time slices, the first 4 time slices are used for status indication, and the last 3 time slices are used for cycle interval identification; when the status indication is flashing, within one time slice, the dual-color indicator light is on for 40 milliseconds and off for 280 milliseconds;

[0027] A shift register and a status register are set for the green light and the red light respectively; the values ​​of the shift register are 000000, 000001, 000011, 000111, 001111, 011111, 111111; the values ​​of the status register are 000000, 000001, 000011, 000111, 001111, which respectively represent off, flash once, flash twice, flash three times, and flash four times;

[0028] The CPLD controls the green light to work based on the corresponding values ​​of the shift register and the status register to indicate the startup status of the CPU;

[0029] The CPLD controls the operation of the red light based on the corresponding values ​​of the shift register and the status register to indicate the fault status;

[0030] Step S43, based on the control instruction input by the CPU, the CPLD controls the dual-color indicator light to turn on, off, or flash at 1 Hz to indicate the host recognition status.

[0031] In a second aspect, the present invention provides a network acceleration card signal indication method based on state feedback, comprising the following modules:

[0032] A timer setting module, used for the CPLD of the network acceleration card to set a first timer for recording the duration of a key being pressed, a second timer for recording the duration of a CPU being powered on, and a third timer for recording the duration of a key being pressed, wherein the maximum count values ​​of the first timer, the second timer, and the third timer are T1, T2, and T3, respectively, and the counting time intervals are Δt1, Δt2, and Δt3, respectively, and 4*T1=2*T2=T3, and Δt1<Δt2=Δt3;

[0033] The timer counting module is used for recording the power-on time t2 of the CPU by the second timer at a time interval of Δt2 after the network acceleration card is turned on; when a key is pressed, the key pressing time t1 is recorded by the first timer at a time interval of Δt1, and the key pressing time t3 is recorded by the third timer at a time interval of Δt3;

[0034] A first signal indication module, used for the CPLD to identify the state feedback of the key based on the t1, t2 and t3, so as to trigger the signal indication of the power on / off function, the reset function or the clear CMOS function;

[0035] The second signal indication module is used to control the dual-color indicator light to provide signal indication of the startup status, fault status or host identification status during the operation of the network acceleration card.

[0036] Furthermore, in the timer setting module, the value of T1 is 4 seconds, the value of T2 is 8 seconds, the value of T3 is 16 seconds, the value of Δt1 is 100 milliseconds, the value of Δt2 is 1 second, and the value of Δt3 is 1 second.

[0037] Furthermore, the timer counting module is specifically used for:

[0038] When the button is pressed in the shutdown state, the CPLD detects that the voltage range of the power module input is (2.4V, 3.3V] through the first voltage sensor, and detects that the CPU power signal CORE_OK is high through the second voltage sensor, and the network acceleration card is powered on;

[0039] The second timer records the CPU power-on time t2 at a time interval of Δt2; when a key is pressed, the first timer records the key pressing time t1 at a time interval of Δt1, and the third timer records the key pressing time t3 at a time interval of Δt3;

[0040] When the key is released, the counts of the first timer and the third timer are cleared; when a low level is detected in the CPU input, the count of the second timer is cleared.

[0041] Furthermore, in the first signal indication module, the triggering of the power on / off function is specifically:

[0042] The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and sends a power-on / off signal PWRBTN to the CPU; if so, then:

[0043] Determine whether t1 recorded by the first timer exceeds 3 seconds, if yes, send a power on / off signal PWRBTN to the CPU; if no, do not send a power on / off signal PWRBTN to the CPU;

[0044] The triggering of the reset function is specifically as follows:

[0045] The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and the reset signal RSTBTN is not sent to the CPU. If yes, then:

[0046] Read t1 recorded by the first timer to determine whether 100 milliseconds ≤ t1 ≤ 1 second is satisfied. If so, send a reset signal RSTBTN to the CPU; if not, do not send a reset signal RSTBTN to the CPU.

[0047] The clear CMOS function is specifically as follows:

[0048] The CPLD reads t3 recorded by the third timer, sets the CMOS clear register when t3 is greater than 12 seconds, turns on the red light and keeps it on, and sends a clear CMOS signal CLEAR_CMOS to the RTC control circuit after detecting that the power module is powered off through the first voltage sensor.

[0049] Furthermore, the second signal indication module specifically includes:

[0050] The control mode selection unit is used for the CPLD to set a control mode register. During the operation of the network acceleration card, the CPLD determines the value of the control mode register. When the value is 0, it is an automatic control mode and the automatic control unit is called; when the value is 1, it is a manual control mode and the manual control unit is called;

[0051] An automatic control unit, used to divide the 2.24-second indication cycle time of the two-color indicator light into seven 320-millisecond time slices, wherein the first four time slices are used for status indication and the last three time slices are used for cycle interval identification; when the status indication is flashing, the two-color indicator light is on for 40 milliseconds and off for 280 milliseconds in one time slice;

[0052] A shift register and a status register are set for the green light and the red light respectively; the values ​​of the shift register are 000000, 000001, 000011, 000111, 001111, 011111, 111111; the values ​​of the status register are 000000, 000001, 000011, 000111, 001111, which respectively represent off, flash once, flash twice, flash three times, and flash four times;

[0053] The CPLD controls the green light to work based on the corresponding values ​​of the shift register and the status register to indicate the startup status of the CPU;

[0054] The CPLD controls the operation of the red light based on the corresponding values ​​of the shift register and the status register to indicate a fault state;

[0055] The manual control unit is used for the CPLD to control the control instructions input by the CPU to control the two-color indicator light to turn on, off or flash at 1Hz to indicate the host recognition status.

[0056] The advantages of the present invention are:

[0057] 1. The first timer, the second timer and the third timer are set by the CPLD of the network acceleration card. After the network acceleration card is turned on, the second timer records the power-on time t2 of the CPU at a time interval of Δt2. When a key is pressed, the first timer records the key pressing time t1 at a time interval of Δt1, and the third timer records the key pressing time t3 at a time interval of Δt3. The difference between the first counter and the third counter lies in the different counting time and precision. Then, based on t1, t2 and t3, the CPLD identifies the state feedback of the key to trigger the signal indication of the power on / off function, the reset function or the clear CMOS function. During the operation of the network acceleration card, the dual-color indicator light is controlled based on the control mode register, the shift register and the status register to indicate the signal of the startup state, the fault state or the host identification state. That is, the power on / off function, the reset function and the clear CMOS function are realized by one key, and the signal indication of the startup state, the fault state and the host identification state are realized by one dual-color indicator light, which greatly improves the functionality of the key and the indicator light, and thus greatly optimizes the spatial layout of the network acceleration card.

[0058] 2. By setting the t2 recorded by the second timer to be equal to T2, and the t1 recorded by the first timer to be in [100 milliseconds, 1 second], the reset signal RSTBTN is sent to the CPU; that is, the CPU needs to be powered on for more than 8 seconds, and the key pressing time meets [100 milliseconds, 1 second] to start the reset. If the key pressing time is less than 100 milliseconds, it is judged as a false action, thereby greatly improving the accuracy of reset function recognition and the reliability of startup.

[0059] 3. By setting the t2 recorded by the second timer to be less than T2, the power-on / off signal PWRBTN is directly sent to the CPU; when t2 is equal to T2 and t1 recorded by the first timer exceeds 3 seconds, the power-on / off signal PWRBTN is sent to the CPU; when the network acceleration card is turned off, pressing the button immediately turns it on. When the network acceleration card is turned on, the button must be pressed for more than 3 seconds to trigger the power-on / off function; that is, there is a time difference between the power-on / off function and the reset function. The length of time the button is pressed is [100 milliseconds, 1 second] for the reset function, (1 second, 3 seconds] for an invalid action, and greater than 3 seconds for the power-on / off function. This can effectively distinguish the reset function from the power-on / off function, thereby greatly improving the reliability of the network acceleration card control.

[0060] 4. By setting the first timer and the third timer to record the duration of button pressing, and the maximum count value of the first timer is 4 seconds, and the maximum count value of the third timer is 16 seconds, the t3 recorded by the third timer needs to be greater than 12 seconds to set the CMOS clear register, which can effectively identify whether the CMOS clear function is triggered, further improving the reliability and convenience of network acceleration card control.

[0061] 5. By dividing the 2.24-second indication cycle time of the two-color indicator light into 7 320-millisecond time slices, the first 4 time slices are used for status indication, and the last 3 time slices are used for cycle interval identification; when the status indication is flashing, the two-color indicator light is on for 40 milliseconds and off for 280 milliseconds in one time slice, so that users can clearly identify the number of flashes and cycle intervals, thereby greatly improving the usability and functionality of the two-color indicator light indication.

[0062] 6. By setting CPLD to control buttons and dual-color indicator lights, the corresponding functions and status indications can be executed even if the CPU is powered off, which greatly improves the reliability of network acceleration card control. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0064] Figure 1 The present invention is a flow chart of a network acceleration card signal indication method based on state feedback.

[0065] Figure 2 It is a structural schematic diagram of a network acceleration card signal indicating device based on state feedback of the present invention.

[0066] Figure 3 It is a circuit principle block diagram of the network acceleration card of the present invention.

[0067] Figure 4 It is a circuit diagram of the RTC control circuit of the present invention.

[0068] Figure 5 It is a circuit diagram of the control mode switching of the present invention. DETAILED DESCRIPTION

[0069] The technical solution in the embodiments of the present application has the following overall idea: using the first timer, the second timer, and the third timer to identify the power on / off function, the reset function, and the clear CMOS function of the button, and controlling the indicator light to indicate the startup state, fault state, and host identification state by controlling the mode register, the shift register, and the status register, so as to improve the functionality of the buttons and indicator lights, reduce the number of buttons and indicator lights arranged on the interface panel of the network acceleration card, and thereby optimize the spatial layout of the network acceleration card.

[0070] Please refer to Figures 1 to 5 As shown, the present invention needs to use the following network acceleration card, including a CPLD, a CPU, an RTC control circuit, a button, a two-color indicator light, a pull-up resistor, a power module, a first voltage sensor and a second voltage sensor;

[0071] The RTC control circuit includes a diode D1, a MOS tube Q1, a capacitor C1 and a resistor R1;

[0072] After the capacitor C1 is connected in parallel with the resistor R1, one end is connected to the source of the MOS tube Q1 and grounded, and the other end is connected to the output end of the diode D1 and the gate of the MOS tube Q1; the CPLD is respectively connected to the CPU, the button, the two-color indicator light, the pull-up resistor, the first voltage sensor, the second voltage sensor and the input end of the diode D1; the output end of the power module is connected to the pull-up resistor and the first voltage sensor; the input end of the second voltage sensor is connected to the CPU.

[0073] The button is a multifunctional touch switch with a jitter elimination function; the button is connected to a power module through a pull-up resistor and connected to an input pin of the CPLD, and the power module is used to provide a 3.3V standby power supply.

[0074] The CPLD uses one pin (CORE_OK) to monitor the power-on status of the CPU, a low level indicates the shutdown status, and a high level indicates the power-on status; one pin (P3V3SB_OK) is used to monitor the standby power supply status of the power module. When the voltage is lower than 2.4V, the output low level indicates that the power has been cut off, otherwise it indicates that the power supply is normal; the CPLD sends a power on / off signal (PWRBTN) and a reset signal (RSTBTN) to the CPU according to the action of the button, and sends a clear CMOS signal (CLEAR_CMOS) to the RTC control circuit.

[0075] When the button is released, the signal fed back to the CPLD is high level, and when the button is pressed, the signal fed back to the CPLD is low level. The CPLD decides whether to send a power on / off signal (PWRBTN) or a reset signal (RSTBTN) to the CPU according to the low level time of the button and the state of CORE_OK.

[0076] A preferred embodiment of a network acceleration card signal indication method based on state feedback of the present invention comprises the following steps:

[0077] Step S10, the CPLD of the network acceleration card sets a first timer for recording the duration of a key being pressed, a second timer for recording the duration of a CPU being powered on, and a third timer for recording the duration of a key being pressed, wherein the maximum count values ​​of the first timer, the second timer, and the third timer are T1, T2, and T3, respectively, and the counting time intervals are Δt1, Δt2, and Δt3, respectively, and 4*T1=2*T2=T3, Δt1<Δt2=Δt3; the first timer and the third timer are both used to record the duration of a key being pressed, and the difference between them is that the maximum count values ​​are different (the maximum values ​​of the recording durations are different) and the counting time intervals are different (the resolutions are different), and by setting Δt1<Δt3, that is, reducing the resolution of the third timer, resource occupation can be reduced;

[0078] Step S20: After the network acceleration card is powered on, the second timer is used to record the power-on time t2 of the CPU at a time interval of Δt2; when a key is pressed, the first timer is used to record the key pressing time t1 at a time interval of Δt1, and the third timer is used to record the key pressing time t3 at a time interval of Δt3;

[0079] Step S30: The CPLD identifies the state feedback of the key based on t1, t2 and t3 to trigger the signal indication of the power on / off function, the reset function or the clear CMOS function;

[0080] Step S40: During the operation of the network acceleration card, the dual-color indicator light is controlled to provide a signal indication of the startup state, fault state, or host identification state. The dual-color indicator light of the network acceleration card is composed of a single green light and a red light. The green light is used to indicate the startup state of the CPU, and the red light is used to indicate the fault state and clear CMOS events. Different states are indicated by the number of flashes. When the green and red lights are on at the same time, the dual-color indicator light is displayed in orange. The dual-color indicator light is automatically controlled by the CPLD by default, and can also be changed to manual control mode through the control mode register (manual_en). In this way, the CPU can also use this dual-color indicator light to indicate the host identification state, that is, the CPLD or CPU outputs the dual-color indicator light control signal led_out.

[0081] In the step S10, the value of T1 is 4 seconds, the value of T2 is 8 seconds, the value of T3 is 16 seconds, the value of Δt1 is 100 milliseconds, the value of Δt2 is 1 second, and the value of Δt3 is 1 second.

[0082] That is, the maximum value of the first timer is 4 seconds, the counting time interval is 100 milliseconds, and the counting starts when the key is pressed and a low level is generated, and the counting stops and the count is cleared when the key is released; the maximum value of the second timer is 8 seconds, the counting time interval is 1 second, and the counting starts when the second voltage sensor outputs a high level, and the counting stops and the count is cleared when the second voltage sensor outputs a low level; the maximum value of the third timer is 16 seconds, the counting time interval is 1 second, and the counting starts when the key is pressed and a low level is generated, and the counting stops and the count is cleared when the key is released. The difference between the first counter and the third counter is the counting time and accuracy.

[0083] The step S20 is specifically as follows:

[0084] When the button is pressed in the shutdown state, the CPLD detects that the voltage range of the power module input is (2.4V, 3.3V] through the first voltage sensor, and detects that the CPU power signal CORE_OK is high through the second voltage sensor, and the network acceleration card is powered on;

[0085] The second timer records the CPU power-on time t2 at a time interval of Δt2; when a key is pressed, the first timer records the key pressing time t1 at a time interval of Δt1, and the third timer records the key pressing time t3 at a time interval of Δt3;

[0086] When the key is released, the counts of the first timer and the third timer are cleared; when a low level is detected in the CPU input, the count of the second timer is cleared.

[0087] In step S30, the power on / off function is triggered specifically as follows:

[0088] The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and sends a power-on / off signal PWRBTN to the CPU; if so, then:

[0089] Determine whether t1 recorded by the first timer exceeds 3 seconds, if yes, send a power on / off signal PWRBTN to the CPU; if no, do not send a power on / off signal PWRBTN to the CPU;

[0090] The control logic of power on and off is that when the network accelerator card is in the off state, the button acts as the power on button, and when the power is just turned on, the button cannot be immediately switched to the reset button; when the network accelerator card is in the on state, long pressing for more than 3 seconds is recognized as the power on and off function.

[0091] The triggering of the reset function is specifically as follows:

[0092] The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and the reset signal RSTBTN is not sent to the CPU. If yes, then:

[0093] Read t1 recorded by the first timer to determine whether 100 milliseconds ≤ t1 ≤ 1 second is satisfied. If so, send a reset signal RSTBTN to the CPU; if not, do not send a reset signal RSTBTN to the CPU.

[0094] The control logic of reset is that when the network accelerator card is powered on, the button acts as a reset button.

[0095] The clear CMOS function is specifically as follows:

[0096] The CPLD reads t3 recorded by the third timer, sets the CMOS clear register when t3 is greater than 12 seconds, turns on the red light and keeps it on, and sends a clear CMOS signal CLEAR_CMOS to the RTC control circuit after detecting that the power module is powered off through the first voltage sensor.

[0097] The control logic requirement for clearing CMOS is that the button is pressed for more than 12 seconds to trigger the event of clearing CMOS (setting the CMOS clear register). The normal operation of CPU clearing CMOS is to pull down the RTCRST_N signal of the CPU when the device is powered off. This operation requires ensuring that the device is in a power-off state and short-circuiting the RTCRST_N signal to ground through a jumper cap. However, due to structural limitations, the network acceleration card cannot design a jumper cap space on the IO interface, and it is not convenient to open the chassis to design a jumper cap inside the card. Therefore, CPLD is used to implement this function.

[0098] If CPLD determines that t3 is greater than 12 seconds, it will set the CMOS clear register and turn on the red light to notify the user that the CMOS clearing work has not been performed at this time; when the user disconnects the power supply of the network acceleration card, the P3V3SB_OK signal is triggered to become a low level, and the power module (P3V3SB) is the last power supply to be powered off on the network acceleration card. At this time, except for the CPLD, all power supplies on the network acceleration card have been powered off. The CPLD generates a CLEAR_CMOS signal according to the CMOS clear register. The CLEAR_CMOS signal is a 20ms high-level pulse signal.

[0099] When CLEAR_CMOS is high, capacitor C1 is quickly charged through diode D1, so that the gate of MOS tube Q1 becomes high and turns on, pulling down the RTCRST_N signal to trigger the clear CMOS action. When CLEAR_CMOS is low, diode D1 is cut off, and the charge on capacitor C1 can only be discharged slowly and gradually through resistor R1. After a few seconds, when the voltage of capacitor C1 is lower than the threshold of the gate of MOS tube Q1, MOS tube Q1 is disconnected, and the RTCRST_N signal returns to its original state.

[0100] The step S40 specifically includes:

[0101] Step S41, CPLD sets a control mode register (manual_en). During the operation of the network acceleration card, CPLD determines the value of the control mode register. When the value is 0, it is the automatic control mode, and the process goes to step S42; when the value is 1, it is the manual control mode, and the process goes to step S43;

[0102] like Figure 5 As shown, in the specific implementation, the control mode can be switched through the reverse, AND gate, or OR gate. When manual_en=0, the auto_ctl signal controls the output of the dual-color indicator light; when manual_en=1, the auto_ctl signal is invalid, and the manual_ctl signal controls the output of the dual-color indicator light;

[0103] Step S42, dividing the 2.24-second indication cycle time of the dual-color indicator light into 7 320-millisecond time slices, the first 4 time slices are used for status indication, and the last 3 time slices are used for cycle interval identification; when the status indication is flashing, within one time slice, the dual-color indicator light is on for 40 milliseconds and off for 280 milliseconds;

[0104] According to the demarcation of the time slice, the two-color indicator light has the following five states:

[0105]

[0106] A shift register and a status register are set for the green light and the red light respectively; the values ​​of the shift register are 000000, 000001, 000011, 000111, 001111, 011111, 111111; the values ​​of the status register are 000000, 000001, 000011, 000111, 001111, which respectively represent off, flash once, flash twice, flash three times, and flash four times;

[0107] The control relationship between the status register and the dual-color indicator light is shown in the following table:

[0108]

[0109] The CPLD controls the green light to work based on the corresponding values ​​of the shift register and the status register to indicate the startup status of the CPU;

[0110] The CPLD controls the operation of the red light based on the corresponding values ​​of the shift register and the status register to indicate the fault status;

[0111] In specific implementation, CPLD controls the dual-color indicator light based on the value relationship between the shift register and the status register. Taking the green light as an example, the comparator compares the values ​​of the shift register and the status register. If the value of the shift register is less than the value of the status register, the green light is controlled to flash within the corresponding time slice; otherwise, the green light is turned off. When the CPU starts to boot, the green light gradually increases the number of flashes until the boot is completed (marked BOOT_OK), and the green light is always on, that is, the user can judge the startup status of the CPU by the number of flashes. The red light indicates the fault level of the fault by the number of flashes, and a high-level fault indication will cover a low-level fault indication.

[0112] That is, the value of the status register is fixed within 2.24 seconds, and the value of the shift register is cyclically shifted within 2.24 seconds. The number of flashes is determined by the value size relationship of each time slice. For example, when the value of the status register is 000011, the values ​​of the shift register that are less than 000011 are only 000000 and 000001, so it flashes twice.

[0113] Step S43, based on the control instruction input by the CPU, the CPLD controls the dual-color indicator light to turn on, off, or flash at 1 Hz to indicate the host recognition status.

[0114] A preferred embodiment of a network acceleration card signal indication device based on state feedback of the present invention includes the following modules:

[0115] A timer setting module, used for the CPLD of the network acceleration card to set a first timer for recording the duration of a key being pressed, a second timer for recording the duration of a CPU being powered on, and a third timer for recording the duration of a key being pressed, wherein the maximum count values ​​of the first timer, the second timer, and the third timer are T1, T2, and T3, respectively, and the counting time intervals are Δt1, Δt2, and Δt3, respectively, and 4*T1=2*T2=T3, Δt1<Δt2=Δt3; the first timer and the third timer are both used to record the duration of a key being pressed, and the difference is that the maximum count values ​​are different (the maximum values ​​of the recording duration are different) and the counting time intervals are different (the resolutions are different), and by setting Δt1<Δt3, that is, reducing the resolution of the third timer, resource usage can be reduced;

[0116] The timer counting module is used for recording the power-on time t2 of the CPU by the second timer at a time interval of Δt2 after the network acceleration card is turned on; when a key is pressed, the key pressing time t1 is recorded by the first timer at a time interval of Δt1, and the key pressing time t3 is recorded by the third timer at a time interval of Δt3;

[0117] A first signal indication module, used for the CPLD to identify the state feedback of the key based on the t1, t2 and t3, so as to trigger the signal indication of the power on / off function, the reset function or the clear CMOS function;

[0118] The second signal indication module is used to control the dual-color indicator light to indicate the startup status, fault status or host identification status during the operation of the network acceleration card. The dual-color indicator light of the network acceleration card consists of a single green light and a red light. The green light is used to indicate the startup status of the CPU, and the red light is used to indicate the fault status and clear CMOS events. The number of flashes indicates different states. When the green and red lights are on at the same time, the dual-color indicator light is displayed in orange. The dual-color indicator light is automatically controlled by the CPLD by default, and can also be changed to manual control mode through the control mode register (manual_en), so that the CPU can also use this dual-color indicator light to indicate the host identification status.

[0119] In the timer setting module, the value of T1 is 4 seconds, the value of T2 is 8 seconds, the value of T3 is 16 seconds, the value of Δt1 is 100 milliseconds, the value of Δt2 is 1 second, and the value of Δt3 is 1 second.

[0120] That is, the maximum value of the first timer is 4 seconds, the counting time interval is 100 milliseconds, and the counting starts when the key is pressed and a low level is generated, and the counting stops and the count is cleared when the key is released; the maximum value of the second timer is 8 seconds, the counting time interval is 1 second, and the counting starts when the second voltage sensor outputs a high level, and the counting stops and the count is cleared when the second voltage sensor outputs a low level; the maximum value of the third timer is 16 seconds, the counting time interval is 1 second, and the counting starts when the key is pressed and a low level is generated, and the counting stops and the count is cleared when the key is released. The difference between the first counter and the third counter is the counting time and accuracy.

[0121] The timer counting module is specifically used for:

[0122] When the button is pressed in the shutdown state, the CPLD detects that the voltage range of the power module input is (2.4V, 3.3V] through the first voltage sensor, and detects that the CPU power signal CORE_OK is high through the second voltage sensor, and the network acceleration card is powered on;

[0123] The second timer records the CPU power-on time t2 at a time interval of Δt2; when a key is pressed, the first timer records the key pressing time t1 at a time interval of Δt1, and the third timer records the key pressing time t3 at a time interval of Δt3;

[0124] When the key is released, the counts of the first timer and the third timer are cleared; when a low level is detected in the CPU input, the count of the second timer is cleared.

[0125] In the first signal indication module, the triggering of the power on / off function is specifically:

[0126] The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and sends a power-on / off signal PWRBTN to the CPU; if so, then:

[0127] Determine whether t1 recorded by the first timer exceeds 3 seconds, if yes, send a power on / off signal PWRBTN to the CPU; if no, do not send a power on / off signal PWRBTN to the CPU;

[0128] The control logic of power on and off is that when the network accelerator card is in the off state, the button acts as the power on button, and when the power is just turned on, the button cannot be immediately switched to the reset button; when the network accelerator card is in the on state, long pressing for more than 3 seconds is recognized as the power on and off function.

[0129] The triggering of the reset function is specifically as follows:

[0130] The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and the reset signal RSTBTN is not sent to the CPU. If yes, then:

[0131] Read t1 recorded by the first timer to determine whether 100 milliseconds ≤ t1 ≤ 1 second is satisfied. If so, send a reset signal RSTBTN to the CPU; if not, do not send a reset signal RSTBTN to the CPU.

[0132] The control logic of reset is that when the network accelerator card is powered on, the button acts as a reset button.

[0133] The clear CMOS function is specifically as follows:

[0134] The CPLD reads t3 recorded by the third timer, sets the CMOS clear register when t3 is greater than 12 seconds, turns on the red light and keeps it on, and sends a clear CMOS signal CLEAR_CMOS to the RTC control circuit after detecting that the power module is powered off through the first voltage sensor.

[0135] The control logic requirement for clearing CMOS is that the button is pressed for more than 12 seconds to trigger the event of clearing CMOS (setting the CMOS clear register). The normal operation of CPU clearing CMOS is to pull down the RTCRST_N signal of the CPU when the device is powered off. This operation requires ensuring that the device is in a power-off state and short-circuiting the RTCRST_N signal to ground through a jumper cap. However, due to structural limitations, the network acceleration card cannot design a jumper cap space on the IO interface, and it is not convenient to open the chassis to design a jumper cap inside the card. Therefore, CPLD is used to implement this function.

[0136] If CPLD determines that t3 is greater than 12 seconds, it will set the CMOS clear register and turn on the red light to notify the user that the CMOS clearing work has not been performed at this time; when the user disconnects the power supply of the network acceleration card, the P3V3SB_OK signal is triggered to become a low level, and the power module (P3V3SB) is the last power supply to be powered off on the network acceleration card. At this time, except for the CPLD, all power supplies on the network acceleration card have been powered off. The CPLD generates a CLEAR_CMOS signal according to the CMOS clear register. The CLEAR_CMOS signal is a 20ms high-level pulse signal.

[0137] When CLEAR_CMOS is high, capacitor C1 is quickly charged through diode D1, so that the gate of MOS tube Q1 becomes high and turns on, pulling down the RTCRST_N signal to trigger the clear CMOS action. When CLEAR_CMOS is low, diode D1 is cut off, and the charge on capacitor C1 can only be discharged slowly and gradually through resistor R1. After a few seconds, when the voltage of capacitor C1 is lower than the threshold of the gate of MOS tube Q1, MOS tube Q1 is disconnected, and the RTCRST_N signal returns to its original state.

[0138] The second signal indication module specifically includes:

[0139] The control mode selection unit is used for the CPLD to set a control mode register (manual_en). During the operation of the network acceleration card, the CPLD determines the value of the control mode register. When the value is 0, it is an automatic control mode and the automatic control unit is called; when the value is 1, it is a manual control mode and the manual control unit is called;

[0140] like Figure 5 As shown, in the specific implementation, the control mode can be switched through the reverse, AND gate, or OR gate. When manual_en=0, the auto_ctl signal controls the output of the dual-color indicator light; when manual_en=1, the auto_ctl signal is invalid, and the manual_ctl signal controls the output of the dual-color indicator light;

[0141] An automatic control unit, used to divide the 2.24-second indication cycle time of the two-color indicator light into seven 320-millisecond time slices, wherein the first four time slices are used for status indication and the last three time slices are used for cycle interval identification; when the status indication is flashing, the two-color indicator light is on for 40 milliseconds and off for 280 milliseconds in one time slice;

[0142] According to the demarcation of the time slice, the two-color indicator light has the following five states:

[0143]

[0144] A shift register and a status register are set for the green light and the red light respectively; the values ​​of the shift register are 000000, 000001, 000011, 000111, 001111, 011111, 111111; the values ​​of the status register are 000000, 000001, 000011, 000111, 001111, which respectively represent off, flash once, flash twice, flash three times, and flash four times;

[0145] The control relationship between the status register and the dual-color indicator light is shown in the following table:

[0146]

[0147] The CPLD controls the green light to work based on the corresponding values ​​of the shift register and the status register to indicate the startup status of the CPU;

[0148] The CPLD controls the operation of the red light based on the corresponding values ​​of the shift register and the status register to indicate the fault status;

[0149] In specific implementation, CPLD controls the dual-color indicator light based on the value relationship between the shift register and the status register. Taking the green light as an example, the comparator compares the values ​​of the shift register and the status register. If the value of the shift register is less than the value of the status register, the green light is controlled to flash within the corresponding time slice; otherwise, the green light is turned off. When the CPU starts to boot, the green light gradually increases the number of flashes until the boot is completed (marked BOOT_OK), and the green light is always on, that is, the user can judge the startup status of the CPU by the number of flashes. The red light indicates the fault level of the fault by the number of flashes, and a high-level fault indication will cover a low-level fault indication.

[0150] That is, the value of the status register is fixed within 2.24 seconds, and the value of the shift register is cyclically shifted within 2.24 seconds. The number of flashes is determined by the value size relationship of each time slice. For example, when the value of the status register is 000011, the values ​​of the shift register that are less than 000011 are only 000000 and 000001, so it flashes twice.

[0151] The manual control unit is used for the CPLD to control the control instructions input by the CPU to control the two-color indicator light to turn on, off or flash at 1Hz to indicate the host recognition status.

[0152] In summary, the advantages of the present invention are:

[0153] 1. The first timer, the second timer and the third timer are set by the CPLD of the network acceleration card. After the network acceleration card is turned on, the second timer records the power-on time t2 of the CPU at a time interval of Δt2. When a key is pressed, the first timer records the key pressing time t1 at a time interval of Δt1, and the third timer records the key pressing time t3 at a time interval of Δt3. The difference between the first counter and the third counter lies in the different counting time and precision. Then, based on t1, t2 and t3, the CPLD identifies the state feedback of the key to trigger the signal indication of the power on / off function, the reset function or the clear CMOS function. During the operation of the network acceleration card, the dual-color indicator light is controlled based on the control mode register, the shift register and the status register to indicate the signal of the startup state, the fault state or the host identification state. That is, the power on / off function, the reset function and the clear CMOS function are realized by one key, and the signal indication of the startup state, the fault state and the host identification state are realized by one dual-color indicator light, which greatly improves the functionality of the key and the indicator light, and thus greatly optimizes the spatial layout of the network acceleration card.

[0154] 2. By setting the t2 recorded by the second timer to be equal to T2, and the t1 recorded by the first timer to be in [100 milliseconds, 1 second], the reset signal RSTBTN is sent to the CPU; that is, the CPU needs to be powered on for more than 8 seconds, and the key pressing time meets [100 milliseconds, 1 second] to start the reset. If the key pressing time is less than 100 milliseconds, it is judged as a false action, thereby greatly improving the accuracy of reset function recognition and the reliability of startup.

[0155] 3. By setting the t2 recorded by the second timer to be less than T2, the power-on / off signal PWRBTN is directly sent to the CPU; when t2 is equal to T2 and t1 recorded by the first timer exceeds 3 seconds, the power-on / off signal PWRBTN is sent to the CPU; when the network acceleration card is turned off, pressing the button immediately turns it on. When the network acceleration card is turned on, the button must be pressed for more than 3 seconds to trigger the power-on / off function; that is, there is a time difference between the power-on / off function and the reset function. The length of time the button is pressed is [100 milliseconds, 1 second] for the reset function, (1 second, 3 seconds] for an invalid action, and greater than 3 seconds for the power-on / off function. This can effectively distinguish the reset function from the power-on / off function, thereby greatly improving the reliability of the network acceleration card control.

[0156] 4. By setting the first timer and the third timer to record the duration of button pressing, and the maximum count value of the first timer is 4 seconds, and the maximum count value of the third timer is 16 seconds, the t3 recorded by the third timer needs to be greater than 12 seconds to set the CMOS clear register, which can effectively identify whether the CMOS clear function is triggered, further improving the reliability and convenience of network acceleration card control.

[0157] 5. By dividing the 2.24-second indication cycle time of the two-color indicator light into 7 320-millisecond time slices, the first 4 time slices are used for status indication, and the last 3 time slices are used for cycle interval identification; when the status indication is flashing, the two-color indicator light is on for 40 milliseconds and off for 280 milliseconds in one time slice, so that users can clearly identify the number of flashes and cycle intervals, thereby greatly improving the usability and functionality of the two-color indicator light indication.

[0158] 6. By setting CPLD to control buttons and dual-color indicator lights, the corresponding functions and status indications can be executed even if the CPU is powered off, which greatly improves the reliability of network acceleration card control.

[0159] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A network acceleration card signal indication method based on state feedback, characterized in that: The steps include: Step S10, the CPLD of the network acceleration card sets a first timer for recording the duration of a key being pressed, a second timer for recording the duration of a CPU being powered on, and a third timer for recording the duration of a key being pressed, the maximum count values ​​of the first timer, the second timer, and the third timer are T1, T2, and T3, respectively, the counting time intervals are Δt1, Δt2, and Δt3, respectively, and 4*T1=2*T2=T3, Δt1<Δt2=Δt3; the value of T1 is 4 seconds, the value of T2 is 8 seconds, the value of T3 is 16 seconds, the value of Δt1 is 100 milliseconds, the value of Δt2 is 1 second, and the value of Δt3 is 1 second; Step S20: After the network acceleration card is powered on, the second timer is used to record the power-on time t2 of the CPU at a time interval of Δt2; when a key is pressed, the first timer is used to record the key pressing time t1 at a time interval of Δt1, and the third timer is used to record the key pressing time t3 at a time interval of Δt3; Step S30: The CPLD identifies the state feedback of the key based on t1, t2 and t3 to trigger the signal indication of the power on / off function, the reset function or the clear CMOS function; Step S40: During the operation of the network acceleration card, the dual-color indicator light is controlled to provide a signal indication of a startup state, a fault state, or a host recognition state; In step S30, the power on / off function is triggered specifically as follows: The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and sends a power-on / off signal PWRBTN to the CPU; if so, then: Determine whether t1 recorded by the first timer exceeds 3 seconds, if yes, send a power on / off signal PWRBTN to the CPU; if no, do not send a power on / off signal PWRBTN to the CPU; The triggering of the reset function is specifically as follows: The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and the reset signal RSTBTN is not sent to the CPU. If yes, then: Read t1 recorded by the first timer to determine whether 100 milliseconds ≤ t1 ≤ 1 second is satisfied. If so, send a reset signal RSTBTN to the CPU; if not, do not send a reset signal RSTBTN to the CPU. The clear CMOS function is specifically as follows: The CPLD reads t3 recorded by the third timer, sets the CMOS clear register when t3 is greater than 12 seconds, turns on the red light and keeps it on, and sends a clear CMOS signal CLEAR_CMOS to the RTC control circuit after detecting that the power module is powered off through the first voltage sensor.

2. A network acceleration card signal indication method based on state feedback as claimed in claim 1, characterized in that: The step S20 is specifically as follows: When the button is pressed in the shutdown state, the CPLD detects that the voltage range of the power module input is (2.4V, 3.3V] through the first voltage sensor, and detects that the CPU power signal CORE_OK is high through the second voltage sensor, and the network acceleration card is powered on; The second timer records the CPU power-on time t2 at a time interval of Δt2; when a key is pressed, the first timer records the key pressing time t1 at a time interval of Δt1, and the third timer records the key pressing time t3 at a time interval of Δt3; When the key is released, the counts of the first timer and the third timer are cleared; when a low level is detected in the CPU input, the count of the second timer is cleared.

3. A network acceleration card signal indication method based on state feedback as claimed in claim 1, characterized in that: The step S40 specifically includes: Step S41, CPLD sets a control mode register. During the operation of the network acceleration card, CPLD determines the value of the control mode register. When the value is 0, it is an automatic control mode, and the process goes to step S42; when the value is 1, it is a manual control mode, and the process goes to step S43; Step S42, dividing the 2.24-second indication cycle time of the dual-color indicator light into 7 320-millisecond time slices, the first 4 time slices are used for status indication, and the last 3 time slices are used for cycle interval identification; when the status indication is flashing, within one time slice, the dual-color indicator light is on for 40 milliseconds and off for 280 milliseconds; A shift register and a status register are set for the green light and the red light respectively; the values ​​of the shift register are 000000, 000001, 000011, 000111, 001111, 011111, 111111; the values ​​of the status register are 000000, 000001, 000011, 000111, 001111, which respectively represent off, flash once, flash twice, flash three times, and flash four times; The CPLD controls the green light to work based on the corresponding values ​​of the shift register and the status register to indicate the startup status of the CPU; The CPLD controls the operation of the red light based on the corresponding values ​​of the shift register and the status register to indicate the fault status; Step S43, based on the control instruction input by the CPU, the CPLD controls the dual-color indicator light to turn on, off, or flash at 1 Hz to indicate the host recognition status.

4. A network acceleration card signal indication device based on state feedback, characterized in that: Includes the following modules: A timer setting module, used for the CPLD of the network acceleration card to set a first timer for recording the duration of a key being pressed, a second timer for recording the duration of a CPU being powered on, and a third timer for recording the duration of a key being pressed, wherein the maximum count values ​​of the first timer, the second timer, and the third timer are T1, T2, and T3, respectively, and the counting time intervals are Δt1, Δt2, and Δt3, respectively, and 4*T1=2*T2=T3, Δt1<Δt2=Δt3; the value of T1 is 4 seconds, the value of T2 is 8 seconds, the value of T3 is 16 seconds, the value of Δt1 is 100 milliseconds, the value of Δt2 is 1 second, and the value of Δt3 is 1 second; The timer counting module is used for recording the power-on time t2 of the CPU by the second timer at a time interval of Δt2 after the network acceleration card is turned on; when a key is pressed, the key pressing time t1 is recorded by the first timer at a time interval of Δt1, and the key pressing time t3 is recorded by the third timer at a time interval of Δt3; A first signal indication module, used for the CPLD to identify the state feedback of the key based on the t1, t2 and t3, so as to trigger the signal indication of the power on / off function, the reset function or the clear CMOS function; The second signal indication module is used to control the dual-color indicator light to indicate the startup state, fault state or host identification state during the operation of the network acceleration card; In the first signal indication module, the triggering of the power on / off function is specifically: The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and sends a power-on / off signal PWRBTN to the CPU; if so, then: Determine whether t1 recorded by the first timer exceeds 3 seconds, if yes, send a power on / off signal PWRBTN to the CPU; if no, do not send a power on / off signal PWRBTN to the CPU; The triggering of the reset function is specifically as follows: The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and the reset signal RSTBTN is not sent to the CPU. If yes, then: Read t1 recorded by the first timer to determine whether 100 milliseconds ≤ t1 ≤ 1 second is satisfied. If so, send a reset signal RSTBTN to the CPU; if not, do not send a reset signal RSTBTN to the CPU. The clear CMOS function is specifically as follows: The CPLD reads t3 recorded by the third timer, sets the CMOS clear register when t3 is greater than 12 seconds, turns on the red light and keeps it on, and sends a clear CMOS signal CLEAR_CMOS to the RTC control circuit after detecting that the power module is powered off through the first voltage sensor.

5. A network acceleration card signal indication device based on state feedback as claimed in claim 4, characterized in that: The timer counting module is specifically used for: When the button is pressed in the shutdown state, the CPLD detects that the voltage range of the power module input is (2.4V, 3.3V] through the first voltage sensor, and detects that the CPU power signal CORE_OK is high through the second voltage sensor, and the network acceleration card is powered on; The second timer records the CPU power-on time t2 at a time interval of Δt2; when a key is pressed, the first timer records the key pressing time t1 at a time interval of Δt1, and the third timer records the key pressing time t3 at a time interval of Δt3; When the key is released, the counts of the first timer and the third timer are cleared; when a low level is detected in the CPU input, the count of the second timer is cleared.

6. A network acceleration card signal indication device based on state feedback as claimed in claim 4, characterized in that: The second signal indication module specifically includes: The control mode selection unit is used for the CPLD to set a control mode register. During the operation of the network acceleration card, the CPLD determines the value of the control mode register. When the value is 0, it is an automatic control mode and the automatic control unit is called; when the value is 1, it is a manual control mode and the manual control unit is called; An automatic control unit, used to divide the 2.24-second indication cycle time of the two-color indicator light into seven 320-millisecond time slices, wherein the first four time slices are used for status indication and the last three time slices are used for cycle interval identification; when the status indication is flashing, the two-color indicator light is on for 40 milliseconds and off for 280 milliseconds in one time slice; A shift register and a status register are set for the green light and the red light respectively; the values ​​of the shift register are 000000, 000001, 000011, 000111, 001111, 011111, 111111; the values ​​of the status register are 000000, 000001, 000011, 000111, 001111, which respectively represent off, flash once, flash twice, flash three times, and flash four times; The CPLD controls the green light to work based on the corresponding values ​​of the shift register and the status register to indicate the startup status of the CPU; The CPLD controls the operation of the red light based on the corresponding values ​​of the shift register and the status register to indicate the fault status; The manual control unit is used for the CPLD to control the control instructions input by the CPU to control the two-color indicator light to turn on, off or flash at 1Hz to indicate the host recognition status.

Images