Capacitor structure

Abstract

The invention relates to a capacitor structure which can be applied to a three-dimensional AND flash memory element. The capacitor structure comprises a substrate, an array lower circuit structure, a bottom conductive layer, a stacking structure and a plurality of columnar structures. The substrate is provided with a capacitor array area and a capacitor step area. The array lower circuit structure is arranged on the substrate. And the bottom conductive layer is arranged on the array lower circuit structure. The stacking structure is arranged on the bottom conductive layer and comprises a plurality of first dielectric layers and a plurality of conductive layers which are alternately stacked, and the plurality of conductive layers in the capacitor step region are arranged in a step form. And the plurality of columnar structures are arranged in the capacitor array region in an array manner and penetrate through the stacking structure and the bottom conductive layer. A portion of the plurality of conductive layers is electrically connected to a first common voltage source, and the remaining portion of the plurality of conductive layers and the bottom conductive layer are electrically connected to a second common voltage source.

Description

Technical Field

[0001] The invention relates to a semiconductor structure, and in particular to a capacitor structure. Background Art

[0002] For three-dimensional AND memory elements, as array loading increases, the need for high capacitance also increases. Generally speaking, capacitance is proportional to area, so the area of ​​the chip occupied by the three-dimensional AND memory element also increases. In particular, when high-capacitance circuits are required, if these capacitors are placed in the peripheral area of ​​the array structure in the three-dimensional AND memory element, a large area of ​​the chip will be occupied. Summary of the invention

[0003] The present invention provides a capacitor structure, wherein a portion of the conductive layers in the stacked structure are electrically connected to a common voltage source, and the remaining portion of the conductive layers in the stacked structure and the bottom conductive layer thereunder are electrically connected to another common voltage source.

[0004] The capacitor structure of the present invention comprises a substrate, a circuit under array (CuA) structure, a bottom conductive layer, a stacked structure and a plurality of columnar structures. The substrate has a capacitor array region and a capacitor step region. The circuit under array structure is arranged on the substrate. The bottom conductive layer is arranged on the circuit under array structure. The stacked structure is arranged on the bottom conductive layer and comprises a plurality of first dielectric layers and a plurality of conductive layers alternately stacked, wherein the plurality of conductive layers in the capacitor step region are arranged in a stepped form. The plurality of columnar structures are arranged in the capacitor array region in an array manner and penetrate the stacked structure and the bottom conductive layer. A portion of the conductive layers in the plurality of conductive layers are electrically connected to a first common voltage source, and the remaining portion of the conductive layers in the plurality of conductive layers and the bottom conductive layer are electrically connected to a second common voltage source.

[0005] In an embodiment of the capacitor structure of the present invention, the conductive layers of the portion include odd-numbered conductive layers among the plurality of conductive layers, and the conductive layers of the remaining portion include even-numbered conductive layers among the plurality of conductive layers.

[0006] In an embodiment of the capacitor structure of the present invention, at least one pair of adjacent conductive layers among the plurality of conductive layers is electrically connected to the first common voltage source or the second common voltage source.

[0007] In an embodiment of the capacitor structure of the present invention, the bottom conductive layer and the lowest conductive layer among the plurality of conductive layers are electrically connected to the first common voltage source or the second common voltage source.

[0008] In an embodiment of the capacitor structure of the present invention, the conductive layer connected to the first common voltage source, the adjacent conductive layer connected to the second common voltage source, and the first dielectric layer therebetween constitute a capacitor unit.

[0009] In one embodiment of the capacitor structure of the present invention, it also includes a plurality of conductive pillars located in the capacitor step region and arranged on the plurality of conductive layers and the bottom conductive layer, so that the plurality of conductive layers and the bottom conductive layer are electrically connected to the corresponding common voltage source through the plurality of conductive pillars.

[0010] In an embodiment of the capacitor structure of the present invention, each of the plurality of columnar structures includes a first insulating column.

[0011] In an embodiment of the capacitor structure of the present invention, each of the plurality of columnar structures further includes a second insulating column disposed in the first insulating column.

[0012] In one embodiment of the capacitor structure of the present invention, each of the plurality of columnar structures further comprises a semiconductor layer and an insulating layer. The semiconductor layer is disposed between the first insulating column and the stacked structure and between the first insulating column and the bottom conductive layer. The insulating layer is disposed between the semiconductor layer and the stacked structure and between the semiconductor layer and the bottom conductive layer.

[0013] In an embodiment of the capacitor structure of the present invention, each of the semiconductor layers is electrically connected to a third common voltage source through a conductive plug.

[0014] In an embodiment of the capacitor structure of the present invention, the conductive layer connected to the first common voltage source, the semiconductor layer, and the insulating layer therebetween constitute a capacitor unit.

[0015] In an embodiment of the capacitor structure of the present invention, the conductive layer connected to the second common voltage source, the semiconductor layer, and the insulating layer therebetween constitute a capacitor unit.

[0016] In an embodiment of the capacitor structure of the present invention, the array-based circuit structure further includes a metal oxide semiconductor capacitor.

[0017] In one embodiment of the capacitor structure of the present invention, the bottom conductive layer and the stacked structure have an annular channel, the annular channel penetrates the bottom conductive layer and the stacked structure, and the stacked structure in the capacitor array area and the capacitor step area is surrounded by the annular channel.

[0018] In one embodiment of the capacitor structure of the present invention, the bottom conductive layer and the stacked structure have a plurality of annular channels, each of the plurality of annular channels penetrates the bottom conductive layer and the stacked structure, and each of the annular channels extends along the column direction of the capacitor array region and surrounds at least one column of the columnar structure and the stacked structure in the capacitor step region to form an independent conductive block.

[0019] In an embodiment of the capacitor structure of the present invention, it further includes a plurality of second dielectric layers disposed between adjacent conductive blocks and located between the plurality of first dielectric layers at positions corresponding to the conductive layers in the stacking direction of the stacking structure.

[0020] In an embodiment of the capacitor structure of the present invention, the second dielectric layer is located between the conductive layers of adjacent conductive blocks.

[0021] In an embodiment of the capacitor structure of the present invention, the material of the second dielectric layer is different from the material of the first dielectric layer.

[0022] Based on the above, in the capacitor structure of the present invention, a portion of the conductive layers in the stacked structure are electrically connected to a common voltage source, and the remaining portion of the conductive layers in the stacked structure and the bottom conductive layer below are electrically connected to another common voltage source. In this way, the two conductive layers and the dielectric layer therebetween can constitute a capacitor unit, and the lowest conductive layer in the stacked structure, the bottom conductive layer below, and the dielectric layer therebetween can constitute a capacitor unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1A FIG. 4 is a cross-sectional schematic diagram of a capacitor structure according to a first embodiment of the present invention.

[0024] Figure 1B FIG. 1 is a schematic top view of a capacitor structure according to a first embodiment of the present invention.

[0025] Figure 2 FIG. 4 is a three-dimensional schematic diagram of a metal oxide semiconductor capacitor included in a circuit structure under an array according to an embodiment of the present invention.

[0026] Figure 3 FIG. 4 is a cross-sectional schematic diagram of a capacitor structure according to a second embodiment of the present invention.

[0027] Figure 4 FIG. 4 is a cross-sectional schematic diagram of a capacitor structure according to a third embodiment of the present invention.

[0028] Figure 5A FIG. 4 is a schematic top view of a capacitor structure according to a fourth embodiment of the present invention.

[0029] Figure 5B For along Figure 5A Schematic diagram of the cross section along the BB section line in FIG.

[0030] Figure 6 FIG. 4 is a three-dimensional schematic diagram of a stacked structure in the capacitor structure of the first embodiment.

[0031] 7A to 7E The invention describes adjusting the electrical connection relationship between the conductive layer in the stacked structure and the bottom conductive layer and the common voltage source to obtain the required capacitance value.

[0032] Description of Reference Numerals

[0033] 10, 30, 40, 50: Capacitor structure

[0034] 10a: Sub-capacitor structure

[0035] 20: Metal oxide semiconductor capacitor

[0036] 20a: Gate dielectric layer

[0037] 20b: Gate

[0038] 22, 24: Contact window

[0039] 100: Base

[0040] 100a: Capacitor array area

[0041] 100b: Capacitor step area

[0042] 102: Circuit structure under the array

[0043] 104: Bottom conductive layer

[0044] 106: Stacked structure

[0045] 106a, 108, 502: dielectric layer

[0046] 106b: Conductive layer

[0047] 1 10a, 1 10b: Conductive pillars

[0048] 112, 300, 400: Columnar structure

[0049] 112a, 112b: Insulation column

[0050] 300a: Semiconductor layer

[0051] 300b: Insulation layer

[0052] 400a: Conductive plug

[0053] 500: Conductive block

[0054] P1, P2, P3: common voltage source

[0055] SW: Sidewall

[0056] SLT: Lateral Trench

[0057] TR, TR1: Annular groove DETAILED DESCRIPTION

[0058] The following examples are listed and described in detail with the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn to their original size. For ease of understanding, the same elements will be described with the same symbols in the following description.

[0059] The terms "include", "including", "have", etc. used in this document are open terms, which means "including but not limited to".

[0060] In addition, the directional terms mentioned herein, such as "upper", "lower", etc., are only used to refer to the directions of the drawings and are not used to limit the present invention. Therefore, it should be understood that "upper" can be used interchangeably with "lower", and when an element such as a layer or film is placed "on" another element, the element can be placed directly on the other element, or there can be an intermediate element. On the other hand, when an element is said to be placed "directly" on another element, there is no intermediate element between the two.

[0061] The capacitor structure of the present invention can be used for application and integration in a three-dimensional AND flash memory element. Furthermore, the capacitor structure of the present invention can be formed in the same process as the three-dimensional AND flash memory structure. The same stacking structure including multiple dielectric layers and multiple conductive layers stacked alternately can be used to form the capacitor structure of the present invention and the three-dimensional AND flash memory structure. In other words, the capacitor structure of the present invention can have a main architecture similar to that of the three-dimensional AND flash memory structure. Therefore, there is no need to set up additional capacitors in the peripheral area of ​​the array structure of the three-dimensional AND memory element, thereby saving the use area of ​​the chip. This will be described in detail below.

[0062] Figure 1A FIG. 4 is a cross-sectional schematic diagram of a capacitor structure according to a first embodiment of the present invention. Figure 1B FIG. 1 is a schematic top view of a capacitor structure according to a first embodiment of the present invention. Figure 1B In order to make the drawings clear and convenient for explanation, the stacking structure including multiple dielectric layers and multiple conductive layers stacked alternately is omitted. Figure 1A Can be along Figure 1B Schematic diagram of the cross section drawn by the AA section line in FIG.

[0063] Also refer to Figure 1A and Figure 1B, the capacitor structure 10 of the present embodiment includes a substrate 100, a circuit structure under the array 102, a bottom conductive layer 104, a stacked structure 106, a dielectric layer 108, a conductive column 110a, a conductive column 110b and a columnar structure 112. In the present embodiment, the substrate 100 may be a silicon substrate, which has a capacitor array area 100a and a capacitor step area 100b. In addition, the substrate 100 may also have a memory area (not shown) outside the capacitor array area 100a and the capacitor step area 100b. Since the capacitor structure 10 of the present embodiment can be formed in the same process as the three-dimensional AND flash memory structure, the two have a similar main architecture, and the above-mentioned memory area will also be provided with components that are the same or similar to those in the capacitor array area 100a and the capacitor step area 100b.

[0064] The array circuit structure 102 is disposed on the substrate 100. The array circuit structure 102 may include a transistor, an interconnect structure, and a dielectric layer covering the transistor and the interconnect structure, but the present invention is not limited thereto. The detailed structure of the array circuit structure 102 is well known to those skilled in the art and will not be described in detail herein. Figure 1A In order to make the drawings clear and convenient for description, the detailed structure of the circuit structure 102 under the array is not shown.

[0065] The bottom conductive layer 104 is disposed on the circuit structure 102 below the array. The bottom conductive layer 104 may be a polysilicon layer, but the present invention is not limited thereto. In this embodiment, the bottom conductive layer 104 located in the capacitor array region 100a and the capacitor step region 100b may be used as an electrode layer of the capacitor (which will be described later), and the bottom conductive layer 104 located in the memory region of the substrate 100 may be used as a ground layer.

[0066] The stacked structure 106 is arranged on the bottom conductive layer 104. The stacked structure 106 includes a plurality of dielectric layers 106a and a plurality of conductive layers 106b that are alternately stacked. In the present embodiment, the dielectric layer 106a can be a silicon oxide layer, and the conductive layer 106b can be a metal layer, but the present invention is not limited thereto. In addition, in the present embodiment, the dielectric layer 106a and the conductive layer 106b are alternately stacked on the bottom conductive layer 104, the uppermost dielectric layer 106a covers the uppermost conductive layer 106b, and in the capacitor step region 100b, these conductive layers 106b are arranged in a stepped form. In other words, in the capacitor step region 100b, the sidewall SW of the end of the conductive layer 106b of the upper layer is located on the top surface of the conductive layer 106b of the lower layer, so that part of the top surface of the conductive layer 106b of the lower layer is exposed. In addition, the uppermost dielectric layer 106a covers a portion of the uppermost conductive layer 106b, so that another portion of the top surface of the uppermost conductive layer 106b is exposed. Figure 1AIn the embodiment, the stacked structure 106 includes 5 dielectric layers 106a and 4 conductive layers 106b, but the invention does not limit the number of the dielectric layers 106a and the conductive layers 106b.

[0067] The dielectric layer 108 covers the stacked structure 106. A plurality of conductive pillars 110a are disposed in the dielectric layer 108 in the capacitor step region 100b, and each of the conductive pillars 110a is connected to a corresponding one of the conductive layers 106b arranged in a step form. In addition, the conductive pillars 110b are disposed in the dielectric layer 108 in the capacitor step region 100b and are connected to the bottom conductive layer 104. In this embodiment, as shown in FIG. Figure 1B As shown, from the top view, the conductive pillars 110a connected to the conductive layers 106b of the first group (such as the even-numbered conductive layers 106b) and the conductive pillars 110a connected to the conductive layers 106b of the second group (such as the odd-numbered conductive layers 106b) are arranged in a staggered manner, and the conductive pillars 110b connected to the bottom conductive layer 104 and the conductive pillars 110a connected to the adjacent lowest conductive layer 106b are arranged in a staggered manner, but the present invention is not limited to this.

[0068] In this embodiment, the capacitor structure 10 may have a similar main structure to the three-dimensional AND flash memory structure in the memory area of ​​the substrate 100, but the difference between the two is that in the capacitor structure 10, a portion of the conductive layer 106b in the stacked structure 106 is electrically connected to a common voltage source through the conductive pillar 110a connected thereto, and the remaining portion of the conductive layer 106b and the bottom conductive layer 104 in the stacked structure 106 are electrically connected to another common voltage source through the conductive pillars 110a and 110b connected thereto. One of the two common voltage sources is a high voltage source, and the other is a low voltage source.

[0069] In detail, in this embodiment, from bottom to top, the bottom conductive layer 104 is electrically connected to the common voltage source P1 through the conductive pillar 110b connected thereto, and the second conductive layer 106 and the fourth conductive layer 106b are electrically connected to the common voltage source P1 through the conductive pillar 110a connected thereto, and the first conductive layer 106b and the third conductive layer 106b are electrically connected to the common voltage source P2 through the conductive pillar 110a connected thereto, and the common voltage source P1 can be a low voltage source and the common voltage source P2 can be a high voltage source. In this way, the bottom conductive layer 104, the first conductive layer 106b and the dielectric layer 106a located therebetween can constitute a capacitor unit, the first conductive layer 106b, the second conductive layer 106b and the dielectric layer 106a located therebetween can constitute a capacitor unit, the second conductive layer 106b, the third conductive layer 106b and the dielectric layer 106a located therebetween can constitute a capacitor unit, and the third conductive layer 106b, the fourth conductive layer 106b and the dielectric layer 106a located therebetween can constitute a capacitor unit.

[0070] For a three-dimensional AND flash memory structure with a similar architecture, the conductive layers in the stacked structure are not connected to a common voltage source, so the conductive layers do not serve as electrodes of a capacitor, and no capacitance is generated between adjacent conductive layers. In other words, although the three-dimensional AND flash memory structure has a similar main architecture to the capacitor structure 10, the two are completely different in function.

[0071] In addition, a plurality of columnar structures 112 are arranged in an array in the capacitor array region 100a and penetrate the stacked structure 106 and the bottom conductive layer 104. In the present embodiment, the columnar structure 112 includes an insulating column 112a and an insulating column 112b located in the insulating column 112a, but the present invention is not limited thereto. In other embodiments, the columnar structure 112 may be composed only of the insulating column 112a. The material of the insulating column 112a is different from the material of the insulating column 112b. In one embodiment, the material of the insulating column 112a may be silicon oxide, and the material of the insulating column 112b may be silicon nitride, but the present invention is not limited thereto. In the present embodiment, the columnar structure 112 is used to support and stabilize the stacked structure 106, and does not have a conductive function.

[0072] In addition, in the present embodiment, a plurality of insulating support columns 113 are disposed in the capacitor step region 100b and penetrate the dielectric layer 108, the stacked structure 106 and the bottom conductive layer 104. The support column 113 may have a structure that is the same as or similar to the columnar structure 112. The width of the support column 113 may be less than the width of the columnar structure 112. These support columns 113 may have the same height. In the present embodiment, two support columns 113 constitute a support column group and are located next to a corresponding conductive column 110a or conductive column 110b. From a top view, since the conductive columns 110a connected to the conductive layer 106b of the first group and the conductive columns 110a connected to the conductive layer 106b of the second group are staggered, and the conductive columns 110b connected to the bottom conductive layer 104 and the conductive columns 110a connected to the lowest conductive layer 106b are staggered, these support column groups are also staggered in the capacitor step region 100b.

[0073] In this embodiment, if Figure 1BAs shown, the bottom conductive layer 104 and the stacked structure 106 have an annular trench TR. The annular trench TR penetrates the bottom conductive layer 104 and the stacked structure 106 and surrounds the stacked structure 106 in the capacitor array area 100a and the capacitor step area 100b, so that the bottom conductive layer 104 in the capacitor structure 10 is separated and electrically separated from the bottom conductive layer 104 outside the annular trench TR (for example, the bottom conductive layer 104 in the memory area). In this way, it can be ensured that the capacitor structure 10 is not affected by the electrical properties of the outside world and can have a stable capacitance. For example, parasitic capacitance can be avoided.

[0074] In addition, in this embodiment, Figure 1B As shown, the bottom conductive layer 104 and the stacked structure 106 have a plurality of transverse trenches SLT. Each transverse trench SLT extends along the column direction (X direction) of the capacitor array region 100a and is located between two adjacent columns of insulating pillars 112 in the row direction (Y direction). In this way, the stacked structure 106 can be divided into a plurality of blocks, and each block can be regarded as an independent sub-capacitor structure in the capacitor structure 10. For example, Figure 6 As shown, the capacitor structure 10 may have four lateral trenches SLT, so the stacked structure 106 may be divided into five sections, that is, the capacitor structure 10 includes five sub-capacitor structures 10a. Figure 6 In order to make the drawings clear and facilitate description, only the bottom conductive layer 104 and the dielectric layer 106a and the conductive layer 106b in the stacked structure 106 are shown for description.

[0075] In addition, in order to further improve the capacitance value of the capacitor structure 10, in one embodiment, the array circuit structure 102 may have a plurality of metal oxide semiconductor capacitors 20. Figure 2 As shown, in the metal oxide semiconductor capacitor 20, the gate dielectric layer 20a and the gate 20b are sequentially disposed on the substrate 100, the contact window 22 is connected to the gate 20b, and the contact window 24 is connected to the substrate 100. The substrate 100 may include a doped region. Each gate 20b is electrically connected to a common voltage source through the contact window 22, and the substrate 100 is electrically connected to another voltage source through the contact window 24. In this way, in each metal oxide semiconductor capacitor 20, the gate 20b, the substrate 100 and the gate dielectric layer 20a located therebetween can constitute a capacitor unit.

[0076] In the capacitor structure 10 of the present embodiment, in addition to the metal oxide semiconductor capacitor 20, a plurality of dielectric layers 106a and a plurality of conductive layers 106b alternately stacked on the bottom conductive layer 104 can constitute a plurality of capacitor units. Therefore, compared with a three-dimensional AND flash memory structure having a similar architecture, the capacitor structure 10 of the present embodiment can have a larger capacitance. In addition, in the present embodiment, the number of capacitor units can be increased by increasing the number of stacked dielectric layers 106a and conductive layers 106b, so that the capacitor structure of the present embodiment can have a higher capacitance per unit area. In other words, without increasing the layout area, a capacitor structure with a higher capacitance can be obtained.

[0077] In addition, for the capacitor structure 10, the electrical connection relationship between the conductive layer 106b and the bottom conductive layer 104 and the common voltage source P1 and the common voltage source P2 can be adjusted according to actual needs to obtain a desired capacitance value. This is described in detail below.

[0078] 7A to 7E The invention describes adjusting the electrical connection relationship between the conductive layer in the stacked structure and the bottom conductive layer and the common voltage source to obtain the required capacitance value. 7A to 7E In order to make the diagram clear and convenient for explanation, only the dielectric layer 106a, the conductive layer 106b, the bottom conductive layer 104 and the common voltage sources P1 and P2 in the stacked structure are shown. 7A to 7E In the present invention, the same components as those in the first embodiment are denoted by the same reference symbols and will not be described further herein.

[0079] Reference Fig. 7A , the stacked structure 106 includes 32 conductive layers 106b. Figure 1A The even-numbered conductive layer 106b and the bottom conductive layer 104 are electrically connected to the common voltage source P1, and the odd-numbered conductive layer 106b is electrically connected to the common voltage source P2. Thus, the capacitor structure 10 has 32 sets of capacitance couplings, and the total capacitance value C is .

[0080] Reference Figure 7B , the conductive layer 106b of the 32nd layer of the stack is adjusted to be connected to the common voltage source P2, and the conductive layer 106b of the 31st layer is adjusted to be connected to the common voltage source P1, so that the conductive layer 106b of the 31st layer and the conductive layer 106b of the 30th layer cannot form a capacitor unit. In this way, the capacitor structure 10 has 31 sets of capacitor couplings, and the total capacitance value is about 96.9% of C.

[0081] Reference Figure 7C, the first conductive layer 106b of the stack is adjusted to be connected to the common voltage source P1, so that the first conductive layer 106b and the second conductive layer 106b cannot form a capacitor unit, and the first conductive layer 106b and the bottom conductive layer 104 cannot form a capacitor unit. In this way, the capacitor structure 10 has 30 sets of capacitive couplings, and the total capacitance value is about 93.8% of C.

[0082] Reference Fig.7D , the conductive layer 106b of the first layer of the stack is adjusted to be connected to the common voltage source P1, the conductive layer 106b of the 32nd layer of the stack is adjusted to be connected to the common voltage source P2, and the conductive layer 106b of the 31st layer is adjusted to be connected to the common voltage source P1, so that no capacitor unit can be formed between the conductive layer 106b of the first layer and the conductive layer 106b of the second layer, between the conductive layer 106b of the first layer and the bottom conductive layer 104, and between the conductive layer 106b of the 31st layer and the conductive layer 106b of the 30th layer. In this way, the capacitor structure 10 has 29 groups of capacitor couplings, and the total capacitance value is about 90.6% of C.

[0083] Reference Fig. 7E , the stacked first and third conductive layers 106b are adjusted to be connected to the common voltage source P1, so that no capacitor unit can be formed between the first conductive layer 106b and the second conductive layer 106b, between the first conductive layer 106b and the bottom conductive layer 104, between the second conductive layer 106b and the third conductive layer 106b, and between the third conductive layer 106b and the fourth conductive layer 106b. In this way, the capacitor structure 10 has 28 groups of capacitive couplings, and the total capacitance value is about 87.5% of C.

[0084] As can be seen from the above, the desired capacitance value can be easily obtained by simply adjusting the electrical connection relationship between the conductive layers in the stacked structure and the bottom conductive layer and the common voltage source.

[0085] Figure 3 FIG. 2 is a cross-sectional schematic diagram of a capacitor structure according to a second embodiment of the present invention. Figure 3 In the present invention, the same components as those in the first embodiment are denoted by the same reference symbols and will not be described further herein.

[0086] Reference Figure 3, the difference between the capacitor structure 30 of the present embodiment and the capacitor structure 10 is that: in the capacitor structure 30, the columnar structure 112 is replaced by a columnar structure 300. In detail, in addition to the insulating column 112a and the insulating column 112b, each columnar structure 300 also includes a semiconductor layer 300a and an insulating layer 300b. The semiconductor layer 300a may include doped polysilicon. The semiconductor layer 300a is disposed between the insulating column 112a and the stacked structure 106 and between the insulating column 112a and the bottom conductive layer 104. The insulating layer 300b is disposed between the semiconductor layer 300a and the stacked structure 106 and between the semiconductor layer 300a and the bottom conductive layer 104. That is, the columnar structure 300 has a similar architecture to the vertical channel column structure in the memory area, wherein the semiconductor layer 300a corresponds to the channel layer of the vertical channel column structure. However, unlike the vertical channel column structure, the columnar structure 300 of the present embodiment is electrically floating (floating), and it is not electrically connected to other components through the conductive column.

[0087] In this embodiment, the bottom conductive layer 104 and the stacked structure 106 have an annular channel penetrating the bottom conductive layer 104 (such as the annular channel of the first embodiment). Figure 1B The annular trench TR in the capacitor structure 30 enables the bottom conductive layer 104 in the capacitor structure 30 to be separated and electrically isolated from the bottom conductive layer 104 in other areas outside the annular trench.

[0088] In the first and second embodiments described above, since the columnar structures 112 and the columnar structures 300 in the capacitor array region 100a do not need to be electrically connected to an external voltage source, that is, no additional circuit layer electrically connected to the columnar structures 112 and the columnar structures 300 need to be disposed above the columnar structures 112 and the columnar structures 300 to connect to the external voltage source. In this way, the circuits in the peripheral areas (such as the memory area) outside the capacitor array region 100a and the capacitor step region 100b can extend through the capacitor array region 100a (the space above the columnar structures 112 and the columnar structures 300), so that the circuit layout design can have greater flexibility.

[0089] Figure 4 FIG. 4 is a cross-sectional schematic diagram of a capacitor structure according to a third embodiment of the present invention. Figure 4 In the present invention, the same components as those in the second embodiment are represented by the same reference symbols and will not be described further herein.

[0090] Reference Figure 4, the difference between the capacitor structure 40 of the present embodiment and the capacitor structure 30 is that: in the capacitor structure 40, the columnar structure 300 is replaced by a columnar structure 400. In detail, in addition to the insulating column 112a, the insulating column 112b, the semiconductor layer 300a and the insulating layer 300b, each columnar structure 400 also includes two conductive plugs 400a. The conductive plugs 400a are arranged in the insulating column 112a and are separated from each other by the insulating column 112b. In addition, the conductive plugs 400a are connected to the semiconductor layer 300a, so that the semiconductor layer 300a can be electrically connected to an external element through the conductive plugs 400a. In other words, the columnar structure 400 has a similar architecture to the vertical channel column structure in the memory area, wherein the semiconductor layer 300a corresponds to the channel layer of the vertical channel column structure, and the conductive plugs 400a correspond to the source / drain column of the vertical channel column structure. However, unlike the vertical channel pillar structure, each semiconductor layer 300 a in this embodiment is electrically connected to the common voltage source P3 through two conductive plugs 400 a connected thereto.

[0091] Thus, in the capacitor structure 40, two adjacent conductive layers 106b and the dielectric layer 106a located therebetween can constitute a capacitor unit; the lowest conductive layer 106b, the bottom conductive layer 104 and the dielectric layer 106a located therebetween can constitute a capacitor unit; the conductive layer 106b, the semiconductor layer 300a and the insulating layer 300b located therebetween can also constitute a capacitor unit.

[0092] In this embodiment, the bottom conductive layer 104 and the stacked structure 106 have an annular channel penetrating the bottom conductive layer 104 (such as the annular channel of the first embodiment). Figure 1B The annular trench TR in the capacitor structure 40 enables the bottom conductive layer 104 in the capacitor structure 40 to be separated and electrically isolated from the bottom conductive layer 104 in other areas outside the annular trench.

[0093] In addition, in order to further accurately control the capacitance of the capacitor structure, the bottom conductive layer 104 and the stacked structure 106 located in the annular trench TR can be divided into a plurality of independent conductive blocks to further avoid the generation of parasitic capacitance. The following is an example of the architecture of the first embodiment (with a columnar structure 112), but the present invention is not limited thereto. In other embodiments, the architecture of other embodiments can be adopted.

[0094] Figure 5A FIG. 4 is a schematic top view of a capacitor structure according to a fourth embodiment of the present invention. Figure 5B For along Figure 5A Schematic diagram of the cross section of the AA section line in. Figure 5A and Figure 5B In the embodiment, the same components as those in the first embodiment are denoted by the same reference symbols and will not be described further herein. Figure 5A In order to make the drawings clear and facilitate description, the dielectric layer 106a in the stacked structure 106 is omitted.

[0095] Also refer to Figure 5A and Figure 5B , a plurality of annular trenches TR1 are provided in the bottom conductive layer 104 and the stacked structure 106. Each annular trench TR1 penetrates the bottom conductive layer 104 and the stacked structure 106 to divide the bottom conductive layer 104 and the stacked structure 106 into a plurality of independent conductive blocks 500. In the present embodiment, each annular trench TR1 extends along the column direction of the capacitor array region 100a and surrounds at least one column of columnar structures 112 and the stacked structure 106 in the capacitor step region 100b. In addition, in the present embodiment, in order to avoid interference (e.g., parasitic capacitance) between adjacent conductive blocks 500, adjacent conductive blocks 500 are separated by spaces including at least two columns of columnar structures 112, but the present invention is not limited thereto.

[0096] In addition, in this embodiment, each conductive block 500 surrounds one column of column structures 112, but the present invention is not limited thereto. In other embodiments, each conductive block 500 may surround 2, 4, 8 or more columns of column structures 112 depending on actual needs.

[0097] In addition, in the present embodiment, in the region between two adjacent conductive blocks 500, in the stacked structure 106, in the stacking direction, the dielectric layer 502 is disposed between adjacent dielectric layers 106a at positions corresponding to the conductive layer 106b. In addition, the dielectric layer 502 is located between the conductive layers 106b in two adjacent columns. The material of the dielectric layer 502 is different from that of the dielectric layer 106a. In one embodiment, the dielectric layer 502 may be a silicon nitride layer, and the dielectric layer 106a may be a silicon oxide layer, but the present invention is not limited thereto.

[0098] In detail, the conductive layer 106b in the stacked structure 106 is formed by replacing the dielectric layer 502 in the alternately stacked multiple dielectric layers 106a and the multiple dielectric layers 502 with a conductive material. The above-mentioned replacement method, for example, first uses hot phosphoric acid to remove the dielectric layer 502 through the annular trench TR1, and then fills the conductive material. In the present embodiment, the portion of the dielectric layer 502 adjacent to the annular trench TR1 is removed, while the other portion is retained. In this way, in addition to being independently set via the annular trench TR1, the conductive block 500 can also be isolated from another adjacent conductive block 500 via the dielectric layer 502. In this way, there is an insulating structure composed of the dielectric layer 106a and the dielectric layer 502 between the two adjacent conductive blocks 500, so that the capacitance of the capacitor structure in the two adjacent conductive blocks 500 can be more stable without being interfered with by each other.

[0099] Although the present invention has been disclosed as above by embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the attached claims.

Claims

1. A capacitor structure, characterized in that: include: A substrate having a capacitor array region and a capacitor step region; The circuit structure below the array is arranged on the substrate; A bottom conductive layer, disposed on the circuit structure below the array; A stacked structure, disposed on the bottom conductive layer, and comprising a plurality of first dielectric layers and a plurality of conductive layers alternately stacked, wherein the plurality of conductive layers in the capacitor step region are arranged in a step form; as well as A plurality of columnar structures are arranged in the capacitor array region in an array manner and penetrate the stacked structure and the bottom conductive layer. A portion of the conductive layers among the plurality of conductive layers are electrically connected to a first common voltage source, and a portion of the conductive layers among the plurality of conductive layers and the bottom conductive layer are electrically connected to a second common voltage source. 2 . The capacitor structure according to claim 1 , wherein the conductive layers of the portion include odd-numbered conductive layers among the plurality of conductive layers, and the conductive layers of the remaining portion include even-numbered conductive layers among the plurality of conductive layers. 3 . The capacitor structure according to claim 1 , wherein at least one pair of adjacent conductive layers among the plurality of conductive layers is electrically connected to the first common voltage source or the second common voltage source. 4 . The capacitor structure according to claim 1 , wherein the bottom conductive layer and a bottommost conductive layer among the plurality of conductive layers are electrically connected to the first common voltage source or the second common voltage source. 5 . The capacitor structure according to claim 1 , wherein a conductive layer connected to the first common voltage source, an adjacent conductive layer connected to the second common voltage source, and the first dielectric layer therebetween constitute a capacitor unit.

6. The capacitor structure according to claim 1 further includes a plurality of conductive pillars located in the capacitor step region and arranged on the plurality of conductive layers and the bottom conductive layer, so that the plurality of conductive layers and the bottom conductive layer are electrically connected to the corresponding common voltage source through the plurality of conductive pillars. 7 . The capacitor structure according to claim 1 , wherein each of the plurality of columnar structures comprises a first insulating column. 8 . The capacitor structure according to claim 7 , wherein each of the plurality of columnar structures further comprises a second insulating column disposed in the first insulating column.

9. The capacitor structure according to claim 7, wherein each of the plurality of columnar structures further comprises: A semiconductor layer, disposed between the first insulating column and the stacked structure and between the first insulating column and the bottom conductive layer; as well as The insulating layer is disposed between the semiconductor layer and the stacked structure and between the semiconductor layer and the bottom conductive layer. 10 . The capacitor structure according to claim 9 , wherein each of the semiconductor layers is electrically connected to a third common voltage source through a conductive plug.

11. The capacitor structure according to claim 10, wherein a conductive layer connected to the first common voltage source, a semiconductor layer, and the insulating layer therebetween constitute a capacitor unit.

12. The capacitor structure according to claim 10, wherein a conductive layer connected to the second common voltage source, a semiconductor layer, and the insulating layer therebetween constitute a capacitor unit.

13. The capacitor structure according to claim 1, wherein the array bottom circuit structure further comprises a metal oxide semiconductor capacitor.

14. The capacitor structure according to claim 1, wherein the bottom conductive layer and the stacked structure have an annular channel, the annular channel penetrates the bottom conductive layer and the stacked structure, and the stacked structure in the capacitor array area and the capacitor step area is surrounded by the annular channel.

15. The capacitor structure according to claim 1, wherein the bottom conductive layer and the stacked structure have a plurality of annular channels, each of the plurality of annular channels penetrates the bottom conductive layer and the stacked structure, and each of the annular channels extends along the column direction of the capacitor array region and surrounds at least one column of the columnar structure and the stacked structure in the capacitor step region to form an independent conductive block. 16 . The capacitor structure according to claim 15 , further comprising a second dielectric layer disposed between adjacent conductive blocks and located between the plurality of first dielectric layers in a stacking direction of the stacking structure at a position corresponding to the conductive layer. 17 . The capacitor structure according to claim 16 , wherein the second dielectric layer is located between the conductive layers of adjacent conductive blocks. 18 . The capacitor structure according to claim 16 , wherein a material of the second dielectric layer is different from a material of the first dielectric layer.

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