Homogeneous pn junction terminal gallium oxide Schottky barrier diode and preparation method thereof

Abstract

The invention discloses a homogeneous pn junction terminal gallium oxide Schottky barrier diode and a preparation method thereof. The problems that gallium oxide p-type doping is difficult, and heterojunction electric leakage is high and voltage resistance is low are solved. The semiconductor device comprises a cathode, an n-Ga2O3 substrate and an n-Ga2O3 epitaxial layer from bottom to top, ion implantation regions are arranged at the left end and the right end of the upper surface of the n-Ga2O3 epitaxial layer, and the upper surface of the n-Ga2O3 epitaxial layer is covered with an anode; the ion implantation region is subjected to annealing treatment to form a p-type Ga2O3 region, and the p-type Ga2O3 region and the n-Ga2O3 epitaxial layer form a homogeneous pn junction terminal, so that the gallium oxide Schottky barrier diode with high voltage resistance and low electric leakage is realized. The preparation method comprises the steps of cleaning an epitaxial wafer, photoetching to form a region to be implanted with ions, carrying out ion implantation, cleaning, carrying out rapid thermal annealing to form p-Ga2O3, and preparing a cathode and an anode. According to the invention, N / P ions are injected, annealing treatment is carried out, a gallium-oxygen-nitrogen-phosphorus compound with a p-type characteristic is generated in the n-Ga2O3 epitaxial layer, and the homogeneous pn junction terminal gallium oxide Schottky barrier diode is realized. The method can be used in high-voltage and high-power fields such as power grids and high-speed rails

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and mainly relates to a gallium oxide-based device, specifically a homogeneous pn junction terminal gallium oxide Schottky barrier diode and a preparation method thereof, which are used to prepare a high-voltage gallium oxide Schottky barrier diode, and can be used in high-power and high-voltage power electronics fields such as smart grids and data centers. Background Art

[0002] β-Ga2O3 has an extremely large bandgap (4.4-4.9eV), which makes its ionization rate lower and the breakdown field strength higher, about 8MV / cm, which is more than 20 times that of Si and more than twice that of SiC and GaN. In addition, the Baliga quality factor of β-Ga2O3 is more than 8 times that of 4H-SiC and more than 4 times that of GaN; the high-frequency Baliga figure of merit is about 150 times that of Si, about 3 times that of 4H-SiC, and 1.5 times that of GaN. Gallium oxide materials have great application prospects in smart grids, new energy electric vehicles, high-speed railways, data centers and other fields. Therefore, gallium oxide semiconductors have become the hottest new field of semiconductor research in recent years. Due to the lack of direct and effective p-type doping in β-Ga2O3, its device performance and application prospects are greatly limited. At present, p-NiO is widely used internationally. x Or other p-type semiconductors to replace p-Ga2O3 to prepare gallium oxide Schottky barrier diodes. Schottky barrier diode type devices have advantages such as high breakdown voltage and low turn-on voltage. x Like other p-type semiconductors, they have poor thermal stability. In applications, it is found that after the device has worked for a long time, the leakage current increases and the withstand voltage decreases, which seriously affects the reliability and stability of the device.

[0003] The structure of the heterogeneous pn junction terminal gallium oxide Schottky barrier diode prepared at present includes cathode electrode, n-Ga2O3 substrate, n-Ga2O3 epitaxial layer from bottom to top, and p-NiO x , p-NiO x , not p-NiO x An anode electrode is provided on the covering n-Ga2O3 epitaxial layer, such as Figure 1 As shown. Usually, the cathode uses metal Ti / Au; the substrate layer uses n-type heavily doped Ga2O3; the n-Ga2O3 layer is a drift layer doped with Si or Sn, and by doping Si and Sn, the carriers of the n-type gallium oxide crystal can be regulated in a larger range; the p-NiO x It is used to solve the problem of lack of effective p-type doping in gallium oxide; the gate electrode uses metal Ni / Au. In this structure of gallium oxide Schottky barrier diode, p-NiO is introduced xThe heterojunction terminal is formed with the n-Ga2O3 epitaxial layer. The modulation of the electric field distribution in the diode by the depletion region of the pn junction alleviates the electric field concentration effect and improves the reverse withstand voltage of the device. x The bandgap width of p-NiO is between 3.8eV and 4.0eV, which is smaller than the bandgap width of Ga2O3 (4.9eV). x The critical electric field strength of p-NiO is also lower than that of Ga2O3. x The thermal conductivity of p-NiO is poor, and long-term leakage conditions can easily cause x damage and deterioration; finally, due to the p-NiO x Different from the lattice constant of n-Ga2O3, a large number of dislocations and defects are easily generated when preparing heterogeneous pn junctions, which reduces the reliability and life of the device and limits its application scope.

[0004] Existing heterojunction pn-terminated gallium oxide Schottky barrier diode, p-NiO x The critical electric field strength is lower than that of Ga2O3, and the theoretical withstand voltage is lower than that of the homogeneous pn junction of gallium oxide; p-NiO x The thermal conductivity of p-NiO is poor, and long-term leakage conditions can easily cause x damage and deterioration; and a large number of dislocations and defects are easily generated when preparing heterogeneous pn junctions, which ultimately reduce the reliability and stability of the device and even cause the device to break down prematurely, limiting its scope of application. Summary of the invention

[0005] The purpose of the present invention is to address the above-mentioned problems existing in heterogeneous pn junction terminal gallium oxide Schottky barrier diodes, and to propose a homogeneous pn junction terminal gallium oxide Schottky barrier diode and a preparation method thereof, which realizes p-type Ga2O3 and forms a homogeneous pn junction terminal, improves the device withstand voltage and reduces the device leakage current.

[0006] The invention discloses a homogeneous pn junction terminal gallium oxide Schottky barrier diode, which is provided with a cathode electrode, an n-Ga2O3 substrate, and an n-Ga2O3 epitaxial layer from bottom to top, ion implantation regions are provided at the left and right ends of the upper surface of the n-Ga2O3 epitaxial layer, and an anode electrode is provided on the upper surface of the n-Ga2O3 epitaxial layer. The invention is characterized in that after annealing treatment, ions implanted in the ion implantation region generate compounds with p-type characteristics, that is, the ion implantation region generates a p-type Ga2O3 region, and the p-type Ga2O3 region and the n-Ga2O3 epitaxial layer constitute a homogeneous pn junction terminal, thereby realizing a gallium oxide Schottky barrier diode with high withstand voltage and low leakage current as a whole.

[0007] The present invention is also a method for preparing a homogeneous pn junction terminal gallium oxide Schottky barrier diode, characterized in that it comprises the following steps:

[0008] 1) Pretreatment of epitaxial wafers: Gallium oxide epitaxial wafers refer to gallium oxide epitaxial wafers with n-Ga2O3 epitaxial layers epitaxially grown on n-type heavily doped gallium oxide substrates. The pretreatment is to put the gallium oxide epitaxial wafers into acetone solution and isopropanol solution for ultrasonic cleaning for 5 minutes to 10 minutes respectively, then rinse with a large amount of deionized water, and finally blow dry with nitrogen to obtain the cleaned epitaxial wafers;

[0009] 2) Photolithography to form the area to be implanted: first, a photoresist is coated on the n-Ga2O3 epitaxial layer to be implanted, and then the photolithography process of pre-baking, alignment and exposure, post-baking, development, hardening and pattern detection is performed to obtain the area to be implanted that is not protected by the photoresist;

[0010] 3) Ion implantation to form an ion implantation area: The ion implantation concentration of the area to be implanted on the upper surface of the epitaxial layer is 1e15cm -3 -5e19cm -3 N / P ions form ion implantation regions at both ends of the n-Ga2O3 epitaxial layer;

[0011] 4) Cleaning the epitaxial wafer after injection: Place the epitaxial wafer after ion injection in an NMP solution and heat it in a water bath for 30 minutes, then place it in an acetone solution and an isopropanol solution in turn and ultrasonically clean it for 5 minutes to 10 minutes each, then rinse it with a large amount of deionized water, and finally blow dry it with nitrogen to obtain a cleaned epitaxial wafer;

[0012] 5) Rapid thermal annealing to form p-Ga2O3: that is, in a N2 environment, the furnace annealing temperature is set to 800℃-1600℃, and the annealing time is set to 10s-10min, so that the ion implantation area becomes a p-type Ga2O3 area, and realizes a homogeneous pn junction termination with the n-Ga2O3 epitaxial layer;

[0013] 6) Preparation of cathode: Ti / Au with a thickness of 60nm / 200nm is deposited on the substrate by electron beam evaporation E-Beam system; then the epitaxial wafer is placed in an annealing furnace, and the annealing temperature in the furnace is set to 500°C in a N2 environment, and the annealing time is 1min to form a cathode with good ohmic contact;

[0014] 7) Preparation of anode: First, the anode area to be prepared is formed on the epitaxial layer by photolithography, and then Ni / Au with a thickness of 60nm / 120nm is deposited in the anode area by electron beam evaporation E-Beam system. The epitaxial wafer after metal deposition is placed in a stripping solution, and the anode is formed by stripping to complete the device manufacturing.

[0015] The present invention solves the problem in the prior art that p-NiO x / The complex manufacturing process of n-Ga2O3 leads to high production cost, difficulty in controlling doping concentration and low device reliability. At the same time, the designed and prepared homogeneous pn junction terminal gallium oxide Schottky barrier diode realizes p-type doping of gallium oxide, which greatly reduces interface defects and dislocation density, further reduces the leakage current of the device, improves the thermal stability and voltage resistance of the device, and improves the reliability of the device.

[0016] Compared with the prior art, the present invention has the following advantages:

[0017] Realizing gallium oxide homogeneous pn junction with simple process: The present invention performs N / P or Mg ion implantation and annealing treatment on the surface of the n-Ga2O3 epitaxial layer. Under N2 atmosphere and high temperature conditions, Ga atoms in Ga2O3 are precipitated and react with the implanted N / P or Mg ions to form gallium oxygen nitrogen (phosphorus, magnesium) compounds with p-type characteristics, forming p-Ga2O3 in the ion implantation area. A gallium oxide homogeneous pn junction is obtained with a relatively simple process, which greatly reduces interface traps at the pn junction interface.

[0018] Improve the breakdown voltage of the device and reduce the turn-on voltage of the device: The present invention introduces a homogeneous pn junction at the edge of the anode, which alleviates the electric field concentration effect at the edge of the anode and increases the breakdown voltage of the device; at the same time, the center of the device is a Schottky contact of Ni and Ga2O3, so that the device has a turn-on voltage lower than the pn junction.

[0019] Reduce the leakage current of the device and improve the reliability and life of the device: the homogeneous pn junction terminal designed by the present invention can significantly reduce the leakage current of the device and reduce the static loss of the device; the present invention only needs to perform ion implantation to form the homogeneous pn junction terminal, thus avoiding a large number of dislocations and defects that are easily generated when preparing heterogeneous pn junctions and p-NiO x It reduces the problem of easy damage and deterioration, thus improving the reliability and life of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the structure of an existing heterogeneous pn junction terminal gallium oxide Schottky barrier diode;

[0021] Figure 2 It is a schematic structural diagram of a homogeneous pn junction terminal gallium oxide Schottky barrier diode of the present invention;

[0022] Figure 3 It is a flowchart of the method for preparing a homogeneous pn junction terminal gallium oxide Schottky barrier diode of the present invention;

[0023] Figure 4 The present invention is a schematic diagram of the process of preparing a homogeneous pn junction terminal gallium oxide Schottky barrier diode. DETAILED DESCRIPTION

[0024] The structure and preparation process of the homogeneous pn junction terminal gallium oxide Schottky barrier diode of the present invention are described in detail below with reference to the accompanying drawings.

[0025] Embodiment 1:

[0026] In situations where high voltage and high current need to be controlled and converted, diodes with high withstand voltage and low on-resistance are required as core components to meet the requirements of the above scenarios. However, due to the low critical breakdown electric field of the p-type material and the high concentration of defects and traps at the pn junction interface, the heterogeneous pn junction terminal gallium oxide Schottky barrier diodes manufactured by the existing technology have low withstand voltage, large leakage current and low reliability. Figure 1 The existing heterogeneous pn junction terminal gallium oxide Schottky barrier diode includes a cathode electrode, an n-Ga2O3 substrate, an n-Ga2O3 epitaxial layer, and p-NiO on both ends of the n-Ga2O3 epitaxial layer. x 、p-NiO x and not p-NiO x The anode electrode is placed on the n-Ga2O3 epitaxial layer. x Low critical breakdown electric field, p-NiO x / n-Ga2O3 junction interface has high defects and trap concentration, which leads to poor withstand voltage characteristics and large leakage current of the device, and p-NiO x The material is easily damaged and deteriorated, which is not conducive to improving the reliability of the device.

[0027] In view of the above problems, the present invention proposes a homogeneous pn junction terminal gallium oxide Schottky barrier diode, which comprises, from bottom to top, a cathode electrode 1, an n-Ga2O3 substrate 2, an n-Ga2O3 epitaxial layer 3, ion implantation regions 4 are provided at the left and right ends of the upper surface of the n-Ga2O3 epitaxial layer, and an anode electrode 5 is provided above the n-Ga2O3 epitaxial layer, see Figure 2 , Figure 2 This is a schematic diagram of the structure of the homogeneous pn junction terminal gallium oxide Schottky barrier diode of the present invention: the ion implantation area 4 generates a p-type Ga2O3 region after annealing, and the p-type Ga2O3 region and the n-Ga2O3 epitaxial layer 3 constitute a homogeneous pn junction terminal, thereby realizing a gallium oxide Schottky barrier diode with high withstand voltage and low leakage current as a whole.

[0028] p-NiO for heterojunction terminated gallium oxide Schottky barrier diodes x The critical breakdown electric field of the material is low, the defects and trap concentration at the pn junction interface are high, and the p-NiO xIn order to solve the problem of easy damage and deterioration, the present invention firstly proposes to use Ga2O3 material with higher critical breakdown electric field to form a homogeneous pn junction, while also avoiding the problems of interface defects and high trap concentration of heterogeneous pn junction; then, due to the higher withstand voltage and smaller leakage brought by the homogeneous pn junction terminal, the risk of device damage is reduced, thereby improving the reliability and life of the device.

[0029] The present invention is an overall technical solution. The innovation lies in that p-Ga2O3 is formed by performing N / P or Mg ion implantation and annealing treatment on the surface of an n-Ga2O3 epitaxial layer, and a gallium oxide homogeneous pn junction is obtained by a relatively simple process, which greatly reduces the interface traps at the pn junction interface; at the same time, the homogeneous pn junction terminal alleviates the electric field concentration effect at the edge of the anode, improves the voltage resistance of the device, and can also significantly reduce the reverse leakage current of the device, reducing the static loss of the device; it also avoids a large number of dislocations and defects that are easily generated when preparing heterogeneous pn junction terminals in the prior art, thereby improving the reliability of the device.

[0030] Embodiment 2:

[0031] The structure of the homogeneous pn junction terminal gallium oxide Schottky barrier diode is the same as that of Example 1. The present invention not only proposes a structure of forming a homogeneous pn junction by forming p-Ga2O3 through ion implantation and annealing, but also studies and discusses the thickness of the p-Ga2O3 region formed by annealing the ion implantation region 4. The thickness of the p-type Ga2O3 region formed by the ion implantation region after annealing in the present invention is controlled by the thickness of the ion implantation region 4 and the annealing conditions, and the thickness ranges from 200nm to 1μm. Under the conditions of rapid thermal annealing, the annealing temperature ranges from 800℃ to 1600℃, and the higher the annealing temperature, the more gallium oxygen nitrogen (phosphorus, magnesium) compounds with p-type characteristics are formed by the precipitated Ga atoms, and the higher the p-type doping concentration; the annealing time ranges from 10s to 10min, and the longer the annealing time, the greater the diffusion distance of the implanted ions, and the greater the thickness of the p-type Ga2O3 region formed. In this example, the thickness of the ion implantation region 4 is 200nm, the annealing conditions are N2800℃, 10s, and the thickness of the formed p-type Ga2O3 region is 200nm. Since long-term annealing treatment under high temperature conditions may cause phase change and damage of the material, the lowest annealing temperature and the minimum annealing time for forming p-Ga2O3 are used to reduce the possibility of phase change and damage to the epitaxial wafer and improve the reliability of device preparation.

[0032] Embodiment 3:

[0033] The structure of the homogeneous pn junction terminal gallium oxide Schottky barrier diode is the same as that of Example 1-2. The thickness of the p-type Ga2O3 region formed by the ion implantation region 4 after annealing in the present invention is 200nm-1μm. In this example, the thickness of the ion implantation region 4 is 700nm, and the annealing conditions are N21600℃, 10min, and the thickness of the p-type Ga2O3 region formed is 1μm. Because the higher the p-type doping concentration, the wider the depletion region width of the pn junction, and the higher the device withstand voltage; and the deeper the p-type region, the larger the spatial range of the electric field that can be modulated, and the more significant the alleviation of the electric field concentration effect, so in this example, the highest annealing temperature and the longest annealing time are used to achieve the highest p-type doping concentration and the largest ion diffusion distance to achieve the thickest p-type Ga2O3 region thickness, providing guidance for subsequent design.

[0034] Embodiment 4:

[0035] The structure of the homogeneous pn junction terminal gallium oxide Schottky barrier diode is the same as that of Examples 1-3. The thickness of the p-type Ga2O3 region formed by the ion implantation region 4 after annealing in the present invention is 200nm-1μm. In this example, the thickness of the ion implantation region 4 is 500nm, and the annealing conditions are N21000℃, 1min, and the thickness of the p-type Ga2O3 region formed is 600nm. The homogeneous pn junction terminal formed by the p-type Ga2O3 region with a thickness of 600nm can comprehensively obtain high withstand voltage characteristics, low leakage and high device reliability, which can better meet the requirements of high voltage and high current application scenarios. In practical applications, the appropriate ion implantation region thickness and annealing conditions can also be selected according to needs to achieve the target p-type Ga2O3 region thickness.

[0036] Embodiment 5:

[0037] The structure of the homogeneous pn junction terminal gallium oxide Schottky barrier diode is the same as that of Examples 1-4. The anode electrode 5 in the present invention is a double-layer metal structure, wherein the lower layer is Ni with a thickness of 50nm-100nm and the upper layer is Au with a thickness of 100nm-200nm.

[0038] In high current and high power application scenarios, the anode metal 6 of the device can adopt a double-layer structure of 100nm Ni in the lower layer and 200nm Au in the upper layer. This design helps to achieve lower on-resistance and parasitic capacitance.

[0039] If it is necessary to enhance the conductivity and thermal management, the anode metal 6 may adopt a double-layer structure of a lower layer of 50 nm Ni and an upper layer of 100 nm Au.

[0040] In this example, a double-layer structure of 60nm Ni in the lower layer and 120nm Au in the upper layer is adopted. This is the preferred value obtained by comprehensively considering contact resistance, reverse leakage current and thermal management in the present invention. In actual application, the different thicknesses of the double-layer metal can be adjusted according to needs.

[0041] Embodiment 6:

[0042] The present invention also provides a method for preparing a homogeneous pn junction terminal gallium oxide Schottky barrier diode, which is prepared for the above-mentioned homogeneous pn junction terminal gallium oxide Schottky barrier diode. The structure of the homogeneous pn junction terminal gallium oxide Schottky barrier diode is the same as that of Embodiments 1-5, see Figure 3 The flowchart of the preparation method of the homogeneous pn junction terminal gallium oxide Schottky barrier diode shown includes the following steps:

[0043] 1) Pretreatment of epitaxial wafers: Gallium oxide epitaxial wafers refer to gallium oxide epitaxial wafers with n-Ga2O3 epitaxial layers epitaxially grown on n-type heavily doped gallium oxide substrates. The pretreatment is to put the gallium oxide epitaxial wafers into acetone solution and isopropanol solution for ultrasonic cleaning for 5 minutes to 10 minutes respectively, then rinse with a large amount of deionized water, and finally blow dry with nitrogen to obtain the cleaned epitaxial wafers;

[0044] 2) Photolithography to form the area to be implanted: first, a photoresist is coated on the n-Ga2O3 epitaxial layer to be implanted, and then the photolithography process of pre-baking, alignment and exposure, post-baking, development, hardening and pattern detection is performed to obtain the area to be implanted that is not protected by the photoresist;

[0045] 3) Ion implantation to form an ion implantation area: The ion implantation concentration of the area to be implanted on the upper surface of the epitaxial layer is 1e15cm -3 -5e19cm -3 N / P ions form ion implantation regions at both ends of the n-Ga2O3 epitaxial layer;

[0046] 4) Cleaning the epitaxial wafer after injection: Place the epitaxial wafer after ion injection in an NMP solution and heat it in a water bath for 30 minutes, then place it in an acetone solution and an isopropanol solution in turn and ultrasonically clean it for 5 minutes to 10 minutes each, then rinse it with a large amount of deionized water, and finally blow dry it with nitrogen to obtain a cleaned epitaxial wafer;

[0047] 5) Rapid thermal annealing to form p-Ga2O3: that is, in a N2 environment, the furnace annealing temperature is set to 800℃-1600℃, and the annealing time is set to 10s-10min, so that the ion implantation area becomes a p-type Ga2O3 area, and realizes a homogeneous pn junction termination with the n-Ga2O3 epitaxial layer;

[0048] 6) Preparation of cathode: Ti / Au with a thickness of 60nm / 200nm is deposited on the substrate by electron beam evaporation E-Beam system; then the epitaxial wafer is placed in an annealing furnace, and the annealing temperature in the furnace is set to 500°C in a N2 environment, and the annealing time is 1min to form a cathode with good ohmic contact;

[0049] 7) Preparation of anode: firstly, the anode region to be prepared is formed on the epitaxial layer by photolithography, and then Ni / Au with a thickness of 60nm / 120nm is deposited on the anode region by an electron beam evaporation E-Beam system, and the epitaxial wafer after metal deposition is placed in a stripping solution, and the anode is formed by stripping, thereby completing the preparation of the homogeneous pn junction terminal gallium oxide Schottky barrier diode device of the present invention.

[0050] The present invention is an overall technical solution. Through the process steps of pre-treating an epitaxial wafer, photolithography to form an ion area to be implanted, ion implantation, cleaning the epitaxial wafer after implantation, rapid thermal annealing to form p-Ga2O3, preparing a cathode, and preparing an anode, p-Ga2O3 is formed on the surface of an n-Ga2O3 epitaxial layer by implanting N / P or Mg ions and performing annealing treatment, a gallium oxide homogeneous pn junction is obtained by a relatively simple process, and the preparation of a homogeneous pn junction terminal gallium oxide Schottky barrier diode device is completed.

[0051] The present invention solves the problem in the prior art that p-NiO x / The complex manufacturing process of n-Ga2O3 leads to high production cost, difficulty in controlling doping concentration and low device reliability. At the same time, the designed and prepared homogeneous pn junction terminal gallium oxide Schottky barrier diode realizes p-type doping of gallium oxide, which greatly reduces interface defects and dislocation density, further reduces the leakage current of the device, improves the thermal stability and voltage resistance of the device, and improves the reliability of the device.

[0052] Embodiment 7:

[0053] Homogeneous pn junction terminal gallium oxide Schottky barrier diode and preparation method are the same as in Example 1-6, step 3) the ion implantation forms the ion implantation area, and the ion to be implanted in the ion implantation area is selected from at least one of N ions, P ions or Mg ions. In this example, N ions and P ions are co-doped, and the implantation concentrations are 1e18 cm -3 and 1e18cm -3 After annealing, a gallium oxygen nitrogen phosphorus compound with p-type characteristics is effectively formed, realizing a gallium oxide homogeneous pn junction termination.

[0054] The structure and preparation process of the homogeneous pn junction terminal gallium oxide Schottky barrier diode of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0055] Embodiment 8:

[0056] Homogeneous pn junction terminal gallium oxide Schottky barrier diode and preparation method are the same as in Example 1-7, refer to Figure 2 The homogeneous pn junction terminal gallium oxide Schottky barrier diode of the present invention comprises: a cathode electrode 1, an n-Ga2O3 substrate 2, an n-Ga2O3 epitaxial layer 3, ion implantation regions 4 are provided at both ends of the n-Ga2O3 epitaxial layer 3, and an anode electrode 5 is provided above the n-Ga2O3 epitaxial layer. During the preparation process, the cathode electrode 1 is located at the bottom of the device, and uses Ti / Au with a thickness of 60nm / 200nm; the n-Ga2O3 substrate 2 is located on the cathode 1, and uses an n-type heavily doped Ga2O3 substrate with a thickness of 100μm-1000μm; the n-Ga2O3 epitaxial layer 3 is located on the substrate 2, and the total thickness is 5μm-30μm; the ion implantation area 4 is located at both ends of the n-Ga2O3 epitaxial layer 3, and the depth is 200nm-700nm; the anode electrode 5 is located on the n-Ga2O3 epitaxial layer, and is a double-layer metal structure, the lower layer is Ni with a thickness of 50nm-100nm, and the upper layer is Au with a thickness of 100nm-200nm. The ion implantation area 4 is annealed to form a p-type Ga2O3 region, and the p-type Ga2O3 region and the n-Ga2O3 epitaxial layer form a homogeneous pn junction terminal, and the whole realizes a high-voltage, low-leakage current gallium oxide Schottky barrier diode.

[0057] Reference Figure 4 The preparation process shown in the figure, in this example, the following three more detailed implementation instructions for preparing homogeneous pn junction terminal gallium oxide Schottky barrier diodes under different substrate thickness, epitaxial layer thickness, ion implantation area depth, anode metal thickness, ion implantation concentration and annealing conditions are given:

[0058] 1. On a 500μm thick n-type heavily doped Ga2O3 substrate and a 10μm thick n-type gallium oxide homoepitaxial wafer, an ion implantation region with a depth of 300nm and anode metal of 60nm / 120nm Ni / Au was produced with an implantation concentration of 1e18cm -3 Mg ions, annealing conditions are N21000℃, 30s to form a homogeneous pn junction gallium oxide Schottky barrier diode with a p-type Ga2O3 region with a thickness of 400nm.

[0059] Step 1, pre-treating the epitaxial wafer, such as Figure 4 (a).

[0060] Homoepitaxial gallium oxide epitaxial wafers were selected and cleaned, that is, the gallium oxide epitaxial wafers were placed in acetone solution and isopropanol solution for ultrasonic cleaning for 5 minutes to 10 minutes respectively, then rinsed with a large amount of deionized water, and then soaked in piranha solution for half an hour to reduce surface states and dangling bonds, and finally dried with nitrogen.

[0061] Step 2, photolithography forms the area to be ion implanted, such as Figure 4 (b).

[0062] First, the photoresist is coated on the n-Ga2O3 epitaxial layer to be ion-implanted, and then the photolithography process of pre-baking, alignment and exposure, post-baking, development, hardening and pattern detection is carried out to obtain the area to be ion-implanted that is not protected by the photoresist.

[0063] Step 3, ion implantation to form an ion implantation region, such as Figure 4 (c).

[0064] The ion implantation concentration in the upper surface of the epitaxial layer is 1e18cm -3 Mg ions are injected into the n-Ga2O3 epitaxial layer to form ion implantation regions at both ends.

[0065] Step 4, cleaning the epitaxial wafer after ion implantation, such as Figure 4 (d).

[0066] The epitaxial wafer after ion implantation was placed in an NMP solution and heated in a water bath for 30 minutes, then placed in an acetone solution and an isopropanol solution for ultrasonic cleaning for 5 minutes to 10 minutes each, then rinsed with a large amount of deionized water, and finally dried with nitrogen to obtain a cleaned epitaxial wafer.

[0067] Step 5, rapid thermal annealing to form a p-type Ga2O3 region, such as Figure 4 (e).

[0068] The epitaxial wafer is placed in an annealing furnace, the furnace gas is set to N2, the annealing temperature is 1000°C, and the annealing time is 30s. The precipitated Ga atoms form gallium-oxygen-nitrogen-magnesium compounds with p-type characteristics, making the ion implantation area a p-type Ga2O3 area, realizing a homogeneous pn junction termination.

[0069] Step 6, make the cathode, such as Figure 4 (f).

[0070] After the ion implantation, cathode deposition was performed on the sample. Ti / Au with a thickness of 60nm / 200nm was deposited on the substrate by electron beam evaporation E-Beam system. Then the sample was placed in an annealing furnace. In a N2 environment, the annealing temperature in the furnace was set to 500℃ and the annealing time was 1min to form a cathode with good ohmic contact.

[0071] Step 7, photolithography is used to form the anode region to be fabricated, such as Figure 4 (g).

[0072] Photolithography is performed on the n-Ga2O3 epitaxial layer of the cathode sample, that is, the anode area to be manufactured is formed through a series of process flows including photoresist coating, pre-baking, alignment and exposure, post-baking, development, hardening and pattern detection.

[0073] Step 8, make the anode, such as Figure 4 (h).

[0074] Anode deposition is performed on the anode area to be fabricated formed after photolithography is completed. Ni / Au with a thickness of 60nm / 120nm is deposited on the substrate through an electron beam evaporation E-Beam system. The sample after metal deposition is placed in a stripping solution, and an anode is formed by stripping to complete device fabrication.

[0075] 2. On a 500μm thick n-type heavily doped Ga2O3 substrate and a 30μm thick n-type gallium oxide homoepitaxial wafer, an ion implantation region with a depth of 500nm and anode metal of 100nm / 200nm Ni / Au was produced with an implantation concentration of 5e18cm -3 N ions and 5e18cm -3 The P ions were annealed at N21200℃ for 5min to form a homogeneous pn junction gallium oxide Schottky barrier diode with a p-type Ga2O3 region with a thickness of 800nm.

[0076] Step 1: pre-treat the epitaxial wafer, such as Figure 4 (a).

[0077] Homoepitaxial gallium oxide epitaxial wafers were selected and cleaned, that is, the gallium oxide epitaxial wafers were placed in acetone solution and isopropanol solution for ultrasonic cleaning for 5 minutes to 10 minutes respectively, then rinsed with a large amount of deionized water, and then soaked in piranha solution for half an hour to reduce surface states and dangling bonds, and finally dried with nitrogen.

[0078] Step 2: Photolithography forms the area to be ion implanted, such as Figure 4 (b).

[0079] First, the photoresist is coated on the n-Ga2O3 epitaxial layer to be ion-implanted, and then the photolithography process of pre-baking, alignment and exposure, post-baking, development, hardening and pattern detection is carried out to obtain the area to be ion-implanted that is not protected by the photoresist.

[0080] Step 3: ion implantation to form an ion implantation area, such as Figure 4 (c).

[0081] Ion implantation is performed on the formed ion implantation area: the implantation concentration is 5e18cm -3 N ions and 5e18cm -3 P ions are injected into the n-Ga2O3 epitaxial layer to form ion implantation regions at both ends of the n-Ga2O3 epitaxial layer.

[0082] Step 4: cleaning the epitaxial wafer after ion implantation. Figure 4 (d).

[0083] The epitaxial wafer after ion implantation was placed in an NMP solution and heated in a water bath for 30 minutes, then placed in an acetone solution and an isopropanol solution for ultrasonic cleaning for 5 minutes to 10 minutes each, then rinsed with a large amount of deionized water, and finally dried with nitrogen to obtain a cleaned epitaxial wafer.

[0084] Step 5: Rapid thermal annealing to form a p-type Ga2O3 region, such as Figure 4 (e).

[0085] The epitaxial wafer is placed in an annealing furnace, the furnace gas is set to N2, the annealing temperature is 1200°C, and the annealing time is 5 minutes. The precipitated Ga atoms form gallium oxygen nitrogen phosphorus compounds with p-type characteristics, making the ion implantation area a p-type Ga2O3 area, realizing a homogeneous pn junction termination.

[0086] Step 6: Make the cathode, such as Figure 4 (f).

[0087] After the ion implantation, cathode deposition was performed on the sample. Ti / Au with a thickness of 60nm / 200nm was deposited on the substrate by electron beam evaporation E-Beam system. Then the sample was placed in an annealing furnace. In a N2 environment, the annealing temperature in the furnace was set to 500℃ and the annealing time was 1min to form a cathode with good ohmic contact.

[0088] Step 7: Photolithography to form the anode area to be fabricated, such as Figure 4 (g).

[0089] Photolithography is performed on the n-Ga2O3 epitaxial layer of the cathode sample, that is, the anode area to be manufactured is formed through a series of process flows including photoresist coating, pre-baking, alignment and exposure, post-baking, development, hardening and pattern detection.

[0090] Step 8: Make the anode, such as Figure 4 (h).

[0091] Anode deposition is performed on the anode area to be fabricated formed after photolithography is completed. Ni / Au with a thickness of 100nm / 200nm is deposited on the substrate through the electron beam evaporation E-Beam system. The sample after metal deposition is placed in the stripping solution, and the anode is formed by stripping to complete the device manufacturing.

[0092] 3. On a 200μm thick n-type heavily doped Ga2O3 substrate and a 10μm thick n-type gallium oxide homoepitaxial wafer, an ion implantation region with a depth of 400nm, anode metal of 50nm / 150nm Ni / Au, and an implantation concentration of 5e18cm -3 N ions and 5e18cm -3 The P ions were annealed at N21000℃ for 1min to form a homogeneous pn junction gallium oxide Schottky barrier diode with a p-type Ga2O3 region with a thickness of 500nm.

[0093] Step A, pre-treating the epitaxial wafer, such as Figure 4 (a).

[0094] Homoepitaxial gallium oxide epitaxial wafers were selected and cleaned, that is, the gallium oxide epitaxial wafers were placed in acetone solution and isopropanol solution for ultrasonic cleaning for 5 minutes to 10 minutes respectively, then rinsed with a large amount of deionized water, and then soaked in piranha solution for half an hour to reduce surface states and dangling bonds, and finally dried with nitrogen.

[0095] Step B, photolithography forms the area to be ion implanted, such as Figure 4 (b).

[0096] First, the photoresist is coated on the n-Ga2O3 epitaxial layer to be ion-implanted, and then the photolithography process of pre-baking, alignment and exposure, post-baking, development, hardening and pattern detection is carried out to obtain the area to be ion-implanted that is not protected by the photoresist.

[0097] Step C, ion implantation to form an ion implantation region, such as Figure 4 (c).

[0098] Ion implantation is performed on the formed ion implantation area: the implantation concentration is 5e18cm -3 N ions and 5e18cm -3 P ions are injected into the n-Ga2O3 epitaxial layer to form ion implantation regions at both ends of the n-Ga2O3 epitaxial layer.

[0099] Step D, cleaning the epitaxial wafer after ion implantation, such as Figure 4 (d).

[0100] The epitaxial wafer after ion implantation was placed in an NMP solution and heated in a water bath for 30 minutes, then placed in an acetone solution and an isopropanol solution for ultrasonic cleaning for 5 minutes to 10 minutes each, then rinsed with a large amount of deionized water, and finally dried with nitrogen to obtain a cleaned epitaxial wafer.

[0101] Step E, rapid thermal annealing to form a p-type Ga2O3 region, such as Figure 4 (e).

[0102] The epitaxial wafer is placed in an annealing furnace, the furnace gas is set to N2, the annealing temperature is 1000°C, and the annealing time is 1 minute. The precipitated Ga atoms form gallium oxygen nitrogen phosphorus compounds with p-type characteristics, making the ion implantation area a p-type Ga2O3 area, realizing a homogeneous pn junction termination.

[0103] Step F, making a cathode, such as Figure 4 (f).

[0104] After the ion implantation, cathode deposition was performed on the sample. Ti / Au with a thickness of 60nm / 200nm was deposited on the substrate by electron beam evaporation E-Beam system. Then the sample was placed in an annealing furnace. In a N2 environment, the annealing temperature in the furnace was set to 500℃ and the annealing time was 1min to form a cathode with good ohmic contact.

[0105] Step G, photolithography to form the anode area to be manufactured, such as Figure 4 (g).

[0106] Photolithography is performed on the n-Ga2O3 epitaxial layer of the cathode sample, that is, the anode area to be manufactured is formed through a series of process flows including photoresist coating, pre-baking, alignment and exposure, post-baking, development, hardening and pattern detection.

[0107] Step H, making an anode, such as Figure 4 (h).

[0108] Anode deposition is performed on the anode area to be fabricated formed after photolithography is completed. Ni / Au with a thickness of 50nm / 150nm is deposited on the substrate through an electron beam evaporation E-Beam system. The sample after metal deposition is placed in a stripping solution, and an anode is formed by stripping to complete the device manufacturing.

[0109] In summary, the present invention is a homogeneous pn junction terminal gallium oxide Schottky barrier diode and a preparation method thereof, which realizes p-type doping of gallium oxide, realizes p-type Ga2O3 through ion implantation and rapid thermal annealing, and solves the problem of difficulty in p-type doping of gallium oxide materials; at the same time, the designed and prepared homogeneous pn junction terminal gallium oxide Schottky barrier diode avoids the problem of p-NiO in the prior art. x / n-Ga2O3 heterojunction manufacturing process is complex, doping concentration is difficult to control, and there are interface defects and high trap concentration problems, which further reduces the leakage current of the device, improves the thermal stability and voltage resistance of the device, and improves the reliability of the device. The present invention includes from bottom to top: a cathode electrode, an n-Ga2O3 substrate, and an n-Ga2O3 epitaxial layer. An ion implantation area is provided at both ends of the n-Ga2O3 epitaxial layer, and an anode electrode is provided above the n-Ga2O3 epitaxial layer; the ion implantation area is annealed to form a p-type Ga2O3 area, and the p-type Ga2O3 area and the n-Ga2O3 epitaxial layer form a homogeneous pn junction terminal, and the whole realizes a high-voltage, low-leakage current gallium oxide Schottky barrier diode. The preparation method includes: pre-treating the epitaxial wafer, photolithography to form the ion implantation area, ion implantation, cleaning the epitaxial wafer after implantation, rapid thermal annealing to form p-Ga2O3, preparing the cathode, and preparing the anode.

[0110] The innovation of the present invention is that after ion implantation and annealing, Ga atoms are precipitated and injected ions form a gallium oxygen nitrogen (phosphorus, magnesium) compound with p-type characteristics to realize p-Ga2O3, and the homogeneous pn junction terminal critical breakdown electric field is high and the interface trap concentration is low, thus realizing a gallium oxide Schottky barrier diode with higher withstand voltage, lower leakage current and high reliability. Not only can this homogeneous pn junction terminal gallium oxide Schottky barrier diode be used in high-power and high-voltage power electronics fields such as smart grids and data centers, but its preparation method has also opened up a new path for the design and preparation of gallium oxide-based devices.

[0111] The above are only multiple embodiments of the present invention and do not constitute any limitation to the present invention. Obviously, for professionals in this field, after understanding the content and principles of the present invention, it is possible to make various modifications and changes in form and details without departing from the principles and structures of the present invention. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A homogeneous pn junction terminal gallium oxide Schottky barrier diode, which is provided with: a cathode electrode, an n-Ga2O3 substrate, and an n-Ga2O3 epitaxial layer from bottom to top, ion implantation regions are provided at the left and right ends of the upper surface of the n-Ga2O3 epitaxial layer, and the upper surface of the n-Ga2O3 epitaxial layer is covered with an anode electrode, characterized in that: After annealing treatment, the injected ions in the ion implantation area generate compounds with p-type characteristics, that is, the ion implantation area generates a p-type Ga2O3 material area, and the p-type Ga2O3 material area and the n-Ga2O3 epitaxial layer form a homogeneous pn junction terminal, thereby realizing a gallium oxide Schottky barrier diode with high withstand voltage and low leakage current as a whole.

2. The homogeneous pn junction terminal gallium oxide Schottky barrier diode according to claim 1, characterized in that: After the ions implanted in the ion implantation area are annealed, the thickness of the generated p-type Ga2O3 material area is 200nm-1μm.

3. The homogeneous pn junction terminal gallium oxide Schottky barrier diode according to claim 1, characterized in that: The compound with p-type characteristics formed after annealing of the implanted ions in the ion implantation region is at least one of a gallium oxygen nitrogen compound, a gallium oxygen nitrogen phosphorus compound, and a gallium oxygen nitrogen magnesium compound.

4. The homogeneous pn junction terminal gallium oxide Schottky barrier diode according to claim 1, characterized in that: The anode electrode is a double-layer metal structure, wherein the lower layer is Ni with a thickness of 50nm-100nm, and the upper layer is Au with a thickness of 100nm-200nm.

5. A method for preparing a homogeneous pn junction terminal gallium oxide Schottky barrier diode, which is for preparing any device of the homogeneous pn junction terminal gallium oxide Schottky barrier diode described in claims 1-4, characterized in that: The steps include: 1) Pretreatment of epitaxial wafers: Gallium oxide epitaxial wafers refer to gallium oxide epitaxial wafers with n-Ga2O3 epitaxial layers epitaxially grown on n-type heavily doped gallium oxide substrates. The pretreatment is to put the gallium oxide epitaxial wafers into acetone solution and isopropanol solution for ultrasonic cleaning for 5 minutes to 10 minutes respectively, then rinse with a large amount of deionized water, and finally blow dry with nitrogen to obtain the cleaned epitaxial wafers; 2) Photolithography to form the area to be implanted: first, a photoresist is coated on the n-Ga2O3 epitaxial layer to be implanted, and then the photolithography process of pre-baking, alignment and exposure, post-baking, development, hardening and pattern detection is performed to obtain the area to be implanted that is not protected by the photoresist; 3) Ion implantation to form an ion implantation area: The ion implantation concentration of the area to be implanted on the upper surface of the epitaxial layer is 1e15cm -3 -5e19cm -3 N / P ions form ion implantation regions at both ends of the n-Ga2O3 epitaxial layer; 4) Cleaning the epitaxial wafer after injection: Place the epitaxial wafer after ion injection in an NMP solution and heat it in a water bath for 30 minutes, then place it in an acetone solution and an isopropanol solution in turn and ultrasonically clean it for 5 minutes to 10 minutes each, then rinse it with a large amount of deionized water, and finally blow dry it with nitrogen to obtain a cleaned epitaxial wafer; 5) Rapid thermal annealing to form p-Ga2O3: that is, in a N2 environment, the furnace annealing temperature is set to 800℃-1600℃, and the annealing time is set to 10s-10min, so that the ion implantation area becomes a p-type Ga2O3 area, and realizes a homogeneous pn junction termination with the n-Ga2O3 epitaxial layer; 6) Preparation of cathode: Ti / Au with a thickness of 60nm / 200nm is deposited on the substrate by electron beam evaporation E-Beam system; then the epitaxial wafer is placed in an annealing furnace, and the annealing temperature in the furnace is set to 500°C in a N2 environment, and the annealing time is 1min to form a cathode with good ohmic contact; 7) Preparation of anode: First, the anode area to be prepared is formed on the epitaxial layer by photolithography, and then Ni / Au with a thickness of 60nm / 120nm is deposited in the anode area by electron beam evaporation E-Beam system. The epitaxial wafer after metal deposition is placed in a stripping solution, and the anode is formed by stripping to complete the device manufacturing.

6. The method for preparing a homogeneous pn junction terminal gallium oxide Schottky barrier diode according to claim 5, characterized in that: Step 3) The ions to be implanted in the ion implantation region formed by the ion implantation include at least one of N ions, P ions or Mg ions.

7. The method for preparing a homogeneous pn junction terminal gallium oxide Schottky barrier diode according to claim 5, characterized in that: Step 5) Rapid thermal annealing forms p-Ga2O3. The preferred conditions for rapid thermal annealing treatment are as follows: the annealing temperature is 1000°C and the annealing time is 1 min.

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