Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprises a semiconductor layer and a trench gate, the semiconductor layer comprises a buried layer, at least part of the buried layer is located at the bottom of the trench gate and is connected with the trench gate; the body region is connected with the side wall of the trench gate; the source region is connected with the side wall of the trench gate, and the source region extends from the first surface to the body region and is connected with the body region; at least part of the drift region is located between the body region and the second surface and connected with the buried layer and the body region, the bottom end of at least part of the buried layer is further provided with an end doping region, and the width of the end doping region is larger than that of the bottom end of the buried layer. The buried layer is arranged at the bottom of the trench gate, and the end doped region is arranged at the bottom end of at least part of the buried layer, so that the voltage endurance capability of the device is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and more specifically, to a semiconductor device with a trench gate structure and a manufacturing method thereof. Background Art

[0002] In a vertical transistor with a trench gate, the drain of the transistor needs to be able to withstand high voltage. Since there is a PN junction between the drain and the source, the ability to withstand high voltage is better.

[0003] However, due to the presence of the gate dielectric layer between the drain and the trench gate, it is not conducive to withstanding high voltage. Especially at the bottom of the trench gate, the high voltage resistance is poor, which reduces the overall withstand voltage of the device. Therefore, it is necessary to improve the device to improve the above problems. Summary of the invention

[0004] In view of the above problems, the purpose of the present disclosure is to provide a semiconductor device and a manufacturing method thereof, by providing a buried layer at the bottom of the trench gate and providing an end doping region at at least a portion of the bottom of the buried layer, thereby improving the voltage resistance of the device.

[0005] According to one aspect of an embodiment of the present disclosure, a semiconductor device is provided, comprising a semiconductor layer and a trench gate, wherein the semiconductor layer has a first surface and a second surface opposite to each other, and the trench gate is located in a trench on the first surface of the semiconductor layer.

[0006] The semiconductor layer comprises:

[0007] A buried layer, at least a portion of which is located at the bottom of the trench gate and connected to the trench gate;

[0008] A body region connected to a sidewall of the trench gate;

[0009] a source region connected to a sidewall of the trench gate, the source region extending from the first surface toward the body region and connected to the body region; and

[0010] a drift region, at least a portion of which is located between the body region and the second surface and connected to the buried layer and the body region,

[0011] Wherein, at least a portion of the bottom end of the buried layer is further provided with an end doping region, and the width of the end doping region is greater than the width of the bottom end of the buried layer.

[0012] Optionally, the source region and the drift region are of a first conductivity type, the buried layer, the end doped region and the body region are of a second conductivity type, and the first conductivity type is opposite to the second conductivity type.

[0013] Optionally, a width of at least a portion of the buried layer gradually narrows from the first surface toward the second surface.

[0014] Optionally, the width of the end doping region does not exceed the width of the wide end of the buried layer.

[0015] Optionally, the buried layer is in a shape of multiple inverted bosses from the first surface toward the second surface.

[0016] Optionally, the doping concentration of the buried layer decreases from the first surface toward the second surface.

[0017] Optionally, the doping concentration of the buried layer decreases from the middle of the buried layer toward the side edge of the buried layer.

[0018] Optionally, an angle between a bottom surface of the trench gate connected to the buried layer and a side edge of the buried layer is 80° to 40°.

[0019] Optionally, the buried layer includes:

[0020] a first buried layer, located at the bottom of the trench gate and connected to the trench gate,

[0021] The end doping region is arranged at the bottom end of the first buried layer.

[0022] Optionally, a width of the trench gate is greater than a width of the first buried layer.

[0023] Optionally, the buried layer includes:

[0024] a second buried layer, separated from the trench gate, the body region being located between the second buried layer and the first surface and connected to the second buried layer,

[0025] The end doping region is arranged at the bottom end of the second buried layer.

[0026] Optionally, along the width direction of the trench gate, the body region, the source region and the second buried layer are all located on two sides of the trench gate.

[0027] According to another aspect of an embodiment of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising:

[0028] forming a buried layer in a semiconductor layer, the semiconductor layer having opposing first and second surfaces;

[0029] forming a well region in the semiconductor layer, wherein the well region extends from the first surface toward the first buried layer and is connected to the buried layer;

[0030] forming a source region in the well region, the source region extending from the first surface into the well region; and

[0031] A trench is formed on the first surface, and a trench gate is formed in the trench, at least part of the buried layer is located at the bottom of the trench gate and connected to the trench gate,

[0032] Wherein, at least a portion of the bottom end of the buried layer is also formed with an end doping region, and the width of the end doping region is greater than the width of the bottom end of the buried layer.

[0033] Optionally, the step of forming a buried layer in the semiconductor layer includes:

[0034] forming a hard mask on the first surface, and performing a first ion implantation into the semiconductor layer through the hard mask; and

[0035] At least one sidewall spacer is formed on the sidewall of the hard mask, and after each sidewall spacer is formed, ion implantation is performed into the semiconductor layer through the hard mask.

[0036] The depth of each ion implantation is greater than the depth of the previous ion implantation.

[0037] Optionally, the step of forming the end doped region includes:

[0038] Between the last formation of the sidewall spacer and the first formation of the sidewall spacer, deep ion implantation is performed into the semiconductor layer through the hard mask to form a deep doped region.

[0039] The deep doped region is not connected to the first surface of the semiconductor layer and is used to form the end doped region.

[0040] One of the above technical solutions has the following beneficial effects:

[0041] By setting a buried layer in the semiconductor layer, and at least part of the buried layer is located at the bottom of the trench gate, the width of the buried layer is gradually reduced along the direction from the first surface to the second surface of the semiconductor layer, so that the carrier flow channel is expanded, thereby reducing the obstruction of the buried layer to the carrier flow and reducing the on-resistance of the device. By setting an end doping region at the narrow end of the buried layer, the PN junction formed by the end doping region and the drift region is used to further improve the voltage resistance of the device, thereby helping to widen the carrier flow channel while improving the voltage resistance of the device.

[0042] In some embodiments, the body region and the source region are disposed on both sides of the trench gate and connected to the sidewalls of the trench gate, so that both sides of the trench gate can be used as conductive channels, thereby reducing the resistance of the device in the on state.

[0043] In some embodiments, the maximum width of the first buried layer is smaller than the width of the bottom of the trench gate, so that the first buried layer only contacts the bottom of the trench gate without wrapping the corners of the trench gate, further reducing the first buried layer's resistance to carrier flow, thereby reducing the on-resistance of the device.

[0044] In some embodiments, multiple ion implantations are performed using a self-alignment process of a hard mask and a sidewall, so that the implantation width is gradually reduced, while the implantation depth is gradually deepened, thereby achieving a morphology in which the buried layer width gradually decreases from the first surface of the semiconductor layer toward the second surface. In addition, the self-alignment process can save the number of mask plates and has high alignment accuracy.

[0045] In some embodiments, an ion implantation process is used to simultaneously form a first buried layer and a second buried layer in the semiconductor layer, which saves the number of masks and eliminates the need for additional alignment of the patterns of the first and second buried layers, thereby reducing process difficulty and saving costs.

[0046] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0048] Figure 1 A schematic top view of the structure of a semiconductor device according to a first embodiment of the present disclosure is shown.

[0049] Figure 2 Shown along Figure 1 Schematic diagram of the cross-sectional structure taken along line AA.

[0050] Figure 3 A schematic structural diagram of a semiconductor device according to a second embodiment of the present disclosure is shown.

[0051] Figure 4 A schematic structural diagram of a semiconductor device according to a third embodiment of the present disclosure is shown.

[0052] Figures 5 to 11 The schematic diagram shows a structure of a part of the stages in the method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] The present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0054] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0055] If the purpose is to describe the situation of being directly on another layer or another area, this article will use expressions such as "directly on..." or "on... and adjacent to...".

[0056] The power device generally includes an active component region, an edge termination region, and a crack-stop or shielding region. The active component region includes an active component array. The present disclosure relates to an active component structure. The size of the active component may vary depending on product requirements, and there may be a body region between active components in the active component region.

[0057] Many specific details of the present disclosure are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present disclosure. However, as those skilled in the art will appreciate, the present disclosure may not be implemented in accordance with these specific details.

[0058] In vertical transistors, such as SiC MOSFET, it is necessary to be able to withstand a high voltage applied to the drain. Since there is a PN junction between the drain and the source, the ability to withstand high voltage is better. However, due to the presence of the gate dielectric layer between the drain and the trench gate, it is not conducive to withstanding high voltage. Especially at the bottom of the trench gate, the gate dielectric layer has poor high voltage resistance and a gate shielding structure needs to be designed separately. In order to improve the above problems, the purpose of the present disclosure is to provide a semiconductor device, which improves the overall voltage resistance of the device by providing a first buried layer at the bottom of the trench gate, and reduces the obstruction of the buried layer to the flow of carriers by gradually reducing the width of the first buried layer, thereby reducing the on-resistance.

[0059] Figure 1 FIG. 1 is a schematic diagram showing a top view of a semiconductor device according to a first embodiment of the present disclosure. Figure 2 Shown along Figure 1 Schematic diagram of the cross-sectional structure cut by line AA, where: Figure 1Only the buried layer and the trench gate are shown, and other structures are omitted in order to more clearly express the positional relationship between the various structures.

[0060] like Figure 1 and Figure 2 As shown, the semiconductor device of the first embodiment of the present disclosure includes a semiconductor layer 100, a plurality of trench gates 150, an interlayer dielectric layer 160, a first conductive layer 171 and a second conductive layer 172. The semiconductor layer 100 has a first surface 101 and a second surface 102 relative to each other and a plurality of trenches located on the first surface 101, and the trenches extend from the first surface 101 to the second surface 102 into the semiconductor layer 100. A plurality of trench gates 150 are located in the corresponding trenches. Among them, the semiconductor layer 100 is, for example, a SiC, GaN, Ga2O3, Al2O3 substrate or a stacked structure consisting of a substrate and an epitaxial layer. However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art can make other settings for the material and number of layers of the semiconductor layer as needed, such as other wide bandgap semiconductor materials.

[0061] The semiconductor layer 100 includes a drift region 110, a buried layer 120, end doped regions 121a and 122a, a body region 131, a source region 141, and a body contact region 142. The buried layer 120 includes a first buried layer 121 and a second buried layer 122, the source region 141 and the drift region 110 are of a first conductivity type, the first buried layer 121, the second buried layer 122, the end doped regions 121a and 121b, the body region 131, and the body contact region 142 are of a second conductivity type, and the doping concentration of the body contact region 142 is greater than the doping concentration of the body region 131. The first conductivity type is opposite to the second conductivity type. The first conductivity type is one of a P type and an N type, and the second conductivity type is the other of a P type and an N type.

[0062] The semiconductor device of this embodiment can be used as a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), and can also be used as an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), for example, a drain contact region is set on the second surface 102 of the semiconductor layer 100, and the conductivity type of the drain contact region is set to the first conductivity type or the second conductivity type. However, the embodiments of the present disclosure are not limited to this, and those skilled in the art can perform other settings on the conductivity type of each region in the semiconductor layer as needed to use the semiconductor device as a MOSFET or an IGBT.

[0063] The trench gate 150 includes a gate dielectric layer 151 and a gate conductor 152. The gate dielectric layer 151 covers the inner surface of the trench, and the gate conductor 152 is located in the trench. The gate dielectric layer 151 is located between the semiconductor layer 100 and the gate conductor 152, and is used to separate the semiconductor layer 100 from the gate conductor 152. The width direction of the trench gate 150 is the X-axis direction, the depth direction is the Z-axis direction, and the length direction is the Y-axis direction. Optionally, the X-axis, Y-axis, and Z-axis directions are perpendicular to each other.

[0064] The first buried layer 121 is located at the bottom of the trench gate 150. Along the X-axis direction, the second buried layer 122, the body region 131, the source region 141 and the body contact region 142 are all located on both sides of the trench gate 150.

[0065] The first buried layer 121 is connected to the trench gate 150 , wherein the width of the first buried layer 121 is smaller than the width of the trench gate 150 , so that the first buried layer 121 is only located at the bottom of the trench gate 150 and does not wrap around the corner of the trench gate 150 .

[0066] The first buried layer 121 and the second buried layer 122 both extend along the Y-axis direction and are separated from each other. The second buried layer 122 is not connected to the trench gate 150. Optionally, the doping concentration of the first buried layer 121 decreases from the first surface 101 of the semiconductor layer 100 toward the second surface 102; the doping concentration of the first buried layer 121 decreases from the middle of the first buried layer 121 toward the side edge of the first buried layer 121. Optionally, the doping concentration distribution of the second buried layer 122 is similar to that of the first buried layer 121.

[0067] The width of the first buried layer 121 gradually narrows from the bottom of the trench gate 150 toward the second surface 102. The second buried layer 122 has a similar morphology to the first buried layer 121, and the width of the second buried layer 122 gradually narrows from the bottom of the body region 131 toward the second surface 102. Accordingly, the drift region 100 between the first buried layer 121 and the second buried layer 122 gradually widens.

[0068] Optionally, the inclination angle α between the first buried layer 121 and the bottom of the trench gate 150 is 80° to 40°, that is, the angle α between the bottom surface of the trench gate 150 connected to the first buried layer 121 and the side edge of the first buried layer 121 is 80° to 40°. In some embodiments, the inclination angle α can be a series of angles such as 80°, 75°, 70°, 65°, 60°, 55°, 50°, 45°, 40°, or other angles.

[0069] The inclination angle between the second buried layer 122 and the bottom of the body region 131 is 80° to 40°. In some embodiments, the inclination angle α can be a series of angles such as 80°, 75°, 70°, 65°, 60°, 55°, 50°, 45°, 40°, or other angles.

[0070] In this embodiment, the end doping region 121a is disposed at the bottom end (narrow end) of the first buried layer 121 and connected to the bottom end of the first buried layer 121, and the width of the end doping region 121a is greater than the bottom end width of the first buried layer 121. The end doping region 122a is disposed at the bottom end (narrow end) of the second buried layer 122 and connected to the bottom end of the second buried layer 122, and the width of the end doping region 122a is greater than the bottom end width of the second buried layer 122.

[0071] Along the X-axis direction, the body region 131 is respectively connected to the two side walls of the trench gate 150 and the second buried layer 122. The source region 141 extends from the first surface 101 of the semiconductor layer 100 toward the body region 131 and is connected to the body region 131. The body contact region 142 extends from the first surface 101 of the semiconductor layer 100 toward the body region 131 and is connected to the body region 131. Optionally, the source region 141 and the body contact region 142 can be connected or separated by the body region 131. At least part of the drift region 110 is located between the body region 131 and the second surface 102 of the semiconductor layer 100, and is connected to the first buried layer 121, the second buried layer 122 and the body region 131.

[0072] The interlayer dielectric layer 160 is located on the first surface 101 of the semiconductor layer 100 and covers the trench gate 150. The first conductive layer 171 serves as a source electrode, covering the first surface 101 of the semiconductor layer 100 and the interlayer dielectric layer 160. The second conductive layer 172 serves as a drain electrode, covering the second surface 102 of the semiconductor layer 100.

[0073] In this embodiment, along the Y-axis direction, a plurality of trench gates 150 are arranged at intervals, and along the Y-axis direction, the body region 131 and the source region 141 are also located between adjacent trench gates 150. In some other embodiments, along the Y-axis direction, the trench gates 150 extend continuously.

[0074] In this embodiment, when the device is turned on, the body region 131 and the part adjacent to the side wall of the trench gate 150 are inverted to form a channel, and carriers flow in from the source (first conductive layer 171), then flow through the source region 141 and the channel to the drift region 110, and finally flow out from the drain (second conductive layer 172), see Figure 2 The carrier flow path is shown by the dashed line.

[0075] By providing the first buried layer 121 and the second buried layer 122, and gradually reducing the width of the first buried layer 121 and the second buried layer 122 from the first surface 101 of the semiconductor layer 100 toward the second surface 102, the flow channel of the carriers is expanded, and the obstacles of the first buried layer 121 and the second buried layer 122 to the flow of the carriers are greatly reduced, thereby reducing the on-resistance of the device. By providing the end doping regions 121a and 122a at the narrow ends of the first buried layer and the second buried layer, the PN junction formed by the end doping regions 121a and 122a and the drift region 110 is used to further improve the withstand voltage capability of the device. As the size of the device continues to shrink, this solution is more conducive to widening the carrier flow channel while taking into account the improvement of the withstand voltage capability of the device.

[0076] Furthermore, by arranging the body region 131 and the source region 141 on both sides of the trench gate 150 and connecting to the side walls of the trench gate 150 , both sides of the trench gate 150 can be used as conductive channels, thereby reducing the resistance of the device in the on state.

[0077] Figure 3 A schematic structural diagram of a semiconductor device according to a second embodiment of the present disclosure is shown.

[0078] like Figure 3 As shown, the similarities between the semiconductor device of the second embodiment of the present disclosure and the first embodiment are not described in detail here, and reference may be made to Figure 1 and Figure 2 The difference is that, in this embodiment, only the end doping region 121a is provided at the narrow end of the first buried layer 121, while the end doping region 122a is not provided at the narrow end of the second buried layer 122. In some optional embodiments, the second buried layer 122 may not be provided.

[0079] Figure 4 A schematic structural diagram of a semiconductor device according to a third embodiment of the present disclosure is shown.

[0080] like Figure 4 As shown, the similarities between the semiconductor device of the third embodiment of the present disclosure and the first embodiment are not described in detail here, and reference may be made to Figure 1 and Figure 2 The difference is that, in this embodiment, the end doping region 122a is only provided at the narrow end of the second buried layer 122, while the end doping region 121a is not provided at the narrow end of the first buried layer 121.

[0081] Figures 5 to 11 The schematic diagram shows a structure of a part of the stages in the method for manufacturing a semiconductor device according to the first embodiment of the present disclosure.

[0082] See also Figure 5, a hard mask 200 is formed on the first surface 101 of the semiconductor layer 100 , wherein the interval between adjacent hard masks 200 corresponds to the first buried layer 121 and the second buried layer 122 formed in subsequent steps.

[0083] In this step, for example, a deposition process is first used to form a hard mask layer on the first surface 101 of the semiconductor layer 100 , and the material of the hard mask layer includes, for example, silicon oxide, silicon nitride, etc. Then, the hard mask layer is patterned by photolithography and etching processes to form a hard mask 200 .

[0084] Furthermore, a first ion implantation is performed into the semiconductor layer 100 through the hard mask 200 to form a first doped region 210 .

[0085] In this step, when the first ion implantation is performed to form the first doping region 210 , the hard mask 200 blocks the doping impurities, and only allows the doping impurities to enter the semiconductor layer 100 from the spaces between adjacent hard masks 200 .

[0086] Furthermore, a first spacer 201 is formed on the sidewall of the hard mask 200, such as Figure 6 shown.

[0087] In this step, for example, a deposition process is first used to cover the hard mask 200 and the first surface 101 of the semiconductor layer 100 to form a sidewall deposition layer, and then there is no need to perform a photolithography step, and an etching process is directly used to remove the sidewall deposition layer on the first surface 101 and the top of the hard mask 200, and the sidewall deposition layer retained on the side wall of the hard mask 200 serves as the first sidewall 201.

[0088] Furthermore, a second ion implantation is performed into the semiconductor layer 100 through the hard mask 200 to form a second doping region 220 .

[0089] In this step, since both the hard mask 200 and the first sidewall 201 block doping impurities, the width of the second doping region 220 is smaller than the width of the first doping region 210. In addition, the second ion implantation depth is greater than the first ion implantation depth, so the depth of the second doping region 220 is greater than the depth of the first doping region 210.

[0090] Furthermore, a second sidewall spacer 202 is formed on the sidewall of the hard mask 200, and the second sidewall spacer 202 is connected to the first sidewall spacer 201, as shown in FIG. Figure 7 As shown, the formation method of the second side wall 202 is similar to that of the first side wall 201, which will not be repeated here.

[0091] Furthermore, a third ion implantation is performed into the semiconductor layer 100 through the hard mask 200 to form a third doping region 230 .

[0092] In this step, since the hard mask 200, the first sidewall 201 and the second sidewall 202 can block the doping impurities, the width of the third doping region 230 is smaller than the width of the second doping region 220. And the third ion implantation depth is greater than the implantation depth of the second ion implantation, so the depth of the third doping region 230 is greater than the depth of the second doping region 220.

[0093] Furthermore, deep ion implantation is performed into the semiconductor layer 100 through the hard mask 200 to form a deep doped region 231 , wherein the deep doped region 231 is not connected to the first surface 101 of the semiconductor layer 100 .

[0094] In this step, the hard mask 200 is still used, and the first sidewall 201 and the second sidewall 202 both block the doping impurities, so the deep doping region 231 has the same width as the third doping region 230. The ion implantation energy for forming the deep doping region 231 is greater than the energy for forming the third doping region 230, so the depth of the deep doping region 231 is greater than the depth of the third doping region 230 and is not connected to the third doping region 230.

[0095] Furthermore, a third sidewall spacer 203 is formed on the sidewall of the hard mask 200, and the third sidewall spacer 203 is connected to the second sidewall spacer 202, as shown in FIG. Figure 8 As shown, the formation method of the third sidewall 203 is similar to that of the first sidewall 201, which will not be repeated here.

[0096] Furthermore, a fourth ion implantation is performed into the semiconductor layer 100 through the hard mask 200 to form a fourth doping region 240 .

[0097] In this step, since the hard mask 200, the first sidewall 201, the second sidewall 202 and the third sidewall 203 can block the doping impurities, the width of the fourth doping region 240 is smaller than the width of the third doping region 230. And the fourth ion implantation depth is greater than the implantation depth of the third ion implantation, so the depth of the fourth doping region 240 is greater than the depth of the third doping region 230 and is connected to the deep doping region 231. Optionally, the bottom of the fourth doping region 240 is the same depth as the bottom of the deep doping region 231, or the bottom of the fourth doping region 240 is the same depth as the top of the deep doping region 231.

[0098] In this embodiment, the first doping region 210, the second doping region 220, the third doping region 230 and the fourth doping region 240 formed by four ion implantations together constitute the first buried layer 121 and the second buried layer 122 with inclined sidewalls. Among them, the deep doping region 231 is used to form the end doping regions 121a and 122a connected to the first buried layer 121 and the second buried layer 122 respectively. Figure 7In this cross section, the pattern formed by the first doping region 210, the second doping region 220, the third doping region 230 and the fourth doping region 240 is composed of a plurality of rectangles, the width of which decreases from top to bottom, thereby forming a first buried layer 121 and a second buried layer 122 having inclined sidewalls. After the trench gate 150 is formed in the subsequent steps, the first buried layer 121 is in the shape of multiple inverted convex terraces from the bottom of the trench gate 150 toward the second surface 102 of the semiconductor layer 100. The multiple inverted convex terraces form the first buried layer 121 having inclined sidewalls with gradually decreasing widths, and the more the number of convex terraces, the smoother the inclined sidewalls of the first buried layer 121, and the second buried layer 122 has a similar morphology to the first buried layer 121.

[0099] In this embodiment, the deep doping region 231 is formed after forming the second sidewall 202, and has the same width as the third doping region 230. In some other embodiments, the deep doping region 231 is formed after forming the first sidewall 201, and in this case, the width of the deep doping region 231 should be the same as the width of the second doping region 220.

[0100] In this embodiment, there is an overlapping area of ​​multiple ion implantations in the middle part of the first buried layer 121, so the doping concentration from the middle part to the side edge part of the first buried layer 121 has a gradient change, and the doping concentration of the middle part is greater than the doping concentration of the side edge part. It is beneficial to make the electric field at the bottom of the trench gate formed subsequently more uniform. Similarly, the doping concentration of the first buried layer 121 from shallow to deep also has a gradient change, that is, in the first buried layer 121, the closer to the first surface 101 of the semiconductor layer 101, the greater the doping concentration due to the overlapping area of ​​multiple ion implantations, and the farther away from the first surface 101, the smaller the doping concentration. The second buried layer 122 has a similar doping concentration distribution to the first buried layer 121.

[0101] In this embodiment, the first sidewall 201, the second sidewall 202 and the third sidewall 203 are not patterned by photolithography when they are formed, but the sidewalls are directly formed by etching after the sidewall deposition layer is formed. Therefore, when forming the first buried layer 121 and the second buried layer 122 with inclined sidewalls, the hard mask layer is patterned only before the first ion implantation, and when the doped region is subsequently formed by the ion implantation process, no additional patterning process is required, but the sidewall process is used in a self-aligned form. The inclination angle of the first buried layer 121 and the second buried layer 122 can be adjusted by changing the spacing between adjacent hard masks 200, the thickness of each sidewall and the energy during ion implantation.

[0102] In the present embodiment, three sidewall spacer processes are used to form the first buried layer 121 and the second buried layer 122. However, the present disclosure is not limited thereto, and those skilled in the art can adjust the number of sidewall spacers and the number of ion implantations as needed. It is necessary to form at least one sidewall spacer on the sidewall of the hard mask 200, and after each sidewall spacer is formed, an ion implantation is performed into the semiconductor layer 100 through the hard mask 200, wherein the depth of each ion implantation is greater than the depth of the previous ion implantation, and between the last sidewall spacer and the first sidewall spacer, a deep ion implantation is performed into the semiconductor layer 100 through the hard mask 200 to form a deep doped region 231.

[0103] In this embodiment, the first buried layer 121 and the second buried layer 122 are simultaneously formed in the semiconductor layer 100 by adopting an ion implantation process, which can save the number of mask plates and eliminate the need for additional alignment of the patterns of the first buried layer 121 and the second buried layer 122, thereby reducing process difficulty and saving costs.

[0104] Furthermore, a well region 130 is formed in the semiconductor layer 100. The well region 130 extends from the first surface 101 of the semiconductor layer 100 toward the first buried layer 121 and the second buried layer 122, and is connected to the first buried layer 121 and the second buried layer 122, respectively. Fig. 9 As shown, the undoped semiconductor layer 100 serves as the drift region 110 .

[0105] Furthermore, a source region 141 and a body contact region 142 are formed in the well region 130. The source region 141 and the body contact region 142 extend from the first surface 101 of the semiconductor layer 100 to the well region 130. Fig.10 As shown, the undoped well region 130 serves as the body region 131 .

[0106] Furthermore, a trench extending from the first surface 101 of the semiconductor layer 100 to the first buried layer 121 is formed, and a trench gate 150 is formed in the trench. Fig.11 The width of the trench gate 150 is greater than the width of the first buried layer 121 .

[0107] Furthermore, an interlayer dielectric layer 160 and a first conductive layer 171 are formed on the first surface 101 of the semiconductor layer 100, and a second conductive layer 172 is formed on the second surface 102 of the semiconductor layer 100, thereby forming Figure 1 and Figure 2 The semiconductor device shown.

[0108] In some embodiments, more sidewall processes and ion implantation processes may be used to form the first buried layer 121 and the second buried layer 122 , and better tilt angle structures of the first buried layer 121 and the second buried layer 122 may be formed through more sidewall processes and ion implantation processes.

[0109] The manufacturing methods of the semiconductor devices of the second and third embodiments of the present disclosure are substantially similar to those of the semiconductor device of the first embodiment, and reference may be made to the relevant description of the first embodiment, except that the end doping region 121a is provided only at the narrow end of the first buried layer 121, while the end doping region 122a is not provided at the narrow end of the second buried layer 122. Alternatively, the end doping region 122a is provided only at the narrow end of the second buried layer 122, while the end doping region 121a is not provided at the narrow end of the first buried layer 121.

[0110] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising a semiconductor layer and a trench gate, wherein the semiconductor layer has a first surface and a second surface opposite to each other, and the trench gate is located in a trench on the first surface of the semiconductor layer. The semiconductor layer comprises: A buried layer, at least a portion of which is located at the bottom of the trench gate and connected to the trench gate; A body region connected to a sidewall of the trench gate; A source region connected to a sidewall of the trench gate, the source region extending from the first surface toward the body region and connected to the body region; as well as a drift region, at least a portion of which is located between the body region and the second surface and connected to the buried layer and the body region, Wherein, at least a portion of the bottom end of the buried layer is further provided with an end doping region, and the width of the end doping region is greater than the width of the bottom end of the buried layer.

2. The semiconductor device according to claim 1, wherein The source region and the drift region are of a first conductivity type, the buried layer, the end doped region and the body region are of a second conductivity type, and the first conductivity type is opposite to the second conductivity type.

3. The semiconductor device according to claim 1, wherein From the first surface toward the second surface, a width of at least a portion of the buried layer gradually narrows.

4. The semiconductor device according to claim 3, wherein: The width of the end doping region does not exceed the width of the wide end of the buried layer.

5. The semiconductor device according to claim 3, wherein: From the first surface toward the second surface, the buried layer is in a shape of multiple inverted bosses.

6. The semiconductor device according to claim 3, wherein: The doping concentration of the buried layer decreases from the first surface toward the second surface.

7. The semiconductor device according to claim 3, wherein: The doping concentration of the buried layer decreases from the middle of the buried layer toward the side edge of the buried layer.

8. The semiconductor device according to claim 3, wherein: The angle between the bottom surface of the trench gate connected to the buried layer and the side edge of the buried layer is 80° to 40°.

9. The semiconductor device according to any one of claims 1 to 8, wherein: The buried layer comprises: a first buried layer, located at the bottom of the trench gate and connected to the trench gate, The end doping region is arranged at the bottom end of the first buried layer.

10. The semiconductor device according to claim 9, wherein The width of the trench gate is greater than the width of the first buried layer.

11. The semiconductor device according to any one of claims 1 to 8, wherein: The buried layer comprises: a second buried layer, separated from the trench gate, the body region being located between the second buried layer and the first surface and connected to the second buried layer, The end doping region is arranged at the bottom end of the second buried layer.

12. A method for manufacturing a semiconductor device, comprising: forming a buried layer in a semiconductor layer, the semiconductor layer having opposing first and second surfaces; forming a well region in the semiconductor layer, wherein the well region extends from the first surface toward the first buried layer and is connected to the buried layer; forming a source region in the well region, wherein the source region extends from the first surface into the well region; as well as A trench is formed on the first surface, and a trench gate is formed in the trench, at least part of the buried layer is located at the bottom of the trench gate and connected to the trench gate, Wherein, at least a portion of the bottom end of the buried layer is also formed with an end doping region, and the width of the end doping region is greater than the width of the bottom end of the buried layer.

13. The manufacturing method according to claim 12, wherein: The step of forming a buried layer in the semiconductor layer comprises: forming a hard mask on the first surface, and performing a first ion implantation into the semiconductor layer through the hard mask; and At least one sidewall spacer is formed on the sidewall of the hard mask, and after each sidewall spacer is formed, ion implantation is performed into the semiconductor layer through the hard mask. The depth of each ion implantation is greater than the depth of the previous ion implantation.

14. The manufacturing method according to claim 13, wherein: The step of forming the end doped region comprises: Between the last formation of the sidewall spacer and the first formation of the sidewall spacer, deep ion implantation is performed into the semiconductor layer through the hard mask to form a deep doped region. The deep doped region is not connected to the first surface of the semiconductor layer and is used to form the end doped region.

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