Semiconductor device

Abstract

Embodiments relate to a semiconductor device. The withstand voltage can be improved and the on-resistance can be reduced. The semiconductor device includes: a first electrode; a first semiconductor layer of a first conductivity type, which is provided on the first electrode, has a plurality of regions, and is connected to the first electrode; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type provided on a portion of the second semiconductor layer; a second electrode provided in each of the plurality of regions and facing the first semiconductor layer with an insulator interposed therebetween; a third electrode disposed along a boundary line between adjacent regions, not disposed in a portion of the boundary line farthest from the second electrode, and facing the second semiconductor layer with an insulator therebetween; and a fourth electrode provided on the third semiconductor layer and connected to the second semiconductor layer, the third semiconductor layer, and the second electrode, and a portion of the fourth electrode disposed at the farthest portion forms a Schottky barrier junction with the first semiconductor layer.

Description

[0001] Related Application:

[0002] This application claims priority from Japanese Patent Application No. 2023-149480 (filing date: September 14, 2023) as a prior application. The present application incorporates the entire contents of the prior application by reference. Technical Field

[0003] Embodiments relate to a semiconductor device. Background Art

[0004] A semiconductor device for power control has been proposed, in which columnar field plate electrodes (hereinafter also referred to as "FP electrodes") are periodically arranged and a gate electrode is disposed between the FP electrodes. Such a semiconductor device is required to have a higher withstand voltage and a lower on-resistance. Summary of the invention

[0005] The semiconductor device involved in the embodiment comprises: a first electrode; a first semiconductor layer of a first conductivity type, which is arranged on the first electrode, has multiple regions and is connected to the first electrode; a second semiconductor layer of a second conductivity type, which is arranged on the first semiconductor layer; a third semiconductor layer of the first conductivity type, which is arranged on a portion of the second semiconductor layer; a second electrode, which is arranged in each of the multiple regions and is opposite to the first semiconductor layer through an insulator; a third electrode, which is arranged along a boundary line between adjacent regions, and a portion farthest from the second electrode that is not arranged in the boundary line is opposite to the second semiconductor layer through an insulator; and a fourth electrode, which is arranged on the third semiconductor layer, is connected to the second semiconductor layer, the third semiconductor layer and the second electrode, and a portion of the fourth electrode arranged at the farthest portion forms a Schottky barrier junction with the first semiconductor layer.

[0006] According to the embodiment, a semiconductor device capable of improving a withstand voltage and reducing an on-resistance can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a plan view showing a semiconductor device according to an embodiment.

[0008] Figure 2 yes Figure 1 A cross-sectional view along line AA' is shown.

[0009] Figure 3 yes Figure 1 A cross-sectional view taken along line BB' is shown.

[0010] Figure 4 Yes means Figure 3 A partial enlarged cross-sectional view of region C.

[0011] Figure 5 It is a plan view showing a semiconductor device according to a comparative example. DETAILED DESCRIPTION

[0012] <Implementation Method>

[0013] Figure 1 It is a plan view showing a semiconductor device according to this embodiment.

[0014] Figure 2 yes Figure 1 A cross-sectional view along line AA' is shown.

[0015] Figure 3 yes Figure 1 A cross-sectional view taken along line BB' is shown.

[0016] Figure 4 Yes means Figure 3 A partial enlarged cross-sectional view of region C.

[0017] In addition, each figure is schematic and is appropriately emphasized and simplified.

[0018] like Figure 1 to Figure 4 As shown, in the semiconductor device 1 involved in this embodiment, a drain electrode 11 (first electrode), a source electrode 12 (fourth electrode), a gate electrode 13 (third electrode), an FP electrode 14 (second electrode) and a semiconductor portion 20 are provided. The semiconductor portion 20 is composed of a semiconductor material such as single crystal silicon (Si), and a predetermined conductivity type and carrier concentration are achieved by introducing impurities into each portion. In addition, in the semiconductor device 1, a gate insulating film 31, an FP insulating film 32, and interlayer insulating films 33 and 34 are provided.

[0019] The drain electrode 11 is disposed on the entire lower surface of the semiconductor portion 20. The interlayer insulating film 33 is disposed on the semiconductor portion 20. The interlayer insulating film 34 is disposed on the interlayer insulating film 33. Openings 35c and 35d are formed in the interlayer insulating films 33 and 34. The source electrode 12 is disposed on the interlayer insulating film 34.

[0020] A plurality of regions R of the same shape are set to be spread out without gaps on the upper surface of the semiconductor portion 20. When viewed from above, the region R has a square shape, for example. When viewed from above, the plurality of square regions R are arranged in a matrix.

[0021] On the upper surface of the semiconductor portion 20, a recess 20c is formed inside each region R. In addition, a recess 20d is formed at the corner of each region R, that is, at the portion where the four regions R are connected. The recess 20c is arranged in the region directly below the opening 35c. The recess 20d is arranged in the region directly below the opening 35d.

[0022] In this specification, an XYZ orthogonal coordinate system is used for convenience of explanation. The direction from the drain electrode 11 toward the source electrode 12 is set as the "Z direction", and the two directions in which the regions R are arranged are set as the "X direction" (first direction) and the "Y direction" (second direction). In addition, the Z direction is also called "up", and the reverse direction of the Z direction is also called "down", but this expression is also for convenience and has nothing to do with the direction of gravity.

[0023] The source electrode 12 includes a lower layer 12a (first metal layer) and an upper layer 12b (second metal layer) provided on the lower layer 12a. The lower layer 12a includes, for example, one or more metals selected from the group consisting of titanium (Ti), nickel (Ni), platinum (Pt), and tungsten (W). The upper layer 12b includes, for example, one or more metals selected from the group consisting of aluminum (Al) and copper (Cu).

[0024] The source electrode 12 is also arranged inside the openings 35c and 35d formed in the interlayer insulating films 33 and 34, and inside the recesses 20c and 20d formed on the upper surface of the semiconductor portion 20. Among the source electrodes 12, the portion arranged inside the opening 35c and the recess 20c is referred to as the "source contact 12c", and the portion arranged inside the opening 35d and the recess 20d is referred to as the "source contact 12d". Figure 1 In order to make the illustration easier to see, only one source contact 12c is shown, and the other parts of the source electrode 12 are omitted.

[0025] The gate electrode 13 and the FP electrode 14 are arranged in the semiconductor portion 20. The gate insulating film 31 covers the lower surface and the side surface of the gate electrode 13. Thus, the gate electrode 13 is insulated from the semiconductor portion 20. The upper surface of the gate electrode 13 is covered by the interlayer insulating film 33. Thus, the gate electrode 13 is insulated from the source electrode 12. The FP insulating film 32 covers the lower surface and the side surface of the FP electrode 14. Thus, the FP electrode 14 is insulated from the semiconductor portion 20. The lower end of the FP electrode 14 is located below the lower end of the gate electrode 13. The average thickness of the FP insulating film 32 is thicker than the average thickness of the gate insulating film 31.

[0026] When viewed from above, that is, in the Z direction, the gate electrode 13 is arranged along the boundary lines of the plurality of regions R. When viewed from above, the gate electrode 13 has a substantially lattice shape. That is, the gate electrode 13 includes a portion 13x extending in the X direction and a portion 13y extending in the Y direction.

[0027] In particular, at the intersection of the grid, i.e., the position where the four regions R are connected, the portion 13x and the portion 13y are not provided, but the frame-shaped portion 13z is provided. When viewed from above, the shape of the frame-shaped portion 13z is, for example, a square frame. The portion 13x and the portion 13y are both connected to the frame-shaped portion 13z, but the portion 13x is not connected to the portion 13y. That is, the gate electrode 13 is arranged along the boundary line of the plurality of regions R, and is not arranged at the corner of the region R.

[0028] The gate electrode 13 is integrally formed of the portion 13x, the portion 13y, and the frame-shaped portion 13z, and is connected to a gate pad (not shown) disposed on the interlayer insulating film 34. In this specification, "connected" means electrically connected.

[0029] When viewed from above, one FP electrode 14 is disposed near the center of each region R. The shape of the FP electrode 14 is substantially cylindrical with the central axis extending in the Z direction. The upper surface of the FP electrode 14 is connected to the source contact 12c. In addition, when viewed from above, the gate electrode 13 surrounds each FP electrode 14. The corner of the region R is a portion Rc farthest from the FP electrode 14 in the boundary line of the plurality of regions R. The portion Rc is located within the frame-shaped portion 13z.

[0030] The semiconductor portion 20 includes a drain layer 21 , a drift layer 22 , a base layer 23 , a base contact layer 24 , a source layer 25 (third semiconductor layer), and a contact layer 26 (fourth semiconductor layer).

[0031] The drain layer 21 is disposed on the drain electrode 11 and connected to the drain electrode 11. The conductivity type of the drain layer 21 is n + The drift layer 22 is disposed on the drain layer 21 and is in contact with the drain layer 21. The conductivity type of the drift layer 22 is n - In addition, "n + "Type" indicates that the carrier concentration is higher than that of "n-type". - The “n-type” exhibits a lower carrier concentration than the “n-type”. The same is true for the p-type. The first semiconductor layer is formed by the drain layer 21 and the drift layer 22.

[0032] The base layer 23 is disposed on the drift layer 22 and is in contact with the drift layer 22. The conductivity type of the base layer 23 is p-type. The base contact layer 24 is disposed on a portion of the base layer 23 and directly below the recess 20c. The conductivity type of the base contact layer 24 is p-type. + The base layer 23 and the base contact layer 24 form a second semiconductor layer.

[0033] The source layer 25 is disposed on another part of the base layer 23. The source layer 25 is disposed along the gate insulating film 31. The lower surface of the source layer 25 is in contact with the base layer 23, the upper surface is in contact with the interlayer insulating film 33, and the side surface is in contact with the gate insulating film 31 and the source contact 12c. The conductivity type of the source layer 25 is n + type.

[0034] The contact layer 26 is arranged at the corner of the portion Rc, i.e., the region R, when viewed from above, and is arranged in the region directly below the recess 20d of the semiconductor portion 20. The contact layer 26 is in contact with the source contact 12d at the bottom surface of the recess 20d. In addition, the contact layer 26 is also in contact with the drift layer 22 and the base layer 23. The conductivity type of the contact layer 26 is p + type.

[0035] The gate electrode 13 faces the upper part of the drift layer 22, the base layer 23, and the source layer 25 via the gate insulating film 31. Thus, an inversion layer can be formed in a region of the base layer 23 in contact with the gate insulating film 31. As a result, a MOSFET is realized in the semiconductor device 1.

[0036] The FP electrode 14 is arranged in the region R when viewed from above, and is opposed to the upper portion of the drift layer 22, the base layer 23, and the base contact layer 24 via the FP insulating film 32. Thus, the charge of the ionized donor in the drift layer 22 is compensated, so that the carrier concentration of the drift layer 22 can be increased, the source-drain withstand voltage in the semiconductor device 1 can be increased, and the on-resistance can be reduced.

[0037] The plurality of FP electrodes 14 and the plurality of contact layers 26 are alternately arranged along the W direction (third direction) which is parallel to the XY plane including the X direction and the Y direction and intersects the X direction and the Y direction. When the shape of the region R is a square, the W direction is a direction inclined by 45° with respect to the X direction and the Y direction.

[0038] At the lower part of the side surface of the recessed portion 20d, a part of the side surface of the source contact 12d is in contact with the drift layer 22. Thus, the lower layer 12a of the source electrode 12 forms a Schottky barrier junction with the drift layer 22. As a result, a Schottky barrier diode S is realized at the portion Rc when viewed from above.

[0039] Next, the operation of this embodiment will be described.

[0040] like Figure 1 As shown, in the semiconductor device 1 according to the present embodiment, an FP electrode 14 is disposed at the center of each region R. The FP electrode 14 compensates the charge of the ionized donor in the drift layer 22, thereby increasing the carrier concentration of the drift layer 22, improving the withstand voltage of the semiconductor device 1, and reducing the on-resistance.

[0041] In addition, in the present embodiment, the gate electrode 13 is not arranged in the portion Rc farthest from the FP electrode 14 in the boundary line of the region R, that is, the corner of each region R, but the source contact 12d is arranged. The lower layer 12a of the source contact 12d is formed of a material that forms a Schottky barrier junction with the drift layer 22. Thus, the source contact 12d arranged at the portion Rc of the source electrode 12 forms a Schottky barrier junction with the drift layer 22. As a result, a Schottky barrier diode S can be realized at the portion Rc.

[0042] Next, the effects of this embodiment will be described.

[0043] In this embodiment, by configuring the source contact 12d at the portion Rc farthest from the FP electrode 14 in the boundary line of the region R, it is possible to avoid a decrease in the withstand voltage at the portion Rc and improve the withstand voltage of the semiconductor device 1. In other words, it is possible to ensure the required withstand voltage of the semiconductor device 1, increase the carrier concentration of the drift layer 22, and reduce the on-resistance.

[0044] Generally speaking, increasing the withstand voltage and reducing the on-resistance are in a trade-off relationship, but according to this embodiment, the balance between the two can be improved. Therefore, it is possible to increase the withstand voltage while keeping the on-resistance constant according to the characteristics required of the semiconductor device 1, or to reduce the on-resistance while keeping the withstand voltage constant, or to achieve both increasing the withstand voltage and reducing the on-resistance.

[0045] In addition, in the semiconductor device 1, an SBD is provided in the portion Rc. Since the SBD has a lower forward voltage than a pn junction diode, the recovery loss (Qrr) of the parasitic diode can be reduced.

[0046] As described above, in this embodiment, in order to avoid a decrease in withstand voltage, the gate electrode 13 is not configured at the portion Rc. Therefore, the portion Rc becomes a dead zone for the MOSFET. In this embodiment, the dead zone is flexibly utilized as an SBD. Thus, compared with the case where the SBD portion is provided separately from the MOSFET portion, the area ratio of the MOSFET portion in the semiconductor device 1 can be increased, and the on-resistance can be reduced.

[0047] In addition, in this embodiment, an example in which the shape of the region R when viewed from above is a square is shown, but the present invention is not limited thereto. The shape of the region R can be any shape that can be filled without gaps, for example, it can also be a polygon, for example, it can also be a quadrilateral. The shape of the region R can also be an equilateral triangle or a regular hexagon.

[0048] In addition, in this embodiment, an example is shown in which the gate electrode 13 is continuously arranged by the portion 13x, the portion 13y, and the frame-shaped portion 13z, but the present invention is not limited thereto. The gate electrode 13 only needs to be not arranged at the position farthest from the FP electrode 14 in the region R. For example, when the portions 13x and 13y are connected to the gate pad via upper wiring, the frame-shaped portion 13z may not be provided.

[0049] Furthermore, in this embodiment, an example of a two-layer structure in which the source electrode 12 is stacked with the lower layer 12a and the upper layer 12b is shown, but the present invention is not limited thereto. At least the portion of the source electrode 12 that is in contact with the drift layer 22 only needs to be formed of a material that forms a Schottky barrier junction with the drift layer 22. For example, the entire source electrode 12 may be formed of a material that forms a Schottky barrier junction with the drift layer 22.

[0050] <Comparative Example>

[0051] Figure 5 It is a plan view showing a semiconductor device according to this comparative example.

[0052] like Figure 5 As shown, in the semiconductor device 101 according to the comparative example, the gate electrode 13 is also arranged at the portion Rc farthest from the FP electrode 14 on the boundary line of the region R.

[0053] The distance D between the portion 13c arranged at the portion Rc of the gate electrode 13 and the center 14c of the FP electrode 14 is the longest distance among the distances between the gate electrode 13 and the center 14c of the FP electrode 14. Therefore, in the portion 13c, the effect of relaxing the electric field concentration by the FP electrode 14 is poor, and the withstand voltage is low. As a result, the withstand voltage of the semiconductor device 101 is lower than that of the semiconductor device 1. If the semiconductor device 101 is to achieve the same level of withstand voltage as the semiconductor device 1, the carrier concentration of the drift layer 22 needs to be reduced, and the on-resistance becomes higher.

[0054] In addition, since no SBD is provided in the semiconductor device 101, the recovery loss (Qrr) of the parasitic diode is large. Although the SBD part can be provided separately from the MOSFET part, in this case, the area ratio of the MOSFET part in the semiconductor device 101 becomes small, and the on-resistance increases.

[0055] According to the above-described embodiments, a semiconductor device capable of improving the withstand voltage and reducing the on-resistance can be realized.

[0056] Several embodiments of the present invention are described above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope or spirit of the invention and are included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device, wherein: have: 1st electrode; a first semiconductor layer of a first conductivity type, provided on the first electrode, having a plurality of regions, and connected to the first electrode; a second semiconductor layer of a second conductivity type, disposed on the first semiconductor layer; a third semiconductor layer of the first conductivity type, disposed on a portion of the second semiconductor layer; a second electrode disposed in each of the plurality of regions and facing the first semiconductor layer via an insulator; a third electrode disposed along a boundary line between adjacent regions, and not disposed at a portion of the boundary line farthest from the second electrode, and facing the second semiconductor layer via an insulator; as well as The fourth electrode is provided on the third semiconductor layer and is connected to the second semiconductor layer, the third semiconductor layer and the second electrode, and a portion of the fourth electrode arranged at the farthest portion forms a Schottky barrier junction with the first semiconductor layer.

2. The semiconductor device according to claim 1, wherein: The shape of the region is a polygon, The farthest parts are corners of the polygon.

3. The semiconductor device according to claim 1, wherein: The shape of the area is a square.

4. The semiconductor device according to claim 1, wherein: Also available: The fourth semiconductor layer of the second conductivity type is provided at the farthest portion and is in contact with the first semiconductor layer and the fourth electrode.

5. The semiconductor device according to claim 4, wherein: The plurality of second electrodes are arranged in a matrix along a first direction and a second direction orthogonal to the first direction. The plurality of second electrodes and the fourth semiconductor layer are alternately arranged along a third direction intersecting the first direction and the second direction.

6. The semiconductor device according to claim 1, wherein: The third electrode surrounds the second electrode.

7. The semiconductor device according to claim 1, wherein: The fourth electrode has: a first metal layer, forming a Schottky barrier junction with the first semiconductor layer; and The second metal layer is provided on the first metal layer.

8. The semiconductor device according to claim 7, wherein: The first metal layer includes one or more metals selected from the group consisting of titanium, nickel, platinum, and tungsten. The second metal layer includes one or more metals selected from the group consisting of aluminum and copper.

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