Semiconductor device and method of manufacturing the same

Abstract

The present application relates to a semiconductor device and a manufacturing method thereof, including: forming a first gate structure, a second gate structure and an interlayer dielectric layer on a substrate, the interlayer dielectric layer covering the substrate on both sides of the first gate structure and the substrate on both sides of the second gate structure, the width of the cross-section of the first gate structure in the direction perpendicular to the surface of the substrate being greater than the width of the cross-section of the second gate structure in the direction perpendicular to the surface of the substrate, and the surface of the first gate structure being higher than the surface of the second gate structure; forming a surface filling layer covering the surfaces of the first gate structure and the second gate structure on the interlayer dielectric layer; thinning the surface filling layer to expose the first gate structure; and etching the first gate structure to make the surface of the first gate structure flush with the surface of the second gate structure. The present application reduces or eliminates the height difference between the first gate structure and the second gate structure, and increases the process window of subsequent process steps.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In the planarization process (Chemical Mechanical Polishing, CMP) of the interlayer dielectric layer (Inter Layer Dielectric, ILD), due to the different grinding rates of different materials, and the different grinding rates corresponding to the portions with different pattern densities in the interlayer dielectric layer, the grinding rate corresponding to the portion with a large-sized gate in the interlayer dielectric layer is slower, resulting in a higher gate height at the large-sized gate, thus causing a height difference between the large-sized gate and the surrounding structures, and even seriously affecting the process window (Windows) of subsequent processes in severe cases. Summary of the Invention

[0003] Based on this, it is necessary to provide a semiconductor device and a manufacturing method thereof to reduce the height difference between different gate structures in the interlayer dielectric layer.

[0004] In a first aspect, the present application provides a manufacturing method of a semiconductor device, including:

[0005] Providing a substrate, on which a first gate structure, a second gate structure, and an interlayer dielectric layer are formed, wherein the interlayer dielectric layer covers the substrates on both sides of the first gate structure and the substrates on both sides of the second gate structure, the width of the cross-section of the first gate structure in the direction perpendicular to the surface of the substrate is greater than the width of the cross-section of the second gate structure in the direction perpendicular to the surface of the substrate, and the surface of the first gate structure is higher than the surface of the second gate structure;

[0006] Forming a surface filling layer on the interlayer dielectric layer, the surface filling layer covering the surface of the first gate structure and the surface of the second gate structure;

[0007] Thinning the surface filling layer to expose the first gate structure;

[0008] Etching the first gate structure to make the surface of the first gate structure flush with the surface of the second gate structure.

[0009] In one embodiment, after etching the first gate structure, the manufacturing method of the semiconductor device further includes:

[0010] Removing the remaining surface filling layer.

[0011] In one embodiment, the material of the surface filling layer includes a photosensitive material with a dielectric constant between 3.0 and 5.0.

[0012] In one embodiment, the material of the surface filling layer includes a polyimide material.

[0013] In one embodiment, the surface filling layer is formed by a spin coating process.

[0014] In one embodiment, the surface filling layer is exposed to light to remove the remaining surface filling layer.

[0015] In one embodiment, the formation process of the first gate structure, the second gate structure, and the interlayer dielectric layer includes:

[0016] A gate material layer is formed on the substrate;

[0017] A gate dielectric layer is formed on the gate material layer;

[0018] The gate material layer and the gate dielectric layer are patterned to form the first gate structure and the second gate structure;

[0019] An interlayer dielectric layer is formed on the substrate, and the interlayer dielectric layer extends and covers the first gate structure and the second gate structure;

[0020] The interlayer dielectric layer is planarized to expose the first gate structure and the second gate structure.

[0021] In one embodiment, the polishing rate of the gate dielectric layer during the planarization process is less than the polishing rate of the interlayer dielectric layer during the planarization process.

[0022] In one embodiment, the planarization process is performed by a chemical mechanical polishing process.

[0023] In a second aspect, the present application also provides a semiconductor device, which is prepared by using the manufacturing method of the semiconductor device as described above.

[0024] An unexpected effect of the present application is that a surface filling layer is formed to cover the surfaces of the first gate structure and the second gate structure, the surface filling layer is thinned and the first gate structure is exposed, and then the first gate structure is etched to make the surface of the first gate structure flush with the surface of the second gate structure, thereby reducing or eliminating the height difference between the first gate structure and the second gate structure, so as to increase the process window of subsequent process steps. Description of the Drawings

[0025] To more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0026] Figure 1 The flowchart of the manufacturing method of the semiconductor device provided by an embodiment of the present application.

[0027] Figure 2 The schematic structural diagram corresponding to the step of providing a substrate in the manufacturing method of the semiconductor device provided by an embodiment of the present application, with a first gate structure, a second gate structure, and an interlayer dielectric layer formed on the substrate.

[0028] Figure 3 The schematic structural diagram corresponding to the step of planarizing the interlayer dielectric layer in the manufacturing method of the semiconductor device provided by an embodiment of the present application.

[0029] Figure 4 The schematic structural diagram corresponding to the step of forming a surface filling layer on the interlayer dielectric layer in the manufacturing method of the semiconductor device provided by an embodiment of the present application.

[0030] Figure 5 The schematic structural diagram corresponding to the step of thinning the surface filling layer in the manufacturing method of the semiconductor device provided by an embodiment of the present application.

[0031] Figure 6 The schematic structural diagram corresponding to the step of etching the first gate structure in the manufacturing method of the semiconductor device provided by an embodiment of the present application.

[0032] Figure 7 The schematic structural diagram corresponding to the step of removing the surface filling layer in the manufacturing method of the semiconductor device provided by an embodiment of the present application.

[0033] Explanation of reference numerals: 100 - substrate; 101 - gate material layer; 102 - gate dielectric layer; 110 - interlayer dielectric layer; 120 - surface filling layer; G1 - first gate structure; G2 - second gate structure. Detailed implementation manners

[0034] To facilitate the understanding of the present application, the following will describe the present application more comprehensively with reference to the relevant accompanying drawings. Embodiments of the present application are given in the accompanying drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the description of this application herein are for the purpose of describing particular embodiments only and are not intended to limit this application.

[0036] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Thus, without departing from the teachings of this application, the first element, component, region, layer, doping type or part discussed below may be denoted as the second element, component, region, layer or part; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types. For example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0037] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0038] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising", "has / including", etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0039] Figure 1 The flowchart of the manufacturing method of the semiconductor device provided by an embodiment of the present application. Refer to Figure 1 In one embodiment of the present application, the manufacturing method of the semiconductor device includes steps S01 to S04.

[0040] Step S01: Provide a substrate, on which a first gate structure, a second gate structure and an interlayer dielectric layer are formed. Wherein, the interlayer dielectric layer covers the substrate on both sides of the first gate structure and the substrate on both sides of the second gate structure. The width of the cross-section of the first gate structure in the direction perpendicular to the surface of the substrate is greater than the width of the cross-section of the second gate structure in the direction perpendicular to the surface of the substrate, and the surface of the first gate structure is higher than the surface of the second gate structure.

[0041] Refer to Figure 2 In one embodiment, the width of the cross-section of the first gate structure G1 in the direction perpendicular to the surface of the substrate 100 is D1, and the width of the cross-section of the second gate structure G2 in the direction perpendicular to the surface of the substrate 100 is D2. And the width D1 of the first gate structure G1 is greater than the width D2 of the second gate structure G2, that is, D1>D2. Therefore, the graphic size corresponding to the first gate structure G1 is also significantly larger than the graphic size corresponding to the second gate structure G2. Correspondingly, since the graphic density is smaller when the graphic size is larger, the pattern density corresponding to the first gate structure G1 is significantly smaller than the pattern density corresponding to the second gate structure G2.

[0042] Refer to Figure 3, in one embodiment, an interlayer dielectric layer 110 is typically deposited on the first gate structure G1, the second gate structure G2, and the substrate 100 first, and then the interlayer dielectric layer 110 is planarized to expose the first gate structure G1 and the second gate structure G2. Since there are differences in the polishing rates of regions with different pattern densities in the interlayer dielectric layer 110, there are differences in the polishing rates corresponding to the regions where the first gate structure G1 is located and the regions where the second gate structure G2 is located. Since the pattern density corresponding to the first gate structure G1 is significantly smaller than the pattern density corresponding to the second gate structure G2, the polishing rate corresponding to the region where the first gate structure G1 is located is less than the polishing rate corresponding to the region where the second gate structure G2 is located.

[0043] It should be noted that the polishing rate corresponding to the region where the first gate structure G1 is located is less than the polishing rate corresponding to the region where the second gate structure G2 is located. Therefore, when a part of the interlayer dielectric layer 110 above the second gate structure G2 is completely polished and the surface of the second gate structure G2 is exposed, a part of the interlayer dielectric layer 110 above the first gate structure G1 may not be completely removed yet; then, during the continuous planarization process until a part of the interlayer dielectric layer 110 above the first gate structure G1 is also completely removed and the surface of the first gate structure G1 is exposed, at most a part of the structure of the second gate structure G2 far from the substrate 100 will also be removed during the planarization process. At this time, the height of the remaining second gate structure G2 (i.e., the cross-sectional height H2 of the second gate structure G2 along the direction perpendicular to the surface of the substrate 100) is significantly less than the height of the first gate structure G1 (i.e., the cross-sectional height H1 of the first gate structure G1 along the direction perpendicular to the surface of the substrate 100), that is, H1 > H2.

[0044] However, the height difference between the first gate structure G1 and the second gate structure G2 will have a negative impact on subsequent process manufacturing. For example, the height difference between the first gate structure G1 and the second gate structure G2 will reduce the process window of subsequent processes, thereby affecting the performance and stability of semiconductor devices. Therefore, it is necessary to reduce or eliminate the height difference between the first gate structure G1 and the second gate structure G2 through steps S02 to S04.

[0045] Step S02: Form a surface filling layer on the interlayer dielectric layer, and the surface filling layer covers the surface of the first gate structure and the surface of the second gate structure.

[0046] Refer to Figure 4, in one embodiment, the surface filling layer 120 can be prepared from a material with good filling performance, leveling performance, and dielectric performance to ensure that the surface filling layer 120 can fill the relatively lower parts within the combined surface formed by the surfaces of the interlayer dielectric layer 110, the first gate structure G1, and the second gate structure G2, while having a high surface flatness (i.e., ensuring that the surface of the surface filling layer 120 has a high flatness). Optionally, the material of the surface filling layer 120 includes a photosensitive material with a dielectric constant between 3.0 and 5.0.

[0047] It should be noted that since the height H2 of the second gate structure G2 in step S02 is significantly smaller than the height H1 of the first gate structure G1, the surface filling layer 120 will preferentially fill the surface of the second gate structure G2 under the action of gravity; at the same time, since the surface filling layer 120 has high leveling performance, the surface of the finally formed surface filling layer 120 has high flatness and will not inherit the unevenness existing in the above combined surface.

[0048] Step S03: Thin the surface filling layer to expose the first gate structure.

[0049] Step S04: Etch the first gate structure to make the surface of the first gate structure flush with the surface of the second gate structure.

[0050] Refer to Figure 5 , in one embodiment, since the surface of the surface filling layer 120 is flat and the surface of the first gate structure G1 is higher than the surface of the second gate structure G2, the thickness of the surface filling layer 120 above the first gate structure G1 is less than the thickness of the surface filling layer above the second gate structure G2. During the thinning process of step S03, since the etching rate at each part of the surface filling layer 120 is the same, when the surface filling layer 120 above the first gate structure G1 is completely removed, there is still a part of the surface filling layer 120 covering above the second gate structure G2. Then, during the etching of the first gate structure G1, the surface filling layer 120 will also continue to be etched until the etching process ends when the surfaces of the first gate structure G1 and the second gate structure G2 are flush.

[0051] It should be noted that since the height of the first gate structure G1 is higher than the height of the second gate structure G2 after step S01, during the thinning process adopted in step S03, as the surface filling layer 120 is thinned, the first gate structure G1 will inevitably be exposed prior to the second gate structure G2. It can be seen that steps S03 and S04 can achieve the self-aligned etching process of the first gate structure G1 without preparing a mask, thereby saving the process cost and process time of preparing the mask and simplifying the process flow.

[0052] The manufacturing method of the semiconductor device as described above forms a surface filling layer to cover the surfaces of the first gate structure and the second gate structure, and then etches the surface filling layer and part of the first gate structure to make the surfaces of the first gate structure and the second gate structure flush, thereby reducing or eliminating the height difference between the first gate structure and the second gate structure, so as to increase the process window of subsequent process steps.

[0053] Continue to refer to Figure 2 , in one embodiment, the material of the substrate 100 is a silicon (Si) substrate, and an isolation trench structure (not labeled in the figure) is also formed in the substrate 100, and the isolation trench structure is formed in the substrate 100 on both sides of the first gate structure G1 and / or the second gate structure G2. In other embodiments of the present application, the material of the substrate 100 can also be silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, or other semiconductor materials formed of III / V compounds, etc. The substrate 100 can also be a stacked structure composed of the above semiconductor materials, or silicon on insulator, stacked silicon on insulator, silicon germanide on insulator, and germanium on insulator, etc. The material of the substrate 100 can be selected according to the type of semiconductor device, and the present application does not make specific limitations in this regard.

[0054] Refer to Figure 2 , in one embodiment, the formation process of the first gate structure G1, the second gate structure G2, and the interlayer dielectric layer 110 includes: forming a gate material layer 101 on the substrate 100; forming a gate dielectric layer 102 on the gate material layer 101; performing patterning on the gate material layer 101 and the gate dielectric layer 102 to form the first gate structure G1 and the second gate structure G2; forming an interlayer dielectric layer 110 on the substrate 100, and the interlayer dielectric layer 110 extends and covers the first gate structure G1 and the second gate structure G2; performing planarization on the interlayer dielectric layer 110 to expose the first gate structure G1 and the second gate structure G2. Optionally, lithography and etching processes are used to pattern the gate material layer 101 and the gate dielectric layer 102.

[0055] In one embodiment, the planarization is performed using a Chemical Mechanical Polishing (CMP) process. Continue to refer to Figure 2 and Figure 3, in one embodiment, the gate dielectric layer 102 is also polished during the planarization process, and the polishing rate of the gate dielectric layer 102 is less than that of the interlayer dielectric layer 110 during the planarization process, so as to reduce the thickness of the gate dielectric layer 102 removed during the planarization process, thereby reducing the height difference between the first gate structure G1 and the second gate structure G2. Optionally, the material of the gate dielectric layer 102 includes silicon nitride, and the material of the interlayer dielectric layer 110 includes silicon oxide.

[0056] Refer to Figure 4 , in one embodiment, the material of the surface filling layer 120 includes polyimide material (Polyimide). Since the polyimide material has good dielectric properties, filling properties and leveling characteristics, the surface filling layer 120 prepared from the polyimide material can well fill the combined surface formed by the surfaces of the first gate structure G1, the second gate structure G2 and the interlayer dielectric layer 110, and at the same time ensure the flatness of the surface of the surface filling layer 120 for subsequent process manufacturing. In one embodiment, the surface filling layer 120 is formed by a spin coating process to improve the surface flatness of the surface filling layer 120.

[0057] In other embodiments of the present application, other materials with good dielectric properties, filling properties and leveling characteristics can also be selected to prepare the surface filling layer 120, as long as it is ensured that the surface filling layer 120 can fill and cover the above combined surface while maintaining the flatness of the surface of the surface filling layer 120. The present application does not limit this.

[0058] Refer to Figure 5 , in one embodiment, a plasma etching process is used to thin the surface filling layer 120 to expose the first gate structure G1. Optionally, the process gas for the plasma etching process includes oxygen and a protective gas (the protective gas is usually an inert gas, such as helium). In other embodiments of the present application, other common process methods can also be used to thin the surface filling layer 120. The present application does not limit this.

[0059] Refer to Figure 6 , in one embodiment, a dry etching process is used to etch the first gate structure G1. Optionally, the process gas for the dry etching process includes carbon tetrafluoride (CF4) and a protective gas (the protective gas is usually an inert gas, such as helium). In other embodiments of the present application, other common process methods can also be used to etch the first gate structure G1. The present application does not limit this.

[0060] It should be noted that in the manufacturing method of the semiconductor device provided in this application, the part of the first gate structure G1 removed during the etching process corresponding to step S04 is the gate dielectric layer 102, and the part of the second gate structure G2 removed during the planarization process corresponding to step S01 is the gate dielectric layer 102. That is, after the planarization process and the etching process of the first gate structure G1, there is still a remaining gate dielectric layer 102 on the gate material layer 101 in the first gate structure G1 and the second gate structure G2 to ensure the normal function of the first gate structure G1 and the second gate structure G2, thereby improving the yield and stability of the semiconductor device.

[0061] In one embodiment, the height of the first gate structure G1 can be controlled by controlling the process time of the etching process in step S04, and the etching process is stopped when the surface of the first gate structure G1 is flush with the surface of the second gate structure G2. In other embodiments of this application, the stop timing of the etching process can be controlled by controlling other process parameters of the etching process in step S04, as long as it is ensured that the surface of the first gate structure G1 is flush with the surface of the second gate structure G2 after the etching ends.

[0062] Refer to Figure 6 , in one embodiment, since the surface filling layer 120 is not completely removed after etching the first gate structure G1, there is still a remaining surface filling layer 120 on the surface of the interlayer dielectric layer 110 and the second gate structure G2. Therefore, the manufacturing method of the semiconductor device proposed in this application further includes step S05.

[0063] Step S05: Remove the remaining surface filling layer.

[0064] Refer to Figure 7 , in one embodiment, when the surface filling layer 120 is a polyimide layer, the surface filling layer 120 can be exposed using I-line (I-Line) to remove the remaining surface filling layer 120, facilitating the smooth progress of subsequent processes. In other embodiments of this application, other photosensitive materials can also be used to form the surface filling layer 120 so as to remove the remaining surface filling layer 120 through exposure treatment.

[0065] This application also provides a semiconductor device prepared by using the manufacturing method of the semiconductor device as described above. Continue to refer to Figure 7, a semiconductor device prepared by the above-mentioned method for manufacturing a semiconductor device includes: a substrate 100, a first gate structure G1, a second gate structure G2, and an interlayer dielectric layer 110. Among them, the first gate structure G1 and the second gate structure G2 are both located on the substrate 100, and the surfaces of the first gate structure G1 and the second gate structure G2 are flush. The interlayer dielectric layer 110 is located on the substrate 100 on both sides of the first gate structure G1 and the second gate structure G2.

[0066] In one embodiment, both the first gate structure G1 and the second gate structure G2 include a gate material layer 101 located on the substrate 100 and a gate dielectric layer 102 located on the gate material layer 101. Optionally, the substrate 100 is, for example, a silicon substrate; the material of the gate dielectric layer 102 is, for example, silicon nitride; the material of the interlayer dielectric layer 110 is, for example, silicon oxide. In other embodiments of the present application, the materials of different film layers and structures in the semiconductor device can be selected according to actual needs, and the present application does not limit this.

[0067] It should be noted that since the surfaces of the first gate structure G1 and the second gate structure G2 are flush, the semiconductor device has a relatively large process window during subsequent process manufacturing, which helps to improve the yield and stability of the semiconductor device.

[0068] An unexpected effect of the present application is: forming a surface filling layer covering the surfaces of the first gate structure and the second gate structure, thinning the surface filling layer to expose the first gate structure, and then etching the first gate structure so that the surface of the first gate structure is flush with the surface of the second gate structure, thereby reducing or eliminating the height difference between the first gate structure and the second gate structure, so as to increase the process window of subsequent process manufacturing.

[0069] In the description of this specification, the description with reference to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials, or features described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0070] The technical features of the above-mentioned embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0071] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the scope of the application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, on which a first gate structure, a second gate structure and an interlayer dielectric layer are formed, wherein the interlayer dielectric layer covers the substrate on both sides of the first gate structure and the substrate on both sides of the second gate structure, the width of the cross section of the first gate structure along a direction perpendicular to the surface of the substrate is greater than the width of the cross section of the second gate structure along a direction perpendicular to the surface of the substrate, and the surface of the first gate structure is higher than the surface of the second gate structure; forming a surface filling layer on the interlayer dielectric layer, wherein the surface filling layer covers the surface of the first gate structure and the surface of the second gate structure, and the material of the surface filling layer is a photosensitive material; Thinning the surface filling layer to expose the first gate structure; Etching the first gate structure so that a surface of the first gate structure is flush with a surface of the second gate structure; The surface filling layer is exposed to light to remove the remaining surface filling layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the surface filling layer includes a material with a dielectric constant between 3.0 and 5.

0.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The material of the surface filling layer includes polyimide material.

4. The method for manufacturing a semiconductor device according to claim 2, wherein: The surface filling layer is formed by a spin coating process.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The formation process of the first gate structure, the second gate structure and the interlayer dielectric layer includes: forming a gate material layer on the substrate; forming a gate dielectric layer on the gate material layer; Performing patterning on the gate material layer and the gate dielectric layer to form the first gate structure and the second gate structure; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer extends to and covers the first gate structure and the second gate structure; The interlayer dielectric layer is planarized to expose the first gate structure and the second gate structure.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The grinding rate of the gate dielectric layer during the planarization process is lower than the grinding rate of the interlayer dielectric layer during the planarization process.

7. The method for manufacturing a semiconductor device according to claim 5, wherein: The planarization process is performed by using a chemical mechanical polishing process.

8. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 7.

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