Photodiode

Abstract

The invention provides a photodiode including a substrate and a semiconductor laminate. The substrate has a main surface. The semiconductor laminate is disposed on the main surface. The semiconductor laminate includes a buffer layer disposed on the main surface and a light absorbing layer disposed on the buffer layer. The light absorbing layer is formed of In < x > Ga < 1-x > As < y > P < 1-y >, wherein x and y are greater than 0 and less than 1. The buffer layer is formed of In < z > Ga < 1-z > As, wherein z is greater than 0 and less than 1.

Description

Technical Field

[0001] The present invention relates to photodiodes. Background Art

[0002] Japanese Patent Application Laid-Open No. 11-54785 discloses a light receiving element. Summary of the invention

[0003] An object of the present invention is to provide a photodiode with reduced dark current.

[0004] The photodiode of the present invention comprises a substrate and a semiconductor stack. The substrate has a main surface. The semiconductor stack is arranged on the main surface. The semiconductor stack includes a buffer layer arranged on the main surface and a light absorbing layer arranged on the buffer layer. The light absorbing layer is composed of In x Ga 1-x As y P 1-y Formed, x and y are greater than 0 and less than 1. The buffer layer is made of In z Ga 1-z As is formed, z is greater than 0 and less than 1.

[0005] The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 This is a schematic cross-sectional view of a photodiode according to an embodiment.

[0007] Figure 2 The photodiode of the embodiment is Figure 1 A schematic partial top view as viewed in the direction of arrow II shown.

[0008] Figure 3 This is a diagram showing the relationship between the lattice constant and the band gap energy of InGaAsP.

[0009] Figure 4 This is a schematic cross-sectional view showing one step of the method for manufacturing a photodiode according to the embodiment.

[0010] Figure 5 The method for manufacturing a photodiode according to the embodiment is shown in Figure 4 A schematic cross-sectional view of the process following the process shown.

[0011] Figure 6 The method for manufacturing a photodiode according to the embodiment is shown in Figure 5 A schematic cross-sectional view of the process following the process shown.

[0012] Figure 7The method for manufacturing a photodiode according to the embodiment is shown in Figure 6 A schematic cross-sectional view of the process following the process shown.

[0013] Figure 8 The method for manufacturing a photodiode according to the embodiment is shown in Figure 7 A schematic cross-sectional view of the process following the process shown.

[0014] Fig. 9 The method for manufacturing a photodiode according to the embodiment is shown in Figure 8 A schematic cross-sectional view of the process following the process shown.

[0015] Fig.10 The method for manufacturing a photodiode according to the embodiment is shown in Fig. 9 A schematic cross-sectional view of the process following the process shown.

[0016] Fig.11 The method for manufacturing a photodiode according to the embodiment is shown in Fig.10 A schematic cross-sectional view of the process following the process shown.

[0017] Fig.12 It is a diagram showing simulation results of the relationship between the bias voltage applied to the photodiode and the dark current of the photodiode.

[0018] Fig.13 This is a diagram showing simulation results of the relationship between the arsenic composition of the light absorbing layer and the dark current of the photodiode at a bias voltage of -1V.

[0019] Fig.14 FIG. 1 is a diagram showing a partial cross-sectional SEM photograph of the photodiode according to the first embodiment.

[0020] Fig.15 It is a figure which shows the SEM photograph of the partial cross section of the photodiode of the first comparative example.

[0021] Fig.16 It is a diagram showing an experimental example of the relationship between the bias voltage and the dark current of the photodiode in the photodiode of the example and the photodiode of the comparative example.

[0022] Fig.17 The figure shows the simulation result of the relationship between the distance between the edge of the opening of the insulating layer defining the p-type diffusion region and the side surface of the mesa structure and the dark current of the photodiode at a bias voltage of -1V. DETAILED DESCRIPTION

[0023] The details of the embodiments of the present invention are described based on the accompanying drawings. In addition, in the following drawings, the same reference numerals are used for the same or corresponding parts, and their description is not repeated. The structures of at least a part of the embodiments described below can also be arbitrarily combined.

[0024] Reference Figure 1 and Figure 2 A photodiode 1 according to an embodiment of the present invention will be described. The photodiode 1 includes a substrate 10 , a semiconductor stack 12 , a p-type contact layer 18 , an insulating layer 21 , an antireflection film 22 , an n-electrode 25 , a p-electrode 26 , and a conductive pad 27 .

[0025] The substrate 10 has a principal surface 10a and a principal surface 10b on the opposite side to the principal surface 10a. The principal surface 10a and the principal surface 10b are both end surfaces in the thickness direction of the substrate 10. The substrate 10 is, for example, a semiconductor substrate such as an InP substrate.

[0026] The semiconductor stack 12 is arranged on the main surface 10a of the substrate 10. The semiconductor stack 12 has a top surface 12a and a bottom surface 12b. The bottom surface 12b is in contact with the main surface 10a. The side surface 12s is connected to the top surface 12a and the bottom surface 12b. The semiconductor stack 12 includes a buffer layer 13, a light absorption layer 14 and a p-type doped diffusion region 16. The semiconductor stack 12 may also include a window layer 15. The semiconductor stack 12 includes a plurality of stacked semiconductor layers. For example, in the semiconductor stack 12, a buffer layer 13, a light absorption layer 14 and a window layer 15 are stacked.

[0027] The buffer layer 13 is arranged on the main surface 10a of the substrate 10. The buffer layer 13 is in contact with the substrate 10. The bottom surface of the buffer layer 13 is the bottom surface 12b of the semiconductor stack 12. The buffer layer 13 is, for example, an i-type semiconductor layer. The thickness of the buffer layer 13 is, for example, more than 10 nm. The thickness of the buffer layer 13 can be more than 100 nm. Therefore, the buffer layer 13 can reduce the crystal defects in the light absorbing layer 14 and make the top surface of the light absorbing layer 14 flatter. The thickness of the buffer layer 13 is smaller than the thickness of the light absorbing layer 14. The thickness of the buffer layer 13 is, for example, less than 1000 nm. The thickness of the buffer layer 13 can be less than 800 nm, less than 600 nm, less than 400 nm, or less than 200 nm. Therefore, the voltage drop in the buffer layer 13 can be reduced, and the reverse bias voltage applied to the light absorbing layer 14 can be increased.

[0028] The buffer layer 13 is made of In z Ga 1-z As is formed, and z is greater than 0 and less than 1. The buffer layer 13 is lattice matched with the substrate 10 (for example, an InP substrate). Figure 3As shown, by adjusting z, the buffer layer 13 can be lattice matched with the InP substrate. In this specification, the buffer layer 13 and the substrate 10 are lattice matched, which means that the difference between the lattice constant of the buffer layer 13 and the lattice constant of the substrate 10 is less than 0.1% of the lattice constant of the substrate 10.

[0029] The light absorbing layer 14 is disposed on the buffer layer 13. The light absorbing layer 14 is in contact with the buffer layer 13. The light absorbing layer 14 is separated from the substrate 10 by the buffer layer 13. The light absorbing layer 14 is, for example, an i-type semiconductor layer. The light absorbing layer 14 absorbs light incident on the photodiode 1. The photodiode 1 detects the intensity of the light.

[0030] The light absorbing layer 14 is made of In x Ga 1-x As y P 1-y The photodiode 1 is formed such that x and y are greater than 0 and less than 1. For example, x is greater than 0.70 and less than 1.00. x is determined according to the wavelength of light detected by the photodiode 1, that is, the wavelength of light absorbed by the light absorbing layer 14. The wavelength of light detected by the photodiode 1 is, for example, less than 1690 nm. The thickness of the light absorbing layer 14 is, for example, greater than 3000 nm and less than 5000 nm. The light absorbing layer 14 is lattice matched with the substrate 10 (for example, an InP substrate). Figure 3 As shown, by adjusting x and y, the band gap energy of the light absorbing layer 14 can be changed while the light absorbing layer 14 is lattice matched with the InP substrate. In this specification, the light absorbing layer 14 is lattice matched with the substrate 10 means that the difference between the lattice constant of the light absorbing layer 14 and the lattice constant of the substrate 10 is less than 0.1% of the lattice constant of the substrate 10.

[0031] The window layer 15 is arranged on the light absorbing layer 14. The window layer 15 may be, for example, an n-type semiconductor layer. The thickness of the window layer 15 may be, for example, greater than 100 nm and less than 2000 nm. The top surface of the window layer 15 may also be the top surface 12a of the semiconductor stack 12. The band gap energy of the window layer 15 is greater than the band gap energy of the light absorbing layer 14. The window layer 15 is transparent to the light detected by the photodiode 1. The band gap wavelength of the window layer 15 is shorter than the wavelength of the light detected by the photodiode 1. The window layer 15 is, for example, an n-InP layer.

[0032] The p-type doped diffusion region 16 is a region where a p-type dopant such as zinc (Zn) is diffused, and is a p-type semiconductor region. The p-type doped diffusion region 16 extends from the top surface 12a of the semiconductor stack 12 to the inside of the light absorbing layer 14. In the present embodiment, the p-type doped diffusion region 16 is formed by doping the light absorbing layer 14 and the window layer 15 with a p-type dopant. The p-type doped diffusion region 16 is connected to the light absorbing layer 14 and the window layer 15. The p-type doped diffusion region 16 is separated from the bottom surface 12b of the semiconductor stack 12.

[0033] The semiconductor stack 12 has a mesa structure 5. The side surface 12s of the semiconductor stack 12 is the side surface 5s of the mesa structure 5. In the present embodiment, the mesa structure 5 is formed in the window layer 15, the light absorbing layer 14, and the buffer layer 13. At least a portion of the side surface 12s of the semiconductor stack 12 may be the side surface 5s of the mesa structure 5. For example, the mesa structure 5 is not formed in the buffer layer 13, but the mesa structure 5 may be formed in the window layer 15 and the light absorbing layer 14.

[0034] The p-type contact layer 18 is arranged on the top surface 12a of the semiconductor stack 12. The p-type contact layer 18 is in contact with the p-type doped diffusion region 16. The p-type contact layer 18 is arranged in the opening 21a of the insulating layer 21. The p-type contact layer 18 is in contact with the insulating layer 21. The thickness of the p-type contact layer 18 is, for example, greater than 10 nm and less than 200 nm. The p-type contact layer 18 is, for example, a p-InGaAs layer. An opening 18a is provided in the p-type contact layer 18. The p-type doped diffusion region 16 is exposed from the p-type contact layer 18 in the opening 18a. The light detected by the photodiode 1 is incident on the light absorbing layer 14 through the opening 18a.

[0035] The insulating layer 21 is arranged on the semiconductor stack 12. The insulating layer 21 is in contact with the top surface 12a of the semiconductor stack 12. The thickness of the insulating layer 21 is, for example, greater than 10 nm and less than 500 nm. The insulating layer 21 is, for example, a silicon nitride layer. An opening 21a is provided in the insulating layer 21. When the main surface 10a is viewed from above, the opening 21a defines the p-type doped diffusion region 16. The insulating layer 21 functions as a mask for defining an injection region of a p-type dopant for the p-type doped diffusion region 16. When the main surface 10a is viewed from above, the minimum distance d2 between the edge of the opening 21a and the side surface 5s of the mesa structure 5 is greater than 20 μm. The minimum distance d2 can be greater than 30 μm, greater than 40 μm, or greater than 50 μm.

[0036] The anti-reflection film 22 reduces the reflectivity of light in the incident surface of the photodiode 1. The anti-reflection film 22 is arranged on the insulating layer 21, the p-type contact layer 18 and the semiconductor stack 12 (more specifically, the p-type doped diffusion region 16). The anti-reflection film 22 is, for example, an insulating layer. The anti-reflection film 22 is, for example, a silicon nitride layer. The anti-reflection film 22 is provided with a through hole 22a. The p-type contact layer 18 is exposed from the anti-reflection film 22 in the through hole 22a.

[0037] The n-electrode 25 is arranged on the main surface 10b of the substrate 10. The p-electrode 26 is arranged on the anti-reflection film 22, in the through hole 22a, and on the p-type contact layer 18 exposed from the through hole 22a. The p-electrode 26 is in contact with the p-type contact layer 18. The p-electrode 26 is electrically connected to the p-type doped diffusion region 16 through the p-type contact layer 18. When the main surface 10a is viewed from above, the p-electrode 26 has an outer edge 26e. The conductive pad 27 is arranged on the anti-reflection film 22 and connected to the p-electrode 26. The n-electrode 25, the p-electrode 26, and the conductive pad 27 are, for example, a stack of a titanium (Ti) layer, a platinum (Pt) layer, and a gold (Au) layer, and the gold layer is the outermost layer of the stack.

[0038] When the main surface 10a is viewed from above, the minimum distance d1 between the outer edge 26e of the p-electrode 26 and the side surface 5s of the mesa structure 5 is greater than 18 μm. The minimum distance d1 may be greater than 28 μm, greater than 38 μm, or greater than 48 μm. The minimum distance d1 between the outer edge 26e of the p-electrode 26 and the side surface 5s of the mesa structure 5 may be smaller than the minimum distance d2 between the edge of the opening 21a of the insulating layer 21 and the side surface 5s of the mesa structure 5. When the main surface 10a is viewed from above, the maximum distance d3 between the outer edge 26e of the p-electrode 26 and the edge of the opening 21a of the insulating layer 21 is less than 2 μm.

[0039] The operation of the photodiode 1 of the present embodiment is described. A reverse bias voltage is applied between the p-electrode 26 and the n-electrode 25. That is, a bias voltage is applied between the p-electrode 26 and the n-electrode 25 in such a manner that the potential of the n-electrode 25 is higher than the potential of the p-electrode 26. Light is incident on the light absorbing layer 14 through the opening 18a. Electrons and holes are generated in the light absorbing layer 14. Due to the reverse bias voltage, electrons move to the p-electrode 26 and holes move to the n-electrode 25. A photocurrent corresponding to the intensity of the light incident on the photodiode 1 is generated. Based on the photocurrent generated in the photodiode 1, the intensity of the light incident on the photodiode 1 is detected.

[0040] Reference Figures 4 to 11 , an example of a method for manufacturing the photodiode 1 according to the present embodiment will be described.

[0041] Reference Figure 4 , a buffer layer 13 is formed on the main surface 10a of the substrate 10. For example, on an InP substrate, a buffer layer 13 made of In is formed by an organic metal chemical vapor deposition (MOCVD) method. z Ga 1-z The buffer layer 13 is formed of As. The buffer layer 13 is lattice matched with the substrate 10 (eg, InP substrate).

[0042] On the buffer layer 13, the light absorbing layer 14 is formed by, for example, MOCVD. The light absorbing layer 14 is made of In xGa 1-x As y P 1-y x and y are greater than 0 and less than 1. For example, x is greater than or equal to 0.70 and less than 1.00. The light absorbing layer 14 is lattice-matched to the substrate 10 (for example, an InP substrate).

[0043] On the light absorbing layer 14, a window layer 15 is formed by, for example, MOCVD. The window layer 15 is, for example, an n-InP layer. In this way, the semiconductor stack 12 is formed on the main surface 10a of the substrate 10. The semiconductor stack 12 has a top surface 12a and a bottom surface 12b.

[0044] Reference Figure 4 The semiconductor layer 17 is formed on the top surface 12a (window layer 15) of the semiconductor stack 12 by, for example, MOCVD. The semiconductor layer 17 is formed on the top surface 12a (window layer 15) so as to be aligned with the p-type doped diffusion region 16 (see FIG. Figure 1 and Figure 2 The semiconductor layer 17 is formed of, for example, InGaAs.

[0045] Reference Figure 5 The semiconductor layer 17 is etched by dry etching such as reactive ion etching (RIE). In a plan view of the main surface 10a, a portion of the top surface 12a of the semiconductor stack 12 or a portion of the window layer 15 is exposed from the semiconductor layer 17.

[0046] Reference Figure 6 , a mesa structure 5 is formed on the semiconductor stack 12 (S8). Specifically, the buffer layer 13, the light absorbing layer 14, and the window layer 15 are etched by dry etching. The dry etching method is, for example, an RIE method using an etching gas such as a chlorine-based gas. Since the mesa structure 5 is formed by dry etching rather than wet etching, it is possible to prevent the side 5s of the mesa structure 5 from being over-etched. Therefore, when the main surface 10a is viewed from above, it is possible to prevent the side 5s of the mesa structure 5 from being too close to the p-type doped diffusion region 16 (see FIG. 1 ). Figure 1 and Figure 2 ) and the distance between the side surface 5s of the mesa structure 5 and the outer edge 26e of the p-electrode 26 (refer to Figure 1 and Figure 2 ) becomes too small.

[0047] Reference Figure 7, a p-type dopant is injected into the semiconductor stack 12 and the semiconductor layer 17 to form a p-type doped diffusion region 16 and a p-type contact layer 18. Specifically, an insulating layer 21 is formed on the top surface 12a of the semiconductor stack 12 or on the portion of the window layer 15 exposed from the semiconductor layer 17, for example, by a plasma CVD method. The semiconductor layer 17 is arranged in the opening 21a of the insulating layer 21. Then, using the insulating layer 21 as a mask, a p-type dopant such as zinc (Zn) is injected into the semiconductor layer 17, the window layer 15, and the light absorbing layer 14. The p-type dopant is doped into the semiconductor layer 17, the window layer 15, and the light absorbing layer 14 through the opening 21a of the insulating layer 21. By injecting the p-type dopant into the semiconductor layer 17, a p-type contact layer 18 is formed. By injecting the p-type dopant into the window layer 15 and the light absorbing layer 14, a p-type doped diffusion region 16 is formed.

[0048] Reference Figure 8 , an opening 18a is formed in the p-type contact layer 18. For example, the opening 18a is formed in the p-type contact layer 18 by an RIE method using an etching gas such as a chlorine-based gas. A portion of the p-type doped diffusion region 16 is exposed from the p-type contact layer 18 in the opening 18a.

[0049] Reference Fig. 9 An anti-reflection film 22 having a through hole 22a is formed on the insulating layer 21, the p-type contact layer 18, and the p-type doped diffusion region 16. For example, the anti-reflection film 22 is formed by a plasma CVD method. A portion of the anti-reflection film 22 is etched by a dry etching method such as an RIE method using an etching gas such as carbon tetrafluoride (CF4) gas, thereby forming the through hole 22a in the anti-reflection film 22. A portion of the p-type contact layer 18 is exposed from the anti-reflection film 22 through the through hole 22a.

[0050] Reference Fig.10 , forming a p-electrode 26 and a conductive pad 27 (refer to Figure 2 ). For example, a titanium (Ti) layer, a platinum (Pt) layer, and a gold (Au) layer are sequentially deposited to form the p-electrode 26 and the conductive pad 27. The p-electrode 26 is formed on the anti-reflection film 22, in the through hole 22a, and on the p-type contact layer 18 exposed from the through hole 22a. The conductive pad 27 is formed on the anti-reflection film 22 and is connected to the p-electrode 26.

[0051] Reference Fig.11 The main surface 10b of the substrate 10 is ground to make the substrate 10 thinner. Then, the n-electrode 25 is formed on the main surface 10b of the substrate 10. For example, the n-electrode 25 is formed by sequentially evaporating a titanium (Ti) layer, a platinum (Pt) layer, and a gold (Au) layer. In this way, Figure 1 and Figure 2 The photodiode 1 is shown.

[0052] The operation of the photodiode 1 of this embodiment will be described. The dark current of the photodiode 1 is reduced due to the following three reasons.

[0053] First, the light absorbing layer 14 is not formed of InGaAs but of InGaAsP. Figure 3 As shown in FIG. 1 , as the composition ratio of As in InGaAsP increases, the band gap energy of InGaAsP increases. The band gap energy of InGaAsP is greater than the band gap energy of InGaAs. Also, as the band gap energy of the light absorbing layer 14 increases, the reverse bias voltage (negative bias voltage V b ) generated by the minority carriers diffused into the depletion layer and the current reduction caused by the trap energy level in the depletion layer. The dark current I d Therefore, if Fig.12 and Fig.13 As shown, as the band gap energy of the light absorbing layer 14 increases, the dark current I d In addition, Fig.12 and Fig.13 The light absorbing layer 14 shown is lattice matched to the substrate 10 which is an InP substrate.

[0054] Second, the light absorbing layer 14 formed of InGaAsP is formed on the buffer layer 13 formed of InGaAs. Fig.14 As shown in FIG. 1 , the crystal defects in the light absorbing layer 14 are reduced, and the top surface of the light absorbing layer 14 becomes flat. Fig.15 As shown in FIG. 1 , in the comparative example in which the light absorbing layer 14 formed of InGaAsP is directly formed on the InP substrate, the light absorbing layer 14 has an InAs region that is not lattice-matched with the InP substrate, so the crystal defects of the light absorbing layer 14 increase. In addition, in the comparative example, the top surface of the light absorbing layer 14 becomes rough. The crystal defects and surface roughness of the light absorbing layer 14 increase the dark current I d Therefore, if Fig.16 As shown, by forming the light absorption layer 14 formed of InGaAsP on the buffer layer 13 formed of InGaAs, the dark current I d Reduce. Fig.16 , the dark current I of the photodiode 1 of the embodiment as an example of this embodiment d The dark current I of the photodiode of the comparative example is reduced to d one third of.

[0055] Third, when the principal surface 10a is viewed from above, the minimum distance d1 between the outer edge 26e of the p-electrode 26 and the side surface 5s of the mesa structure 5 is greater than 18 μm. Therefore, the distance between the outer edge 26e of the p-electrode 26 and the side surface 5s of the mesa structure 5 increases. When a reverse bias voltage (negative bias voltage V b ), the electric field is concentrated on the outer edge 26e of the p-electrode 26, and the outer edge 26e of the p-electrode 26 becomes a strong electric field region in the photodiode 1, but it is possible to prevent the strong electric field region in the photodiode 1 from reaching the side 5s of the mesa structure 5. Therefore, the dark current I d Reduce.

[0056] When the main surface 10a is viewed from above, the minimum distance d2 between the edge of the opening 21a of the insulating layer 21 and the side surface 5s of the mesa structure 5 is greater than 20 μm. Therefore, the distance between the p-type doped diffusion region 16 defined by the opening 21a of the insulating layer 21 and the side surface 5s of the mesa structure 5 increases. When a reverse bias voltage (negative bias voltage V b ), the p-type doped diffusion region 16 becomes a strong electric field region in the photodiode 1, but it is possible to prevent the strong electric field region in the photodiode 1 from reaching the side surface 5s of the mesa structure 5. Fig.17 As shown, the dark current I of photodiode 1 d On the other hand, when the minimum distance d2 between the edge of the opening 21a of the insulating layer 21 and the side 5s of the mesa structure 5 is 10 μm, the strong electric field region in the photodiode 1 reaches the side 5s of the mesa structure 5, as shown in FIG. Fig.17 As shown, the dark current I of photodiode 1 d Increase.

[0057] When the principal surface 10a is viewed from above, the maximum distance d3 between the outer edge 26e of the p-electrode 26 and the edge of the opening 21a of the insulating layer 21 is 2 μm or less. Therefore, the distance between the outer edge 26e of the p-electrode 26 and the side surface 5s of the mesa structure 5 and the distance between the p-type doped diffusion region 16 and the side surface 5s of the mesa structure 5 increase. When a reverse bias voltage (negative bias voltage V b ), it is possible to prevent the strong electric field region in the photodiode 1 from reaching the side surface 5s of the mesa structure 5. Therefore, the dark current I of the photodiode 1 d Reduce.

[0058] The effects of the photodiode 1 according to the present embodiment will be described.

[0059] The photodiode 1 of this embodiment includes a substrate 10 and a semiconductor stack 12. The substrate 10 has a main surface 10a. The semiconductor stack 12 is arranged on the main surface 10a of the substrate 10. The semiconductor stack 12 includes a buffer layer 13 arranged on the main surface 10a of the substrate 10 and a light absorbing layer 14 arranged on the buffer layer 13. The light absorbing layer 14 is made of In x Ga 1-x As y P 1-y The buffer layer 13 is formed by In z Ga 1-z As is formed, z is greater than 0 and less than 1.

[0060] The light absorbing layer 14 is not formed of InGaAs but of InGaAsP. And, the band gap energy of InGaAsP is larger than the band gap energy of InGaAs. In addition, the light absorbing layer 14 formed of InGaAsP is formed on the buffer layer 13 formed of InGaAs, so that the crystal defects in the light absorbing layer 14 are reduced, and the top surface of the light absorbing layer 14 becomes flat. Therefore, the dark current of the photodiode 1 is reduced.

[0061] In the photodiode 1 of the present embodiment, the substrate 10 is an InP substrate, and the light absorbing layer 14 and the buffer layer 13 are lattice matched to the InP substrate.

[0062] Therefore, crystal defects in the light absorbing layer 14 and the buffer layer 13 are reduced, and the dark current of the photodiode 1 is reduced.

[0063] In the photodiode 1 of the present embodiment, y is equal to or greater than 0.70 and less than 1.00.

[0064] Therefore, using the photodiode 1 , the intensity of light in the wavelength range of 1400 nm to 1690 nm can be detected with high accuracy.

[0065] The photodiode 1 of the present embodiment further includes a p-electrode 26. The semiconductor stack 12 further includes a p-type doped diffusion region 16 and has a mesa structure 5. The p-type doped diffusion region 16 is in contact with the light absorbing layer 14 and is electrically connected to the p-electrode 26. When viewed from above the main surface 10a of the substrate 10, the minimum distance d1 between the outer edge 26e of the p-electrode 26 and the side surface 5s of the mesa structure 5 is 18 μm or more.

[0066] Therefore, the distance between the outer edge 26e of the p-electrode 26 and the side 5s of the mesa structure 5 increases. When a reverse bias voltage is applied to the photodiode 1, the electric field is concentrated on the outer edge 26e of the p-electrode 26, and the outer edge 26e of the p-electrode 26 becomes a strong electric field region in the photodiode 1, but the strong electric field region in the photodiode 1 can be prevented from reaching the side 5s of the mesa structure 5. The dark current of the photodiode 1 is reduced.

[0067] The photodiode 1 of the present embodiment further includes an insulating layer 21 disposed on the semiconductor stack 12. An opening 21a is provided in the insulating layer 21. When viewed from above the main surface 10a of the substrate 10, the opening 21a of the insulating layer 21 defines the p-type doped diffusion region 16. When viewed from above the main surface 10a, the minimum distance d2 between the edge of the opening 21a of the insulating layer 21 and the side surface 5s of the mesa structure 5 is 20 μm or more.

[0068] Therefore, the distance between the p-type doped diffusion region 16 and the side surface 5s of the mesa structure 5 increases. When a reverse bias voltage is applied to the photodiode 1, the p-type doped diffusion region 16 becomes a strong electric field region in the photodiode 1, but the strong electric field region in the photodiode 1 can be prevented from reaching the side surface 5s of the mesa structure 5. The dark current of the photodiode 1 is reduced.

[0069] In the photodiode 1 of the present embodiment, the maximum distance d3 between the outer edge 26 e of the p-electrode 26 and the edge of the opening 21 a of the insulating layer 21 is 2 μm or less in a plan view of the principal surface 10 a of the substrate 10 .

[0070] Therefore, the distance between the outer edge 26e of the p-electrode 26 and the side 5s of the mesa structure 5 and the distance between the p-type doped diffusion region 16 and the side 5s of the mesa structure 5 are increased. When a reverse bias voltage is applied to the photodiode 1, it is possible to prevent the strong electric field region in the photodiode 1 from reaching the side 5s of the mesa structure 5. The dark current of the photodiode 1 is reduced.

[0071] Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

[0072] (Note 1)

[0073] A photodiode comprising:

[0074] a substrate having a main surface; and

[0075] a semiconductor stack disposed on the main surface,

[0076] The semiconductor stack includes: a buffer layer disposed on the main surface; and a light absorbing layer disposed on the buffer layer.

[0077] The light absorbing layer is composed of Inx Ga 1-x As y P 1-y Formation, x and y are greater than 0 and less than 1,

[0078] The buffer layer is composed of In z Ga 1-z As is formed, z is greater than 0 and less than 1.

[0079] (Note 2)

[0080] A photodiode as described in Appendix 1, wherein:

[0081] The substrate is an InP substrate,

[0082] The light absorbing layer and the buffer layer are lattice matched with the InP substrate.

[0083] (Note 3)

[0084] The photodiode as described in Appendix 1 or 2, wherein y is greater than or equal to 0.70 and less than 1.00.

[0085] (Note 4)

[0086] The photodiode according to any one of Supplement 1 to Supplement 3, wherein:

[0087] Also includes a p-electrode,

[0088] The semiconductor stack further includes a p-type doped diffusion region and has a mesa structure.

[0089] The p-type doped diffusion region is connected to the light absorbing layer and is electrically connected to the p-electrode.

[0090] When the main surface is viewed from above, a minimum distance between an outer edge of the p-electrode and a side surface of the mesa structure is 18 μm or more.

[0091] (Note 5)

[0092] A photodiode according to Appendix 4, wherein:

[0093] It also includes an insulating layer disposed on the semiconductor stack.

[0094] The insulating layer is provided with an opening,

[0095] In the plan view of the main surface, the opening defines the p-type doped diffusion region,

[0096] In the plan view of the main surface, a minimum distance between an edge of the opening and the side surface of the mesa structure is 20 μm or more.

[0097] (Note 6)

[0098] A photodiode as described in Appendix 5, wherein:

[0099] In the plan view of the main surface, a maximum distance between the outer edge of the p-electrode and the edge of the opening is 2 μm or less.

[0100] The embodiments disclosed this time should be considered as illustrative in all aspects and not restrictive. The scope of the present invention is indicated by the scope of the claims rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the scope of the claims.

Claims

1. A photodiode, characterized in that: include: a substrate having a main surface; and a semiconductor stack disposed on the main surface, The semiconductor stack includes: a buffer layer disposed on the main surface; and a light absorbing layer disposed on the buffer layer. The light absorbing layer is composed of In x Ga 1-x As y P 1-y Form, x and y are greater than 0 and less than 1, The buffer layer is composed of In z Ga 1-z As is formed, z is greater than 0 and less than 1.

2. The photodiode according to claim 1, characterized in that: The substrate is an InP substrate, The light absorbing layer and the buffer layer are lattice matched with the InP substrate.

3. The photodiode according to claim 1, characterized in that: The y is greater than or equal to 0.70 and less than 1.

00.

4. The photodiode according to any one of claims 1 to 3, characterized in that: Also includes a p-electrode, The semiconductor stack further includes a p-type doped diffusion region and has a mesa structure. The p-type doped diffusion region is connected to the light absorbing layer and is electrically connected to the p-electrode. When the main surface is viewed from above, a minimum distance between an outer edge of the p-electrode and a side surface of the mesa structure is 18 μm or more.

5. The photodiode according to claim 4, characterized in that: It also includes an insulating layer disposed on the semiconductor stack. The insulating layer is provided with an opening, In the plan view of the main surface, the opening defines the p-type doped diffusion region, In the plan view of the main surface, a minimum distance between an edge of the opening and the side surface of the mesa structure is 20 μm or more.

6. The photodiode according to claim 5, wherein: In the plan view of the main surface, a maximum distance between the outer edge of the p-electrode and the edge of the opening is 2 μm or less.

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