Dynamic random access memory (DRAM) row hammer mitigation

Abstract

An effect, referred to as a "row hammer", can be mitigated in a DRAM organized into two or more rows of sub-repositories. A sub-repository oriented row activation command may be detected. A number of row activation commands occurring within the refresh window may be counted and compared to a threshold. When it is detected that the number of row activation commands within the refresh window exceeds the threshold, additional refresh commands may be provided to the DRAM.

Description

[0001] Related technical description

[0002] Dynamic random access memory ("DRAM") may be included in a wide variety of computing devices. Maintaining data integrity in DRAM is an important consideration.

[0003] It has been observed that repeatedly activating one or more rows of a DRAM array within a single refresh window may compromise data integrity, i.e., may cause stored data to become corrupted. Repeatedly activating one or more rows of a DRAM array may cause one or more cells of physically adjacent rows to leak their stored charge, resulting in an increased probability of bit flips. This phenomenon is often referred to as "row hammering" or "row hammer" and can be exploited by an attacker to intentionally corrupt stored data.

[0004] A variety of row hammer mitigation methods have been developed. Some row hammer mitigation methods may throttle or limit the rate of row activations when rapid row activations are detected. Other row hammer mitigation methods may refresh potential victim rows when rapid row activations are detected. Row hammer mitigation methods may count the number of row activations that occur within a refresh window. A threshold number of row activations may be determined above which the probability of a bit flip is deemed unacceptably high, and mitigation may be applied when the count of row activations reaches the threshold. Improvements to row hammer mitigation are desired. Summary of the invention

[0005] Systems, methods, memory controllers, and other examples are disclosed for mitigating row hammer in dynamic random access memory (DRAM) systems.

[0006] An exemplary method may include: detecting a row activation command for a DRAM sub-bank. The DRAM array or bank may be organized into two or more sub-banks, each of which may include two or more rows of the bank. The exemplary method may also include: counting the number of row activation commands that occur within a window between a first refresh command and a second refresh command. The exemplary method may also include: comparing the counted number of row activation commands with a first threshold. The exemplary method may also include: providing an additional refresh command to the DRAM array within the window in response to detecting that the counted number of row activation commands exceeds the first threshold.

[0007] A system for mitigating row hammering may include command detection logic configured to detect a row activation command for a sub-bank of a DRAM. The system may also include activation command counting logic configured to count the number of row activation commands that occur within a window between a first refresh command and a second refresh command. The activation command counting logic may also be configured to compare the counted number of row activation commands to a threshold. The system may also include an additional refresh command generator configured to provide additional refresh commands to the DRAM array within the window in response to detecting that a first number of row activation commands exceeds a first threshold.

[0008] Another exemplary system for mitigating row hammering may include components for detecting a row activation command for a sub-bank of a DRAM. The exemplary system may also include components for counting a number of row activation commands occurring within a window between a first refresh command and a second refresh command and for comparing the counted number of row activation commands to a threshold. The exemplary system may also include components for providing additional refresh commands to the DRAM array within the window in response to detecting that the counted number of row activation commands exceeds a first threshold.

[0009] An exemplary memory controller may include a command generator logic element configured to generate a DRAM command in response to a memory transaction request. The DRAM command may include a row activation command and a refresh command. The exemplary memory controller may also include a command detection logic element configured to detect a row activation command for a DRAM-oriented sub-bank. The exemplary memory controller may also include an activation command counting logic element configured to count the number of row activation commands occurring within a window between a first refresh command and a second refresh command. The activation command counting logic element may also be configured to compare the counted number of row activation commands with a threshold value. The exemplary memory controller may also include an additional refresh command generator configured to provide an additional refresh command to the DRAM array within the window in response to detecting that a first number of row activation commands exceeds a first threshold value. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the drawings, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with letter character designations, such as "101A" or "101B", the letter character designation may distinguish between two similar parts or elements in the same figure. The letter character designation of a reference numeral may be omitted when it is intended that the reference numeral encompass all parts having the same reference numeral in all figures.

[0011] Figure 1 is a block diagram of a DRAM system and a client device according to an exemplary embodiment.

[0012] Figure 2 is a diagram similar to that of FIG. 1 showing the characteristics of a DRAM according to an exemplary embodiment. Figure 1 Block diagram of the .

[0013] Figure 3 is a flow chart illustrating a method for row hammer mitigation according to an exemplary embodiment.

[0014] Figure 4 is a block diagram illustrating a row hammer mitigation system in a memory controller according to an exemplary embodiment.

[0015] Figure 5 is a flow chart illustrating another method for row hammer mitigation according to an exemplary embodiment.

[0016] Figure 6 is a block diagram illustrating another row hammer mitigation system in a memory controller according to an exemplary embodiment.

[0017] Figure 7 is a block diagram illustrating a row hammer mitigation system with arbitration and pipeline logic in a memory controller according to an exemplary embodiment.

[0018] Figure 8 A DRAM array organized into sub-banks according to an exemplary embodiment is illustrated.

[0019] Fig. 9 is a block diagram illustrating a row hammer mitigation system configured to count activation commands on a sub-repository basis according to an exemplary embodiment.

[0020] Fig.10 Row address hashing in a DRAM array organized into sub-banks according to an exemplary embodiment is illustrated.

[0021] Fig.11 is a block diagram illustrating a row hammer mitigation system with row address hashing in a memory controller according to an exemplary embodiment.

[0022] Fig.12 is a block diagram of a portable computing device according to an exemplary embodiment. DETAILED DESCRIPTION

[0023] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." The word "exemplary" may be used herein synonymously with "exemplary." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0024] like Figure 1 As shown, in an exemplary or example embodiment, system 100 may include client device 102, memory controller 104, and one or more dynamic random access memory ("DRAM") arrays 106. As described below, memory controller 104 or, alternatively or additionally, DRAM array 106 may include features to mitigate the effects of a phenomenon often referred to as "row hammer."

[0025] Row hammer is a disturbance error that may cause data stored in the DRAM array 106 to be corrupted. Repeated activation of one or more rows 108, 110, etc. may cause cells in another row 112 that are physically adjacent to the one or more rows 108, 110, etc. to become corrupted. Figure 1 The charge stored in the cell (not separately shown) leaks the charge, thereby increasing the probability of a bit flip. That is, as a result of a row hammer attack, the probability that the bit value read from the cell is different from the bit value originally stored in the cell may increase. More specifically, a "1" stored before the row hammer attack may be incorrectly read as a "0" after the row hammer attack, or a "0" stored before the row hammer attack may be incorrectly read as a "1" after the row hammer attack. Rows 108, 110, etc. may be referred to as "aggressor" rows, and row 112 (represented in FIG. 1 for emphasis) may be incorrectly read as a "0" after the row hammer attack. Figure 1 108 and 110. In the illustrated example, victim row 112 is immediately adjacent to each of aggressor rows 108 and 110. In other examples of row hammer attacks, such victim rows may be adjacent to only one aggressor row. Although only three rows 108, 110, and 112 are shown for example, DRAM array 106 may have any number of rows, such as, for example, 16k, 32k, etc., as understood by one of ordinary skill in the art.

[0026] like Figure 2 As shown, system 200 may include client device 202, cache system 204, memory controller 206, and DRAM 208. Some or all of these elements may be included in a "system on a chip" or "SoC" that includes one or more types of processors, such as a central processing unit ("CPU"), a graphics processing unit ("GPU"), a digital signal processor ("DSP"), a neural processing unit ("NPU"), etc. Client device 202 may be implemented, for example, in a CPU (not separately shown) or an application processor. Although not shown in the figure for clarity, the client device 202 may be implemented in a CPU (not separately shown) or an application processor. Figure 2 , but the system 200 may be included in a computing device, such as, for example, a portable computing device. The system 200 may be the system 100 ( Figure 1 ) example.

[0027] The client device 202 may issue DRAM transaction requests, which may include read requests (i.e., requests to read data from the DRAM 208) and write requests (i.e., requests to store data in the DRAM 208). DRAM transaction requests may also be referred to as requests to access the DRAM 208. Each DRAM transaction request may include a target address in the DRAM 208, a size or amount of data to be accessed, and other information. A write request also includes data that the memory controller 206 will store in the DRAM 208 in response to the write request, which may be referred to as a payload.

[0028] However, for the features described herein with respect to row hammer mitigation, the structure and operation of memory controller 206 and DRAM 208 are well known to those of ordinary skill in the art. However, the following brief description is provided as background.

[0029] Among other functions, the memory controller 206 may convert transaction requests into DRAM commands ("Cmd") and physical DRAM addresses ("Addr"), and provide the commands and addresses to the DRAM 208. The memory controller 206 may queue the transaction requests and provide the associated commands and addresses to the DRAM 208 in a determined order using a scheduling algorithm. When providing the commands and addresses to the DRAM 208, the memory controller 206 may control the timing of such commands and addresses with respect to each other. As these aspects are well known to those of ordinary skill in the art, they are not described in further detail herein.

[0030] DRAM 208 can be any type that does not contradict the description herein. For example, DRAM 208 can be double data rate synchronous DRAM ("DDR-SDRAM"), sometimes referred to as "DDR". As DDR technology has evolved, DDR versions such as fourth-generation low-power DDR ("LPDDR4") and fifth-generation low-power DDR ("LPDDR5") have been developed. DRAM 208 may include, for example, LPDDR4, LPDDR4X, LPDDR5, LPDDR5X, etc. Yet another type of DDR includes graphics DDR ("GDDR"). Although in the examples described herein, DRAM 208 can be DDR, in other examples, such DRAM can be another type of low-power DRAM, such as SDRAM in a high-bandwidth memory ("HBM").

[0031] DRAM 208 may include two memory banks 210, which may be referred to as Rank_0 and Rank_1. Although two memory banks 210 are shown in this example, in other examples there may be only one memory bank or more than two memory banks. Since the two memory banks 210 are identical to each other, the following description applies to each memory bank 210. Memory bank 210 includes two or more ("M") memory banks 212, which may be referred to as Bank_0 to Bank_M-1. Each memory bank 212 is organized as a two-dimensional array 213 of cells or storage locations, where a storage location in array 213 is accessed by selecting a row and a column. The charge of a cell represents a stored data value, i.e., "1" or "0". Array 213 may be Figure 1 An example of array 106 is shown in a more conceptual form in FIG. Array 213 may have any number of rows, such as, for example, 16k, 32k, etc.

[0032] For illustration purposes, Figure 2 213 are highlighted with cross-hatching. In some examples, rows may also be referred to as word lines. Also, although not shown in FIG. Figure 2 2, DRAM 208 may be further organized into memory bank groups. For example, each memory bank 210 may be composed of four memory bank groups (not shown), and each of those memory bank groups may be composed of four memory banks. In such an example, DRAM 208 is therefore composed of 32 different (i.e., individually addressable) memory banks 212. Although Figure 2 In the illustrated example, DRAM 208 has two memory banks 210, each memory bank has four memory bank groups, and each of the four memory bank groups has four memory banks 212, but in other examples, such DRAM may be organized in any other manner, including more or fewer memory banks, memory banks, memory bank groups, etc. than in the illustrated example.

[0033] The physical address through which the memory controller 206 accesses the DRAM 208 may include a row address, a column address, a bank group address, and a bank address. Also, although not shown for clarity, in response to a bank address provided by the memory controller 206 (e.g., a chip select bit included in a read or write command), the bank address decoding logic may select one of the banks 210. Although also not shown for clarity, in response to a bank address provided by the memory controller 206, the bank address decoding logic may select one of the banks 212 in the selected bank group of the selected bank 210. In response to a row address provided by the memory controller 206, the row address decoder 214 may select a row in the rows of the selected bank 212 in the selected bank group in the selected bank 210. Similarly, in response to a column address provided by the memory controller 206, the column address decoder 216 may select one of the columns of the selected bank 212 in the selected bank group in the selected bank 210. Sequential row addresses may correspond to sequential row physical locations. That is, the row with address X+1 may be physically adjacent to the row with address X, and the row with address X-1 may similarly be physically adjacent to the row with address X. Figure 1 In the depicted example, victim row 112 may have address X, and aggressor rows 108 and 110 may have addresses X+1 and X-1. Sequential row addresses do not necessarily correspond to sequential row physical locations in all DRAMs, but may be used in conjunction with the DRAM. Figure 1 Such an example is shown in FIG. 1 to more clearly illustrate the hammer principle.

[0034] Each memory bank 210 may have a read latch 218 to buffer read data and a write latch 220 to buffer write data. Each memory bank 210 may also have input / output ("I / O") logic 222 configured to direct read data from selected memory locations and direct write data to selected memory locations.

[0035] Each memory bank 212 may have a row buffer 224. The row buffer 224 stores the contents of the selected row. The row must be selected or "opened" before it can be written or read. In response to an activate ("ACT") command, the DRAM 208 opens a row, that is, stores the contents of the row in the row buffer 224. Once the row is opened, the DRAM 208 can read from or write to any number of columns in the row buffer 224 in response to a read or write command (also known as a column address select ("CAS") command). After the read or write command, data is serially transmitted between the memory controller 206 and the DRAM 208 in units called "bursts", which can be, for example, eight bits per data signal line. The row must be restored or "closed" after writing to or reading from the row buffer 224. The DRAM 208 closes the row in response to a precharge ("PRE") command.

[0036] When converting a read request or a write request, the memory controller 206 determines the sequence and timing of one or more commands required to fulfill the request. The memory controller 206 also performs periodic refresh operations on all rows in all memory banks 212 of both banks 210 to maintain data integrity, and there are commands associated with such refresh operations, such as, for example, a per-bank refresh ("PBR") command.

[0037] A "refresh window" refers to a fixed amount of time ("tREFW") within which all rows of memory bank 212 must receive a refresh operation to maintain data integrity. Within each refresh window, a fixed number of refresh operations must be performed, such as, for example, 8192 (i.e., 8k) PBR operations to refresh all rows of memory bank 212. That is, in such an example, after 8192 PBR operations have been performed, all rows in memory bank 212 have been refreshed. A refresh window may be referred to as a sliding window because, although its length, tREFW, is fixed, a refresh window may occur at any time with respect to other DRAM-related signals.

[0038] As noted above, within each refresh window, there may be a threshold number of activations of an aggressor row above which the probability of a bit flip in a victim row is deemed unacceptably high. This threshold number of activations may be determined empirically and may vary based on factors such as the physical distance between adjacent rows, semiconductor process variations, temperature, etc. Similarly, a maximum activation count (“MAC_bank”) for a given memory bank 212 may be determined. MAC_bank is a threshold number of row activations of the same memory bank above which the probability of a bit flip in a victim row of that memory bank exceeds a threshold. As long as fewer than MAC_bank+1 activations occur within a sliding refresh window (i.e., within tREFW), the probability of a bit flip will not exceed this probability threshold. Stated conversely, when the (MAC_bank+1)th activation occurs within tREFW, the probability of a bit flip will exceed this threshold. Thus, a maximum or threshold number of row activations of the same memory bank (“MAC_ref”) may be defined, where MAC_ref is MAC_bank divided by the number of refresh operations required to refresh all rows of the memory bank 212. In the example where 8192 refresh operations are required to refresh all rows of memory bank 212, MAC_ref = MAC_bank / 8192.

[0039] According to one aspect of an exemplary method for mitigating row hammering, row activations of the same bank may be throttled so that MAC_ref is never exceeded. The number of row activations of the same bank within a refresh window may be counted and compared to a count threshold. For example, a counter may be incremented in response to each row activation command and reset in response to each refresh command.

[0040] exist Figure 3 , the method 300 is illustrated in flowchart form. As indicated by block 302, the method 300 may include: detecting the memory controller 206 ( Figure 2 ) issued in a memory controller. In embodiments where method 300 is performed in a memory controller, the row activation command issued in the memory controller may also be detected in the memory controller. However, in other embodiments, method 300 may be performed in another element, such as in the DRAM itself.

[0041] As indicated by block 304, method 300 may include: counting the number of row activation commands that occur within a refresh window (i.e., between a first refresh command and a second refresh command). For clarity, in this counting instance, the number of row activation commands may also be referred to as the "first" number of row activation commands. The first refresh command and the second refresh command may be consecutive. That is, in such examples, there is no intervening refresh command between the first refresh command and the second refresh command. Alternatively, in other examples of method 300, the first number of row activation commands may be the number of row activation commands counted between non-consecutive refresh commands.

[0042] As indicated by block 306, method 300 may include: comparing the first number of row activation commands with a threshold. For clarity, the threshold in this comparison instance may also be referred to as the "first" threshold. As indicated by block 308, method 300 may include: in response to detecting that the first number of row activation commands exceeds the first threshold, increasing the time gap between commands provided to the DRAM array. For example, the time gap between an ACT command and an associated CAS command may be increased.

[0043] In some examples, after the first increase (block 308) of the row activation time gap, method 300 may be repeated one or more additional times in an iterative manner. For example, according to block 304, the number of second row activation commands that occur within another refresh window between two other first refresh commands and a second refresh command may be counted. According to block 306, the sum of the first number and the second number of row activation commands may be compared with a second threshold. According to block 308, in response to detecting that the sum of the first number and the second number of row activation commands exceeds the second threshold, the time gap between some commands provided to the DRAM array may be further increased (i.e., increased to a time amount greater than the time amount to which the time gap was previously increased).

[0044] In an example of method 300, within a first sequence of P activation commands, consecutive activation commands may be spaced apart from each other by a first time interval (i.e., time gap), where P < MAC_ref. If it is determined after those P activation commands that the number of activation commands within the refresh window exceeds the first threshold, then within a second sequence of Q activation commands, consecutive activation commands may be spaced apart from each other by a second time interval that is greater than the first time interval, where P + Q <= MAC_ref. If it is determined after those Q activation commands that the number of activation commands within the refresh window exceeds the second threshold, then within a third sequence of R activation commands, consecutive activation commands may be spaced apart from each other by a third time interval that is greater than the second time interval, where P + Q + R <= MAC_ref, and so on.

[0045] In Figure 4, a memory controller portion 402 including a hammer mitigation system 403 is illustrated in block diagram form. The memory controller portion 402 may be a memory controller 104 ( Figure 1 ) or memory controller 206 ( Figure 2 ) is an example of a portion of . Figure 4 Only logic elements related to the exemplary row hammer mitigation solution are shown; other memory controller portions, such as some conventional memory controller logic, are not shown for clarity. It should be understood that the memory controller 104 ( Figure 1 ) and 206( Figure 2 ) can be configured to operate in a conventional manner in addition to being configured to operate in accordance with the row hammer mitigation solution described herein. Such conventional memory controller operations and corresponding structural elements (i.e., hardware or other logic) are well known to those of ordinary skill in the art and therefore may not be described in detail herein.

[0046] The memory controller portion 402 may include a command generator 404 that receives commands from a client device ( Figure 4 The command generator 404 converts a transaction request (not shown) into a sequence of DRAM commands (including row activation commands). In addition to generating commands in response to transaction requests, the command generator 404 can also generate periodic refresh commands. Since such command generator 404 is well known to those of ordinary skill in the art, it will not be described in further detail herein.

[0047] The row hammer mitigation system 403 of the memory controller portion 402 may include a command detector 406. The command detector 406 may be configured to detect row activation ("ACT") commands and refresh commands generated by the command generator 404. The row hammer mitigation system 403 may also include a row activation command counter 408 coupled to the command detector 406. The row activation command counter 408 may maintain a count of row activation commands and increment the count in response to each detection of a row activation command by the command detector 406. The activation command counter 408 may reset the count in response to each detection of a refresh command by the command detector 406. The row activation command counter 408 may compare the count to a threshold (amount) and generate an indication when the count reaches the threshold.

[0048] The hammer mitigation system 403 may also include a timing controller 410. Figure 3 ), the timing controller 410 may adjust (e.g., increase) the number of commands sent from the memory controller to the DRAM array ( Figure 4As described above with respect to method 300, increasing the timing gap between, for example, an ACT command and a corresponding CAS command can throttle or slow down access to the DRAM array. Note that while command generator 404 and other logic (e.g., scheduling, pipelining, etc.) typically controls the timing of commands sent to the DRAM array, timing controller 410 can override or adjust that timing.

[0049] The hammer mitigation system 403 may include hardware logic, software logic, or any combination of the two. For example, the hammer mitigation system 403 may include a state machine, a processor logic configured by software or firmware, etc., as understood by one of ordinary skill in the art. The hammer mitigation system 403 may be configured to perform or control the above method 300 ( Figure 3 ). Elements of the row hammer mitigation system 403 may serve as components for performing or controlling aspects of the method 300 .

[0050] According to another aspect of the exemplary method for mitigating row hammering, additional refresh commands may be provided to the DRAM array when the number of row activations of the same memory bank reaches a threshold. The "additional" refresh commands may be refresh commands in addition to the periodic refresh commands generated by the command generator 404. Alternatively, the "additional" refresh commands may be provided by rescheduling a previously scheduled periodic refresh command to occur earlier.

[0051] exist Figure 5 , method 500 is illustrated in flowchart form. As indicated by block 502, method 500 may include detecting a row activation command. In embodiments where method 500 is performed in a memory controller, a row activation command issued in the memory controller may also be detected in the memory controller. However, in other embodiments, method 300 may be performed in another element, such as in the DRAM itself.

[0052] As indicated at block 504, method 500 may include counting the number of row activation commands that occur within a refresh window (i.e., between a first refresh command and a second refresh command). The first refresh command and the second refresh command may be consecutive. Alternatively, in other examples of method 500, the number of row activation commands between non-consecutive refresh commands may be counted.

[0053] As indicated at block 506, method 500 may include comparing the counted number of row activation commands that occurred within the refresh window to a threshold. As indicated at block 508, method 500 may include providing an additional refresh command to the DRAM array in response to detecting that the counted number of row activation commands exceeds the threshold. Note that the additional refresh command is provided to the DRAM array within the refresh window (i.e., before the aforementioned second refresh command). Thus, in the event that the count of the number of row activation commands does not reach the threshold, the row in the DRAM array is refreshed earlier than would otherwise be.

[0054] exist Figure 6 , a memory controller portion 602 including a hammer mitigation system 603 is illustrated in block diagram form. The memory controller portion 602 may include a command generator 604, which may be similar to the command generator 404 ( Figure 4 The row hammer mitigation system 603 of the memory controller portion 602 may include a command detector 606 and a row activation command counter 608, which may be similar to the command detector 406 and the row activation command counter 408 described above, respectively. Figure 4 The row hammer mitigation system 603 may also include an additional refresh command generator 610. The additional refresh command generator 610 may send an additional refresh command to the DRAM array ( ) in response to an indication from the row activation command counter 608 that the count has reached the threshold. Figure 6 Each time the count reaches the threshold (and therefore each time an additional refresh command is provided), the row activation command counter 608 may reset the count. Note that each time any type of refresh command occurs (including refresh commands that occur on a periodic basis), the row activation command counter 608 may reset the count. In yet other embodiments, the memory controller portion (not shown) may include the memory controller portion described above with respect to Figure 4 The timing controller 410 described above and Figure 6 Both additional refresh command generators 610 are described.

[0055] The hammer mitigation system 603 may include hardware logic, software logic, or any combination of the two. For example, the hammer mitigation system 603 may include a state machine, a processor logic configured by software or firmware, etc., as understood by those of ordinary skill in the art. The hammer mitigation system 603 may be configured to perform or control the above method 500 ( Figure 5 ).

[0056] Although in the illustrated embodiment, the above-mentioned hammer mitigation system 403 ( Figure 4 ) and 603( Figure 6) are included in the corresponding memory controller portions 402 and 602, but in other embodiments (not shown), such a row hammer mitigation system can be included in the DRAM itself. In such other embodiments, the DRAM can be coupled with a conventional memory controller.

[0057] exist Figure 7 , another example of a memory controller portion 702 is illustrated in block diagram form. Figure 7 In contrast, the memory controller portion 702 illustrates an example of a row hammer mitigation system 704 along with arbitration and pipeline logic that involves routing of DRAM commands to and from the row hammer mitigation system 704 to a DRAM (not shown).

[0058] The row hammer mitigation system 704 may include per-bank ACT counter logic 706. As described below with respect to features referred to as sub-banks, in other examples, such counter logic may count row activation commands per sub-bank (rather than per bank). The ACT counter logic 706 may be configured to detect an ACT (i.e., row activation) command. The row activation command may be directed to any of the banks of DRAM. The ACT counter logic 706 may include counters 706A, 706B, etc. to 706N, where the number of counters 706A to 706N is equal to the number of banks of DRAM. Figure 7 In the example shown, there are 16 counters 706A to 706N corresponding to 16 DRAM banks (not shown). However, in other examples, there may be any number of such counters corresponding to any number of DRAM banks. In the example shown, the 16 counters 706A to 706N may also be referred to as Bank_0 ACT counter to Bank_15 ACT counter, respectively. Each counter 706A to 706N maintains a count and increments the count when the ACT counter logic 706 detects a row activation command for the corresponding DRAM bank. The ACT counter logic 706 may include a comparator logic 708 that is configured to compare the count to a threshold value (i.e., a fixed number or constant).

[0059] The output of the comparator logic 708 may be coupled to a refresh rate modulator 710 and configured to provide an indication to the refresh rate modulator 710 when any of the counters 706 reaches a count equal to the threshold. The refresh rate modulator 710 may be configured to detect whether any of the comparator logic 708 provides such an indication to the refresh rate modulator 710, and if such an indication is detected, temporarily increase the rate at which a refresh command is issued to the DRAM device. The refresh rate modulator 710 may be coupled to a refresh interval timer 712. The refresh rate modulator 710 may be configured to signal the refresh interval timer 712 that a different refresh rate is applicable. The refresh interval timer may be coupled to a command generation logic 714, which may be configured to insert a refresh command into a command sequence given a programmed refresh rate. The refresh rate modulator 710 may be further configured to reset the refresh rate interval to its initial value when the comparator logic 708 reports that no counter exceeds the programmed threshold. The command generation logic 714 may be configured to generate additional refresh commands. As mentioned above, divided by the periodic mode (given by Figure 7 This additional refresh command is generated in addition to the refresh command generated by the source (not shown in the figure).

[0060] Figure 7 The remaining logic shown involves routing of DRAM commands to and from the row hammer mitigation system 704. The asynchronous input FIFO 716 may receive DRAM commands including read-related DRAM commands and write-related DRAM commands (by Figure 7 716). The read queue 718 and the write queue 720 may be coupled to the output of the asynchronous input FIFO 716. Commands associated with read requests and write requests are queued separately in the read queue 718 and the write queue 720, respectively. Arbitration logic elements 722 and 724 may be coupled to the outputs of the read queue 718 and the write queue 720, respectively. The arbitration logic elements 722 and 724 arbitrate the commands in the read queue 718 and the write queue 720, respectively, to determine what command to add to the pipelines 726 and 728 next based on priority and schedulability, respectively. Pipeline logic elements 726 and 728 may be coupled to the outputs of the arbitration logic elements 722 and 724, respectively. Pipeline logic elements 726 and 728 may be configured to align DRAM commands in a timely manner with respect to other signals and events. Further arbitration logic element 730 may be coupled to the outputs of the pipeline logic elements 728 and 730, and is configured to arbitrate between read-related commands and write-related commands. Further pipeline logic 732 may be coupled to the output of arbitration logic 730 .

[0061] The row hammer mitigation system 704 may be configured to receive DRAM commands from the output of the pipeline logic 732. The per-bank ACT counter 706 of the row hammer mitigation system 704 may be configured to detect ACT and refresh (i.e., PBR) commands. The output of the row hammer mitigation system 704 (which may include additional refresh commands that may be generated) may be coupled to yet further arbitration logic 734. The output of the pipeline logic 732 may also be coupled to the arbitration logic 734. The arbitration logic 734 may be configured to compare the additional refresh commands generated by the row hammer mitigation system 704 with the source (i.e., PBR) of read-related commands and write-related commands. Figure 7 In other words, the arbitration logic 734 forms a command stream that combines the additional refresh command with read-related commands and write-related commands, such as ACT, CAS, etc. Further pipeline logic 736 may be coupled to the output of the arbitration logic 734. The output of the pipeline logic 736 may be coupled to the DRAM (not shown). Figure 7 It should be understood that the above-described arrangement of various arbitration and pipeline logic elements is intended only as an example, and that other arrangements will be readily apparent to one of ordinary skill in the art in view of the teachings herein.

[0062] like Figure 8 As shown, DRAM array 802 may include any number of rows, such as, for example, 32 rows, which may be referred to as Row_0, Row_1, Row_2, etc. to Row_31 in the illustrated example. DRAM array 802 may represent one bank of DRAM. Figure 8 8, but the DRAM bank represented by DRAM array 802 may be one of a plurality of banks in the DRAM, as described above with respect to Figure 2Described. Conceptually, the DRAM array 802 may be organized into a plurality of sub-banks, each of which includes two or more rows. For example: a first sub-bank, Sub-bank_0, may include Row_0 to Row_8; a second sub-bank, Sub-bank_1, may include Row_7 to Row_16; a third sub-bank, Sub-bank_2, may include Row_15 to Row_24; and a fourth sub-bank, Sub-bank_3, may include Row_23 to Row_31. Note that in the illustrated example, the sub-banks overlap with each other: Row_7 and Row_8 are included in both Sub-bank_0 and Sub-bank_1; Row_15 and Row_16 are included in both Sub-bank_1 and Sub-bank_2; and Row_23 and Row_24 are included in both Sub-bank_2 and Sub-bank_3. That is, in the illustrated example, two rows of each sub-bank overlap with two rows of another sub-bank. However, in other examples, more than two rows of each sub-bank may overlap with more than two rows of another sub-bank. For example, in a DRAM array (not shown) having at least 32 rows, 16 rows of each sub-bank may overlap with 16 rows of another sub-bank. In one example, a DRAM array (not shown) may have 8k (i.e., 8192) rows organized into 256 sub-banks, each sub-bank consisting of 32 rows, and 16 rows of each sub-bank may overlap with 16 rows of another sub-bank.

[0063] like Fig. 9 As shown, a hammer mitigation system 904 may be provided, which is similar to the hammer mitigation system 704 described above ( Figure 7 ), except that the row hammer mitigation system 904 may include a per-sub-bank ACT counter logic 906. The per-sub-bank ACT counter logic 906 may count row activation commands per sub-bank (rather than per bank). For example, the per-sub-bank ACT counter logic 906 may include counters 906A, 906B, 906C, and 906D corresponding to Figure 8Four sub-memory banks in the example shown. Each counter 906A to 906D maintains a count and increments the count when the ACT counter logic 906 detects a row activation command for a row of the corresponding sub-memory bank. Other elements of the row hammer mitigation system 904 may be similar to the corresponding elements of the row hammer mitigation system 704 described above. Therefore, the comparator logic 908 may be configured to compare the count of activations for the sub-memory banks with a threshold. Similarly, the row hammer mitigation system 904 may include a refresh rate modulator 910, a refresh interval timer 912, and a command generation logic 914, and the configuration methods of the refresh rate modulator, the refresh interval timer, and the command generation logic are respectively the same as those described above with respect to the refresh rate modulator 710, the refresh interval timer 712, and the command generation logic 714 ( Figure 7 ) is configured in the same manner as described above. The hammer mitigation system 904 may be included in the memory controller portion ( Fig. 9 ), as described above with respect to Figure 7 As described.

[0064] Correspondingly, in the above method 300 ( Figure 3 ) and 500( Figure 5 ), the number of counted row activations may be counted on a per-sub-repository basis (blocks 304 and 504). The number of row activations for each sub-repository within the refresh window may be counted and compared to a threshold (blocks 306 and 506).

[0065] Counting row activations on a per-subbank basis (rather than a per-bank basis) can improve performance in benign cases (i.e., when the memory system is not under attack). When the memory system is not under attack, there is a high probability that row activations are scattered across the banks rather than concentrated around a specific (victim) row. When row activations are scattered across the banks rather than concentrated, a larger number of counters will be incremented during the refresh window, but at a lower rate than when row accesses are concentrated.

[0066] like Fig.10As shown, row hashing can be used to access the DRAM array 1002. As understood by one of ordinary skill in the art, "hashing" refers to applying a function that produces output data of a fixed size to input data. Another property of a hash function is that a small change in the input data results in a large change in the output data. Hashing has been conventionally used, for example, to spread memory accesses more evenly across multiple memory banks. In this use of hashing, the output of the hash function is a memory bank address. According to the present disclosure, a method for mitigating row hammering may include hashing (i.e., applying a hash function to) a row address associated with each row activation command, and providing the resulting hashed row address to the DRAM array 1002 in association with the row activation command rather than the original (pre-hashed) row address. Hashing the row address can help spread memory accesses over a larger number of rows. In examples where the DRAM array is organized into sub-memory banks (as described above with respect to Figures 8 to 9 As described above, hashing the row address can help spread memory accesses over a larger number of sub-memory banks.

[0067] exist Fig.10 In the example of row hashing shown, each row in Sub_bank_1 (i.e., in the range of Row_7 to Row_16) can be accessed. Each row access includes a row activation command and an associated (original) row address. The original row address is provided as input to a hash function (not shown), which produces a hashed row address as output. For example, Fig.10 As indicated by the arrows in , the hash function may generate: a hashed row address of Row_0 in response to the original row address of Row_7; a hashed row address of Row_10 in response to the original row address of Row_11; a hashed row address of Row_20 in response to the original row address of Row_8; a hashed row address of Row_31 in response to the original row address of Row_9; a hashed row address of Row_25 in response to the original row address of Row_10; and so on. Although Fig.10 Only five row accesses are illustrated in , but there may be any number of accesses to any row in any sub-repository. Fig.10 In the example shown, although all of the original row addresses are in Sub-bank_1, the hashed row addresses are spread among all of the sub-banks in Sub-bank_0, Sub-bank_1, Sub-bank_2, and Sub-bank_3.

[0068] exist Fig.11 , a memory controller portion 1102 including a hammer mitigation system 1103 is illustrated in block diagram form. The memory controller portion 1102 may include a command generator 1104, which may be similar to the command generator 404 described above ( Figure 4) or 604( Figure 6 The hammer mitigation system 1103 of the memory controller portion 1102 may be similar to the hammer mitigation system 403 described above ( Figure 4 ), the above-mentioned hammer relief system 603 ( Figure 6 ) or a combination of both. The row hammer mitigation system 1103 may also include a row hash logic 1106 configured to apply a row hash function to the original row address to obtain a hashed row address. Fig.11 The row hammer mitigation system 1103 may be configured to provide the DRAM (not shown) with the original row address directly or via one or more intermediate elements (such as, for example, memory mapping logic 1108). Fig.11 ) provides a hashed row address and an associated row activation command. Fig.11 In the illustrated example, the row address hashing logic 1106 is located after the output of the memory mapping logic 1108, but in another example (not shown), such row address hashing logic 1106 may be located elsewhere in the memory controller portion 1102, such as before the memory mapping logic 1108 (which may convert the physical address in the transaction request to a memory bank, memory bank, row, column, etc.), and may be configured to hash the physical address before the command generator 1104 generates any corresponding command for the transaction request.

[0069] Fig.12 An example of a portable computing device ("PCD") 1200 is illustrated in which exemplary embodiments of systems, methods, computer-readable media, and other examples of a hammer mitigation solution may be provided. The PCD 1200 may be, for example, a laptop or palmtop computer, a cellular or smartphone, a personal digital assistant, a navigation device, a smartbook, a portable game console, a satellite phone, etc. For clarity, Fig.12 Some data buses, interconnects, signals, etc. are not shown.

[0070] PCD 1200 may include SoC 1202. SoC 1202 may include a central processing unit ("CPU") 1204, a graphics processing unit ("GPU") 1206, a digital signal processor ("DSP") 1207, an analog signal processor 1208, a modem / modem subsystem 1254, or other processors. CPU 1204 may include one or more CPU cores, such as a first CPU core 1204A, a second CPU core 1204B, and so on to an Nth CPU core 1204N. CPU 1204 or a portion of the CPU may be the client device 102 ( Figure 1 ) or 202( Figure 2 ) example.

[0071] 1204. A display controller 1210 and a touch screen controller 1212 may be coupled to the CPU 1204. A touch screen display 1214 external to the SoC 1202 may be coupled to the display controller 1210 and the touch screen controller 1212. The PCD 1200 may also include a video decoder 1216 coupled to the CPU 1204. A video amplifier 1218 may be coupled to the video decoder 1216 and the touch screen display 1214. A video port 1220 may be coupled to the video amplifier 1218. A universal serial bus (“USB”) controller 1222 may also be coupled to the CPU 1204, and a USB port 1224 may be coupled to the USB controller 1222. A subscriber identity module (“SIM”) card 1226 may also be coupled to the CPU 1204.

[0072] One or more memories may be coupled to CPU 1204. The one or more memories may include both volatile memory and non-volatile memory. Examples of volatile memory include static random access memory ("SRAM") 1228 and dynamic random access memory ("DRAM") 1230 and 1231. Such memories may be located external to SoC 1202 (such as DRAM 1230) or internal to SoC 1202 (such as DRAM 1231). A DRAM controller 1232 coupled to CPU 1204 may control writing data to and reading data from DRAM 1230 and 1231. DRAM controller 1232 may be the memory controller 104 (described above). Figure 1 ) or 206( Figure 2 ) are examples of any one of the above. Therefore, the DRAM controller 1232 can be configured (eg, by software, firmware, hardware logic, etc.) as: including the above-mentioned memory controller portion 402 ( Figure 2 )、602( Figure 6 ) or 1102( Fig.11 ), and executing or controlling the above method 300 ( Figure 3 )、500( Figure 5 ) or any other method. DRAM 1230 or 1231 may have a structure similar to that of DRAM 208 ( Figure 2 ) structure.

[0073] A stereo audio codec 1234 may be coupled to the analog signal processor 1208. Further, an audio amplifier 1236 may be coupled to the stereo audio codec 1234. A first stereo speaker 1238 and a second stereo speaker 1240 may be coupled to the audio amplifier 1236, respectively. In addition, a microphone amplifier 1242 may be coupled to the stereo audio codec 1234, and a microphone 1244 may be coupled to the microphone amplifier 1242. A frequency modulation ("FM") radio tuner 1246 may be coupled to the stereo audio codec 1234. An FM antenna 1248 may be coupled to the FM radio tuner 1246. Further, a stereo headset 1250 may be coupled to the stereo audio codec 1234. Other devices that may be coupled to the CPU 1204 include one or more digital (e.g., CCD or CMOS) cameras 1252.

[0074] A modem or RF transceiver 1254 may be coupled to the analog signal processor 1208 and the CPU 1204. An RF switch 1256 may be coupled to the RF transceiver 1254 and the RF antenna 1258. In addition, a keypad 1260, a mono headset 1262 with a microphone, and a vibrator device 1264 may be coupled to the analog signal processor 1208.

[0075] SoC 1202 may have one or more internal or on-chip thermal sensors 1270A and may be coupled to one or more external or off-chip thermal sensors 1270B. Analog-to-digital converter controller 1272 may convert the voltage drop generated by thermal sensors 1270A and 1270B into a digital signal. Power source 1274 and power management integrated circuit (“PMIC”) 1276 may provide power to SoC 1202.

[0076] The firmware or software may be stored in any of the above memories, such as DRAM 1230 or 1231, SRAM 1228, etc., or may be stored in local memory that is directly accessible by the processor hardware on which the software or firmware is executed. The execution of such firmware or software may control aspects of any of the above methods or configure aspects of any of the above systems. Any such memory or other non-transitory storage medium having firmware or software stored therein in a computer-readable form for execution by processor hardware may be an example of a "computer-readable medium" as that term is understood in the patent dictionary.

[0077] Specific implementation examples are described in the following numbered clauses.

[0078] 1. A method, comprising:

[0079] detecting a row activation command directed to a sub-bank of a plurality of sub-banks, each sub-bank comprising a plurality of rows of a bank of a DRAM array;

[0080] counting a first number of the row activation commands occurring within a window between a first refresh command and a second refresh command;

[0081] comparing the first number of row activate commands to a first threshold; and

[0082] Additional refresh commands are provided to the DRAM array within the window in response to detecting that the first number of row activate commands exceeds the first threshold.

[0083] 2. The method of clause 1, wherein the plurality of rows of each sub-repository overlap with the plurality of rows of another sub-repository.

[0084] 3. A method according to clause 1 or 2, wherein at least 16 rows of each sub-repository overlap with at least 16 rows of another sub-repository.

[0085] 4. The method of any of clauses 1 to 3, wherein the first refresh command and the second refresh command are consecutive.

[0086] 5. The method of any one of clauses 1 to 4, further comprising: increasing a timing gap between consecutive commands provided to the DRAM array in response to detecting that the first number of row activation commands exceeds the first threshold.

[0087] 6. The method according to clause 5, further comprising, after increasing the timing gap:

[0088] counting a second number of row activation commands occurring within the window;

[0089] comparing a sum of the first number and the second number of row activation commands to a second threshold; and

[0090] The timing gap between consecutive commands provided to the DRAM array is further increased in response to detecting that the sum of the first number and the second number of row activate commands exceeds the second threshold.

[0091] 7. A method according to any one of clauses 1 to 6, further comprising: hashing an original row address associated with each row activation command, and providing the hashed row address instead of the original row address to the DRAM array in association with the row activation command.

[0092] 8. A system, comprising:

[0093] command detection logic configured to detect a row activation command directed to a sub-bank of a plurality of sub-banks, each sub-bank comprising a plurality of rows of a bank of a DRAM array;

[0094] an activate command counting logic configured to count a first number of the row activate commands occurring within a window between a first refresh command and a second refresh command and to compare the first number of row activate commands to a first threshold; and

[0095] An additional refresh command generator is configured to provide additional refresh commands to the DRAM array within the window in response to detecting that the first number of row activate commands exceeds the first threshold.

[0096] 9. The system of clause 8, wherein the multiple rows of each sub-repository overlap with the multiple rows of another sub-repository.

[0097] 10. A system according to clause 8 or 9, wherein at least 16 rows of each sub-repository overlap with at least 16 rows of another sub-repository.

[0098] 11. The system of any of clauses 8 to 10, wherein the first refresh command and the second refresh command are consecutive.

[0099] 12. The system of any one of clauses 8 to 11, further comprising a timing controller configured to increase a timing gap between consecutive commands provided to the DRAM array in response to detecting that the first number of row activation commands exceeds the first threshold.

[0100] 13. A system according to clause 12, wherein:

[0101] The activation command counting logic is further configured to count a second number of row activation commands occurring within the window after the timing interval is incremented; and

[0102] The timing controller is further configured to compare the sum of the first number and the second number of row activation commands with a second threshold, and to further increase the timing gap between consecutive commands provided to the DRAM array in response to detecting that the sum of the first number and the second number of row activation commands exceeds the second threshold.

[0103] 14. A system according to any one of clauses 8 to 13, wherein the system also includes a row address hashing logic element, which is configured to: hash an original row address associated with each row activation command, and provide the hashed row address instead of the original row address to the DRAM array in association with the row activation command.

[0104] 15. A system, comprising:

[0105] means for detecting a row activation command directed to a sub-bank of a plurality of sub-banks, each sub-bank comprising a plurality of rows of a bank of a DRAM array;

[0106] means for counting a first number of said row activate commands occurring within a window between a first refresh command and a second refresh command and for comparing said first number of row activate commands to a first threshold; and

[0107] Means for providing additional refresh commands to the DRAM array within the window in response to detecting that the first number of row activate commands exceeds the first threshold.

[0108] 16. The system of clause 15, wherein the plurality of rows of each sub-repository overlap with the plurality of rows of another sub-repository.

[0109] 17. A system according to clause 15 or 16, wherein at least 16 rows of each sub-repository overlap with at least 16 rows of another sub-repository.

[0110] 18. The system of any of clauses 15 to 17, wherein the first refresh command and the second refresh command are consecutive.

[0111] 19. The system of any of clauses 15 to 18, further comprising means for increasing a timing gap between consecutive commands provided to the DRAM array in response to detecting that the first number of row activate commands exceeds the first threshold.

[0112] 20. The system of clause 19, further comprising, after increasing the timing gap:

[0113] means for counting a second number of row activation commands occurring within said window;

[0114] means for comparing a sum of said first number and said second number of row activation commands to a second threshold value; and

[0115] means for further increasing the timing gap between consecutive commands provided to the DRAM array in response to detecting that the sum of the first number and the second number of row activate commands exceeds the second threshold.

[0116] 21. A system according to any one of clauses 15 to 20, the system further comprising a component for: hashing an original row address associated with each row activation command, and providing the hashed row address instead of the original row address to the DRAM array in association with the row activation command.

[0117] 22. A memory controller, the memory controller comprising:

[0118] a command generator logic element configured to generate a dynamic random access memory (DRAM) command in response to a memory transaction request, the DRAM command including a row activate command and a refresh command;

[0119] command detection logic configured to detect a row activation command directed to a sub-bank of a plurality of sub-banks, each sub-bank comprising a plurality of rows of a bank of a DRAM array;

[0120] an activate command counting logic configured to count a first number of the row activate commands occurring within a window between a first refresh command and a second refresh command and to compare the first number of row activate commands to a first threshold; and

[0121] An additional refresh command generator is configured to provide additional refresh commands to the DRAM array within the window in response to detecting that the first number of row activate commands exceeds the first threshold.

[0122] 23. The memory controller of clause 22, wherein the plurality of rows of each sub-bank overlap with the plurality of rows of another sub-bank.

[0123] 24. A memory controller as recited in clause 22 or 23, wherein the first refresh command and the second refresh command are consecutive.

[0124] 25. A memory controller according to any one of clauses 22 to 24, the memory controller further comprising a timing controller configured to increase a timing gap between consecutive commands provided to the DRAM array in response to detecting that the first number of row activation commands exceeds the first threshold.

[0125] 26. A memory controller as described in any of clauses 22 to 25, further comprising row address hashing logic configured to:

[0126] An original row address associated with each row activate command is hashed, and the hashed row address is provided to the DRAM array in association with the row activate command instead of the original row address.

[0127] Alternative embodiments will become apparent to those of ordinary skill in the art.Thus, while selected aspects have been illustrated and described in detail, it should be understood that various substitutions and changes may be made therein.

Claims

1. A method, comprising: detecting a row activation command directed to a sub-bank of a plurality of sub-banks, each sub-bank comprising a plurality of rows of a bank of a DRAM array; counting a first number of the row activation commands occurring within a window between a first refresh command and a second refresh command; comparing said first number of row activation commands to a first threshold; as well as Additional refresh commands are provided to the DRAM array within the window in response to detecting that the first number of row activate commands exceeds the first threshold. 2 . The method of claim 1 , wherein the multiple rows of each sub-repository overlap with the multiple rows of another sub-repository.

3. The method of claim 2, wherein at least 16 rows of each sub-repository overlap with at least 16 rows of another sub-repository. The method of claim 1 , wherein the first refresh command and the second refresh command are consecutive.

5. The method according to claim 1, further comprising: A timing gap between consecutive commands provided to the DRAM array is increased in response to detecting that the first number of row activate commands exceeds the first threshold.

6. The method according to claim 5, further comprising, after increasing the timing gap: counting a second number of row activation commands occurring within the window; comparing a sum of the first number and the second number of row activation commands to a second threshold; as well as The timing gap between consecutive commands provided to the DRAM array is further increased in response to detecting that the sum of the first number and the second number of row activate commands exceeds the second threshold.

7. The method according to claim 1, further comprising: An original row address associated with each row activate command is hashed, and the hashed row address is provided to the DRAM array in association with the row activate command instead of the original row address.

8. A system, comprising: command detection logic configured to detect a row activation command directed to a sub-bank of a plurality of sub-banks, each sub-bank comprising a plurality of rows of a bank of a DRAM array; an activation command counting logic element configured to count a first number of the row activation commands occurring within a window between a first refresh command and a second refresh command, and configured to compare the first number of row activation commands to a first threshold; as well as An additional refresh command generator is configured to provide additional refresh commands to the DRAM array within the window in response to detecting that the first number of row activate commands exceeds the first threshold.

9. The system of claim 8, wherein the plurality of rows of each sub-repository overlaps with the plurality of rows of another sub-repository.

10. The system of claim 9, wherein at least 16 rows of each sub-repository overlap with at least 16 rows of another sub-repository.

11. The system of claim 8, wherein the first refresh command and the second refresh command are consecutive.

12. The system of claim 8, further comprising a timing controller configured to increase a timing gap between consecutive commands provided to the DRAM array in response to detecting that the first number of row activation commands exceeds the first threshold.

13. The system of claim 12, wherein: The activation command counting logic is further configured to count a second number of row activation commands occurring within the window after the timing interval is incremented; and The timing controller is further configured to compare the sum of the first number and the second number of row activation commands with a second threshold, and to further increase the timing gap between consecutive commands provided to the DRAM array in response to detecting that the sum of the first number and the second number of row activation commands exceeds the second threshold.

14. The system of claim 8, further comprising a row address hashing logic element configured to hash an original row address associated with each row activation command, and to provide the hashed row address instead of the original row address to the DRAM array in association with the row activation command.

15. A system, comprising: means for detecting a row activation command directed to a sub-bank of a plurality of sub-banks, each sub-bank comprising a plurality of rows of a bank of a DRAM array; means for counting a first number of said row activation commands occurring within a window between a first refresh command and a second refresh command and for comparing said first number of row activation commands to a first threshold; as well as Means for providing additional refresh commands to the DRAM array within the window in response to detecting that the first number of row activate commands exceeds the first threshold.

16. The system of claim 15, wherein the plurality of rows of each sub-repository overlaps with the plurality of rows of another sub-repository.

17. The system of claim 16, wherein at least 16 rows of each sub-repository overlap with at least 16 rows of another sub-repository.

18. The system of claim 15, wherein the first refresh command and the second refresh command are consecutive.

19. The system of claim 15, further comprising means for increasing a timing gap between consecutive commands provided to the DRAM array in response to detecting that the first number of row activate commands exceeds the first threshold.

20. The system according to claim 19, further comprising, after increasing the timing gap: means for counting a second number of row activation commands occurring within said window; means for comparing a sum of said first number and said second number of row activation commands to a second threshold; as well as means for further increasing the timing gap between consecutive commands provided to the DRAM array in response to detecting that the sum of the first number and the second number of row activate commands exceeds the second threshold.

21. The system of claim 15, further comprising means for hashing an original row address associated with each row activation command, and providing the hashed row address to the DRAM array instead of the original row address in association with the row activation command.

22. A memory controller, the memory controller comprising: a command generator logic element configured to generate a dynamic random access memory (DRAM) command in response to a memory transaction request, the DRAM command including a row activate command and a refresh command; command detection logic configured to detect a row activation command directed to a sub-bank of a plurality of sub-banks, each sub-bank comprising a plurality of rows of a bank of a DRAM array; an activation command counting logic element configured to count a first number of the row activation commands occurring within a window between a first refresh command and a second refresh command, and configured to compare the first number of row activation commands to a first threshold; as well as An additional refresh command generator is configured to provide additional refresh commands to the DRAM array within the window in response to detecting that the first number of row activate commands exceeds the first threshold.

23. The memory controller of claim 22, wherein the plurality of rows of each sub-bank overlap with the plurality of rows of another sub-bank.

24. The memory controller of claim 22, wherein the first refresh command and the second refresh command are consecutive.

25. The memory controller of claim 22, further comprising a timing controller configured to increase a timing gap between consecutive commands provided to the DRAM array in response to detecting that the first number of row activation commands exceeds the first threshold.

26. The memory controller of claim 22, further comprising a row address hashing logic element configured to hash an original row address associated with each row activation command, and to provide the hashed row address instead of the original row address to the DRAM array in association with the row activation command.

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