Electric energy meter signal processing system based on differential resistance potential-divider network and circuit thereof

Abstract

The invention relates to an electric energy meter signal processing system based on a differential resistance voltage-dividing network and a circuit thereof, and relates to the technical field of circuit differential resistance adjustment, and the system comprises a positive end signal analysis module which collects a voltage output signal of a positive input end of the differential resistance voltage-dividing network for analysis so as to determine a signal waveform deviation value; the waveform deviation analysis module is used for analyzing the signal waveform deviation value through a preset mirror image resistance value analysis strategy so as to determine the mirror image resistance value of the positive input end of the voltage dividing network; the negative end resistance value adjusting module is used for extracting a corresponding negative end resistance value adjusting instruction from a preset adjustable resistance value database according to the mirror image resistance value; and the resistance value of a negative-end adjustable resistor in the differential voltage dividing network is controlled through the negative-end resistance adjusting instruction. The test circuit has the effect of improving the stability when the test circuit is detected.

Description

Technical Field

[0001] The present application relates to the technical field of circuit differential resistance adjustment, and in particular to an electric energy meter signal processing system and circuit based on a differential resistance voltage divider network. Background Art

[0002] The differential voltage divider network is a voltage signal test circuit with good anti-interference characteristics and is widely used in measurement circuits of electrical equipment.

[0003] In the related art, the differential resistor network includes a voltage input module, a voltage divider module, a voltage signal sampling module, a digital-to-analog conversion module and a sampling value output module. When the differential resistor network is connected to the power supply under test, the measured voltage signal is transmitted to the voltage divider module through the voltage input module for voltage division processing, and then transmitted to the voltage signal sampling module through the voltage divider module. After the voltage signal sampling module samples the signal, it transmits the sampling signal to the digital-to-analog conversion module for sampling value conversion, and the converted sampling value is output through the sampling value output module.

[0004] Regarding the above-mentioned related technologies, in the signal test circuit of the differential voltage divider network, when there is an interference signal wave in the connected line, it is easy to affect the stability of the measured signal, causing the sample value data obtained during continuous sampling in the test circuit to fluctuate greatly. Summary of the invention

[0005] In order to improve the stability of detection in a test circuit, the present application provides an electric energy meter signal processing system and circuit based on a differential resistor voltage divider network.

[0006] In a first aspect, the present application provides an electric energy meter signal processing system based on a differential resistor voltage divider network, which adopts the following technical solution: An electric energy meter signal processing system based on a differential resistor voltage divider network comprises: The positive terminal signal analysis module collects the voltage output signal of the positive input terminal of the differential voltage divider network for analysis to determine the signal waveform deviation value; The waveform deviation analysis module analyzes the signal waveform deviation value through a preset mirror image resistance analysis strategy to determine the mirror image resistance value at the positive input end of the voltage divider network; A negative terminal resistance adjustment module extracts a corresponding negative terminal resistance adjustment instruction from a preset adjustable resistance database according to the mirror resistance; The resistance value of the negative terminal adjustable resistor in the differential voltage divider network is controlled by the negative terminal resistance adjustment instruction.

[0007] Optionally, the mirror image resistance analysis strategy includes: Obtaining signal deviation values ​​of the positive terminal input electrical signal and the positive terminal output electrical signal, and bringing the signal deviation values ​​into a preset deviation analysis model for analysis to determine waveform deviation characteristics; The waveform deviation value is calculated according to the waveform deviation characteristics, and a difference gain model is constructed according to the waveform deviation value. The difference gain model expression is: ,in, Indicates the deviation gain value, The characteristic value representing the waveform deviation characteristic is generated by comparing data with the preset database. Indicates the deviation amplitude corresponding to the waveform deviation feature; The mirror resistance is calculated based on the deviation gain value and the pre-built current mirror using the following formula: , , , Among them, among them, Indicates the output voltage, Represents the differential mode gain value, Represents the positive input voltage, Represents the negative input voltage, Represents the drain current of the metal oxide semiconductor field effect transistor. Represents the gate-source voltage of the metal oxide semiconductor field effect transistor, Represents the threshold voltage of the metal oxide semiconductor field effect transistor, It represents the channel width-to-length ratio of the metal oxide semiconductor field effect transistor. represents the mobility of carriers in the channel, represents the gate oxide capacitance per unit area, Represents the image resistance value, Represents the power supply voltage of the metal oxide semiconductor field effect transistor.

[0008] Optionally, when determining the mirror image resistance value of the positive input terminal of the voltage divider network, it also includes: The resistance value input of the negative input terminal of the analog differential voltage divider network is used to determine the analog input voltage signal; Analyze the analog input voltage signal and the voltage input signal at the positive input end of the differential voltage divider network to determine the input voltage difference of the voltage corresponding to the voltage signal; When the input voltage difference is not within the preset good difference range, the resistance of the positive input end of the differential voltage divider network is calculated according to the preset difference comprehensive adjustment strategy to determine the corrected mirror image resistance.

[0009] Optionally, calculating the resistance of the positive input terminal of the differential voltage divider network according to a preset difference comprehensive adjustment strategy includes: The theoretical common-mode voltage is determined by calculating the output voltage and input differential voltage analytical formula based on the differential mode gain and the preset differential voltage network. The output voltage and input differential voltage analytical formula of the differential voltage network are as follows: , , , ; in, represents the common-mode voltage of the differential circuit, represents the differential mode gain, Indicates the negative input voltage, Indicates the positive input voltage, and They represent the detected negative input current and positive input current respectively. and Represent the simulated negative terminal resistance and positive terminal resistance respectively, Indicates the voltage influence coefficient of a circuit element in a differential circuit.

[0010] Optionally, when determining the corrected image resistance value, it also includes: Input a preset fluctuation signal into a differential resistor voltage divider network and collect a positive output signal and a negative output signal for analysis to determine a positive output waveform and a negative output model; Perform simulation based on the positive-end output signal and the negative-end output signal to determine a positive-end analog output waveform and a negative-end analog output waveform; Calculate and analyze the positive end output waveform and the positive end deviation waveform of the positive end simulation output waveform, and the negative end deviation waveform of the negative end output waveform and the negative end simulation waveform; Determine the output waveform deviation based on the positive end deviation waveform and the negative end deviation waveform analysis, and match the resistance optimization coefficient corresponding to the output waveform deviation in the preset resistance adjustment database; Generate a resistance optimization adjustment instruction based on the resistance optimization coefficient.

[0011] Optionally, when controlling the resistance value of the negative-end adjustable resistor in the differential voltage divider network, the method further includes: Analyze the negative end analog waveform and the positive end analog waveform to determine the waveform symmetry; Matching the symmetry influence factor corresponding to the waveform symmetry in the preset waveform deviation database, and comparing the symmetry influence factor with the preset benchmark influence factor; When the symmetric impact factor is greater than the preset reference impact factor, the waveform is corrected using a preset interference adjustment strategy.

[0012] Optionally, the preset interference adjustment strategy includes: Performing numerical calculation based on the symmetric impact factor and the preset benchmark impact factor to determine the symmetric impact factor difference; Matching the resistance feedback adjustment parameter corresponding to the symmetry influence factor difference in the preset dynamic fine-tuning database; The multi-level adjustable resistor is adjusted based on the resistance feedback adjustment parameter and the feedback waveform is collected for waveform symmetry analysis. When the symmetry influence factor of the waveform symmetry is less than the preset reference influence factor, an adjustment end instruction is generated.

[0013] Optionally, also include: First, the multi-level adjustable resistor is sequentially adjusted according to the preset resistance test parameters to determine the resistance adjustment state of the multi-level adjustable resistor; When the resistance adjustment state is inconsistent with the preset effective adjustment state, the invalid adjustment resistance is screened to determine the effective adjustment resistance; The resistance adjustment analysis is performed based on the effective adjustment resistance to determine the adjustable mirror resistance range.

[0014] In a second aspect, the present application provides an electric energy meter signal processing circuit based on a differential resistor voltage divider network, which adopts the following technical solution: An electric energy meter signal processing circuit based on a differential resistor voltage divider network comprises: A positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal, a first positive resistor is formed between the positive input terminal and the positive output terminal, a first negative resistor is formed between the negative input terminal and the negative output terminal, a second positive resistor is arranged between the positive output terminal and the ground terminal, a second negative resistor is arranged between the negative output terminal and the ground terminal, the first negative resistor and the first positive resistor have the same resistance value, and the second negative resistor and the second positive resistor have the same resistance value; The first negative resistor is a multi-level adjustable resistor, and the second negative resistor is an adjustable resistor. In summary, the present application includes at least one of the following beneficial technical effects: 1. The voltage signal at the positive output end is analyzed and simulated to determine the mirror resistor required to balance the voltage at the negative end, and the multi-level adjustable resistor pre-connected on the negative end is adjusted according to the mirror resistor, so that the positive end and the negative end maintain the same resistance value, which helps to stabilize the voltage signal of the differential voltage divider network, so that the differential voltage divider network can obtain stable test data when detecting the access circuit; 2. By establishing a current mirror in the differential voltage divider network and calculating the mirror resistance value based on the differential mode gain of the current mirror, the consistency between the resistance value used when adjusting the resistance value of the negative input terminal and the positive input terminal is further improved, which helps to reduce the signal fluctuation amplitude of the positive input terminal and the negative input terminal in the voltage divider network.

[0015] 3. When the multi-stage adjustable resistor is adjusted for mirror resistance, a resistance adjustment test is performed in advance to screen out the resistors that fail to adjust, and the mirror resistance adjustment is performed on the adjustable resistors that are effectively adjusted, thereby improving the accuracy of the mirror resistance adjustment of the resistors that fail to adjust. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a method flow chart of steps S1 to S4 in this application.

[0017] Figure 2 It is a method flow chart of steps S201 to S202 in this application.

[0018] Figure 3 It is a method flow chart of steps S203 to S206 in this application.

[0019] Figure 4 It is a method flow chart of steps S2051 to S2054 in this application.

[0020] Figure 5 It is a method flow chart of steps S401 to S403 in this application.

[0021] Figure 6 It is a method flow chart of steps S4031 to S4033 in this application.

[0022] Figure 7 It is a method flow chart of steps S500 to S502 in this application.

[0023] Figure 8 It is a simplified equivalent circuit diagram of the electric energy meter signal processing circuit of the differential resistor voltage divider network in the present application.

[0024] Fig. 9 It is a line graph of the sampling value fluctuation ratio of differential network sampling and single-ended network sampling in this application.

[0025] Fig.10 It is a data fluctuation diagram of the first sampling channel after the differential network in this application performs mirror resistance adjustment.

[0026] Fig.11 It is a data fluctuation diagram of the second sampling channel after the differential network in this application performs mirror resistance adjustment. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of this application more clear, the following Figure 1-11 It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0028] The embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0029] The embodiment of the present application discloses an electric energy meter signal processing system based on a differential resistor voltage divider network, which analyzes the voltage signal at the positive input end of the differential voltage divider network and the corresponding resistance value of the positive input end, thereby forming a mirror resistance value according to the resistance value of the positive input end, and adjusting the multi-stage adjustable resistance of the negative input end, so that the negative input end and the positive input end can have resistances with the same resistance value. Since the positive and negative ends are completely symmetrical, the interference signal introduced on the transmission cable is attenuated by the same amplitude, and the interference signal of the same amplitude is retained in the sampled signal. After entering the differential voltage divider network, the amplitudes thereof cancel each other out, which helps to improve the accuracy and stability of the measurement.

[0030] Reference Figure 1 The method flow of the electric energy meter signal processing system based on the differential resistor voltage divider network includes the following steps: Step S1: a positive terminal signal analysis module collects and analyzes the voltage output signal of the positive input terminal of the differential voltage divider network to determine the signal waveform deviation value; The differential voltage divider network consists of a positive input terminal, a negative input terminal, a positive output terminal, a negative output terminal and a voltage divider resistor. The voltage signal is transmitted from the outside to the positive input terminal and the negative input terminal, and then divided by the voltage divider resistor, and finally the voltage signal is output from the positive output terminal and the negative output terminal respectively.

[0031] By performing amplitude and phase analysis on the voltage input signal continuously input to the positive input terminal, a waveform diagram of the input signal is generated, and the phase difference between the waveform diagram and the sinusoidal alternating current image is analyzed. The difference is defined as the signal waveform deviation value for easy reference in subsequent further analysis.

[0032] Step S2: The waveform deviation analysis module analyzes the signal waveform deviation value through a preset mirror image resistance analysis strategy to determine the mirror image resistance value of the positive input end of the voltage divider network; The mirror image resistance analysis strategy is to calculate and analyze the input voltage signal at the positive input end of the differential voltage divider network to obtain the mirror image resistance. The specific strategy will be further explained in the subsequent steps. The purpose of analyzing and obtaining the mirror image resistance is to facilitate the subsequent adjustment of the resistance at the negative input end so that the two parallel input lines of the differential voltage divider network maintain symmetrical input and output signals.

[0033] Step S3: The negative terminal resistance adjustment module extracts the corresponding negative terminal resistance adjustment instruction from a preset adjustable resistance database according to the mirror resistance; Step S4: controlling the resistance value of the negative-end adjustable resistor in the differential voltage divider network through the negative-end resistance adjustment instruction.

[0034] The multi-level adjustable resistor is an adjustable resistor pre-arranged in a differential voltage divider network, and there are multiple adjustable resistors, and the multiple adjustable resistors form a voltage divider connection. When calculating, the mirror resistance is divided by the upper limit of the resistance adjustment of the multiple adjustable resistors, and the obtained resistance is used as the adjustment sub-parameter of the corresponding adjustable resistor. The multiple adjustment sub-parameters are recorded to form a resistance distribution parameter, and a burden resistance adjustment instruction prompt signal is issued to prompt the multi-level adjustable resistor to adjust the resistance.

[0035] Step S4: Based on the negative terminal resistance adjustment instruction, the resistance of the multi-stage adjustable resistor is adjusted according to the resistance distribution parameter to form a negative terminal mirror resistor of a stable differential voltage divider network waveform.

[0036] After receiving the negative terminal resistance adjustment instruction, corresponding adjustments are made according to the resistance distribution parameters, so that symmetrical mirror-image resistance values ​​are formed in the lines corresponding to the positive input and negative input ends, so that the external power supply signal has the same current and voltage signals when passing through the two lines, forming a more stable signal data channel.

[0037] Reference Figure 2 , the image resistance analysis strategy includes: Step S201: obtaining signal deviation values ​​of the positive terminal input electrical signal and the positive terminal output electrical signal, and bringing the signal deviation values ​​into a preset deviation analysis model for analysis to determine waveform deviation characteristics; Step S202: Calculate the waveform deviation value according to the waveform deviation feature, and construct a difference gain model according to the waveform deviation value. The difference gain model expression is: ,in, Indicates the deviation gain value, The characteristic value representing the waveform deviation characteristic is generated by comparing data with the preset database. Indicates the deviation amplitude corresponding to the waveform deviation feature; Step S203: Calculate the mirror resistance value according to the deviation gain value and the pre-built current mirror, using the following formula: , , , Among them, among them, Indicates the output voltage, Represents the differential mode gain value, Represents the positive input voltage, Represents the negative input voltage, Represents the drain current of the metal oxide semiconductor field effect transistor. Represents the gate-source voltage of the metal oxide semiconductor field effect transistor, Represents the threshold voltage of the metal oxide semiconductor field effect transistor, It represents the channel width-to-length ratio of the metal oxide semiconductor field effect transistor. represents the mobility of carriers in the channel, represents the gate oxide capacitance per unit area, Represents the image resistance value, Represents the power supply voltage of the metal oxide semiconductor field effect transistor.

[0038] Reference Figure 3 , when determining the mirror resistance value of the positive input terminal of the voltage divider network, it also includes: Step S203: simulating the resistance input of the negative input terminal of the differential voltage divider network to determine the simulated input voltage signal; By pre-establishing a data calculation simulation network model, a mapping relationship is formed between the voltage signal and the resistance value. When the resistance value changes, the output voltage signal changes with the resistance value. When the data calculation simulation network model inputs different resistance values, different voltage signals are output. The voltage signal is defined as an analog input voltage signal.

[0039] Step S204: analyzing the analog input voltage signal and the voltage input signal at the positive input end of the differential voltage divider network to determine an input voltage difference between the voltage signal and the voltage corresponding to the voltage signal; By comparing and calculating the analog input voltage signal and the positive input terminal signal, the difference can be analyzed and obtained. When there is no interference in the differential voltage divider network, the input voltage signal and the output signal are equal.

[0040] Step S205: when the input voltage difference is not within the preset good difference range, the resistance of the positive input end of the differential voltage divider network is calculated according to the preset difference comprehensive adjustment strategy to determine the corrected mirror resistance; The good difference range is a preset value range, indicating that the input voltage difference is small and within a reasonable fluctuation range. When the input voltage difference is not within the good difference range, it indicates that the voltage difference is large. At this time, the mirror resistance is corrected through further calculation so that after the adjustable resistance of the negative end is adjusted, the resistance of the lines where the positive input end and the negative output end are located can be kept consistent. The comprehensive difference adjustment strategy represents the method steps for adjusting the resistance value, which will be further explained in the subsequent steps.

[0041] Step S206: replacing the mirror image resistance value according to the corrected mirror image resistance value.

[0042] The corrected mirror image resistance value is replaced and updated, so that the negative input terminal is corrected accordingly before adjusting the multi-stage adjustable resistance, which helps to improve the adjustment accuracy.

[0043] Reference Figure 4 , executing step S205: calculating the resistance of the positive input terminal of the differential voltage divider network according to the preset difference comprehensive adjustment strategy includes: Step S2051: Calculate the theoretical common mode voltage based on the differential mode gain and the output voltage and input differential voltage analytical formula of the preset differential voltage network. The output voltage and input differential voltage analytical formula of the differential voltage network is as follows: , , , ; in, It represents the common-mode voltage of the differential circuit. The value of the common-mode voltage can be determined by measuring the differential circuit. represents the differential mode gain, Indicates the negative input voltage, which can be obtained through detection. Indicates the positive input voltage, and They represent the detected negative input current and positive input current respectively. and Represent the simulated negative terminal resistance and positive terminal resistance respectively, Indicates the voltage influence coefficient of a circuit element in a differential circuit.

[0044] When executing step S205: determining the modified image resistance value, the method further includes: Step S2052: inputting a preset fluctuation signal into a differential resistor voltage divider network and collecting a positive output signal and a negative output signal for analysis to determine a positive output waveform and a negative output model; Step S2053: performing simulation based on the positive end output signal and the negative end output signal to determine a positive end simulation output waveform and a negative end simulation output waveform; Step S2054: Calculate and analyze the positive end output waveform and the positive end deviation waveform of the positive end analog output waveform, and the negative end deviation waveform of the negative end output waveform and the negative end analog waveform; Step S2055: determining the output waveform deviation based on the positive end deviation waveform and the negative end deviation waveform analysis, and matching the resistance optimization coefficient corresponding to the output waveform deviation in the preset resistance adjustment database; Step S2056: Generate a resistance optimization adjustment instruction based on the resistance optimization coefficient.

[0045] Step S2052: performing waveform simulation based on the voltage input signal of the positive input terminal and the analog input voltage signal to determine a negative terminal analog waveform and a positive terminal analog waveform; By performing waveform simulation on the analog input voltage signal and the voltage input signal at the positive input terminal, a waveform diagram of the corresponding voltage signal can be generated. The purpose of generating the waveform diagram at this time is to further analyze whether the sinusoidal waveform of the waveform diagram is standard, so as to further analyze the signal stabilization effect of the differential network circuit after the mirror resistance value is adjusted.

[0046] Step S2053: performing deviation waveform feature recognition based on the negative end analog waveform and the positive end analog waveform to determine the negative end peak amplitude of the negative end analog waveform and the positive end peak amplitude of the positive end analog waveform; By identifying and comparing the waveform features of the waveform diagram, the peaks and troughs of the negative-end analog waveform and the positive-end analog waveform can be obtained, and the peaks of the analog waveforms are analyzed. The peak value of the negative-end analog waveform is defined as the negative-end peak amplitude, and the peak value of the positive-end analog waveform is defined as the positive-end peak amplitude.

[0047] Step S2054: determining the peak difference based on the negative end peak amplitude and the positive end peak amplitude, and matching the resistance optimization coefficient corresponding to the peak difference in the preset resistance adjustment database; The peak amplitude of the negative end and the peak amplitude of the positive end are calculated to obtain a peak difference. The peak difference in the resistance adjustment database is a pre-established resistance optimization coefficient search database, which stores different peak differences and resistance optimization coefficients with mapping relationships. When the corresponding peak difference is input, the mapped resistance optimization coefficient is automatically searched and output. Among them, the resistance optimization coefficient represents the coefficient value that optimizes the mirror resistance so that the peak difference is reduced, and the corresponding resistance optimization coefficient is searched.

[0048] Step S2055: issuing a mirror image resistance optimization instruction based on the resistance optimization coefficient.

[0049] A mirror image resistance optimization instruction is issued according to the found optimization coefficient to optimize and adjust the mirror image resistance so that the mirror image resistance is closer to the line resistance of the positive input terminal, thereby eliminating the influence of inconsistent resistance on the signal in the differential network.

[0050] Reference Figure 5 , when forming the negative mirror resistor of the stable differential voltage divider network waveform, it also includes: Step S401: Analyze the negative end simulation waveform and the positive end simulation waveform to determine the waveform symmetry; By performing symmetry analysis on the waveform diagrams of the negative-end analog waveform and the positive-end analog waveform, the symmetry of the waveform can be known, so as to facilitate subsequent further analysis of whether a large difference occurs in the amplitude and phase.

[0051] Step S402: matching the symmetry influence factor corresponding to the waveform symmetry in the preset waveform deviation database, and comparing the symmetry influence factor with the preset reference influence factor; The waveform deviation database is pre-established by the staff and stores different deviation values ​​and symmetric influence factors with mapping relationships. The symmetric influence factor indicates the influence weight value on the data detection of the differential network circuit when the waveform is asymmetric. The benchmark influence factor indicates that when the waveform is asymmetric, the influence on the differential network circuit is less than the required upper limit weight value. When the influence factor is less than the benchmark influence factor, it means that the waveform deviation is small and will not affect the signal transmission. Otherwise, it means that it affects the signal transmission.

[0052] Step S403: When the symmetric impact factor is greater than the preset reference impact factor, waveform correction is performed using a preset interference adjustment strategy.

[0053] By performing interference adjustment on the waveform, the influence on the stability of signal transmission in the differential network can be reduced, wherein the interference adjustment strategy is a method step of performing feedback adjustment on the resistance value, and the specific strategy is further explained in subsequent steps.

[0054] Reference Figure 6 , the preset interference adjustment strategies include: Step S4031: performing numerical calculation according to the symmetric impact factor and the preset reference impact factor to determine the symmetric impact factor difference; By calculating the symmetry influence factor difference, it is possible to know the symmetry influence factor value that needs to be adjusted when the symmetry influence factor of the signal waveform is restored to symmetry.

[0055] Step S4032: matching the resistance feedback adjustment parameter corresponding to the symmetry influence factor difference in the preset dynamic fine-tuning database; The resistance feedback adjustment parameter indicates the adjustment value and the upward and downward adjustment direction when fine-tuning the mirror resistance. By adjusting the resistance upward and downward according to the adjustment value, the waveform change of the output signal can be obtained. The dynamic fine-tuning database is pre-established by the staff and stores different resistance feedback adjustment parameters and the symmetry influence factor difference corresponding to the resistance feedback adjustment parameters. When the symmetry influence factor difference is input, the corresponding resistance feedback adjustment parameter is matched and found.

[0056] Step S4033: adjusting the multi-level adjustable resistor based on the resistance feedback adjustment parameter and collecting the feedback waveform for waveform symmetry analysis, and generating an adjustment end instruction when the symmetry influence factor of the waveform symmetry is less than the preset reference influence factor.

[0057] After finding the corresponding resistance feedback adjustment parameters, the resistance of the multi-stage adjustable resistor is adjusted, and the signal waveform symmetry of the output signal after adjustment is analyzed again. Then, a comparative analysis is performed based on the symmetry influencing factor and the benchmark influencing factor. It can be determined whether the signal waveform is in a symmetrical state at this time, thereby reflecting that the output signal is not affected by other factors, and an adjustment end instruction is generated to indicate the stop of feedback adjustment.

[0058] Additionally, it includes: Step S500: first sequentially adjust the multi-level adjustable resistor according to the preset resistance test parameters to determine the resistance adjustment state of the multi-level adjustable resistor; The resistance test parameter is a resistance adjustment parameter for testing a multi-level adjustable resistor. After adjustment, it can reflect whether the resistor can be adjusted according to the output signal. By analyzing the amplitude and phase of the output signal, it can be known whether the corresponding single resistor in the multi-level adjustable resistor has an effective adjustment, and the adjustment behavior is defined as the resistance adjustment state, including the effective adjustment state and the invalid adjustment state.

[0059] Step S501: when the resistance adjustment state is inconsistent with the preset effective adjustment state, the invalid adjustment resistors are screened to determine the effective adjustment resistors; When the resistance adjustment state is inconsistent with the set effective adjustment state, it means that the corresponding adjustable resistor cannot respond to resistance adjustment during the resistance adjustment test. In this case, multiple adjustable resistors are screened, and the adjustable resistors whose resistance adjustment state is consistent with the effective adjustment state are marked as effective adjustment resistors for easy call during subsequent further adjustment.

[0060] Step S502: performing resistance adjustment analysis based on the effective adjustable resistance to determine the adjustable mirror resistance range.

[0061] By calculating and summing the resistance adjustment range of the effective adjustment resistor, the total resistance adjustment range can be obtained, so that when performing mirror resistance adjustment, the maximum resistance adjustment range can be analyzed, thereby preventing invalid adjustment from occurring.

[0062] Reference Figure 8 Based on the same inventive concept, an embodiment of the present invention provides an electric energy meter signal processing circuit of a differential resistor voltage divider network, comprising: A positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal, a first positive resistor is formed between the positive input terminal and the positive output terminal, a first negative resistor is formed between the negative input terminal and the negative output terminal, a second positive resistor is arranged between the positive output terminal and the ground terminal, a second negative resistor is arranged between the negative output terminal and the ground terminal, the first negative resistor and the first positive resistor have the same resistance value, the second negative resistor and the second positive resistor have the same resistance value, the first negative resistor is a multi-stage adjustable resistor, and the second negative resistor is an adjustable resistor.

[0063] It should be noted that the first positive resistor includes the sixth resistor R6, the seventh resistor R7, the eighth resistor R8 and the ninth resistor R9 connected in sequence, the first negative resistor includes the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13 and the fourteenth resistor R14, the second positive resistor is the adjustable resistor R10, the second negative resistor is the adjustable resistor R15, V+ represents the positive input terminal, Vs+ represents the positive output terminal, V- represents the negative input terminal, and Vs- represents the negative output terminal.

[0064] Among them, refer to Fig. 9 and Fig.10 When the electric energy meter signal processing circuit using the differential resistor voltage divider network performs differential sampling, the fluctuation of the sampling signal is smaller than the signal fluctuation generated by single-ended sampling. After the differential voltage divider network is adjusted accordingly, the sampling fluctuation during data stability detection in multiple sampling channels is as follows: Fig.10 As shown, the sampling fluctuations within half an hour can remain in a relatively stable state and are not prone to large fluctuations.

[0065] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device and unit described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0066] An embodiment of the present invention provides a computer-readable storage medium storing a computer program that can be loaded and executed by a processor for an electric energy meter signal processing system based on a differential resistor voltage divider network.

[0067] Computer storage media include, for example, various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks or optical disks.

[0068] Based on the same inventive concept, an embodiment of the present invention provides an intelligent terminal including a memory and a processor, wherein the memory stores a computer program that can be loaded and executed by the processor for an electric energy meter signal processing system based on a differential resistor voltage divider network.

[0069] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device and unit described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0070] The above are all preferred embodiments of the present application, and are not intended to limit the protection scope of the present application. Any feature disclosed in this specification (including the abstract and drawings), unless otherwise stated, can be replaced by other equivalent or alternative features with similar purposes. That is, unless otherwise stated, each feature is only an example of a series of equivalent or similar features.

Claims

1. An electric energy meter signal processing system based on a differential resistor voltage divider network, characterized in that: include: The positive terminal signal analysis module collects the voltage output signal of the positive input terminal of the differential voltage divider network for analysis to determine the signal waveform deviation value; The waveform deviation analysis module analyzes the signal waveform deviation value through a preset mirror image resistance analysis strategy to determine the mirror image resistance value at the positive input end of the voltage divider network; A negative terminal resistance adjustment module extracts a corresponding negative terminal resistance adjustment instruction from a preset adjustable resistance database according to the mirror resistance; The resistance value of the negative terminal adjustable resistor in the differential voltage divider network is controlled by the negative terminal resistance adjustment instruction.

2. The electric energy meter signal processing system based on a differential resistor voltage divider network according to claim 1, characterized in that: The mirror image resistance analysis strategy includes: Obtaining signal deviation values ​​of the positive terminal input electrical signal and the positive terminal output electrical signal, and bringing the signal deviation values ​​into a preset deviation analysis model for analysis to determine waveform deviation characteristics; The waveform deviation value is calculated according to the waveform deviation characteristics, and a difference gain model is constructed according to the waveform deviation value. The difference gain model expression is: ,in, Indicates the deviation gain value, The characteristic value representing the waveform deviation characteristic is generated by comparing data with the preset database. Indicates the deviation amplitude corresponding to the waveform deviation feature; The mirror resistance is calculated based on the deviation gain value and the pre-built current mirror using the following formula: ， , ， Among them, among them, Indicates the output voltage, Represents the differential mode gain value, Represents the positive input voltage, Represents the negative input voltage, Represents the drain current of the metal oxide semiconductor field effect transistor. Represents the gate-source voltage of the metal oxide semiconductor field effect transistor, Represents the threshold voltage of the metal oxide semiconductor field effect transistor, It represents the channel width-to-length ratio of the metal oxide semiconductor field effect transistor. represents the mobility of carriers in the channel, represents the gate oxide capacitance per unit area, Represents the mirror image resistance, Represents the power supply voltage of the metal oxide semiconductor field effect transistor.

3. The electric energy meter signal processing system based on a differential resistor voltage divider network according to claim 1, characterized in that: When determining the mirror resistor value at the positive input of the voltage divider network, also include: The resistance value input of the negative input terminal of the analog differential voltage divider network is used to determine the analog input voltage signal; Analyze the analog input voltage signal and the voltage input signal at the positive input end of the differential voltage divider network to determine the input voltage difference of the voltage corresponding to the voltage signal; When the input voltage difference is not within the preset good difference range, the resistance of the positive input end of the differential voltage divider network is calculated according to the preset difference comprehensive adjustment strategy to determine the corrected mirror image resistance.

4. The electric energy meter signal processing system based on a differential resistor voltage divider network according to claim 3, characterized in that: The calculation of the resistance at the positive input end of the differential voltage divider network according to the preset differential comprehensive adjustment strategy includes: The theoretical common-mode voltage is determined by calculating the output voltage and input differential voltage analytical formula based on the differential mode gain and the preset differential voltage network. The output voltage and input differential voltage analytical formula of the differential voltage network are as follows: ， ， ， ； in, represents the common-mode voltage of the differential circuit, represents the differential mode gain, Indicates the negative input voltage, Indicates the positive input voltage, and They represent the detected negative input current and positive input current respectively. and Represent the simulated negative terminal resistance and positive terminal resistance respectively, Indicates the voltage influence coefficient of a circuit element in a differential circuit.

5. The electric energy meter signal processing system based on a differential resistor voltage divider network according to claim 3, characterized in that: When determining the corrected image resistance, also include: Input a preset fluctuation signal into a differential resistor voltage divider network and collect a positive output signal and a negative output signal for analysis to determine a positive output waveform and a negative output model; Perform simulation based on the positive-end output signal and the negative-end output signal to determine a positive-end analog output waveform and a negative-end analog output waveform; Calculate and analyze the positive end output waveform and the positive end deviation waveform of the positive end simulation output waveform, and the negative end deviation waveform of the negative end output waveform and the negative end simulation waveform; Determine the output waveform deviation based on the positive end deviation waveform and the negative end deviation waveform analysis, and match the resistance optimization coefficient corresponding to the output waveform deviation in the preset resistance adjustment database; Generate a resistance optimization adjustment instruction based on the resistance optimization coefficient.

6. The electric energy meter signal processing system based on a differential resistor voltage divider network according to claim 5, characterized in that: When controlling the resistance value of the negative adjustable resistor in the differential voltage divider network, it also includes: Analyze the negative end analog waveform and the positive end analog waveform to determine the waveform symmetry; Matching the symmetry influence factor corresponding to the waveform symmetry in the preset waveform deviation database, and comparing the symmetry influence factor with the preset benchmark influence factor; When the symmetric impact factor is greater than the preset reference impact factor, the waveform is corrected using a preset interference adjustment strategy.

7. The electric energy meter signal processing system based on a differential resistor voltage divider network according to claim 6, characterized in that: The preset interference adjustment strategy includes: Performing numerical calculation based on the symmetric impact factor and the preset benchmark impact factor to determine the symmetric impact factor difference; Match the resistance feedback adjustment parameter corresponding to the symmetry influence factor difference in the preset dynamic fine-tuning database; The multi-level adjustable resistor is adjusted based on the resistance feedback adjustment parameter and the feedback waveform is collected for waveform symmetry analysis. When the symmetry influence factor of the waveform symmetry is less than the preset reference influence factor, an adjustment end instruction is generated.

8. The electric energy meter signal processing system based on a differential resistor voltage divider network according to claim 1 or 7, characterized in that: Also includes: First, the multi-level adjustable resistor is sequentially adjusted according to the preset resistance test parameters to determine the resistance adjustment state of the multi-level adjustable resistor; When the resistance adjustment state is inconsistent with the preset effective adjustment state, the invalid adjustment resistance is screened to determine the effective adjustment resistance; The resistance adjustment analysis is performed based on the effective adjustment resistance to determine the adjustable mirror resistance range.

9. An electric energy meter signal processing circuit based on a differential resistor voltage divider network, characterized in that: include: A positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal, a first positive resistor is formed between the positive input terminal and the positive output terminal, a first negative resistor is formed between the negative input terminal and the negative output terminal, a second positive resistor is arranged between the positive output terminal and the ground terminal, a second negative resistor is arranged between the negative output terminal and the ground terminal, the first negative resistor and the first positive resistor have the same resistance value, and the second negative resistor and the second positive resistor have the same resistance value; The first negative resistor is a multi-level adjustable resistor, and the second negative resistor is an adjustable resistor.

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