Interference synchronization method, system, medium and equipment for chip reliability test

Abstract

The invention provides an interference synchronization method, an interference synchronization system, a medium and equipment for chip reliability testing, which are applied to the technical field of chip testing. According to the invention, the execution opportunity of the sensitive instruction is adjusted through the pre-delay time, and then the opportunity of the interference source to generate the interference signal is adjusted based on the specific time relationship among the interference generation delay time, the pre-delay time and the interference trigger delay time measured in advance. The coupling between interference generation and sensitive instruction execution opportunities can be effectively adjusted, so that the chip reliability test can be more effectively carried out.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to an interference synchronization method, system, medium and equipment for chip reliability testing. Background Art

[0002] In modern electronic devices, especially home appliances, chips are core control units, and their reliability is crucial. However, in practical applications, chips often face complex working conditions of inductive and capacitive interference, which can have a serious impact on the normal operation of the chip. Especially when executing certain sensitive instructions (such as stacking and popping operations at the interrupt site), the impact of interference may cause bit errors in instruction cache or reading, thereby causing occasional failures. Such failures are often random, which brings great challenges to product reliability detection and fault location.

[0003] When the chip is in an environment with inductive interference, especially in home appliances with inductive components such as heating wires, these components will generate interference signals during the on-off process. When these interference signals happen to couple to the chip to execute key sensitive instructions, faults will occur. However, there is no fixed synchronization relationship between the occurrence of this interference and the execution of instructions, which makes the coupling between the two random and increases the unpredictability of faults.

[0004] Therefore, how to adjust the coupling between the occurrence of interference and the execution timing of sensitive instructions becomes the key to effectively detecting the reliability of the chip under specific interference conditions. Summary of the invention

[0005] In view of the above problems, the present invention provides an interference synchronization method, system, medium and device for chip reliability testing that overcomes the above problems or at least partially solves the above problems. The technical solution is as follows:

[0006] An interference synchronization method for chip reliability testing, comprising:

[0007] Before the sensitive instruction of the chip under test is executed, the chip under test outputs a synchronous interference control instruction to the interference synchronization control module, wherein there is a lead delay time between the output time of the synchronous interference control instruction and the execution time of the sensitive instruction;

[0008] After receiving the synchronous interference control instruction output by the chip under test, the interference synchronization control module waits for the interference generation delay time to end, and when the interference generation delay time ends, controls the generation and output of the interference signal, wherein there is a specific time relationship between the interference generation delay time and the lead delay time and the pre-measured interference trigger delay time, so as to ensure that the interference signal can synchronously intervene in the execution process of the sensitive instruction.

[0009] Optionally, the method further includes:

[0010] The interference synchronization control module determines whether the execution time of the sensitive instruction is after the output time of the interference signal before the end of the interference generation delay time, and if so, determines whether the interference generation delay time satisfies the time synchronization condition composed of the pre-delay time and the interference trigger delay time;

[0011] In a case where the interference generation delay time satisfies the time synchronization condition, the interference synchronization control module controls the generation and output of the interference signal when the interference generation delay time ends.

[0012] Optionally, the method further includes:

[0013] In the case where the interference generation delay time does not meet the time synchronization condition, the interference synchronization control module adjusts the interference generation delay time according to the time synchronization condition;

[0014] The interference synchronization control module controls the generation and output of the interference signal when the adjusted interference generation delay time ends.

[0015] Optionally, the method further includes:

[0016] In the case where the execution time of the sensitive instruction is not after the output time of the interference signal, the interference synchronization control module adjusts the lead delay time according to the time synchronization condition;

[0017] Based on the adjusted lead delay time, before the sensitive instruction of the chip under test is executed, the chip under test re-outputs the synchronous interference control instruction.

[0018] Optionally, the time synchronization condition is that the interference generation delay time is equal to the lead delay time minus the interference trigger delay time, plus a preset synchronization constant, wherein the preset synchronization constant is related to the accuracy of the relay that triggers the interference source to generate the interference signal.

[0019] Optionally, the interference trigger delay time is the average delay time between the interference synchronization control module receiving the synchronous interference control instruction and outputting the interference signal.

[0020] Optionally, the chip under test outputs a no-operation instruction within the lead delay time.

[0021] An interference synchronization system for chip reliability testing comprises: a chip to be tested, an interference synchronization control module, a relay and an interference source.

[0022] The chip under test is used to output a synchronous interference control instruction to the interference synchronization control module within the execution function body of the sensitive instruction, wherein there is a lead delay time between the output time of the synchronous interference control instruction and the execution time of the sensitive instruction;

[0023] The interference synchronization control module is used to wait for the interference generation delay time to end after receiving the synchronous interference control instruction output by the chip under test, and control the relay to trigger the interference source to generate and output an interference signal when the interference generation delay time ends, wherein there is a specific time relationship between the interference generation delay time and the lead delay time and the pre-measured interference trigger delay time to ensure that the interference signal can be synchronously intervened in the execution process of the sensitive instruction.

[0024] A computer-readable storage medium stores a program, and when the program is executed by a processor, the interference synchronization method for chip reliability testing is implemented.

[0025] An electronic device comprises at least one processor, and at least one memory and a bus connected to the processor; wherein the processor and the memory communicate with each other via the bus; and the processor is used to call program instructions in the memory to execute the interference synchronization method for chip reliability testing.

[0026] By means of the above technical scheme, the interference synchronization method, system, medium and equipment for chip reliability testing provided by the present invention, before the sensitive instructions of the tested chip are executed, the tested chip outputs a synchronous interference control instruction to the interference synchronization control module, wherein there is a lead delay time between the output time of the synchronous interference control instruction and the execution time of the sensitive instruction; after receiving the synchronous interference control instruction output by the tested chip, the interference synchronization control module waits for the end of the interference generation delay time, and controls the generation and output of the interference signal when the interference generation delay time ends, wherein there is a specific time relationship between the interference generation delay time and the lead delay time and the pre-measured interference trigger delay time, so as to ensure that the interference signal can be synchronously intervened in the execution process of the sensitive instruction. The present invention adjusts the execution timing of sensitive instructions by the lead delay time, making it later than the interference signal, and then adjusts the timing of the interference source generating the interference signal by the interference generation delay time determined by the lead delay time and the interference trigger delay time, which can effectively adjust the coupling between the occurrence of interference and the execution timing of sensitive instructions, thereby ensuring that the output of the interference signal and the execution of the sensitive instruction have good time coordination, so that the interference effect can intervene in time when the sensitive instruction is executed, thereby achieving more accurate testing and verification, and improving the reliability detection effect of the chip under specific working conditions. Through this adjustment mechanism, not only can the sensitivity to interference effects be improved, but also the working environment under real application scenarios can be more accurately simulated, the probability of fault reproduction can be increased, and strong support is provided for subsequent problem location and resolution.

[0027] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0029] Figure 1 A schematic diagram illustrating that an interference signal is earlier than a sensitive instruction provided by an embodiment of the present invention is shown;

[0030] Figure 2 A schematic diagram illustrating that an interference signal is later than a sensitive instruction provided by an embodiment of the present invention is shown;

[0031] Figure 3A schematic flow chart of an implementation of an interference synchronization method for chip reliability testing provided by an embodiment of the present invention is shown;

[0032] Figure 4 A schematic diagram illustrating synchronous coupling of an interference signal and a sensitive instruction provided by an embodiment of the present invention is shown;

[0033] Figure 5 A schematic diagram of the architecture of an interference synchronization system for chip reliability testing provided by an embodiment of the present invention is shown;

[0034] Figure 6 A schematic diagram illustrating an electronic device provided by an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0035] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to enable the scope of the present invention to be fully communicated to those skilled in the art.

[0036] At present, chips are generally considered qualified and can be put into product applications after being screened by wafer testing (Chip Probing, CP) and final testing (Final Test, FT) after chip packaging. However, since these tests fail to simulate the interference conditions that may occur under real working conditions, qualified chips may still fail in specific interference environments. Such failures often gradually appear after the product is put on the market, and due to their sporadic characteristics, they bring great difficulties to engineering and technical personnel in fault location and reliability testing. The consequences of failures can be catastrophic, such as the tampering of key bits of sensitive instructions, resulting in the disabling of global interrupts, which in turn causes the functional failure of home appliances and even affects the quality of items stored in the equipment.

[0037] In this regard, how to effectively synchronize the execution of interference signals and chip sensitive instructions has become an important choice for improving chip reliability detection and rapid fault location under specific working conditions. In order to verify the interference of electrical and electronic equipment to transient switching processes such as inductive loads and relay contact bounce, household appliances usually undergo electrical fast transient pulse group anti-interference tests before leaving the factory. This method couples fast pulse groups at the power supply, control, signal and ground ports of the device to ensure that the product complies with relevant standards (such as GB-T 17626.4-2008). Although this method can detect fault points to a certain extent, since the timing of the pulse signal's serial insertion is asynchronous with the execution time of the chip's sensitive instructions, its coupling is in a random state, so there is still a risk of gradually exposing faults in actual use.

[0038] like Figure 1 and Figure 2 As shown, taking the interruption site pop instruction as an example, the applicant of the present invention has confirmed through a large number of experiments that even if pulse groups are frequently applied to various ports of the chip, it is difficult to achieve effective synchronous coupling between the interference signal and the sensitive instruction. This leads to the situation that different devices still fail at different time points in products that meet the relevant standards. The coupling relationship between the randomness of the interference signal and the execution timing of the sensitive instruction makes it extremely difficult to capture and locate the fault, which brings huge challenges to the after-sales maintenance of the product. Therefore, it is particularly important to conduct in-depth research on the relationship between inductive interference and chip sensitive instructions, and to find effective detection and positioning methods.

[0039] Based on this, in an embodiment of the present invention, an interference synchronization method for chip reliability testing is provided. First, by adjusting the execution timing of the sensitive instruction to be later than the interference signal, it is ensured that the influence of the interference signal can be effectively controlled when the sensitive instruction is executed. Secondly, the synchronous interference control instruction issued by the chip under test when executing the sensitive instruction is received to adjust the timing of the interference source generating the interference signal. This process effectively changes the asynchrony between the sensitive instruction and the interference signal, and realizes the synchronous coupling of the two. Obviously, this method not only improves the reliability detection efficiency of the chip in a specific interference environment, but also can increase the frequency of fault reproduction in faulty household appliances, thereby accelerating the problem location. As a result, the reliability detection time and labor costs of the product can be significantly saved, while the economic expenses of fault maintenance are reduced, and the overall market competitiveness of the product is improved.

[0040] like Figure 3 As shown, a flowchart of an implementation of an interference synchronization method for chip reliability testing provided by an embodiment of the present invention is provided. The method may include:

[0041] S100. Before the sensitive instruction of the chip under test is executed, the chip under test outputs a synchronous interference control instruction to the interference synchronization control module, wherein there is a lead delay time between the output time of the synchronous interference control instruction and the execution time of the sensitive instruction.

[0042] The chip under test (Microcontroller Unit, MCU) refers to an integrated circuit or microprocessor that has reliability testing and evaluation requirements. It is understandable that the chip under test can be a microcontroller that controls the functions of home appliances, a power management chip that is responsible for the management and conversion of power in home appliances, or a sensor chip used to detect environmental information.

[0043] Among them, sensitive instructions refer to instructions involving key operations or data processing in the chip under test.

[0044] Optionally, sensitive instructions may include interrupt site pop instructions, memory access instructions, register read and write instructions, conditional jump instructions, unconditional jump instructions, function call instructions and return instructions, sensor start and stop instructions, execution of communication protocol instructions, timer instructions, counter instructions, system resource acquisition instructions and memory management instructions.

[0045] Among them, the synchronous interference control instruction is an instruction output by the chip under test to control the interference source. The function of the synchronous interference control instruction is to ensure that the generation of the interference signal and the execution of the sensitive instruction can be coordinated in time, so as to ensure that the interference signal can be properly intervened when the sensitive instruction is executed, thereby simulating a real interference environment.

[0046] The lead delay time refers to the time delay set before executing sensitive instructions to ensure that the interference signal can intervene in time. This time delay is used to adjust the timing of interference generation so that when the sensitive instruction is executed, the interference signal can be triggered at the appropriate time point, thereby achieving effective interference testing.

[0047] Before the chip under test executes sensitive instructions, it is necessary to first obtain the synchronous interference control instructions output by the chip. These synchronous interference control instructions will be issued before the sensitive instructions are executed, and there is a lead delay time between the two.

[0048] Specifically, before the execution of sensitive instructions, the chip under test will first output synchronous interference control instructions. The embodiment of the present invention can insert a lead delay time between the time when the chip under test outputs the synchronous interference control instructions and the time when the sensitive instructions are executed, to ensure that the caching or reading process of the sensitive instructions will be performed after the interference signal occurs, thereby improving the accuracy and reliability of the interference test.

[0049] Optionally, the chip under test outputs a no operation instruction (No Operation, NOP) within the lead delay time.

[0050] It is understandable that the execution of no-operation instructions will not cause any changes to the system state, which provides a stable state window for the chip. During this time period, the system can focus on processing the upcoming synchronous interference control instructions without worrying about interference from other operations. This stability helps ensure the accurate transmission and execution of synchronous interference control instructions, thereby enhancing the system's responsiveness to interference.

[0051] S110, after receiving the synchronous interference control instruction output by the chip under test, the interference synchronization control module waits for the interference generation delay time to end, and controls the generation and output of the interference signal when the interference generation delay time ends, wherein there is a specific time relationship between the interference generation delay time, the lead delay time and the pre-measured interference trigger delay time, so as to ensure that the interference signal can be synchronously intervened in the execution process of the sensitive instruction.

[0052] The interference generation delay time refers to the delay time period set before the interference source is triggered to output the interference signal. The setting of the interference generation delay time is to ensure that the interference signal can intervene in time when executing sensitive instructions, thereby affecting the behavior of the chip. The setting of the interference generation delay time needs to consider the specific relationship between the lead delay time and the pre-measured interference trigger delay time.

[0053] The interference source refers to a device or module that can generate specific interference signals. These interference signals may be electromagnetic interference, power fluctuations or other types of signals. The purpose is to test the stability and reliability of the chip under test when it is subject to external interference.

[0054] Among them, interference signals are signals generated by interference sources. These signals are injected into the working environment of the chip under test at a specific time point to simulate the impact of external interference on chip operation.

[0055] The interference trigger delay time is the average delay time between the interference synchronization control module receiving the synchronization interference control instruction and outputting the interference signal. The measurement and control of this time period is an important factor in ensuring that the interference signal can intervene in the execution process of sensitive instructions at the appropriate time. By accurately measuring the interference trigger delay time, the interference generation process can be optimized to achieve the expected test effect.

[0056] The interference synchronization method for chip reliability testing provided by the present invention comprises: before the sensitive instruction of the tested chip is executed, the tested chip outputs a synchronous interference control instruction to an interference synchronization control module, wherein there is a pre-delay time between the output time of the synchronous interference control instruction and the execution time of the sensitive instruction; after receiving the synchronous interference control instruction output by the tested chip, the interference synchronization control module waits for the end of the interference generation delay time, and controls the generation and output of the interference signal at the end of the interference generation delay time, wherein there is a specific time relationship between the interference generation delay time and the pre-delay time and the interference trigger delay time measured in advance, so as to ensure that the interference signal can be synchronously intervened in the execution process of the sensitive instruction. The present invention adjusts the execution timing of the sensitive instruction by the pre-delay time so that it is later than the interference signal, and then adjusts the timing of the interference source generating the interference signal by combining the interference generation delay time determined by the pre-delay time and the interference trigger delay time, which can effectively adjust the coupling between the occurrence of interference and the execution timing of the sensitive instruction, thereby ensuring that the output of the interference signal and the execution of the sensitive instruction have good time coordination, so that the interference effect can intervene in time when the sensitive instruction is executed, thereby achieving more accurate testing and verification, and improving the reliability detection effect of the chip under specific working conditions. Through this adjustment mechanism, not only can the sensitivity to interference be improved, but also the working environment in real application scenarios can be simulated more accurately, the probability of fault reproduction can be increased, and strong support can be provided for subsequent problem location and solution. The present invention adjusts the execution timing of sensitive instructions by the lead delay time, making it later than the interference signal, and then adjusts the timing of the interference source generating the interference signal by combining the interference generation delay time determined by the lead delay time and the interference trigger delay time, which can effectively adjust the coupling between the occurrence of interference and the execution timing of sensitive instructions, thereby ensuring that the output of the interference signal and the execution of the sensitive instruction have good time coordination, so that the interference effect can intervene in time when the sensitive instruction is executed, thereby achieving more accurate testing and verification, and improving the reliability detection effect of the chip under specific working conditions. Through this adjustment mechanism, not only can the sensitivity to interference be improved, but also the working environment in real application scenarios can be simulated more accurately, the probability of fault reproduction can be increased, and strong support can be provided for subsequent problem location and solution.

[0057] Optionally, the interference synchronization control module can also determine whether the execution time of the sensitive instruction is after the output time of the interference signal before the interference generation delay time ends. If so, it determines whether the interference generation delay time satisfies the time synchronization condition composed of the lead delay time and the interference trigger delay time; when the interference generation delay time satisfies the time synchronization condition, the interference synchronization control module controls the generation and output of the interference signal at the end of the interference generation delay time.

[0058] Specifically, in order to ensure that the interference signal intervenes in the execution process of the sensitive instruction, the execution time of the sensitive instruction must be after the output time of the interference signal. The embodiment of the present invention can pre-estimate the execution time of the sensitive instruction and the output time of the interference signal based on the current lead delay time, the interference generation delay time and the interference trigger delay time, and judge whether the execution time of the sensitive instruction is after the output time of the interference signal by comparing the execution time of the sensitive instruction with the output time of the interference signal.

[0059] Optionally, when the execution time of the sensitive instruction is not after the output time of the interference signal, the interference synchronization control module adjusts the lead delay time according to the time synchronization condition; before the sensitive instruction of the chip under test is executed, the chip under test re-outputs the synchronous interference control instruction.

[0060] It is understandable that, since the execution time of the sensitive instruction is not after the output time of the interference signal, the interference signal cannot intervene in the execution process of the sensitive instruction under the current lead delay time. At this time, it is necessary to readjust the lead delay time of the chip under test from the output of the synchronous interference control instruction to the execution of the sensitive instruction to ensure that the interference signal can be output in time before the execution of the sensitive instruction, thereby intervening in the execution process of the sensitive instruction. After adjustment, the lead delay time is updated to a new value, and this new lead delay time will serve as the basis for subsequent operations. The embodiment of the present invention can ensure that the output of the interference signal can be performed before the execution of the sensitive instruction by adjusting the lead delay time based on the time synchronization condition, thereby achieving the purpose of the interference test.

[0061] Optionally, the time synchronization condition can be that the interference generation delay time is equal to the lead delay time minus the interference trigger delay time, so as to ensure that the interference signal is properly intervened in the process of executing sensitive instructions, thereby helping to improve the effectiveness of the test and ensure the reliability of the test results.

[0062] Optionally, the time synchronization condition may be that the interference generation delay time is equal to the lead delay time minus the interference trigger delay time, plus a preset synchronization constant, wherein the preset synchronization constant is related to the accuracy of the relay that triggers the interference source to generate the interference signal. The embodiment of the present invention can improve the timing synchronization between the interference signal and the sensitive instruction by introducing the preset synchronization constant into the time synchronization condition. By referring to the accuracy of the relay that controls the interference source, it can be ensured that the output of the interference signal is more accurate, so that the interference signal can achieve the best interference effect when the sensitive instruction is executed.

[0063] If the execution time of the sensitive instruction is indeed after the output time of the interference signal, then it is necessary to determine whether the interference generation delay time meets the time synchronization condition composed of the lead delay time and the interference trigger delay time. This condition is confirmed to ensure that the interference signal can intervene in the execution process of the sensitive instruction at the appropriate time, so as to conduct effective interference testing. When the interference generation delay time meets the time synchronization condition, it means that the output timing of the interference signal is appropriate when executing the sensitive instruction. At this time, the interference source can be triggered to output the interference signal by synchronizing the interference control instruction.

[0064] The embodiment of the present invention can effectively ensure that the output of the interference signal is carried out at an appropriate time by judging the execution time of the sensitive instruction before the end of the interference generation delay time, thereby maximizing the impact on the execution of the sensitive instruction. This method can not only avoid the ineffective influence of the interference signal on the execution of sensitive instructions, but also ensure the accuracy and reliability of interference control by verifying whether the interference generation delay time meets the time synchronization conditions. Ultimately, when the conditions are met, the output step of the interference signal is implemented, which will enhance the effectiveness of the test, accurately evaluate the anti-interference ability of the chip under test, and provide a scientific basis for subsequent design optimization.

[0065] Optionally, when the interference generation delay time does not meet the time synchronization condition, the interference synchronization control module adjusts the interference generation delay time according to the time synchronization condition. When the adjusted interference generation delay time ends, the interference synchronization control module controls the generation and output of the interference signal.

[0066] It is understandable that if the current interference generation delay time cannot meet the time synchronization condition, it means that the interference signal may be triggered at an inappropriate timing, and the expected interference effect cannot be achieved, that is, the execution process of the sensitive instruction cannot be accurately intervened. In order to solve the above problem, it is necessary to adjust the interference generation delay time. By analyzing the time synchronization condition, a new interference generation delay time will be calculated to ensure that the output of the interference signal can be effectively synchronized with the execution of the sensitive instruction. Once the interference generation delay time is adjusted, subsequent operations will be performed based on this new interference generation delay time. This means that all subsequent synchronous interference control instructions and interference signal outputs will be based on the latest interference generation delay time, thereby ensuring the effectiveness of the interference signal. After the new interference generation delay time ends, the interference source will be triggered and the interference signal will be output, thereby ensuring that the interference can intervene at the right time point, thereby producing the expected interference effect on the execution of the sensitive instruction.

[0067] In the case where the interference generation delay time does not meet the time synchronization condition, the embodiment of the present invention can ensure that the output of the interference signal can match the execution of the sensitive instruction at the right time by adjusting the time, thereby achieving effective interference. This adjustment mechanism not only improves the interference effect of the interference signal, but also enhances the accuracy and reliability of the test, which helps to more comprehensively evaluate the anti-interference ability of the chip under test. In addition, the subsequent interference signal generation operation based on the adjusted interference generation delay time can ensure that the triggering of the interference source meets the predetermined timing requirements, which provides an important reference basis for the design and optimization of the chip under test.

[0068] Figure 4 The figure shows a schematic diagram illustrating the synchronous coupling of the interference signal and the sensitive instruction provided by the embodiment of the present invention. The experimental results show that the coupling effect between the sensitive instruction and the interference signal is significant, and the chip under test exhibits abnormal performance when executing the sensitive instruction. After many experimental observations, the frequency of failure of the chip under test has been significantly improved, from the initial sporadic failures that occurred every 2 days, 15 days, or even several months, to an average of once every 3 to 4 minutes under synchronous interference conditions. This improvement greatly improves the efficiency of locating chip problems in an interference environment.

[0069] Although operations are depicted in a particular order, this should not be understood as requiring that the operations be performed in the particular order shown or in a sequential order.Multitasking and parallel processing may be advantageous under certain circumstances.

[0070] It should be understood that the various steps described in the method embodiments of the present invention may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present invention is not limited in this respect.

[0071] Corresponding to the above method embodiment, the embodiment of the present invention also provides an interference synchronization system for chip reliability testing, the architecture of which is as follows: Figure 5 As shown, the system may include: a chip under test, an interference synchronization control module, a relay and an interference source.

[0072] The chip under test is used to output a synchronous interference control instruction to an interference synchronization control module within the execution function body of the sensitive instruction, wherein there is a lead delay time between the output time of the synchronous interference control instruction and the execution time of the sensitive instruction;

[0073] The interference synchronization control module is used to wait for the interference generation delay time to end after receiving the synchronous interference control instruction output by the chip under test, and when the interference generation delay time ends, control the relay to trigger the interference source to generate and output an interference signal, wherein there is a specific time relationship between the interference generation delay time and the lead delay time and the pre-measured interference trigger delay time, so as to ensure that the interference signal can be synchronously intervened in the execution process of the sensitive instruction.

[0074] like Figure 5 As shown, the interference synchronization system for chip reliability testing provided by the embodiment of the present invention can cut off the direct control channel of the chip to the interference source in advance ( Figure 5 Indicated by "X" in the figure), so that before the sensitive instruction is executed, the chip under test outputs the synchronous interference control instruction to the interference synchronization control module ( Figure 5 After receiving the synchronous interference control instruction, the interference synchronization control module will insert the interference generation delay time and trigger the generation of the interference signal at an appropriate time ( Figure 5 This method significantly increases the coupling probability between interference signals and sensitive instruction execution, thereby increasing the frequency of problem reproduction.

[0075] In the specific implementation process, the embodiment of the present invention first uses an oscilloscope to collect the delay between the interference signal and the sensitive instruction through multiple experiments (100 to 1000 times, the specific number can be adjusted according to the actual situation), and calculates its average value as the initial lead delay time. The interference synchronization control module is implemented in software form, and the interference synchronization control flag is inserted before the sensitive instruction is executed. When the flag is valid, the module will insert the corresponding delay, and then trigger the interference source to initiate the interference signal. During implementation, the system will insert the synchronous interference control instruction and the lead delay time before the sensitive instruction is executed. Taking the interruption site stack as an example, the insertion of the lead delay time is mainly through adding a NOP instruction before the end of the interrupt processing to ensure that the reading or caching of the sensitive instruction occurs after the interference signal. After receiving the synchronous interference control instruction from the chip under test, the interference synchronization control module will calculate the time interval between the instruction and the interference signal, that is, the interference trigger delay time. In practical applications, due to the fluctuation of the relay pull-in time, the average value can be collected and calculated by the oscilloscope multiple times as the interference trigger delay time. Subsequently, the interference synchronization control module will insert the interference generation delay time, observe the relative position of the sensitive instructions and the interference signal through the oscilloscope, and adjust the lead delay time and the interference generation delay time so that the lead delay time, the interference trigger delay time and the interference generation delay time meet the time synchronization conditions to ensure the optimal coupling of the sensitive instructions and the interference signal.

[0076] An embodiment of the present invention provides a computer-readable storage medium on which a program is stored. When the program is executed by a processor, the interference synchronization method for chip reliability testing is implemented.

[0077] An embodiment of the present invention provides a processor, which is used to run a program, wherein the interference synchronization method for chip reliability testing is executed when the program is running.

[0078] like Figure 6 As shown, an embodiment of the present invention provides an electronic device 1000, which includes at least one processor 1001, at least one memory 1002 connected to the processor 1001, and a bus 1003; wherein the processor 1001 and the memory 1002 communicate with each other through the bus 1003; the processor 1001 is used to call the program instructions in the memory 1002 to execute the above-mentioned interference synchronization method for chip reliability testing. The electronic device in this article can be a server, a PC, a PAD, a mobile phone, etc.

[0079] The present invention also provides a computer program product, which, when executed on an electronic device, is suitable for executing a program for initializing the interference synchronization method steps for chip reliability testing.

[0080] The present invention is described with reference to flowcharts and / or block diagrams of methods, systems, electronic devices, and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable device to generate a machine, so that the instructions executed by the processor of the computer or other programmable device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0081] In a typical configuration, an electronic device includes one or more processors (CPU), a memory, and a bus. The electronic device may also include an input / output interface, a network interface, and the like.

[0082] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip. The memory is an example of a computer-readable medium.

[0083] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0084] In the description of the present invention, it should be understood that the terms "up", "down", "front", "back", "left" and "right" etc. indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the positions or elements referred to must have specific directions, be constructed and operate in specific directions. Therefore, they should not be understood as limitations of the present invention.

[0085] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. It should also be noted that the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0086] It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0087] The above are only embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. An interference synchronization method for chip reliability testing, characterized in that: include: Before the sensitive instruction of the chip under test is executed, the chip under test outputs a synchronous interference control instruction to the interference synchronization control module, wherein there is a lead delay time between the output time of the synchronous interference control instruction and the execution time of the sensitive instruction; After receiving the synchronous interference control instruction output by the chip under test, the interference synchronization control module waits for the interference generation delay time to end, and when the interference generation delay time ends, controls the generation and output of the interference signal, wherein there is a specific time relationship between the interference generation delay time and the lead delay time and the pre-measured interference trigger delay time, so as to ensure that the interference signal can synchronously intervene in the execution process of the sensitive instruction.

2. The method according to claim 1, characterized in that Also includes: The interference synchronization control module determines whether the execution time of the sensitive instruction is after the output time of the interference signal before the interference generation delay time ends, and if so, determines whether the interference generation delay time satisfies the time synchronization condition composed of the pre-delay time and the interference trigger delay time; In a case where the interference generation delay time satisfies the time synchronization condition, the interference synchronization control module controls the generation and output of the interference signal when the interference generation delay time ends.

3. The method according to claim 2, characterized in that Also includes: In the case where the interference generation delay time does not meet the time synchronization condition, the interference synchronization control module adjusts the interference generation delay time according to the time synchronization condition; The interference synchronization control module controls the generation and output of the interference signal when the adjusted interference generation delay time ends.

4. The method according to claim 2, characterized in that: Also includes: In the case where the execution time of the sensitive instruction is not after the output time of the interference signal, the interference synchronization control module adjusts the lead delay time according to the time synchronization condition; Based on the adjusted lead delay time, before the sensitive instruction of the chip under test is executed, the chip under test re-outputs the synchronous interference control instruction.

5. The method according to claim 2, characterized in that: The time synchronization condition is that the interference generation delay time is equal to the lead delay time minus the interference trigger delay time, plus a preset synchronization constant, wherein the preset synchronization constant is related to the accuracy of the relay that triggers the interference source to generate the interference signal.

6. The method according to claim 1, characterized in that The interference trigger delay time is the average delay time between the interference synchronization control module receiving the synchronization interference control instruction and outputting the interference signal.

7. The method according to any one of claims 1 to 6, characterized in that The chip under test outputs a no-operation instruction within the lead delay time.

8. An interference synchronization system for chip reliability testing, characterized in that: include: The chip under test, interference synchronization control module, relay and interference source, The chip under test is used to output a synchronous interference control instruction to the interference synchronization control module within the execution function body of the sensitive instruction, wherein there is a lead delay time between the output time of the synchronous interference control instruction and the execution time of the sensitive instruction; The interference synchronization control module is used to wait for the interference generation delay time to end after receiving the synchronous interference control instruction output by the chip under test, and control the relay to trigger the interference source to generate and output an interference signal when the interference generation delay time ends, wherein there is a specific time relationship between the interference generation delay time and the lead delay time and the pre-measured interference trigger delay time to ensure that the interference signal can be synchronously intervened in the execution process of the sensitive instruction.

9. A computer-readable storage medium having a program stored thereon, characterized in that: When the program is executed by a processor, the interference synchronization method for chip reliability testing according to any one of claims 1 to 7 is implemented.

10. An electronic device, characterized in that: The electronic device includes at least one processor, and at least one memory and a bus connected to the processor; wherein the processor and the memory communicate with each other through the bus; the processor is used to call program instructions in the memory to execute the interference synchronization method for chip reliability testing as described in any one of claims 1 to 7.

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