PMIC multi-channel time sequence fault detection circuit

Abstract

The embodiment of the invention provides a PMIC multi-channel time sequence fault detection circuit, which belongs to the technical field of circuit testing and signal fault detection and comprises an enable signal generation module, a logic control module, an output channel module and a fault monitoring module. The enable signal generation module generates a multi-channel enable signal according to a user configuration connection signal and a system enable signal, the logic control module performs logic operation on the multi-channel enable signal to generate a logic enable signal, and the output channel module generates a channel output signal and a soft start signal according to the logic enable signal and a channel reference voltage signal. And the fault monitoring module generates a fault logic signal. According to the embodiment of the invention, redundancy design is carried out on the enable signal of the fault detection circuit, time sequence errors generated by a single time module architecture or layout are eliminated, it is ensured that channels are accurately started in sequence according to user configuration connection signals, and the time sequence control requirement of ASIL D is met.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of circuit testing and signal fault detection, and specifically to a PMIC multi-channel timing fault detection circuit. Background Art

[0002] Power Management Integrated Circuits (PMIC) is a general-purpose power module whose main function is to manage and control power in electronic systems, including voltage conversion, current control, power rail management, power monitoring, fault diagnosis and timing control. PMIC has the characteristics of configurability, programmability, high integration, high efficiency and precise power-on timing, providing scalable, safe and flexible solutions for automobiles and industries. With the development of electric and intelligent vehicles, the market demand for functional safety PMIC is increasing. The power-on sequence of each module in a complex system is crucial, and the wrong power-on sequence may cause damage to the application module.

[0003] like Figure 1A As shown, in the related art, the PMIC multi-channel power-on timing is as follows: VIN is the PMIC power supply, EN is the enable signal, VOUT1~VOUT[x] correspond to the multi-channel output, and the user configures the power-on sequence of the PMIC output channel through ON_Delay. The safety mechanism designed in the embodiment of the present application is expected to ensure that VOUT[x] is powered on at the power-on time T[x] when the user configures the turn-on signal ON_Delay[x]. Summary of the invention

[0004] The main purpose of the embodiments of the present application is to provide a PMIC multi-channel timing fault detection circuit to solve the problem of incorrect power-on sequence of device modules in the related art.

[0005] According to one aspect of an embodiment of the present application, a PMIC multi-channel timing fault detection circuit is provided, including an enable signal generating module, a logic control module, an output channel module, and a fault monitoring module, wherein: the enable signal generating module is configured to generate a multi-channel enable signal according to a user-configured connection signal and a system enable signal; the logic control module is configured to receive the multi-channel enable signal, perform a logic operation on the multi-channel enable signal, and generate a corresponding logic enable signal; the output channel module is configured to generate a channel output signal and a soft start signal according to the logic enable signal and a channel reference voltage signal; the fault monitoring module is configured to generate a fault logic signal according to the logic enable signal, the soft start signal, and the channel output signal.

[0006] According to at least one implementation of the embodiments of the present application, the enable signal generating module includes a first timing module and a second timing module, the first timing module and the second timing module are respectively used to receive the user configuration connection signal and the system enable signal, the multi-channel enable signal includes a first channel enable signal and a second channel enable signal, the first timing module is used to output the first channel enable signal, and the second timing module is used to output the second channel enable signal.

[0007] According to at least one implementation of the embodiments of the present application, the logic enable signal includes a first logic enable signal and a second logic enable signal, the first logic enable signal is the result of a logical AND operation of the first and second channel enable signals, and the second logic enable signal is the result of a logical OR operation of the first and second channel enable signals.

[0008] According to at least one embodiment of the embodiments of the present application, a first logic AND gate and a first logic OR gate are provided in the logic control module, the input end of the first logic AND gate receives the first and second channel enable signals, the output end of the first logic AND gate outputs the first logic enable signal, the input end of the first logic OR gate receives the first and second channel enable signals, and the output end of the first logic OR gate outputs the second logic enable signal.

[0009] According to at least one implementation of the embodiments of the present application, the output channel module includes a first logic enable unit and a second logic enable unit, the logic enable signal includes a first logic enable signal and a second logic enable signal, the second logic enable signal is input into the second logic enable unit, the second logic enable unit outputs a channel reference voltage and a soft start signal, the first logic enable signal and the channel reference voltage are input into the first logic enable unit, and the first logic enable unit outputs the channel output signal.

[0010] According to at least one implementation of the embodiments of the present application, when the second logic enable signal is at a high level, the generated channel reference voltage and soft start signal are both at a high level.

[0011] According to at least one embodiment of the embodiments of the present application, the fault monitoring module includes a third logic enable unit and a second logic AND gate, the third logic enable unit is used to input the channel output signal and the second logic enable signal, the third logic enable unit outputs a normal start signal, and the second logic AND gate is used to input the normal start signal and the soft start signal, and output a fault signal.

[0012] According to at least one implementation of the embodiments of the present application, a second logic OR gate is included between the second logic AND gate and the third logic enable unit, the input end of the second logic OR gate is connected to the third logic enable unit, and the output end of the second logic OR gate is connected to the second logic AND gate.

[0013] According to at least one implementation of the embodiments of the present application, the third logic enable unit outputs a first judgment signal and a second judgment signal, the first judgment signal and the second judgment signal are logically ORed through a second logic OR gate, and the operation result output by the second logic OR gate is sent to a second logic AND gate.

[0014] According to at least one embodiment of the embodiments of the present application, when the second logic enable signal is a high level and the channel output signal is a high level, the operation result of the second logic OR gate output is a low level to start normally; when the second logic enable signal is a high level and the channel output signal is a low level, the operation result of the second logic OR gate output is a high level to start a fault.

[0015] The beneficial technical effects of the embodiments of the present application are: The PMIC multi-channel timing fault detection circuit provided in the embodiment of the present application generates a heterogeneous multi-channel enable signal, performs logical operations on the multi-channel enable signal through a logic control module, generates a corresponding logic enable signal and a soft start signal, performs logical judgment according to the status of the logic enable signal and the soft start signal, outputs a corresponding fault logic signal, and performs redundant design on the enable signal, thereby eliminating the timing error caused by a single time module architecture or layout, ensuring that the channel is started accurately and sequentially according to the user-configured connection signal, and meeting the timing control requirements of ASIL D.

[0016] The PMIC multi-channel timing fault detection circuit of the embodiment of the present application makes timing faults no longer failures that cannot be monitored and controlled. The circuit design adopts a redundant module architecture to detect timing errors caused by physical layout or other hardware failures. If the output channel is not started according to the user-configured turn-on signal, fault reporting can be implemented to support the design requirements of ASILD functional safety products. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific implementation methods of the embodiments of the present application or the technical solutions in the related technologies, the drawings required for use in the specific implementation methods or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some implementation methods of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1It is an application scenario framework diagram of an embodiment of the present application; Figure 1A It is the timing diagram of PMIC multi-channel power-on; Figure 2 is a circuit schematic diagram of an enable signal generating module; Figure 3 It is the circuit schematic diagram of the logic control module; Figure 4 It is the circuit schematic diagram of the output channel module; Figure 4A It is the circuit schematic diagram of the BUCK circuit module and the timing module in the output channel module; Figure 5 It is the circuit schematic diagram of the fault monitoring module; Figure 6 It is the overall circuit schematic diagram of the PMIC multi-channel timing fault detection circuit; Figure 7 It is a timing diagram of the PMIC multi-channel timing fault detection circuit. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only implementation methods of a part of the embodiments of the present application, rather than all implementation methods. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the embodiments of the present application.

[0020] It should be noted that the terms "first", "second", etc. in the specification and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0021] In addition, the terms "installed", "set", "provided with", "connected", "connected", and "socketed" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0022] like Figure 1 Combined with Figure 1A As shown, in the related art, the power-on timing of the automotive or industrial PMIC power supply channel is generated by only one time module. This structure is a typical single point failure, that is, if a single timerA module or timerB module generates a random failure, it will cause hardware failure, making the channel power-on abnormal, thereby affecting the normal operation of the entire system. To this end, the embodiment of the present application proposes the following technical solution, which includes an enable signal generation module A, a logic control module B, an output channel module C, and a fault monitoring module D: The enable signal generation module A is configured to generate heterogeneous multi-channel enable signals according to the user-configured on-signal ON_DELAY[x] and the system enable signal SYS_EN. The enable signal generation module A provides a redundant design and can generate heterogeneous multi-channel enable signals, thereby avoiding single point failures existing in related technologies. The user-configured on-signal ON_DELAY[x] can be a delay time pre-set in the system or circuit, so that a certain output or event occurs after a certain delay after the input signal is activated.

[0023] The logic control module B is configured to receive the multi-channel enable signal sent from the enable signal generation module A, perform logic operations on the multi-channel enable signal, and generate corresponding logic enable signals.

[0024] The output channel module C is configured to generate a channel output signal and a soft start signal according to a logic enable signal and a channel reference voltage signal, and record a soft start time Tss when generating the soft start signal.

[0025] The fault monitoring module D is configured to generate a fault logic signal according to the logic enable signal, the soft start signal and the channel output signal.

[0026] Figure 1The content shown is one of the main application scenarios of the embodiment of the present application. In this main application scenario, through the collaborative work of multiple modules, the power-on sequence of each module in the complex system is effectively managed and fault monitored. Heterogeneous multi-channel enable signals are generated through redundant design, avoiding the risk of single point failure, thereby improving the overall reliability of the system, being able to monitor the system status in real time, accurately control the generation of various enable signals, and generate corresponding fault logic signals in real time to determine the stability and safety of the power-on sequence.

[0027] like Figure 2 The circuit schematic diagram of the enable signal generating module A shown in FIG. 1 includes a first timing module timerA and a second timing module timerB. The first timing module timerA and the second timing module timerB are respectively used to receive the user configuration connection signal ON_DELAY[x] and the system enable signal SYS_EN, that is, the first timing module timeA receives the user configuration connection signal ON_DELAY[x] and the system enable signal SYS_EN, and the second timing module timeB receives the user configuration connection signal ON_DELAY[x] and the system enable signal SYS_EN. When the user configuration connection signal ON_DELAY[x] and the system enable signal SYS_EN are respectively input between the first and second timing modules timeA and timeB, the first timing module timeA outputs a first channel enable signal ENA[x], and the second timing module timeB outputs a second channel enable signal ENB[x]. The first channel enable signal ENA[x] and the second channel enable signal ENB[x] will be used as inputs of the logic control module B for the next step of processing.

[0028] like Figure 3 The circuit schematic diagram of the logic control module B shown in the figure, in which the logic enable signal includes a first logic enable signal EN_BUCK[x] and a second logic enable signal EN_SS_VM[x]. The first logic enable signal EN_BUCK[x] is the result of a logic AND operation of the first channel enable signal ENA[x] and the second channel enable signal ENB[x]. The second logic enable signal EN_SS_VM[x] is the result of a logic OR operation of the first channel enable signal ENA[x] and the second channel enable signal ENB[x]. When the first logic enable signal EN_BUCK[x] and the second logic enable signal EN_SS_VM[x] are both 1 (high level), a channel output signal VOUT[x] is generated.

[0029] like Figure 4The output channel module C shown in the figure has input signals of the first logic enable signal EN_BUCK[x] and the second logic enable signal EN_SS_VM[x]. After the second logic enable signal EN_SS_VM[x] is input into the output channel module C, a channel reference voltage signal Vref_SS[x] and a soft start signal SSOK[x] are generated. When the first logic enable signal EN_BUCK[x] and the channel reference voltage signal Vref_SS[x] are both 1 (high level), the channel output signal VOUT[x] is 1, that is, the corresponding output channel is powered on.

[0030] like Figure 4A As shown, in some embodiments, the output channel module C includes a BUCK circuit module BUCK[x] and a timing module SS[x], wherein the BUCK circuit module BUCK[x] includes a control logic module, an upper power tube Q1, a lower power tube Q2, a first inductor L1, and a filter capacitor Cout, the sources of the upper power tube Q1 and the lower power tube Q2 are respectively connected to the control logic module, the drain of the upper power tube Q1 is connected to the PMIC power supply VIN, the source of the upper power tube Q1 is connected to the drain of the lower power tube Q2, the source of the lower power tube Q2 is grounded, one end of the first inductor L1 is connected between the source of the upper power tube Q1 and the drain of the lower power tube Q2, the other end of the first inductor L1 is used for outputting the channel output signal VOUT[x], one end of the filter capacitor Cout is connected to the first inductor L1, and the other end is grounded. The function of the timing module SS[x] is to control the soft start time of VOUT.

[0031] The working principle of the BUCK circuit module BUCK[x] can be briefly described as including two stages: (1) Switch on stage: The upper power tube Q1 is closed, and the lower power tube Q2 is reverse biased and cut off; The input voltage Vin is directly applied to the inductor and the load; The current of the first inductor L1 increases linearly, and the inductor stores energy; When the inductor current is greater than the load current, the capacitor is charged and the output voltage VOUT[x] gradually increases.

[0032] (2) Switch off stage: The upper power tube Q1 is disconnected, and the inductor current needs to form a loop through the lower power tube Q2; The inductor releases the stored energy and maintains the load current; The inductor current decreases linearly. When the inductor current is less than the load current, the capacitor discharges and the output voltage of the channel output signal VOUT[x] decreases.

[0033] Exemplarily, the BUCK circuit module BUCK[X] may adopt a synchronous step-down DC-DC converter, and utilize the synchronous step-down DC-DC converter to generate a channel output signal and a soft start signal based on the Buck circuit principle.

[0034] like Figure 5 The fault monitoring module D shown in the figure includes a third logic enable unit VM[x] and a second logic AND gate A2 in the fault monitoring module D. The third logic enable unit VM[x] is used to input the channel output signal VOUT[x] and the second logic enable signal EN_SS_VM[x]. The third logic enable unit VM[x] outputs a normal start signal UV / OV (when UV / OV=0, it indicates that the signal is started normally). The second logic AND gate A2 is used to input the normal start signal UV / OV=0 and the soft start signal SSOK[x], and output the fault signal ERROR. In some embodiments, a second logic OR gate U2 is included between the second logic AND gate A2 and the third logic enable unit VM[x]. The input end of the second logic OR gate U2 is connected to the third logic enable unit VM[x], and the output end of the second logic OR gate U2 is connected to the second logic AND gate A2. The third logic enable unit VM[x] outputs a first judgment signal UV[x] and a second judgment signal OV[x]. The first and second judgment signals are logically ORed through a second logic OR gate U2, and the operation result OVUV is output. <x>The signal is sent to the second logic AND gate A2, and the output end of the second logic AND gate A2 is used to output a fault signal ERROR.

[0035] Exemplarily, the third logic enable unit VM[x] can be a comparator, in which a reference voltage is set, and the channel output signal VOUT[x] is compared with the reference voltage. If the channel output signal VOUT[x] is greater than the reference voltage, the second judgment signal OV[x] (overvoltage signal) is output; if the channel output signal VOUT[x] is less than the reference voltage, the first judgment signal UV[x] (undervoltage signal) is output; if the channel output signal VOUT[x] is equal to the reference voltage, it is a normal state.

[0036] When the corresponding channel starts normally, that is, the channel output signal VOUT[x] and the second logic enable signal EN_SS_VM[x] are both equal to 1, the fault monitoring module D outputs a normal start signal, that is, the operation result OVUV <x>=0, the operation result is OVUV <x>The soft start signal SSOK[x] is sent to the second logic AND gate A2, and the second logic AND gate A2 outputs the fault signal ERROR as 0, and no fault reporting is performed.

[0037] When the corresponding channel is not started normally, that is, the second logic enable signal EN_SS_VM[x]=1, and the channel output signal VOUT[x]=0, the fault monitoring module D will output the operation result OVUV <x>=1. Operation result OVUV <x>The soft start signal SSOK[x] is sent to the second logic AND gate A2, and the second logic AND gate outputs the fault signal ERROR as 1 to report the fault.

[0038] like Figure 6 Combined with Figure 7 and Figure 1 As shown, the following embodiment will illustrate the implementation process of the PMIC multi-channel timing fault detection circuit. Through the OTP configuration of the user configuration on-signal ON_DELAY[x] of the corresponding channel, the output channel starts the timing of the output channel output signal VOUT2-VOUTX according to the user configuration on-signal ON_DELAY[x]. In this process, when the system enable signal SYS_EN and the user configuration on-signal ON_DELAY[x] are both 1, the channel output signal VOUT[x]=1.

[0039] The user-configured on-signal ON_DELAY[x] generates the corresponding first channel enable signal ENA[x] and second channel enable signal ENB[x] through the first timing module TimerA and the second timing module TimerB, and then performs a logic operation in the logic control module B, generates the first logic enable signal EN_BUCK[x] through the logic AND operation of the first channel enable signal ENA[x] and the second channel enable signal ENB[x], generates the second logic enable signal EN_SS_VM[x] through the logic OR operation of the first channel enable signal ENA[x] and the second channel enable signal ENB[x], and then performs a logic operation in the output channel module C to obtain the channel reference voltage Vref_SS[x] and the soft start signal SSOK[x], and then obtains the first and second judgment signals OV[x] according to various logic operation units in the fault monitoring module D and outputs the corresponding logic operation result OVUV <x>, the fault signal ERROR is output only when the soft start signal SSOK[x]=1, to avoid error reporting when the channel has not been established during the system startup phase.

[0040] The channel output signal VOUT[x] starts at time T0, considering the following working conditions: Normal state: There is no timing error between the first timing module TimerA and the second timing module TimerB, T_ENA[x] and T_ENB[x]=T0, EN_SS[x]= EN_BUCK[x]= EN_VM[x]=1, SSOK[x]=1, UV / OV[x]=0, channel T0 starts normally, and RESET remains high without fault.

[0041] Fault state: A timing module Timer is advanced, assuming T_ENB[x]=T_ENA[x]+ΔT; Fault state: a timing module Timer delay, assuming T_ENB[x]=T_ENA[x]-ΔT; Considering the four abnormal states in the attached figure, all of them can report faults after the soft start time (Tss), realizing precise control of the power-on timing.

[0042] As shown in Table 1, Table 1 is the circuit feedback result for timing errors: Table 1

[0043] In the description of the specification of the embodiments of the present application, the description with reference to the terms "some embodiments", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0044] In the several embodiments provided in the embodiments of the present application, it should be understood that the disclosed circuits and their principles and implementation schemes can be implemented in other ways, that is, the device embodiments described above are merely illustrative. In some embodiments, the division of units is only a logical function division, and there may be other division methods in actual implementation; for example, multiple units or components can be combined or integrated into another system, or some features can be ignored, or certain instructions are not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms not shown.

[0045] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and set in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition, they may be divided into multiple submodules or subunits or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive, all features disclosed in the specification of the embodiments of the present application (including the corresponding claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in the specification of the embodiments of the present application (including the corresponding claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, rather than to limit them. Although the embodiments of the present application have been described in detail with reference to the aforementioned specific implementation methods, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned specific implementation methods, or replace some or all of the technical features therein with equivalents, and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.< / x> < / x> < / x> < / x> < / x> < / x>

Claims

1. A PMIC multi-channel timing fault detection circuit, characterized in that: It includes an enable signal generation module, a logic control module, an output channel module, and a fault monitoring module, wherein: The enable signal generating module is configured to generate a multi-channel enable signal according to a user-configured connection signal and a system enable signal; The logic control module is configured to receive the multi-channel enable signal, perform a logic operation on the multi-channel enable signal, and generate a corresponding logic enable signal; The output channel module is configured to generate a channel output signal and a soft start signal according to the logic enable signal and the channel reference voltage signal; The fault monitoring module is configured to generate a fault logic signal according to the logic enable signal, the soft start signal and the channel output signal.

2. The PMIC multi-channel timing fault detection circuit according to claim 1, characterized in that: The enable signal generating module includes a first timing module and a second timing module, the first timing module and the second timing module are respectively used to receive the user configuration connection signal and the system enable signal, the multi-channel enable signal includes a first channel enable signal and a second channel enable signal, the first timing module is used to output the first channel enable signal, and the second timing module is used to output the second channel enable signal.

3. The PMIC multi-channel timing fault detection circuit according to claim 1, characterized in that: The logic enable signal includes a first logic enable signal and a second logic enable signal, wherein the first logic enable signal is a result of a logic AND operation of the first and second channel enable signals, and the second logic enable signal is a result of a logic OR operation of the first and second channel enable signals.

4. The PMIC multi-channel timing fault detection circuit according to claim 3, characterized in that: The logic control module is provided with a first logic AND gate and a first logic OR gate, the input end of the first logic AND gate receives the first and second channel enable signals, the output end of the first logic AND gate outputs the first logic enable signal, the input end of the first logic OR gate receives the first and second channel enable signals, and the output end of the first logic OR gate outputs the second logic enable signal.

5. The PMIC multi-channel timing fault detection circuit according to claim 1, characterized in that: The output channel module includes a first logic enable unit and a second logic enable unit, the logic enable signal includes a first logic enable signal and a second logic enable signal, the second logic enable signal is input into the second logic enable unit, the second logic enable unit outputs a channel reference voltage and a soft start signal, the first logic enable signal and the channel reference voltage are input into the first logic enable unit, and the first logic enable unit outputs the channel output signal.

6. The PMIC multi-channel timing fault detection circuit according to claim 5, characterized in that: When the second logic enable signal is at a high level, the generated channel reference voltage and soft start signal are both at a high level.

7. The PMIC multi-channel timing fault detection circuit according to claim 1, characterized in that: The fault monitoring module includes a third logic enable unit and a second logic AND gate. The third logic enable unit is used to input the channel output signal and the second logic enable signal. The third logic enable unit outputs a normal start signal. The second logic AND gate is used to input the normal start signal and the soft start signal and output a fault signal.

8. The PMIC multi-channel timing fault detection circuit according to claim 7, characterized in that: A second logic OR gate is included between the second logic AND gate and the third logic enable unit, the input end of the second logic OR gate is connected to the third logic enable unit, and the output end of the second logic OR gate is connected to the second logic AND gate.

9. The PMIC multi-channel timing fault detection circuit according to claim 8, characterized in that: The third logic enabling unit outputs a first judgment signal and a second judgment signal, the first judgment signal and the second judgment signal are subjected to a logic OR operation through a second logic OR gate, and the operation result output by the second logic OR gate is sent to a second logic AND gate.

10. The PMIC multi-channel timing fault detection circuit according to claim 9, characterized in that: When the second logic enable signal is at a high level and the channel output signal is at a high level, the operation result output by the second logic OR gate is a low level to start a normal state; When the second logic enable signal is at a high level and the channel output signal is at a low level, the operation result output by the second logic OR gate is a high level that starts a fault.

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