FPGA-based closed-loop tracking position solver for inductive synchronizer and its design method

Abstract

An FPGA-based closed-loop tracking position solver for an inductive synchronizer and its design method belong to the field of industrial automation. The position solver includes a signal-connected detection module, a tracker module, and a sine-cosine transform module; wherein: the detection module is used to perform carrier multiplication and filtering on the two-phase output electromotive force of the inductive synchronizer; the tracker module is used to cross-multiply the filtered signal with the output of the sine-cosine transform module and then take the difference as the output, and after passing through an integrator cascade proportional-integral controller, the output of the proportional-integral tracker is used as the tracking angle, and is used as the output for subsequent compensation; the sine-cosine transform module is used to use the result of amplitude periodization of the tracking angle according to 360° as the input of the sine-cosine solution, and then pass the output of the sine-cosine solution as the feedback signal to the tracker module. The present invention enhances the anti-interference capability by optimizing the algorithm structure and ensures the real-time performance of the algorithm by utilizing parallel processing technology.

Description

Technical Field

[0001] The present invention belongs to the field of industrial automation, and in particular relates to an FPGA-based inductive synchronizer closed-loop tracking position solver and a design method thereof. Background Art

[0002] In recent years, with the advancement of science and technology, the industrial automation sector has placed increasingly stringent requirements on the real-time performance and accuracy of its angle measurement systems. This is especially true for harsh environments, which place even higher demands on the reliability of angle measurement components. For applications requiring both high-precision positioning and high reliability, inductive synchronizers are a suitable choice.

[0003] Inductive synchronizer angle calculation methods are categorized by their structure: open-loop and closed-loop. The open-loop approach is simpler and faster, often used in scenarios with less demanding device requirements and minimal environmental fluctuations. The closed-loop approach, on the other hand, offers greater system-level interference resistance and is more suitable for complex environments.

[0004] FPGA is a programmable logic device that can be programmed at the hardware level. It is highly flexible and reconfigurable. It contains a large number of programmable logic units and interconnection resources. It can be designed and programmed using hardware description language. Its advantages lie in strong parallel processing capabilities, low latency, low power consumption, and the ability to implement complex logic and algorithms.

[0005] The inductive synchronizer processing system has very high requirements for signal sampling speed and accuracy. The subsequent angle solution structure is relatively complex and has certain constraints on the real-time performance of each internal module. The properties of FPGA can meet these requirements. Summary of the Invention

[0006] The purpose of the present invention is to solve the above problems existing in the prior art and to provide an FPGA-based inductive synchronizer closed-loop tracking position solver and a design method thereof.

[0007] The present invention enhances the anti-interference capability by optimizing the algorithm structure and ensures the real-time performance of the algorithm by utilizing the parallel processing technology.

[0008] To achieve the above object, the technical solution adopted by the present invention is:

[0009] An FPGA-based closed-loop tracking position solver for an inductive synchronizer includes a detection module, a tracker module, and a sine-cosine transform module, which are sequentially connected in signal.

[0010] The detection module is used to obtain the envelope signals of the sine phase and cosine phase by synchronous demodulation of the collected induced electromotive force digital signals with orthogonal sine and cosine phases, and transmit the envelope signals to the tracker module;

[0011] The tracker module is used to cross-multiply the sine and cosine phase envelope signals with the cosine and sine of the feedback output angle, and then take the difference. The result is sent to the integrator and proportional-integral controller in sequence as the tracking error, and the final tracked value is output to complete the angle tracking process. The data is then passed to the sine-cosine transform module for feedback processing and as output for subsequent compensation.

[0012] The sine-cosine transform module is used to build the CORDIC IP core. It transforms the angle output by the tracker module into sine and cosine respectively, and feeds them back to the input end respectively.

[0013] Furthermore, the detection module includes a carrier multiplication module and a filtering module, and the carrier multiplication module and the filtering module are signal-connected; wherein:

[0014] The carrier multiplication module is used to multiply the collected two-phase output electromotive force with the same-phase carrier signal corresponding to the output potential. The specific formula is as follows:

[0015]

[0016] The multiplication is implemented using the multiplier IP core, E A With E B The induced electromotive force of the sine and cosine phases output by the induction synchronizer is orthogonal to each other, E A Phase ratio E B Lag 90°; E′ A and E′ B The signal is a low-pass filtered signal after the sine and cosine two-phase carriers are multiplied. ω is the excitation frequency of the induction synchronizer, and β is the phase of the induction synchronizer excitation signal. The sin(ωt+β) signal is generated by the DDS IP core.

[0017] The filtering module is used to filter the envelope signal after carrier multiplication through an FIR low-pass filter and pass the filtered envelope signal to the tracker module.

[0018] Furthermore, the filtering module is used to filter the envelope signal after carrier multiplication through an FIR low-pass filter and pass the filtered envelope signal to the tracker module, specifically:

[0019] The filtering module converts E′ A and E′ BThrough the FIR low-pass filter, the sampling frequency, cutoff frequency, window function and filter order of the FIR low-pass filter are set in the MATLAB filter designer. After the cutoff frequency is 1 / 10 of the excitation frequency of the induction synchronizer, the filter coefficients are derived and loaded into the FIR Compiler IP core. The sine and cosine phase envelope signals are filtered and used as the signal E" of the input tracker module. A and E″ B .

[0020] Furthermore, the tracker module includes a comparison module and a type II tracker, and the comparison module is signal-connected to the type II tracker; wherein:

[0021] Comparison module, used to convert signal E″ A and E″ B Multiply the cosine and sine values ​​of the final output signal φ respectively, and then make the difference to obtain the processed result ∈rror; the specific formula is as follows:

[0022] ∈rror=E″ A cosφ-E″ B sinφ

[0023] in: The cosine and sine values ​​are implemented using the CORDIC IP core. The number of bits of the final output angle is determined. Based on the required delay, the number of bits and accuracy of the CORDIC output value are determined.

[0024] The multiplication in the above formula is implemented using the multiplier IP core, and the error data uses a 32-bit fixed-point number with 27 decimal places;

[0025] The Type II tracker takes the error result processed by the comparison module as input, first feeds it into the integrator, multiplies it by a coefficient, and then feeds it into the proportional-integral controller. Assuming the input of the proportional-integral link is r(t) and the output is c(t), the expression is:

[0026] c(t)=K p r(t)+K i ∫r(t)dt

[0027] The integrator is implemented using an accumulator. A gain needs to be cascaded at the front end of the accumulator. The gain and the integrator share a multiplier IP core as input to compensate for the sampling frequency multiplied by the accumulator relative to the integrator. The proportional link of the proportional-integral controller uses a multiplier IP core. The integral link has the same structure as the integrator. The addition of the proportional and integral results requires an adder IP core. The output of the proportional-integral controller is the tracking angle output value φ.

[0028] Furthermore, the sine-cosine transform module is used to transform the angle output by the tracker module into sine and cosine respectively, and feed them back to the input end respectively; specifically:

[0029] The sine-cosine transform module performs a signal carry transformation on the tracking angle output value φ of the tracker module according to an amplitude of 360° as a cycle, and inputs the result of this transformation into the CORDIC IP core as the final output angle.

[0030] A design method for a closed-loop tracking position solver for an inductive synchronizer based on FPGA, the design method comprising the following steps:

[0031] Step 1: Use the Simulink model library and written functions to simulate the closed-loop tracking position solver and use this as the evaluation criteria for hardware functional simulation;

[0032] Step 2: Implement the closed-loop tracking position solver module using Verilog HDL language;

[0033] Step 3: The closed-loop tracking position solver module involves addition, multiplication, and sine and cosine operations, which are processed by calling the IP core in the Vivado environment;

[0034] Step 4: Perform functional simulation of the angle calculation algorithm built using the hardware description language under Vivado's SIMULATION. Compare the simulation results with those of the Simulink model to determine the correctness of the algorithm function.

[0035] The beneficial effects of the present invention over the prior art are: the design method of the present invention has obvious advantages over the currently commonly used DSP software architecture. The method has the following advantages:

[0036] 1. The algorithm structure has strong anti-interference ability;

[0037] 2. The entire algorithm can be integrated into an FPGA;

[0038] 3. The system has strong real-time performance.

[0039] The FPGA-based closed-loop tracking position solver for induction synchronizers proposed in this paper achieves high-precision and high-stability position measurement, making it particularly suitable for industrial automation. The solver's modular design simplifies user experience, requiring only configuration of appropriate adjustment parameters to meet specific requirements. It also enables dynamic adjustment of the induction synchronizer to achieve high-precision measurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1This is a flow chart of a design method of an FPGA-based inductive synchronizer closed-loop tracking position solver of the present invention.

[0041] Figure 2 This is the Sinulink simulation model diagram of the closed-loop tracking method.

[0042] Figure 3 This is the Simulink simulation result diagram.

[0043] Figure 4 This is the simulation result diagram under the Vivado environment.

[0044] Figure 5 This is the FPGA flow chart of the implementation example. DETAILED DESCRIPTION

[0045] Specific embodiment 1: This embodiment discloses a closed-loop tracking position solver based on FPGA induction synchronizer, the position solver includes a detection module, a tracker module and a sine-cosine transform module connected in sequence; the detection module, the tracker module and the sine-cosine transform module are connected in sequence according to the signal. Figure 1 Build the system using hardware description language;

[0046] The detection module is used to obtain the envelope signals of the sine phase and cosine phase using a synchronous demodulation method (which is a prior art) from the collected sine phase and cosine phase orthogonal induced electromotive force digital signals, and transmit the envelope signals to the tracker module;

[0047] The tracker module is used to cross-multiply the envelope signals of the sine and cosine phases with the cosine and sine of the feedback output angle respectively (the sine phase is multiplied by the cosine of the feedback output angle, and the cosine phase is multiplied by the sine of the feedback output angle), then perform the subtraction and send the result as the tracking error to the integrator and proportional-integral controller in sequence, output the final tracked value, complete the angle tracking process, and pass the data to the sine-cosine transform module for feedback processing and as output for subsequent compensation;

[0048] The sine-cosine transform module is used to build the CORDIC IP core. It transforms the angle output by the tracker module into sine and cosine respectively, and feeds them back to the input end respectively.

[0049] Furthermore, the detection module includes a carrier multiplication module and a filtering module, and the carrier multiplication module and the filtering module are signal-connected (the detection module improves the efficiency and accuracy of signal processing by combining the carrier multiplication module and the filtering module); wherein:

[0050] The carrier multiplication module is used to multiply the collected two-phase output electromotive force with the same-phase carrier signal corresponding to the output potential. The specific formula is as follows:

[0051]

[0052] The multiplication (i.e., the two brackets on the right side of the equal sign are multiplication relations) is implemented using the multiplier IP core, E A With E B The induced electromotive force of the sine and cosine phases output by the induction synchronizer is orthogonal to each other, E A Phase ratio E B Lag 90°; E′ A and E′ B The signal is a low-pass filtered signal after the sine and cosine two-phase carriers are multiplied. ω is the excitation frequency of the induction synchronizer, and β is the phase of the induction synchronizer excitation signal. The sin(ωt+β) signal is generated by the DDS IP core.

[0053] The filtering module is used to filter the envelope signal after carrier multiplication through an FIR low-pass filter (to ensure the quality of the signal and the accuracy of tracking), and pass the filtered envelope signal to the tracker module.

[0054] Furthermore, the filtering module is used to filter the envelope signal after carrier multiplication through an FIR low-pass filter and pass the filtered envelope signal to the tracker module, specifically:

[0055] The filtering module converts E′ A and E′ B Through the FIR low-pass filter, the sampling frequency, cutoff frequency, window function and filter order of the FIR low-pass filter are set in the MATLAB filter designer. After the cutoff frequency is 1 / 10 of the excitation frequency of the induction synchronizer, the filter coefficients are derived and loaded into the FIR Compiler IP core. The sine and cosine phase envelope signals are filtered and used as the signal E" of the input tracker module. A and E″ B The effect is: improving the efficiency and effect of filtering, ensuring the quality of the signal and the accuracy of tracking.

[0056] Furthermore, the tracker module includes a comparison module and a type II tracker, and the comparison module is signal-connected to the type II tracker; wherein:

[0057] Comparison module, used to convert signal E″ A and E″ B Multiply the cosine and sine values ​​of the final output signal φ respectively, and then make the difference to get the processed result error; the specific formula is as follows:

[0058] error=E″ A cosφ-E″ Bsinφ

[0059] The cosine and sine values ​​of φ are implemented using the CORDIC IP core. The number of bits of the final output angle is determined, and the number of bits and accuracy of the CORDIC output value are determined based on the required delay.

[0060] The multiplication in the above formula is implemented using the multiplier IP core, and the error data uses a 32-bit fixed-point number with 27 decimal places;

[0061] The Type II tracker takes the error result processed by the comparison module as input, first feeds it into the integrator (the first-stage integral link), multiplies it by a coefficient, and then feeds it into the proportional-integral controller (the second-stage proportional-integral link). Assuming the input of the proportional-integral link is r(t) and the output is c(t), the expression is:

[0062] c(t)=K p r(t)+K i ∫r(t)dt

[0063] The integrator is implemented using an accumulator. A gain is cascaded to the front end of the accumulator. The gain and the integrator share a multiplier IP core as input to compensate for the accumulator's sampling frequency multiplication relative to the integrator. The proportional-integral controller (the second-stage proportional-integral link) uses a multiplier IP core for the proportional link. The integral link has the same structure as the integrator, and the addition of the proportional and integral results is implemented using an adder IP core (here, the outputs of the proportional and integral links, that is, the data formats of the two adder inputs, must be as consistent as possible, achieved through data truncation). The output of the proportional-integral controller is the tracking angle output value φ. This improves angle tracking accuracy and system stability.

[0064] Furthermore, the sine-cosine transform module is used to transform the angle output by the tracker module into sine and cosine respectively, and feed them back to the input end respectively; specifically:

[0065] The sine-cosine transform module performs a signal carry transformation on the tracking angle output value φ from the tracker module, with an amplitude of 360° as a cycle. The result of this transformation is input to the CORDIC IP core as the final output angle, thus achieving periodic signal processing.

[0066] Specific embodiment 2: This embodiment is a design method for a closed-loop tracking position solver for an inductive synchronizer based on FPGA as described in specific embodiment 1. The present invention uses MATLAB software in a Simulink environment to model and simulate a system for the uniform speed operation of an inductive synchronizer. The simulation mainly analyzes the two-phase output and position solution of the inductive synchronizer to verify the rationality and correctness of the algorithm and the entire system construction. The design method includes the following steps:

[0067] Step 1: Use the Simulink model library and written functions to simulate the closed-loop tracking position solver (angle calculation algorithm), and use this as the evaluation standard for hardware (FPGA) functional simulation;

[0068] Step 2: Implement the closed-loop tracking position solver module using Verilog HDL language;

[0069] Step 3: The closed-loop tracking position solver module involves addition, multiplication, and sine and cosine operations, which are processed by calling the IP core in the Vivado environment;

[0070] Step 4: Perform functional simulation of the angle calculation algorithm built using the hardware description language under Vivado's SIMULATION. Compare the simulation results with those of the Simulink model to determine the correctness of the algorithm function.

[0071] The present invention uses MATLAB software in the Simulink environment to model and simulate the system of the uniform speed operation of the induction synchronizer. The simulation mainly analyzes the two-phase output and position decoding of the induction synchronizer to verify the rationality and correctness of the algorithm and the construction of the entire system.

[0072] The design method of this invention utilizes a Simulink model library and written functions to simulate a closed-loop tracking angle calculation algorithm, using this as an evaluation criterion for FPGA functional simulation testing. Analysis of the closed-loop tracking algorithm reveals that the position solver primarily comprises a detection module, a tracking module, and a sine-cosine solver module. Figure 2 The following is a SinuLink simulation model diagram for the closed-loop tracking method (i.e., the SimuLink simulation model diagram for the feedback tracking solver). Following a top-down design approach, the various modules of the closed-loop tracking position solver were designed in the Vivado environment. Based on the previous analysis of the algorithm, the basic framework for implementing the closed-loop tracking position solver (closed-loop tracking angle solver) on an FPGA can be designed.

[0073] During the design and coding process, each functional module is simulated and verified step by step, and the results of FPGA simulation test correspond to the results of Simulink model simulation. The present invention selects Xilinx xc7z020clg400-2 as the loading carrier of bit stream.

[0074] Example 1:

[0075] This embodiment discloses a design method for a closed-loop tracking position solver for an inductive synchronizer based on an FPGA, which generally includes the following steps:

[0076] 1) Analyze the characteristics of the two-phase output signal of the induction synchronizer, determine the demodulation scheme and the characteristics of the angle change, and determine the type of tracker.

[0077] 2) Using Matlab software in Simulink environment, the feedback tracking method is modeled and simulated. The simulation results are as follows: Figure 3 As shown in Figure 1, it mainly includes tracking error and tracking angle. The simulation results of the model are used as a reference standard for FPGA algorithm design.

[0078] 3) Xilinx xc7z020clg400-2 chip is selected as the hardware platform, and Verilog HDL is used to implement the feedback tracking algorithm.

[0079] 4) Compile the code in the Vivado2017.4 environment and simulate each module of the software. On the premise that the functions of each module are correct, perform an overall simulation and compare the simulation results with the Simulink simulation results.

[0080] 5) Implement the module in a comprehensive manner and generate a bitstream to download to the board for onboard debugging.

[0081] The details of Example 1 include the following steps:

[0082] 1) The modules subdivided on FPGA are as follows Figure 5 As shown in the figure, the DDS IP core is used to simulate the digital signal of the two-phase electromotive force of the induction synchronizer input by the 16-bit AD converter in the actual system.

[0083] 2) The two-phase EMFs are transmitted to the detection module. This involves multiplying the two-phase output signals with a sinusoidal signal generated by the DDS IP core, which has the same frequency and phase as the induction synchronizer excitation signal. The signals are then passed through an FIR filter to produce the detected waveform. After adjusting the FIR filter's frequency characteristics in MATLAB's filter designer, a filter parameter file is generated. This file is then imported into the FIR compiler IP core in Vivado to implement the digital filter functionality.

[0084] 3) Multiply the filtered signal by the cosine and sine values ​​of the final output, and perform the subtraction using a subtractor to obtain the input to the tracking system. The sine and cosine transform of the final output angle is implemented using the CORDIC IP core.

[0085] 4) Determine that the tracker is a type II tracker, multiply the input of the tracking system and the gain through a multiplier, and input the multiplication result into the accumulator of the first stage.

[0086] 5) The output of the first-stage accumulator is fed into the subsequent proportional and integral modules. The proportional module multiplies the first-stage accumulator output by the proportional gain to produce an integral output. The integral module multiplies the first-stage accumulator output by the integral gain and feeds the multiplication result into the accumulator, which then outputs the integral output. The proportional and integral outputs are added together via an adder to produce the tracking result.

[0087] 6) Normalize the tracking results periodically and use them as input to the CORDIC IP core to obtain the final output results, such as Figure 4 As shown, Figure 4 It includes the demodulated output signal of the inductive synchronizer, the tracking error, and the normalized angle tracking signal.

[0088] The number of bits of all data in the above process is Figure 5 format to set it.

[0089] The above specific implementation methods or examples are only used to explain the technical solutions of the present invention and are not intended to limit the present application. The detailed description parts are regarded as conventional technical means or common knowledge in the field. Ordinary technicians in this field should understand that based on the design concept of the present application, the technical solutions recorded in the aforementioned implementation methods should be adaptively modified, or some or all of the technical features therein should be replaced by equivalents. These modifications and replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

[0090] The above are only preferred specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with this technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solutions and inventive concepts of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. An FPGA-based inductive synchronizer closed-loop tracking position solver, characterized by: The position solver includes a detection module, a tracker module and a sine-cosine transform module which are sequentially connected in signal; wherein: The detection module is used to obtain the envelope signals of the sine and cosine phases by synchronous demodulation from the collected digital signals of the induced electromotive force with orthogonal sine and cosine phases, and transmit the envelope signals to the tracker module; the detection module includes a carrier multiplication module and a filtering module, and the carrier multiplication module and the filtering module are signal-connected; wherein: The carrier multiplication module is used to multiply the collected two-phase output electromotive force with the same-phase carrier signal corresponding to the output potential. The specific formula is as follows: The multiplication is implemented using the multiplier IP core. and The sine and cosine phases of the induction synchronizer are orthogonal to each other and are the induced electromotive force. Phase ratio Lag 90°; and It is the signal after the sine and cosine two-phase carriers are multiplied and waiting for low-pass filtering. is the excitation frequency of the induction synchronizer, is the phase of the induction synchronizer excitation signal; The signal is generated by the DDS IP core; A filtering module is used to filter the envelope signal after carrier multiplication through an FIR low-pass filter and pass the filtered envelope signal to the tracker module; The tracker module is used to cross-multiply the sine and cosine phase envelope signals with the cosine and sine of the feedback output angle, and then take the difference. The result is sent to the integrator and proportional-integral controller in sequence as the tracking error, and the final tracked value is output to complete the angle tracking process. The data is then passed to the sine-cosine transform module for feedback processing and as output for subsequent compensation. The sine-cosine transform module is used to build the CORDIC IP core. It transforms the angle output by the tracker module into sine and cosine respectively, and feeds them back to the input end respectively.

2. The position resolver according to claim 1, wherein: The filtering module is used to filter the envelope signal after carrier multiplication through the FIR low-pass filter and pass the filtered envelope signal to the tracker module. Specifically: The filter module will and Through the FIR low-pass filter, the sampling frequency, cutoff frequency, window function and filter order of the FIR low-pass filter are set in the MATLAB filter designer. After the cutoff frequency is 1 / 10 of the excitation frequency of the induction synchronizer, the filter coefficients are derived and loaded into the FIR Compiler IP core. The sine phase and cosine phase envelope signals are filtered and used as the signals of the input tracker module. and .

3. The position resolver according to claim 2, wherein: The tracker module includes a comparison module and a type II tracker, and the comparison module is signal-connected to the type II tracker; wherein: Comparison module, used to convert the signal and The final output signal Multiply the cosine and sine values ​​of the sine and then make the difference to get the processed result. The specific formula is as follows: in: The cosine and sine values ​​are implemented using the CORDIC IP core. The number of bits of the final output angle is determined. Based on the required delay, the number of bits and accuracy of the CORDIC output value are determined. The multiplication in the above formula is implemented using the multiplier IP core. The data is a 32-bit fixed-point number with 27 decimal places; Type II tracker is used to compare the results processed by the module As input, it is first sent to the integrator, multiplied by a coefficient, and then sent to the proportional-integral controller; assuming the input of the proportional-integral link is r(t) and the output is c(t), the expression is: Among them: the integrator is implemented by an accumulator, and a gain needs to be cascaded at the front end of the accumulator. The gain and the integrator share a multiplier IP core as input to compensate for the sampling frequency of the accumulator multiplied by the integrator. The proportional link of the proportional-integral controller uses a multiplier IP core, and the integral link has the same structure as the integrator. The addition of the proportional and integral results needs to be implemented using an adder IP core. The output of the proportional-integral is the tracking angle output value. .

4. The position resolver according to claim 3, wherein: The sine-cosine transform module is used to transform the angle output by the tracker module into sine and cosine respectively, and feed them back to the input end respectively; specifically: The sine-cosine transform module converts the tracking angle output value of the tracker module into The signal is transformed with an amplitude of 360° as a cycle, and the result of this transformation is input into the CORDIC IP core as the final output angle.

5. A method for designing a closed-loop tracking position solver for an induction synchronizer based on FPGA according to any one of claims 1 to 4, characterized in that: The design method comprises the following steps: Step 1: Use the Simulink model library and written functions to simulate the closed-loop tracking position solver and use this as the evaluation criteria for hardware functional simulation; Step 2: Implement the closed-loop tracking position solver module using Verilog HDL language; Step 3: The closed-loop tracking position solver module involves addition, multiplication, and sine and cosine operations, which are processed by calling the IP core in the Vivado environment; Step 4: Perform functional simulation of the angle calculation algorithm built using the hardware description language under Vivado's SIMULATION. Compare the simulation results with those of the Simulink model to determine the correctness of the algorithm function.

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