Rapid control prototype test system and method for power system

Abstract

The embodiment of the invention relates to the technical field of semi-physical simulation, and discloses a rapid control prototype test system and method for a power system. The system comprises an upper computer used for establishing a CPU model, an FPGA model and a control algorithm of the CPU model and the FPGA model and converting the CPU model and the FPGA model into control information for a simulation machine; the simulation machine is used for bearing and operating a CPU model and an FPGA model, the CPU model adjusts level output by using a static synchronous compensator STATCOM model, the FPGA model is integrated with an Aurora communication IP core, and the Aurora communication IP core is used for performing data exchange with the simulation machine; the simulation machine is further used for controlling the CPU model and the FPGA model to operate according to the control information, collecting operation state information and feeding back the operation state information to the upper computer. Therefore, all-around debugging verification from the RCP of the rapid control prototype to the communication protocol is realized.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of semi-physical simulation, and in particular to a rapid control prototype testing system and method for an electric power system. Background Art

[0002] The Rapid Control Prototype (RCP) development method uses a combination of a rapid prototype controller and a real controlled object. Researchers only need to build and debug a simulation model containing the required control algorithm in the commercial software MATLAB / Simulink, and then use the rapid prototype controller to control the simulation machine and verify the control algorithm in a real-time environment. This can effectively overcome the difficulties in programming and developing complex control systems and improve R&D efficiency.

[0003] Currently, rapid control prototypes mostly simulate the voltage environment of two-level inverters. However, with the development of the power industry, power systems need to achieve higher output voltage and power to meet the needs of medium-high voltage and high-power applications. However, the current rapid control prototypes that simulate two-level inverters cannot meet more level requirements in the test scenarios, that is, they cannot simulate the Aurora protocol verification of SVG cascaded multi-level controllers. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a rapid control prototype test system and method for an electric power system, so as to realize all-round debugging and verification from rapid control prototype (RCP) to communication protocol.

[0005] To solve the above technical problems, an embodiment of the present invention provides a rapid control prototype test system for an electric power system, comprising: a host computer, used to establish a CPU model and an FPGA model, and their control algorithms, and convert them into control information for a simulator; a simulator, used to carry and run the CPU model and the FPGA model, wherein the CPU model uses a static synchronous compensator STATCOM model to adjust the level output, and the FPGA model integrates an Aurora communication IP core, and the Aurora communication IP core is used to exchange data with the simulator; the simulator is also used to control the operation of the CPU model and the FPGA model according to the control information, collect operating status information, and feed back the operating status information to the host computer.

[0006] An embodiment of the present invention also provides a rapid control prototype testing method for an electric power system, which is applied to the rapid control prototype testing system of the above-mentioned electric power system. The method includes: using system modeling software in a host computer to establish a CPU model and an FPGA model, and their control algorithms, and using a control module in the system modeling software to convert the control algorithms into control information for a simulation machine; the simulation machine controls the operation of the CPU model and the FPGA model carried by it according to the control information, and collects the operating status information of the CPU model and the FPGA model, and feeds back the operating status information to the host computer to obtain test results.

[0007] Compared with the prior art, the embodiment of the present invention builds a CPU model and an FPGA model in the system to achieve hardware and software adaptation. A static synchronous compensator STATCOM model is established in the CPU model, and the static synchronous compensator STATCOM model is used to adjust the level output. The Aurora communication IP core is integrated in the FPGA model to simulate the communication protocol of the real controller. By detecting the operating status of the CPU model and the FPGA model in the simulation environment, all-round debugging and verification from rapid control prototyping RCP to communication protocol is achieved.

[0008] In addition, the STATCOM model is a three-phase system model composed of a single-phase modular multilevel converter MMC model; wherein the voltage and current phases of each phase of the three-phase system model differ by 120 degrees.

[0009] In addition, the FPGA model also includes: an IO interface; the IO interface is used to realize data interaction between the FPGA model and the simulation machine.

[0010] In addition, the CPU model includes: a data framing and parsing model; the data framing and parsing model is used to generate and parse the communication data frames exchanged between the Aurora communication IP core and the simulation machine.

[0011] In addition, the communication data frame at least includes: a pulse width modulation PWM signal and capacitor voltage information.

[0012] In addition, the CPU model includes: a power grid model; the power grid model is used to simulate the voltage, frequency and load characteristics of the power grid.

[0013] In addition, the CPU model includes: a transformer model; the transformer model is used to simulate the voltage conversion and power transfer between the power grid and the static synchronous compensator STATCOM model.

[0014] In addition, the CPU model includes: a load model; the load model is used to simulate the load condition on the power grid.

[0015] In addition, the CPU model includes: a fault model; the fault model is used to simulate the fault situation occurring in the power grid. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0017] Figure 1 is a structural schematic diagram of a rapid control prototype test system for an electric power system according to an embodiment of the present invention;

[0018] Figure 2 is an equivalent circuit diagram of a single-phase MMC model of a rapid control prototype test system for an electric power system according to an embodiment of the present invention;

[0019] Figure 3 is a structural schematic diagram of a CPU model of a rapid control prototype test system for an electric power system according to an embodiment of the present invention;

[0020] Figure 4 is a structural schematic diagram of an FPGA model of a rapid control prototype test system for an electric power system according to an embodiment of the present invention;

[0021] Figure 5 is a structural schematic diagram of another rapid control prototype test system for an electric power system according to an embodiment of the present invention;

[0022] Figure 6 is a structural schematic diagram of a simulator of a rapid control prototype test system for an electric power system according to an embodiment of the present invention;

[0023] Figure 7 It is a schematic diagram of simulation results of optical port CH00 sending and CH01 receiving delay test of a rapid control prototype test system of an electric power system according to an embodiment of the present invention;

[0024] Figure 8 It is a schematic diagram of a simulation result of a CH00 sending data number verification test of a rapid control prototype test system of an electric power system according to an embodiment of the present invention;

[0025] Fig. 9 2 is a schematic diagram of simulation results of a CH00 data transmission validity verification test of a rapid control prototype test system for an electric power system according to an embodiment of the present invention;

[0026] Fig.10 The present invention is a flowchart of a rapid control prototype testing method for a power system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are provided to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented.

[0028] The following embodiments are divided for the convenience of description and shall not constitute any limitation on the specific implementation of the present invention. The embodiments may be combined with each other and referenced to each other without contradiction.

[0029] The embodiment of the present invention relates to a rapid control prototype test system for an electric power system, comprising: a host computer, which is used to establish a CPU model and an FPGA model, and a control algorithm thereof, and convert them into control information for a simulator; a simulator, which is used to carry and run the CPU model and the FPGA model, wherein the CPU model uses a static synchronous compensator STATCOM model to adjust the level output, and the FPGA model integrates an Aurora communication IP core, and the Aurora communication IP core is used to exchange data with the simulator; the simulator is also used to control the operation of the CPU model and the FPGA model according to the control information, collect operating status information, and feed back the operating status information to the host computer. In order to achieve all-round debugging and verification from rapid control prototype RCP to communication protocol. The implementation details of the rapid control prototype test system for an electric power system of this embodiment are described in detail below. The following content is only the implementation details provided for the convenience of understanding, and is not necessary for the implementation of this solution.

[0030] The rapid control prototype test system of the power system in this embodiment is as follows Figure 1 As shown, it specifically includes: a host computer 10, which is used to establish a CPU model 21 and a FPGA model 22, and their control algorithms, and convert them into control information for the simulator 20; the simulator 20, which is used to carry and run the CPU model 21 and the FPGA model 22, wherein the CPU model 21 uses a static synchronous compensator STATCOM model to adjust the level output, and the FPGA model 22 integrates an Aurora communication IP core, and the Aurora communication IP core is used to exchange data with the simulator 20; the simulator 20 is also used to control the operation of the CPU model 21 and the FPGA model 22 according to the control information, collect the operation status information, and feed back the operation status information to the host computer 10.

[0031] Compared with the prior art, the embodiment of the present invention builds a CPU model and an FPGA model in the system to achieve hardware and software adaptation. A static synchronous compensator STATCOM model is established in the CPU model, and the static synchronous compensator STATCOM model is used to adjust the level output. The Aurora communication IP core is integrated in the FPGA model to simulate the communication protocol of the real controller. By detecting the operating status of the CPU model and the FPGA model in the simulation environment, all-round debugging and verification from rapid control prototyping RCP to communication protocol is achieved.

[0032] The following is a detailed introduction to the different subsystems in the rapid control prototype test system of the power system:

[0033] The host computer can be a computer, server or other equipment. The underlying software installed in the host computer includes MATLAB / Simulink, easyPSST simulation toolbox based on MATLAB / Simulink, SCILAB, RTLAB, dSPACE, RTDS, CCS, Keil, etc. The underlying software MATLAB / Simulink is used to build mathematical models, including CPU models and FPGA models. RTLAB is used to manage the semi-physical simulation interface. After the software compiles the code, the mathematical model (CPU model and FPGA model) will be downloaded to the semi-physical CPU and FPGA development board of the simulator in separate cores. In addition, the host computer is also installed with the underlying software design kit VIVADO, which is used for data packet capture. The host computer is connected to the lower computer through the Joint Test Action Group (JTAG) line for operation.

[0034] The simulator carries a CPU model and an FPGA model. The CPU model includes a STATCOM model, which is used to adjust the level output. The STATCOM model is a three-phase system model composed of a single-phase modular multilevel converter MMC model; the voltage and current phases of each phase of the three-phase system model differ by 120 degrees. The single-phase modular multilevel converter MMC model is a mathematical model. The single-phase MMC equivalent circuit diagram is shown in Figure 2 As shown, the controlled voltage source 1 is connected to the signal Vsp; the controlled voltage source 2 is connected to the signal Vsn. The driving voltage of the controlled voltage source is calculated using the control pulse, and the DC current is determined by the coefficient k. The specific calculation logic is:

[0035] Vsp=Vsn=kVdc+Iac*Ron*2; k=1,g=[1,0,0,1]; k=-1,g=[0,1,1,0]

[0036] Vsp=Vsn=Iac*Ron*2; k=0,g=[1,0,1,0]||g=[0,1,0,1]

[0037] Vsp=kVdc+Iac*Ron*2; Vsn=-kVdc+Iac*Ron*2; k=1; g=[0,0,0,0]&Iac≥0

[0038] Vsp=kVdc+Iac*Ron*2; Vsn=-kVdc+Iac*Ron*2; k=-1; g=[0,0,0,0]&Iac≥0

[0039] Vdc represents the DC voltage, Iac represents the AC current, Ron represents the on-resistance, and the coefficient k represents the relationship between the DC current and the AC current: Idc = k*Iac. Idc represents the DC current.

[0040] By combining the three phases of the single-phase MMC model in parallel, the single-phase model is connected according to the corresponding topology to form a complete three-phase system. The voltage and current phase of each phase differ by 120 degrees to achieve a balanced three-phase power system.

[0041] In addition, if Figure 3 As shown, the CPU model 21 includes: a power grid model 211, which is used to simulate the voltage, frequency and load characteristics of the power grid. A transformer model 212, which is used to simulate the voltage conversion and power transfer between the power grid and the STATCOM. A load model 213, which is used to simulate various loads on the power grid, including qualitative and quantitative load characteristics. A data framing and parsing model 214, which is used to generate and parse communication data frames, including information such as PWM signals and SM capacitor voltage. A fault model 215, which is used to simulate various fault conditions that may occur in the power grid, such as short circuit, open circuit, etc. A STATCOM model 216 is defined as a STATCOM valve body mathematical model and control algorithm.

[0042] In addition, if Figure 4 As shown, the FPGA model 22 includes: Aurora communication IP core 221 integrates and configures a high-performance Aurora communication IP core for high-speed data exchange with the simulator. The IO interface 222 designs the input and output interface of the simulator to ensure data interaction and synchronization with the FPGA.

[0043] After the various sub-models in the above-mentioned CPU model and FPGA model are converted by the corresponding software compilation code, they are divided into cores and downloaded to the semi-physical CPU and FPGA development board to achieve parallel operation and collaborative work.

[0044] After the CPU model and FPGA model are downloaded to the simulator, the internal structure of the simulator is as follows: Figure 5As shown in the figure, the STATCOM cascade multi-level system outputs the level signal according to the control information sent by the host computer. The output signal is sent to the analog output AO interface and the digital output DO interface of the FPGA model. After the analog signal generated by the IO configuration module in the CPU model, the analog current transformer PT and the voltage transformer CT obtain the current and voltage signals of the power system and convert them into digital signals for FPGA processing. The processed signal is returned to the STATCOM digital controller through the analog input AI interface and the digital input DI interface. At the same time, the data framing analysis model in the CPU model ( Figure 5 The protocol analysis shown in Figure 1 is used to generate communication data frames and send them to the Aurora communication IP core, such as Figure 5 The figure shows that CH00, CH01, CH02, CH03, CH04, and CH05 are included in the six data transmission channels. The data transmission channels use the Aurora protocol to transparently transmit data on the fiber channel interface to achieve high-speed data exchange. The communication data is analyzed through the signal monitoring module to determine the normal working state, abnormal signal state, data loss or error state, etc., and verify the performance of the framing and unpacking modules in various situations. In addition, the performance and effect of the STATCOM rapid control prototype, such as the dynamic response speed, stability, and response capability to power grid faults and changes, are evaluated.

[0045] The simulation model of the rapid control prototype test system of the power system is as follows Figure 6 As shown, the power grid is connected to STATCOM through a transformer, and the output level of the power grid is changed through STATCOM to control the voltage Vcap input to the optical fiber communication protocol group frame, and the optical fiber communication protocol group frame forms a closed-loop control with STATCOM through the CH00 sending interface and the CH00 receiving interface. A load model (load) and a fault model (fault simulation) are connected between the power grid and the transformer, and different loads are controlled by the load switch, and different fault conditions are simulated. In addition, a closed-loop control is formed between the CH01 sending interface and the CH01 receiving interface of the optical fiber communication protocol group frame and the STATCOM simulation controller.

[0046] The following examples illustrate the simulation results of several network-related functional tests performed by the rapid control prototype test system in the embodiment of the present invention:

[0047] The simulation results of the delay test of optical port CH00 sending and CH01 receiving are as follows: Figure 7 As shown in the figure, the simulation results of the verification test on the number of data sent by optical port CH00 are as follows Figure 8 As shown in the figure, the simulation results of the data validity verification test for optical port CH00 are as follows Fig. 9 shown.

[0048] The following is a detailed description of the control information sent by the host computer:

[0049] The control module is built in the host computer. Specifically, a variety of control modules are added in the Simulink environment. The control module can include PI controller, filter, modulator, etc., which are used to implement the multi-layer control strategy of STATCOM. The stability and response speed of the system are ensured by accurately setting and debugging the parameters of each control module.

[0050] The above control modules can be used to control various working environments of the system:

[0051] 1. Realize multi-layer control of capacitor voltage:

[0052] For example: Global voltage control: used to maintain the total voltage level of the entire system and ensure the normal operation of the system. Global voltage control achieves voltage stability throughout the entire system by monitoring and adjusting the capacitor voltage. Phase-to-phase voltage control: used to balance the voltage between different phases. Phase-to-phase voltage control ensures voltage balance in the three-phase system by adjusting the voltage difference of the capacitors in each phase, avoiding harmonics and power loss caused by voltage imbalance. Intra-phase voltage control: used to further refine the control and achieve voltage balance in each phase. Intra-phase voltage control ensures the consistency of voltage in each module by adjusting the voltage difference of each module in a single phase, thereby improving the stability and efficiency of the system.

[0053] 2. Realize current control on the AC side:

[0054] For example: on the AC side, a current control strategy is adopted, including inner loop current control and outer loop voltage control. Through the coordinated control of the inner and outer loops, fast dynamic response and high-precision steady-state control are achieved.

[0055] 3. Implement carrier phase shift modulation strategy:

[0056] For example, the cascaded STATCOM adopts a carrier phase shift modulation strategy, which can effectively reduce the switching loss of the system, reduce electromagnetic interference, and improve the quality of the output voltage waveform by phase shifting multiple carrier signals.

[0057] In addition to controlling the STATCOM model, the host computer also controls and verifies the FPGA model. Specifically, a communication data format framing module is built in Simulink to manage and analyze various control signals and feedback information. The specific design is as follows:

[0058] Data frame structure design: A data frame structure for transmitting various control and feedback information is designed in Simulink. The data content includes information such as PWM signal sending and receiving, capacitor voltage sending and receiving of each submodule (SM), etc. The format of each data frame is designed according to the requirements of the communication protocol, including frame header, data segment, checksum, etc. to ensure the integrity and correctness of the data.

[0059] Data packing and unpacking: It realizes the data packing (framing) and unpacking (parsing) functions. The PWM signal sent by the controller and the received SM capacitor voltage and other data are packed through the framing module to form a data frame that meets the requirements of the communication protocol. At the receiving end, the received data frame is unpacked, the valid data is extracted and parsed.

[0060] Data parsing: Unpack the received data frame and extract the capacitance and voltage value of each submodule. The unpacking process includes frame header recognition, data segment extraction, checksum verification and other steps to ensure the accuracy and integrity of the data.

[0061] Design a variety of test cases, including normal working conditions, abnormal signal conditions, data loss or error conditions, etc., to verify the performance of the framing and depacketization modules in various situations.

[0062] All modules involved in this embodiment are logic modules. In practical applications, a logic unit may be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of the present invention, this embodiment does not introduce units that are not closely related to solving the technical problem proposed by the present invention, but this does not mean that there are no other units in this embodiment.

[0063] The embodiment of the present invention also relates to a rapid control prototype test method for an electric power system, which is applied to the rapid control prototype test system of the electric power system, such as Fig.10 As shown, the method comprises the following steps:

[0064] Step 1001: Use system modeling software to establish a CPU model and an FPGA model, as well as a control algorithm, in a host computer, and use a control module in the system modeling software to convert the control algorithm into control information for a simulation machine.

[0065] Step 1002: The simulator controls the operation of the CPU model and FPGA model carried by the simulator according to the control information, collects the operation status information of the CPU model and the FPGA model, and feeds back the operation status information to the host computer to obtain the test result.

[0066] Compared with the prior art, the embodiment of the present invention builds a CPU model and an FPGA model in the system to achieve hardware and software adaptation. A static synchronous compensator STATCOM model is established in the CPU model, and the static synchronous compensator STATCOM model is used to adjust the level output. The Aurora communication IP core is integrated in the FPGA model to simulate the communication protocol of the real controller. By detecting the operating status of the CPU model and the FPGA model in the simulation environment, all-round debugging and verification from rapid control prototyping RCP to communication protocol is achieved.

[0067] In addition, the rapid control prototype testing method of the power system in this embodiment is implemented by the rapid control prototype testing system of the power system in the above embodiment, that is, the implementation method mentioned in the above system embodiment is also applicable to the method implementation of this embodiment. To avoid repetition, it will not be repeated here.

[0068] The step division of the above methods is only for the purpose of clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent; adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the scope of protection of this patent.

[0069] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present invention, and that in actual applications, various changes may be made in form and detail without departing from the spirit and scope of the present invention.

Claims

1. A rapid control prototype test system for an electric power system, characterized in that: include: The host computer is used to establish the CPU model and FPGA model, as well as their control algorithms, and convert them into control information for the simulator; A simulator, used to carry and run the CPU model and the FPGA model, wherein the CPU model uses a static synchronous compensator STATCOM model to adjust the level output, and the FPGA model integrates an Aurora communication IP core, and the Aurora communication IP core is used to exchange data with the simulator; The simulation machine is also used to control the operation of the CPU model and the FPGA model according to the control information, collect operation status information, and feed back the operation status information to the host computer.

2. The rapid control prototype test system for the power system according to claim 1, characterized in that: The STATCOM model is a three-phase system model composed of single-phase modular multilevel converter MMC models; wherein the voltage and current phases of each phase of the three-phase system model differ by 120 degrees.

3. The rapid control prototype test system for the power system according to claim 1, characterized in that: The FPGA model also includes: an IO interface; The IO interface is used to implement data interaction between the FPGA model and the simulation machine.

4. The rapid control prototype test system for the power system according to claim 1, characterized in that: The CPU model includes: a data framing parsing model; The data framing and parsing model is used to generate and parse the communication data frames exchanged between the Aurora communication IP core and the simulator.

5. The rapid control prototype test system for the power system according to claim 4, characterized in that: The communication data frame at least includes: a pulse width modulation (PWM) signal and capacitor voltage information.

6. The rapid control prototype test system for an electric power system according to any one of claims 1 to 5, characterized in that: The CPU model includes: a power grid model; The power grid model is used to simulate the voltage, frequency and load characteristics of the power grid.

7. The rapid control prototype test system for the power system according to claim 6, characterized in that: The CPU model Includes: Transformer model; The transformer model is used to simulate the voltage conversion and power transfer between the power grid and the static synchronous compensator STATCOM model.

8. The rapid control prototype test system for the power system according to claim 6, characterized in that: The CPU model includes: a load model; The load model is used to simulate the load condition on the power grid.

9. The rapid control prototype test system for the power system according to claim 6, characterized in that: The CPU model includes: a fault model; The fault model is used to simulate a fault condition occurring in the power grid.

10. A rapid control prototype testing method for an electric power system, characterized in that: A rapid control prototype test system for an electric power system according to any one of claims 1 to 9, the method comprising: Using system modeling software to establish a CPU model and an FPGA model, as well as a control algorithm thereof, in a host computer, and using a control module in the system modeling software to convert the control algorithm into control information for a simulation machine; The simulator controls the operation of the CPU model and the FPGA model carried by the simulator according to the control information, collects the operation status information of the CPU model and the FPGA model, and feeds back the operation status information to the host computer to obtain the test result.

Images