Current and clock frequency management

Abstract

The invention relates to current and clock frequency management. Current sensing circuitry and clock management circuitry provide current and clock frequency management. In one example, an apparatus may include a voltage regulator, current sense circuitry configured to: detect a current associated with the voltage regulator of a system on chip (SoC), and determine when the current transitions from a first current to a second current; and clock management circuitry configured to generate a clocked signal for the SoC, select a gradient frequency change based on the detected current, and change a frequency of the generated clocked signal to the gradient frequency change in response to the detected current transition.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to digital logic circuits, and more particularly, to current and clock frequency management. Background Art

[0002] The memory system may include one or more digital circuits that may include various circuit systems. Typically, a portion of the circuit system may provide voltage signals to power the digital circuits and / or to power components of the memory system. Summary of the invention

[0003] One aspect of the present disclosure relates to an apparatus for clock frequency management, comprising: a voltage regulator; a current sensing circuit system configured to: detect a current associated with the voltage regulator of a system on chip (SoC); and determine when the current transitions from a first current to a second current; and a clock management circuit system configured to: generate a timing signal for the SoC; select a gradient frequency change based on the detected current; and change the frequency of the generated timing signal to the gradient frequency change in response to the detected current transition.

[0004] Another aspect of the present disclosure relates to a method for clock frequency management, comprising: detecting, by a current sensing circuit system, a current associated with a voltage regulator of a system on chip (SoC); determining, by the current sensing circuit system, when the detected current transitions from a first current to a second current; generating, by a clock management circuit system coupled to the current sensing circuit system, a timing signal for the SoC; selecting, by the clock management circuit system, a gradient frequency change based on the detected current; and changing, by the clock management circuit system, a frequency of the generated timing signal to the gradient frequency change in response to the detected current transition.

[0005] Another aspect of the present disclosure relates to a system for clock frequency management, comprising: a plurality of computing components coupled to a system on chip (SoC), wherein the SoC comprises: a voltage regulator; a current sensing circuit configured to: detect a current associated with the voltage regulator of the SoC; and determine when the current transitions from a first current to a second current; and a clock management circuit system configured to: generate a timing signal for the SoC; select a gradient frequency change based on the current; and change the frequency of the generated timing signal to the gradient frequency change in response to the detected current transition; and apply the timing signal having the changed frequency to one or more of the plurality of computing components, or to one or more components of the SoC. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example system including a current sensing circuit for current and clock frequency management according to some embodiments of the present disclosure is described.

[0008] Figure 2 A diagram illustrating example timing signals used for clock frequency management in a prior system.

[0009] Figure 3 Diagram illustrating example timing signals for current and clock frequency management according to some embodiments of the present disclosure.

[0010] Figure 4 is a flow chart corresponding to a method for current and clock frequency management according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0011] Aspects of the present disclosure relate to current and clock frequency management. Current and clock frequency management can be achieved through the use of current sensing circuits that can determine the current (e.g., instantaneous or near instantaneous current) associated with a system (e.g., a system on a chip (SoC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other hardware circuit system) and a clock management circuit system to reduce power consumption and / or improve performance in the system compared to methods that do not employ such management. Current sensing circuits in conjunction with the clock management circuit system described herein can provide benefits in systems that rely on instantaneous (or near instantaneous) current sensing to dynamically track, limit, adjust, and / or manipulate power consumption and / or noise. The following is combined with Figure 1 etc. describe examples of devices and systems that employ current and clock frequency management according to embodiments of the present disclosure.

[0012] The current and clock frequency management systems and devices described herein can dynamically and automatically adjust the generated timing signals during power mode transitions based on the detected current. The current sensing circuit can be used to detect instantaneous or near-instantaneous current readings associated with the system and provide the detected current to the clock management circuit system. The clock management circuit system can generate timing signals for the system in response to the detected current. In this way, the present disclosure provides less power mode transition delay compared to previous systems and methods. In addition, the present disclosure allows power mode transitions to be terminated without performance interruptions. In addition, the present disclosure is able to dynamically and automatically adjust to adapt to IR drops and / or other types of current irregularities while still compensating for temperature and voltage fluctuations. These and other aspects of the present disclosure can also reduce power consumption in various types of systems, computing devices and / or circuits; thereby providing improvements to computing devices in which aspects of the present disclosure are deployed.

[0013] By utilizing the current sensing circuitry and / or clock management circuitry described herein, current and clock frequency management may be provided to a system and / or components coupled to the system. For example, the current sensing circuitry may be deployed in a system (e.g., an SoC, an ASIC, an FPGA, etc.) to detect current characteristics (e.g., a current drop or "IR drop," a current increase, etc.) in locations within the system that may be prone to exhibiting IR drop phenomena. As described in more detail herein, in response to the current characteristics determined by the current sensing circuitry, the clock management circuitry may change the frequency of a timing signal generated by the system. In this way, the frequency of the timing signal may be locked to correspond to a threshold current value determined by the current sensing circuitry. Thus, the clock management circuitry may provide a corresponding frequency of a timing signal for a clock gradient associated with a detected current of the system.

[0014] Figure 1 An example system 100 including a current sensing circuit (e.g., a current sensor 102, etc.) according to some embodiments of the present disclosure is described. The example system 100, which may be referred to as an "apparatus" in an alternative example, includes a voltage regulator 101, which is configured to generate a power supply signal (e.g., a supply voltage signal) and apply the power supply signal to components of the system 100. As used herein, the voltage regulator 101 may be a device or a system of devices that can manipulate or change an output voltage. For example, the voltage regulator 101 may include one or more of the following: a power supply, one or more converters, one or more inverters, one or more generators, and other electrical components that can change voltage or current. In another example, the voltage regulator 101 may include a battery or solar element having a switch that connects different battery elements to manipulate voltage.

[0015] System 100 may be coupled to one or more computing components. The computing components are typically external to system 100 (i.e., the computing components are physically distinct from a chip, such as a SoC, on which system 100 is deployed), but are communicatively coupled to system 100 such that signaling may be exchanged between system 100 and the computing components. Non-limiting examples of computing components may include controllers, memory devices, graphics processing units, processors / coprocessors and / or logic blocks, etc. and other components connected to a computer in which system 100 operates.

[0016] In some embodiments, the current sensor 102 may be a current mirror sensor, a current transformer, and / or other types of current sensors capable of instantaneous or near-instantaneous current measurement. The current sensor 102 may be a current mirror sensor residing on the voltage regulator 101. As used herein, a current mirror sensor may be a sensor for detecting a current level flowing within a circuit. In some embodiments, the current mirror sensor may be a configuration of transistors that replicate or mirror the current flowing through one transistor to another transistor. In some embodiments, the current mirror sensor may include a reference current source and a sensing transistor. The reference current source may be a stable or well-controlled current source that can provide a known or constant current. The sensing transistor may be coupled in line or in the path of the current to be measured or detected. In some embodiments, a reference current from the current source is mirrored onto the sensing transistor. This is achieved by adjusting the bias and size of the sensing transistor so that it replicates the current flowing through the reference current source. By monitoring the characteristics of the sensing transistor (e.g., its voltage or output current), we can infer the current flowing through the circuit. The change or difference between the behavior of the sensing transistor and the behavior of the reference current source can be used to determine the current being measured.

[0017] In some embodiments, the current sensor 102 may be a current transformer sensor coupled to a switching power supply. As used herein, a current transformer (CT) may refer to a current sensor used to measure alternating current (AC) flowing through a conductor without being directly connected to the conductor. In some embodiments, the current transformer operates according to the principle of electromagnetic induction. When an alternating current passes through a primary winding (the conductor being measured), it generates a magnetic field around the conductor. The core of the current transformer is usually made of a magnetic material. Wrapped around this core is a secondary winding, which is composed of many turns of wire. Compared to the primary winding, the secondary winding is designed to have a large number of turns. This ratio between the primary winding and the secondary winding determines the transformation ratio of the current transformer. By knowing the transformation ratio of the current transformer, the secondary voltage can be used to determine the primary current. Then, a measurement device connected to the secondary winding can process this voltage to provide an accurate representation of the primary current.

[0018] like Figure 1 , the current sensor 102 may signal a first clock controller 104-1 and / or a second clock controller 104-2 (e.g., clock management circuitry, etc.) indicating a current level. Although a first clock controller 104-1 and a second clock controller 104-2 are illustrated, more or fewer clock controllers may be utilized. For example, the system 100 may utilize one of the first clock controller 104-1 or the second clock controller 104-2. In other embodiments, the clock controllers may reside on partition A 103-1, partition B 103-2, and / or partition C 103-N.

[0019] The system 100 may include a clock controller 104-1, 104-2 that includes a clock management circuit system. The clock controller 104-1, 104-2 or the clock management circuit system may be configured to generate and apply timing signals to various components of the system 100, such as partition A 103-1, partition B 103-2, partition C 103-N, and / or additional partitions not illustrated. In some embodiments, partition A 103-1 may be a first logic block, and partition B 103-2 may be a second logic block separate from the first logic block. However, embodiments are not limited thereto, and the clock controller 104-1, 104-2 or the clock management circuit system may generate and apply the timing signals to components external to the system 100, as described in more detail herein. Advantageously, the clock controller 104-1, 104-2 may be configured to alter the frequency of the clock signal generated thereby, which will be described in more detail below.

[0020] Partition A 103-1, Partition B 103-2, and / or Partition C 103-N may include various hardware forming one or more cores (e.g., "intellectual property (IP) cores"). As used herein, a "core" or "IP core" generally refers to one or more data and / or logic blocks that form a constituent component of an application specific integrated circuit or a field programmable gate array. Partition A 103-1, Partition B 103-2, and / or Partition C 103-N may be designed, constructed, and / or otherwise configured to perform specific tasks and / or functions within the systems described herein. In some embodiments, the current sensor 102 may take action (or cause action to be taken) to track, limit, adjust, or manipulate the dynamic power available to Partition A 105-1 and / or Partition B 105-N.

[0021] Clock controllers 104-1, 104-2 may include hardware circuitry configured to perform the operations described herein. For example, clock controllers 104-1, 104-2 may include one or more chips or other hardware circuitry configured to generate a periodic oscillating signal (e.g., a square wave) that is applied to components of system 100. In some embodiments, clock controllers 104-1, 104-2 include throttling circuitry, clock division circuitry, and / or a voltage controlled oscillator to facilitate embodiments of the present disclosure.

[0022] In some embodiments, at least one of the clock controllers 104-1, 104-2, and / or the current sensor 102 may reside on one of the partitions (partition A 103-1, partition B 103-2, as illustrated, on partition C 103-N, etc.). As used herein, the term "resides on" refers to something that is physically located on a particular component. For example, the current sensor 102 and / or the clock controller 104-2 "resides on partition C 103-N" refers to a situation where the hardware circuitry including the current sensor 102 and / or the clock controller 104-N is physically located on partition C 103-N. The term "resides on" may be used interchangeably herein with other terms such as "deployed on" or "located on".

[0023] In a non-limiting example, the system 100 may include a current sensor 102, which may be configured to detect a current associated with a system on chip (SoC) and determine when the current changes from a first current to a second current. The current may be generated by a voltage regulator 101 and / or associated with one or more components of the system 100. In some embodiments, the current transition may correspond to a specific current change (e.g., a current reduction, a current increase) that the SoC is consuming. In some embodiments, the current change may correspond to a change from an idle current to a full current or from an idle mode to a normal or full mode. As used herein, full current refers to a specified or specified current level at which an electrical component, device, or system is designed to operate. It can serve as a standard reference point for manufacturers and engineers to design, build, and operate various electrical and electronic equipment. Thus, when the current sensor 102 detects the full current, the system 100 can operate in a normal mode or an operating mode. As used herein, the idle current may refer to the minimum current used to maintain data associated with the system 100. Thus, the idle current may refer to the current provided by the voltage regulator 101 during a sleep mode or a low power mode of the system 100. In these embodiments, the full current may be greater than the idle current. Thus, the current transition from the first current to the second current may include a current transition of the SoC from an idle state to an active state or from an active state to an idle state.

[0024] As described herein, the system 100 further includes clock controllers 104-1, 104-2 (collectively referred to as clock controllers 104), which can be configured to generate timing signals for the SoC. The clock controller 104 can be configured to select a gradient frequency change based on the current. In these embodiments, the clock controller 104 can be configured to change the frequency of the generated timing signal to the gradient frequency change in response to the detected current transition. In some embodiments, the frequency of the generated timing signal is changed to correspond to the value of the detected current. In some embodiments, the gradient frequency includes a specific clock frequency utilized within a specific current value range.

[0025] In some embodiments, the clock controller 104 can detect transient current at the voltage regulator 101. In some embodiments, the voltage regulator 101 is a low dropout regulator (LDO). In some embodiments, the voltage regulator 101 includes voltage sensing feedback to compensate for current-resistance drop.

[0026] In this way, the clock controller 104 can receive a specific current value from the current sensor 102 and generate a frequency of the timing signal corresponding to the gradient frequency change associated with the specific current value. In some embodiments, the clock controller 104 can lock the frequency of the timing signal to the detected current, so that an increase in the detected current causes an increase in the frequency of the timing signal, and a decrease in the detected current causes a decrease in the frequency of the timing signal.

[0027] In some embodiments, the clock controller 104 may be configured to change the frequency of the timing signal by reducing the frequency of the timing signal according to the gradient frequency change. The frequency of the timing signal may be referred to as the clock frequency or clock speed. The frequency of the timing signal is a parameter in digital systems and electronic devices. The frequency of the timing signal may represent the rate at which the clock signal alternates between its high state and low state (or transitions between 1 and 0) within a specific time interval. The clock signal may be used to synchronize various components and operations in a digital circuit, thereby ensuring that actions occur at precise and coordinated times. The clock frequency may be measured in Hertz (Hz) and represents the number of clock cycles that occur per second. A higher clock frequency generally indicates faster processing power and faster data transfer within a digital system.

[0028] In some embodiments, the clock controller 104 may be configured to change the frequency of the timing signal by increasing the frequency of the timing signal according to the gradient frequency change. As further described herein, the gradient frequency change may be a gradient frequency threshold that includes a specified frequency for a range of current values. That is, a first gradient frequency change includes a specific frequency of the timing signal to be generated when the detected current level is within a threshold range of current levels. In this way, during relatively small changes in the detected current, the frequency of the timing signal is not changed. That is, when the detected current exceeds or drops below the current threshold associated with the current gradient frequency change, the frequency of the timing signal is changed to a different gradient frequency change.

[0029] In some embodiments, the clock controller 104 may be configured to change the frequency of the generated timing signal without a clock management timing component. As used herein, a clock management timing component refers to hardware or software that controls the timing or frequency of a clock to synchronize the clock with multiple features of the system. Since the clock is fixed to one of multiple gradient frequency changes based on the detected current, no additional hardware and / or software may be required. The power mode transition termination may include a termination signal that stops the transition from the first power mode to the second power mode during the transition. For example, a transition from an idle mode to an operating mode may occur. Early termination of the power mode prevents the system from transitioning from the idle mode to the operating mode, so that the system returns to the idle mode before reaching the operating mode. Since the detected current does not reach the full current associated with the operating mode, the timing signal does not reach the full operating mode frequency. In this way, the frequency of the timing signal may increase between the idle current and the termination signal. When the termination signal is received, the detected current and the frequency of the timing signal may be reduced back to the current and frequency of the timing signal associated with the idle mode.

[0030] In some embodiments, the clock controller 104 may be configured to apply a power mode transition termination during a power mode transition. In some embodiments, the clock controller 104 may be configured to apply a timing signal having a modified frequency to one or more of the plurality of computing components, or to one or more components of the SoC. As described herein, the timing signal may be provided to a plurality of components not associated with the SoC and to a plurality of components associated with the SoC. In this way, the components of the SoC and the plurality of computing components may be synchronized by the timing signal provided by the clock controller 104.

[0031] In some embodiments, the current sensing circuit of the current sensor 102 may be disposed on a memory system or otherwise included in a memory system (e.g., a storage device, a memory module, or a hybrid of a storage device and a memory module). Examples of storage devices include solid state drives (SSDs), flash memory drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0032] In other embodiments, the current sensing circuit of the current sensor 102 may be deployed on or otherwise included in a computing device such as a desktop computer, a laptop computer, a server, a network server, a mobile computing device, a vehicle such as an airplane, a drone, a train, a car, or other transportation vehicle, an Internet of Things (IoT) enabled device, an embedded computer such as an embedded computer included in a vehicle, industrial equipment, or a networked commercial device, or such a computing device including a memory and a processing device. As used herein, the term "mobile computing device" generally refers to a handheld computing device having a phablet or tablet form factor. Typically, a phablet form factor may include a display screen of between approximately 3 inches and 5.2 inches (measured diagonally), while a tablet form factor may include a display screen of between approximately 5.2 inches and 7 inches (measured diagonally). However, examples of a "mobile computing device" are not limited thereto, and in some embodiments, a "mobile computing device" may refer to an IoT device, as well as other types of edge computing devices.

[0033] Such a computing device may include a host system coupled to a memory system (e.g., one or more storage devices, memory modules, or a hybrid of storage devices and memory modules). The host system may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system uses the storage devices, memory modules, or a hybrid of storage devices and memory modules to, for example, write data to the storage devices, memory modules, or a hybrid of storage devices and memory modules, and read data from the storage devices, memory modules, or a hybrid of storage devices and memory modules.

[0034] In these examples, the host system may include a processing unit, such as a central processing unit (CPU), configured to execute an operating system. In some embodiments, the processing unit may execute a complex instruction set computer architecture, such as x86 or other architecture suitable for use as a CPU for the host system.

[0035] The host system may be coupled to the memory system via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system and the memory system. When the memory system is coupled to the host system via a PCIe interface, the host system may further utilize an NVM Express (NVMe) interface to access the component. The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory system and the host system. In general, the host system may access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0036] The memory system may include any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory devices may be, but are not limited to, random access memory (RAM), such as dynamic random-access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0037] Some examples of non-volatile memory devices include non-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on bulk resistance changes in conjunction with a stackable cross-grid data access array. Furthermore, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without previously erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0038] Although nonvolatile memory components such as three-dimensional cross-point arrays of nonvolatile memory cells and NAND-type memories (e.g., 2D NAND, 3D NAND) have been described, the memory device may be based on any other type of nonvolatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), "NOR" (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0039] The memory system may also include additional circuitry or components. In some embodiments, the memory system may include a cache or buffer (such as a DRAM) and address circuitry (such as a row decoder and a column decoder) that can receive addresses from a memory system controller and decode the addresses to access memory devices.

[0040] In some embodiments, the memory device includes a local media controller that operates in conjunction with the memory system controller to perform operations on one or more memory cells of the memory device. For example, an external controller may manage the memory device externally (e.g., perform media management operations on the memory device). In some embodiments, the memory device is a managed memory device, which is a raw memory device combined with a local controller for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0041] Figure 2 A diagram 220 illustrating example timing signals for clock frequency management of a prior system. Diagram 220 illustrates a mode 221, clock signal 222, current 223, and voltage 224 of a prior system. Thus, diagram 220 illustrates how a prior system would perform a transition from an idle mode to an operating mode, and how clock signal 222, current 223, and / or voltage 224 are affected by the transition of mode 221.

[0042] Mode 221 may illustrate an idle mode 225 with a transition 226 to an operating mode 227. During idle mode 225, clock signal 222 is in idle clock 228 and starts at full clock 229 in response to transition 226. Figure 2 The clock signal 222 is shown as a square wave, but the clock signal 222 can be any periodic signal (e.g., a sawtooth wave, a sine wave, etc.). In this article, the clock signal 222 can be generated by a clock management circuit system, such as Figure 1 The clock management circuit system of the clock controller 104 is described in detail.

[0043] Graph 220 may illustrate how transient load 232 or transition current 223 affects voltage 224 in a previous (existing) system when mode 221 transitions from idle mode 225 to operating mode 227. Transient load 232 is a rapid increase from idle current 230 to full current 231 due to transition 226 of mode 221 from idle mode 225 to operating mode 227 causing clock signal 222 to transition from idle clock 228 to full clock 229.

[0044] In some embodiments, voltage 224 and / or current 223 may be provided by a voltage regulator (e.g., Figure 1 , etc.) is provided, which includes voltage sensing feedback using a compensation loop to compensate for static IR drop. As used herein, voltage sensing feedback or voltage feedback is a control mechanism for regulating the output voltage of a voltage regulator in electronic circuits and systems. In some embodiments, voltage sensing feedback includes measuring the output voltage and using this information to adjust system operation in order to maintain a specific output voltage level. Although voltage feedback is utilized, the compensation loop is not instantaneous, which results in a V-shaped undervoltage / overshoot voltage response to a step load change at position 234, as illustrated by voltage 224. That is, in response to a rapid increase in transient load 232, there is an IR drop at position 234 between idle voltage 235 and operating voltage 233.

[0045] Thus, the diagram 220 illustrates that the mode 221 may include a mode transition 226 from an idle mode 225 to an operating mode 227. During the mode transition 226, the clock signal 222 may transition directly from an idle clock 228 to a full clock 229. In this diagram 220, the current 230 may include a transient load 232 between the idle current 230 and the full current 231. Furthermore, during the transient load 232, the voltage 224 may include an undervoltage / overshoot voltage response at a location 234. That is, the voltage 224 illustrates the excessive IR drop caused by the mode transition 226 from the idle mode 225 to the operating mode 227 during the transient load 232.

[0046] Figure 3 Graph 340 illustrates example timing signals for current and clock frequency management according to some embodiments of the present disclosure. Graph 340 illustrates a mode 341, clock signal 342, current 343, and voltage 344 of a system utilizing current and clock frequency management as described herein. Thus, Graph 340 illustrates how the system of the present disclosure performs a mode transition 346 from an idle mode 345 to an operating mode 347, and how the clock signal 342, current 343, and / or voltage 344 are affected by the mode transition 346. Although in Figure 3 Shown as a square wave, the clock signal 342 may be any periodically occurring signal (e.g., a sawtooth wave, a sine wave, etc.). In this context, the clock signal 342 may be generated by a clock management circuit system, such as Figure 1 The clock management circuit system of the clock controller 104 is described in detail.

[0047] As described herein, the transition from mode 341 can be identified by mode transition 346. In some embodiments, mode transition 346 includes a signal that the system is transitioning from idle mode 345 to operating mode 347. In other embodiments, mode transition 346 can be identified based on a current or voltage transition. As described herein, the detected current can be used to determine a particular timing gradient from a plurality of timing gradients 349, 350, 351, 352. In this way, current 343 can be gradually increased from idle current 355 to full current 360 without excessive IR drop (e.g., excessive IR drop at location 234 during transient load 232, such as Figure 2 In some embodiments, by controlling the current thresholds 356, 357, 358, 359 and the timing gradients 349, 350, 351, 352, an optimal transient current distribution can result in a minimum IR drop 362 and overshoot / undershoot voltage.

[0048] As described herein, diagram 340 illustrates when mode 341 includes a mode transition 346 from an idle mode 345 to an operating mode 347. Although diagram 340 illustrates mode transition 346 as an idle to operational transition, other types of transitions are possible. For example, mode transition 346 may be from an operational mode to an idle mode. Other possible mode transitions are possible, including a transition from a first current level to a second current level. In this way, the transition from the first current level to the second current level may be more gradual than in previous implementations to avoid IR drops and overshoot / undershoot voltages while providing a timing signal illustrated by clock signal 342 during the transition.

[0049] The clock signal 342 may include an idle timing signal 348. In these embodiments, the idle timing signal 348 may not include the frequency of the timing signal to save power during the idle operating mode. In some embodiments, the clock signal 342 may include a subthreshold clock gradient 349 for the subthreshold current 356. In some embodiments, the subthreshold clock gradient 349 may be the frequency of the timing signal generated when the detected current level is within the subthreshold current 356. In some embodiments, the subthreshold current 356 may be a current range that can be defined based on factors that affect the system IR drop. In some embodiments, the clock signal 342 may include a first threshold clock gradient 350 for a first threshold current 357. The first threshold clock gradient 350 may be the frequency of the timing signal generated when the detected current level is within the first threshold current 357 or between the subthreshold current 356 and the first threshold current 357. In some embodiments, the first threshold current 357 may be a current range that can be defined based on factors that affect the system IR drop.

[0050] In some embodiments, the clock signal 342 may include a second threshold clock gradient 351 for a second threshold current 358. The second threshold clock gradient 351 may be a frequency of a timing signal generated when the detected current level is within the second threshold current 358 or between the first threshold current 357 and the second threshold current 358. In some embodiments, the second threshold current 358 may be a current range that may be defined based on factors that affect the system IR drop. In some embodiments, the clock signal 342 may include a third threshold clock gradient 352 for a third threshold current 359. The third threshold clock gradient 352 may be a frequency of a timing signal generated when the detected current level is within the third threshold current 359 or between the second threshold current 358 and the third threshold current 359. In some embodiments, the third threshold current 359 may be a current range that may be defined based on factors that affect the system IR drop.

[0051] In some embodiments, clock signal 342 may include full clock 354 for full current 360. Full clock 354 may be the frequency of a timing signal generated when the detected current level is at full current 360 and / or at or above a current level of third threshold current 359. In some embodiments, full current 360 may be an operating current of the system when the system is operating in a normal mode or an operating mode.

[0052] Graph 340 illustrates that voltage 344 is less affected by IR drop 362 during transient load 363 or transition of current from idle current 355 through multiple threshold currents 356, 357, 358, 359 to full current 360. Thus, current 343 can be gradually increased from idle current 355 to full current 360 to reduce IR drop 362 of voltage 344. During the gradual increase of current 343, clock signal 342 can be generated according to multiple clock gradients 349, 350, 351, 352 corresponding to multiple threshold currents 356, 357, 358, 359. Thus, the frequency of clock signal 342 can be determined based on which of the multiple threshold currents 356, 357, 358, 359 the detected current is within. Thus, the current can be detected to determine a specific current threshold and a corresponding clocking gradient with a corresponding clocking frequency.

[0053] Figure 4 is a flow chart corresponding to a method 470 for current and clock frequency management according to some embodiments of the present disclosure. The method 470 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 470 is performed by Figure 1 The processes of system 100 are performed by one or more components of the system 100. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes may be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0054] At operation 471, method 470 may include detecting, by current sensing circuitry, a current associated with a voltage regulator of the SoC. As described herein, current sensing circuitry or a current sensor may be connected to a voltage regulator or power supply to determine an instantaneous or near instantaneous current drawn by the system. In some embodiments, the current sensor is coupled to a switch circuitry that may allow the current sensor to determine the current through a particular switch or group of switches. In this way, the current sensing circuitry may be used to detect current changes in the system and provide an instantaneous current level to the clock management circuitry.

[0055] At operation 472, method 470 may include determining, by the current sensing circuitry, when the detected current transitions from the first current to the second current. In some embodiments, the transition from the first current to the second current may be an indication that the device or apparatus has changed from a first mode or state to a second mode or state. For example, the transition from the first current to the second current may be a transition from an idle current to an operating current, which may indicate that the system is transitioning from an idle mode to an operating mode.

[0056] In other embodiments, the transition from the first current to the second current may be a transition from a first current level within a first current range, and the second current may be a second current level within a second current range. Thus, the transition from the first current to the second current may be a transition from a first current threshold to a second current threshold. Thus, the transition may correspond to a transition from a first current gradient frequency change corresponding to the first current threshold to a second current gradient frequency change corresponding to the second current threshold.

[0057] At operation 473, method 470 may include generating a timing signal for the SoC by a clock management circuit system coupled to the current sensing circuit system. As described herein, the clock management circuit system or clock controller may be communicatively coupled to the current sensing circuit system so that the current sensing circuit system may send a communication signal to the clock management circuit system. In this way, the clock management circuit system may receive the communication signal from the current sensing circuit system. For example, the current sensing circuit system may determine or detect the current of the SoC in real time and provide the real time current to the clock management circuit system. In this way, the clock management circuit system may receive the real time current level of the SoC.

[0058] At operation 474, method 470 may include selecting, by the clock management circuitry, a gradient frequency change based on the detected current. As described herein, the clock management circuitry may receive the detected current from the current sensing circuitry and utilize the detected current to select the gradient frequency change. As described herein, the gradient frequency change includes a specific frequency for the timing signal generated by the clock management circuitry. The gradient frequency change may have a corresponding current level range. Thus, the detected current level may be utilized to determine within which current level range the detected current is and select a corresponding frequency change.

[0059] At operation 475, method 470 may include changing, by the clock management circuitry in response to the detected current transition, the frequency of the generated timing signal to a gradient frequency change. When the gradient frequency change is selected, the generated timing signal may be changed to a frequency identified by the gradient frequency change.

[0060] In some embodiments, method 470 may include determining the initiation of a low power mode of the SoC (e.g., a retention mode that utilizes a minimum current to retain data, etc.), detecting by a current sensing circuit system that a current associated with a voltage regulator of the SoC is transitioning to a lower current in response to the initiation of the low power mode, and changing the frequency to a corresponding lower frequency based on a gradient frequency change corresponding to the lower current by a clock management circuit system. As described herein, when the system transitions from an idle mode to an operating mode, the current associated with the voltage regulator may increase, and when the system transitions from an operating mode to an idle mode, the current may decrease. When the detected current level exceeds a threshold current level, a corresponding gradient frequency change may be selected, and the frequency of the timing signal may be changed to the selected gradient frequency change.

[0061] In some embodiments, method 470 may include determining an early termination of an idle mode of the SoC, detecting by the current sensing circuitry that a current associated with the SoC is transitioning to a higher current in response to the termination of the idle mode, and changing by the clock management circuitry a frequency higher to a corresponding higher frequency based on a gradient frequency change corresponding to the higher current. As described herein, the early termination of the idle mode may be an early termination of a transition from an operating mode to an idle mode. In these embodiments, the current of the SoC will decrease during the idle mode transition, and in response to the early termination of the idle mode, the current of the SoC will increase. In this way, the clock management circuitry can dynamically adjust the frequency of the timing signal in response to the changing current and prevent overshoot / undershoot, as described herein.

[0062] In some embodiments, method 470 may include generating, by the clock management circuitry, a clock signal at a frequency identified by the gradient frequency modification based on the detected current value. As described herein, the detected current value may correspond to a range of current values ​​associated with a particular gradient frequency modification. In these embodiments, the gradient frequency modification may be associated with a particular frequency of the timing signal that may be utilized when the current is within the range of current values.

[0063] In some embodiments, method 470 may include generating, by the clock management circuitry, a clock signal without a predicted current or predicted voltage associated with the SoC. Because the clock management circuitry receives the detected current in real time, the predicted current and / or predicted voltage of the SoC is not necessary to predict the frequency change of the timing signal. Thus, the predicted current and / or predicted voltage is not used to adjust the frequency of the timing signal.

[0064] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the art of data processing to most effectively convey the substance of their work to others skilled in the art. Here, an algorithm is generally considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient, at times, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0065] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0066] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0067] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures for various of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure described herein.

[0068] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0069] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings should be regarded in an illustrative rather than a restrictive sense.

Claims

1. A device (100) for clock frequency management, comprising: Voltage regulator (101); A current sensing circuit system (102) configured to: detecting a current associated with the voltage regulator (101) of a system on chip (SoC); and determining when the current changes from a first current to a second current; and Clock management circuitry (104-1, 104-N) configured to: generating a timing signal for the SoC; selecting a gradient frequency change based on the detected current; and The frequency of the generated timing signal is changed to the gradient frequency change in response to the detected current transition.

2. The apparatus of claim 1 , wherein the clock management circuitry is configured to change the frequency of the timing signal by decreasing the frequency of the timing signal in accordance with the gradient frequency change and increasing the frequency of the timing signal in accordance with the gradient frequency change.

3. The apparatus of claim 1, wherein the current transition from the first current to the second current comprises a current transition of the SoC from a first state to a second state, and wherein a plurality of gradient frequency changes are selectable between the first state and the second state.

4. The apparatus of any one of claims 1 to 3, wherein the gradient frequency comprises a specific clock frequency to be utilized within a specific range of current values.

5. The apparatus of any one of claims 1-3, wherein the clock management circuitry is further configured to apply a power mode transition termination during a power mode transition.

6. The apparatus of any one of claims 1-3, wherein the current sensing circuit is further configured to detect a transient current at the voltage regulator.

7. The apparatus of any one of claims 1 to 3, wherein the voltage regulator includes voltage sensing feedback to compensate for current-resistance drop.

8. A method for clock frequency management, comprising: detecting, by a current sensing circuit system (102), a current associated with a voltage regulator (101) of a system on chip (SoC); determining, by the current sensing circuitry (102), when the detected current transitions from a first current to a second current; Generating a timing signal for the SoC by clock management circuitry (104-1, 104-N) coupled to the current sensing circuitry (102); selecting, by the clock management circuitry (104-1, 104-N), a gradient frequency change based on the detected current; and The clock management circuitry (104-1, 104-N) changes the frequency of the generated timing signal to the gradient frequency change in response to the detected current transition.

9. The method according to claim 8, further comprising: Determining initiation of a low power mode of the SoC; detecting, by the current sensing circuitry, that the current associated with the voltage regulator of the SoC is transitioning to a lower current in response to the initiation of the low power mode; and The frequency is changed, by the clock management circuitry, to a corresponding lower frequency based on the gradient frequency change corresponding to the lower current.

10. The method according to claim 9, further comprising: determining early termination of the low power mode of the SoC; detecting, by the current sensing circuitry, that the current associated with the SoC is transitioning to a higher current in response to the termination of the low power mode; and The frequency is changed, by the clock management circuitry, to a corresponding higher frequency based on the gradient frequency change corresponding to the higher current.

11. The method according to claim 8, further comprising: generating, by the clock management circuitry, the clock signal at the frequency identified by the gradient frequency change based on the detected current; and The clock signal is generated by the clock management circuitry without a predicted current or a predicted voltage associated with the SoC.

12. A system (100) for clock frequency management, comprising: A plurality of computing components coupled to a system-on-chip (SoC), wherein the SoC comprises: Voltage regulator (101); A current sensing circuit (102) configured to: detecting a current associated with the voltage regulator (101) of the SoC; and determining when the current changes from a first current to a second current; and Clock management circuitry (104-1, 104-N) configured to: generating a timing signal for the SoC; Selecting a gradient frequency change based on the current; and changing the frequency of the generated timing signal to the gradient frequency change in response to the detected current transition; The clocking signal having the altered frequency is applied to one or more of the plurality of computing components, or to one or more components of the SoC. 13 . The system of claim 12 , wherein the voltage regulator is a low dropout regulator (LDO) and the current sensing circuit is a current mirror in the LDO.

14. The system of claim 12, wherein the plurality of computing components are located external to the SoC.

15. The system of claim 12, wherein the current sensing circuit is a current transformer in a switching power supply.

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