Memory system, electronic device, operating method, host system, and storage medium

Abstract

The embodiment of the invention provides a memory system, electronic equipment, an operation method, a host system and a storage medium. The memory system includes: a memory device including a first memory area including a plurality of first memory cells that store data in a unit mode and a second memory area including a plurality of second memory cells that store data in a multi-bit mode; and the memory controller is coupled with the memory device and is configured to transfer the data stored in the first storage area to the second storage area according to a preset transfer mode according to the current storage space of the first storage area and at least one adjustment threshold value.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a memory system, an electronic device and an operating method, a host system, and a storage medium. Background Art

[0002] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become a mainstream product in the storage market due to its high storage density, controllable production cost, suitable editing and erasing speed and retention characteristics. Summary of the invention

[0003] Based on this, the embodiments of the present application propose a memory system, an electronic device and an operation method, a host system, and a storage medium.

[0004] An embodiment of the present application proposes a memory system, comprising: a memory device, comprising a first storage area and a second storage area, the first storage area comprising a plurality of first storage units that store data in a single-bit mode, and the second storage area comprising a plurality of second storage units that store data in a multi-bit mode; a memory controller, coupled to the memory device and configured to: transfer the data stored in the first storage area to the second storage area according to a preset transfer mode based on the current storage space of the first storage area and at least one adjustment threshold.

[0005] In some embodiments, the at least one adjustment threshold includes multiple ones; the memory controller is configured to: determine a transfer mode for transferring data stored in the first storage area to the second storage area based on a size relationship between the current storage space of the first storage area and the total space and the multiple adjustment thresholds, and different transfer modes correspond to different transfer frequencies and / or transfer data volumes.

[0006] In some embodiments, the multiple adjustment thresholds include a first adjustment threshold corresponding to a first proportion, a second adjustment threshold corresponding to a second proportion, and a third adjustment threshold corresponding to a third proportion, the first proportion is less than the second proportion, and the second proportion is less than the third proportion; the memory controller is configured to: when the current storage space of the first storage area accounts for less than or equal to the first proportion of the total space, use a first transfer mode to transfer at least part of the data stored in the first storage area to the second storage area at a first frequency; when the current storage space of the first storage area accounts for more than the first proportion but less than the second proportion of the total space, use a second transfer mode to transfer part of the data stored in the first storage area to the second storage area at a second frequency; when the current storage space of the first storage area accounts for more than the third proportion of the total space, use a third transfer mode to transfer at most part of the data stored in the first storage area to the second storage area at a third frequency; wherein the first frequency corresponding to the first transfer mode is greater than the second frequency corresponding to the second transfer mode, and the second frequency corresponding to the second transfer mode is greater than the third frequency corresponding to the third transfer mode.

[0007] In some embodiments, the first transfer mode is to continuously transfer data when the storage memory system is in an idle state until all data is transferred or the storage memory system exits the idle state; the second transfer mode is to transfer a portion of the data when the storage memory system is in an idle state; and the third transfer mode is to stop transferring data.

[0008] In some embodiments, the memory controller is specifically configured to: receive a first instruction, the first instruction instructing the storage memory system to enter an automatic adjustment mode; in response to the first instruction, receive a second instruction, the second instruction including the at least one adjustment threshold; and obtain the current storage space of the first storage area according to a preset period.

[0009] In some embodiments, the memory controller is further configured to: receive a third instruction, the third instruction instructing the storage memory system to enter a passive adjustment mode; after the third instruction, receive a fourth instruction, the fourth instruction instructing to transfer the data stored in the first storage area to the second storage area according to a specified transfer mode; in response to the fourth instruction, transfer the data stored in the first storage area to the second storage area according to the specified transfer mode.

[0010] In some embodiments, the memory controller is configured to: control the memory device to read the data stored in the first storage area according to a preset transfer mode, and write the read data into the second storage area.

[0011] An embodiment of the present application further proposes a host system, comprising: a memory unit; an interface; a controller unit, configured to: use the interface to send a first instruction, the first instruction instructing the memory system to enter an automatic adjustment mode; the memory system comprises a memory device, the memory device comprises a first storage area and a second storage area, the first storage area comprises a plurality of first storage units that store data in a single-bit mode, the second storage area comprises a plurality of second storage units that store data in a multi-bit mode; after sending the first instruction, send a second instruction, the second instruction comprises at least one adjustment threshold, the at least one adjustment threshold and the current storage space of the first storage area provide a basis for a transfer mode of transferring data stored in the first storage area to the second storage area.

[0012] In some embodiments, the controller unit is configured to: send a third instruction, wherein the third instruction instructs the storage memory system to enter a passive adjustment mode; after sending the third instruction, send a fourth instruction, wherein the fourth instruction instructs the data stored in the first storage area to be transferred to the second storage area according to a specified transfer mode.

[0013] An embodiment of the present application also proposes an electronic device, comprising: a host system and a memory system coupled to the host system; wherein the memory system comprises a memory device, the memory device comprises a first storage area and a second storage area, the first storage area comprises a plurality of first storage units storing data in a unit mode, and the second storage area comprises a plurality of second storage units storing data in a multi-bit mode; the host system is configured to: send a first instruction; the memory system is configured to: receive the first instruction, and enter an automatic adjustment mode in response to the first instruction; the host system is further configured to: send a second instruction after the first instruction, the second instruction comprising at least one adjustment threshold; the memory system is further configured to: receive the second instruction; obtain the current storage space of the first storage area; and transfer the data stored in the first storage area to the second storage area according to a preset mode based on the current storage space of the first storage area and the at least one adjustment threshold.

[0014] In some embodiments, the host system is further configured to: send a third instruction; the memory system is further configured to: receive the third instruction, and enter a passive adjustment mode in response to the third instruction; the host system is further configured to: send a fourth instruction after sending the third instruction; the memory system is further configured to: in response to the fourth instruction, transfer the data stored in the first storage area to the second storage area according to a specified transfer mode.

[0015] An embodiment of the present application further proposes an electronic device, comprising: a host system and a memory system coupled to the host system; wherein the memory system comprises a memory device, the memory device comprises a first storage area and a second storage area, the first storage area comprises a plurality of first storage units that store data in a unit mode, and the second storage area comprises a plurality of second storage units that store data in a multi-bit mode; the host system is configured to: send a fifth instruction; the memory system is configured to: receive the fifth instruction, and in response to the fifth instruction, feedback the current storage space of the first storage area; the host system is further configured to: receive the current storage space of the first storage area, obtain at least one adjustment threshold; determine a transfer mode for transferring the data stored in the first storage area to the second storage area according to the current storage space of the first storage area and the at least one adjustment threshold; send a sixth instruction; the memory system is configured to: receive the sixth instruction, and in response to the sixth instruction, transfer the data stored in the first storage area to the second storage area according to the determined transfer mode.

[0016] An embodiment of the present application also proposes an operating method of a memory system, wherein the memory system includes: a memory device, wherein the memory device includes a first storage area and a second storage area, wherein the first storage area includes a plurality of first storage units that store data in a single-bit mode, and the second storage area includes a plurality of second storage units that store data in a multi-bit mode; the operating method includes: transferring the data stored in the first storage area to the second storage area according to a preset transfer mode based on the current storage space of the first storage area and at least one adjustment threshold.

[0017] In some embodiments, the at least one adjustment threshold includes multiple ones; based on the current storage space of the first storage area and at least one adjustment threshold, at least part of the data stored in the first storage area is transferred to the second storage area according to a preset transfer frequency, including: based on the size relationship between the current storage space of the first storage area to the total space and the multiple adjustment thresholds, determining the transfer mode for transferring the data stored in the first storage area to the second storage area, different transfer modes correspond to different transfer frequencies and / or transfer data amounts.

[0018] In some embodiments, the multiple adjustment thresholds include a first adjustment threshold corresponding to a first proportion, a second adjustment threshold corresponding to a second proportion, and a third adjustment threshold corresponding to a third proportion, the first proportion is less than the second proportion, and the second proportion is less than the third proportion; the transfer mode for transferring at least part of the data stored in the first storage area to the second storage area according to the size relationship between the proportion of the current storage space of the first storage area to the total space and the multiple adjustment thresholds includes: when the current storage space of the first storage area to the total space accounts for less than or equal to the first proportion, using the first transfer mode to transfer at least part of the data stored in the first storage area to the second storage area according to a first frequency; when the current storage space of the first storage area to the total space accounts for more than the first proportion and less than the second proportion, using the second transfer mode to transfer part of the data stored in the first storage area to the second storage area according to a second frequency; when the current storage space of the first storage area to the total space accounts for more than the third proportion, using the third transfer mode to transfer at most part of the data stored in the first storage area to the second storage area; wherein the first frequency corresponding to the first transfer mode is greater than the second frequency corresponding to the second transfer mode, and the second frequency corresponding to the second transfer mode is greater than the third frequency corresponding to the third transfer mode.

[0019] In some embodiments, the method further includes: receiving a first instruction, the first instruction instructing the storage memory system to enter an automatic adjustment mode; in response to the first instruction, receiving a second instruction, the second instruction including the at least one adjustment threshold; and obtaining the current storage space of the first storage area according to a preset period.

[0020] In some embodiments, the method further includes: receiving a third instruction, wherein the third instruction instructs the storage memory system to enter a passive adjustment mode; after the third instruction, receiving a fourth instruction, wherein the fourth instruction instructs the data stored in the first storage area to be transferred to the second storage area according to a specified transfer mode; and in response to the fourth instruction, transferring the data stored in the first storage area to the second storage area according to the specified transfer mode.

[0021] In some embodiments, transferring at least part of the data stored in the first storage area to the second storage area according to a preset transfer mode includes: reading at least part of the data stored in the first storage area according to the preset transfer mode, and writing the read part of the data to the second storage area.

[0022] An embodiment of the present application further proposes an operating method of an electronic device, wherein the electronic device includes a host system and a memory system coupled to the host system; wherein the memory system includes a memory device, the memory device includes a first storage area and a second storage area, the first storage area includes a plurality of first storage units that store data in a single-bit mode, and the second storage area includes a plurality of second storage units that store data in a multi-bit mode; the method includes: the host system sends a first instruction; the memory system receives the first instruction and enters an automatic adjustment mode in response to the first instruction; the host system sends a second instruction after the first instruction, the second instruction including at least one adjustment threshold; the memory system receives the second instruction; the current storage space of the first storage area is obtained according to a preset cycle; and according to the current storage space of the first storage area and the at least one adjustment threshold, the data stored in the first storage area is transferred to the second storage area according to a preset transfer mode.

[0023] In some embodiments, the method further includes: the host system sends a third instruction; the memory system receives the third instruction and enters a passive adjustment mode in response to the third instruction; after sending the third instruction, the host system sends a fourth instruction; and in response to the fourth instruction, the memory system transfers the data stored in the first storage area to the second storage area according to a specified transfer mode.

[0024] An embodiment of the present application also proposes an operating method of an electronic device, the electronic device comprising: a host system and a memory system coupled to the host system; wherein the memory system comprises a memory device, the memory device comprising a first storage area and a second storage area, the first storage area comprising a plurality of first storage units that store data in a unit mode, and the second storage area comprising a second storage unit that stores data in a multi-bit mode; the method comprises: the host system sends a fifth instruction; the memory system receives the fifth instruction, and in response to the fifth instruction, feeds back the current storage space of the first storage area; the host system receives the current storage space of the first storage area and obtains at least one adjustment threshold; according to the current storage space of the first storage area and the at least one adjustment threshold, determines the transfer frequency of transferring the data stored in the first storage area to the second storage area; sends a sixth instruction; the memory system receives the sixth instruction, and in response to the sixth instruction, transfers the data stored in the first storage area to the second storage area according to the determined transfer mode.

[0025] The embodiment of the present application further proposes a storage medium, on which executable instructions are stored. When the executable instructions are executed, the steps of the method described in the embodiment of the present application can be implemented.

[0026] In the embodiment of the present application, the read and write speed of the first storage area of ​​the memory device in the memory system is greater than the read and write speed of the second storage area, and the memory control in the memory system determines the transfer mode of transferring the data in the first storage area to the second storage area according to the size relationship between the current storage space of the first memory and at least one adjustment threshold. In the embodiment of the present application, according to the size relationship between the remaining storage space of the first memory and the adjustment threshold, the transfer mode is flexibly adjusted to better adapt to different application scenarios, taking into account both lower power consumption and better read and write performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of an exemplary system having a memory system according to an embodiment of the present application;

[0028] Figure 2a A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present application;

[0029] Figure 2b A schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present application;

[0030] Figure 3a A schematic diagram of the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present application;

[0031] Figure 3b A schematic diagram of an exemplary memory including a peripheral circuit according to an embodiment of the present application;

[0032] Figure 4 A cross-sectional schematic diagram of a memory cell array including a NAND memory string according to an embodiment of the present application;

[0033] Figure 5 A schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present application;

[0034] Figure 6 A schematic diagram of the function implementation of a write performance enhancement module (Write Booster) provided in an embodiment of the present application;

[0035] Figure 7 A schematic diagram of the structure of an electronic device provided in one embodiment of the present application;

[0036] Figure 8 A schematic diagram of the interaction process between a host system and a memory system is provided for an embodiment of the present application;

[0037] Fig.9A A schematic diagram of a command interaction situation in an electronic device provided in an embodiment of the present application;

[0038] Fig. 9B A schematic diagram of a command interaction situation in another electronic device provided by an embodiment of the present application;

[0039] Fig. 9C A schematic diagram of a command interaction situation in another electronic device provided in an embodiment of the present application;

[0040] Fig. 10A A schematic diagram of a step flow of an operating method of an electronic device provided in one embodiment of the present application;

[0041] Fig. 10B A schematic diagram of a process flow of another method for operating an electronic device provided in an embodiment of the present application;

[0042] Fig.11 A schematic diagram of the composition structure of a storage medium provided in an embodiment of the present application.

[0043] In the above drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0044] The exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0045] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0046] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0047] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0048] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0049] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0050] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0051] The memory device in the embodiments of the present application includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is taken as an example for description.

[0052] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present application is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1 As shown in , the system 100 may include a host system 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host system 108 may be a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host system 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0053] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host system 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host system 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment solid state drive (SSD) or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0054] The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host system 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer mini interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0055] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products. Figure 2a In one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host system 108 in FIG. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0056] Figure 3a A schematic diagram of the structure of a storage cell array of a three-dimensional NAND memory is given as an example. Figure 3a As shown, the memory cell array of the three-dimensional NAND memory is composed of several parallel and staggered rows of memory cell rows parallel to the gate isolation structure, each of the several rows of memory cell rows is separated by the gate isolation structure and the upper selection gate isolation structure, and each memory cell row includes a plurality of memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure, the first gate isolation structure divides the memory cell array into a plurality of memory blocks (Blocks), the plurality of second gate isolation structures may divide the memory blocks into a plurality of finger storage areas (Fingers), and the upper selection gate isolation structure provided in each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. Figure 3a A storage block shown in FIG. 1 includes 6 storage slices. In actual applications, the number of storage slices in a storage block is not limited thereto.

[0057] In some embodiments, each memory block may be coupled to multiple word lines.

[0058] It should be noted that Figure 3a The number of memory cell rows between the gate isolation structure and the upper selection gate isolation structure given in the present application is only an exemplary demonstration and is not used to limit the number of memory cell rows contained in a finger storage area of ​​the three-dimensional NAND memory in the present application. In actual applications, the number of memory cell rows contained in a finger storage area can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0059] Figure 3b 1 is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present application. The memory device 300 may be Figure 1300 is an example of a memory device 104 in FIG. The memory device 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 is taken as an example of a three-dimensional NAND-type memory cell array, wherein the memory cell 306 is a NAND-type memory cell, and the memory cell 306 is provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons captured in the region of the memory cell 306. Each memory cell 306 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0060] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible storage states and can therefore store one bit of data. For example, the first storage state "0" may correspond to a first voltage range, and the second storage state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-bit memory cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell (also referred to as a two-bit memory cell, Double-Level Cell), three bits per cell (also referred to as a three-bit memory cell (TLC, Trinary-Level Cell)), four bits per cell (also referred to as a four-bit memory cell (QLC, Quad-Level Cell)), five bits per cell (also referred to as a five-bit memory cell (PLC, Penta-level cell)), or more than five bits per cell. Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLCs can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell, a fourth nominal storage value can be used for the erased state.

[0061] like Figure 3bAs shown in , each memory string 308 may include a lower selection transistor 310 (also known as a source side selection transistor, which includes a source selection gate BSG) at its source terminal and an upper selection transistor 312 (also known as a drain side selection transistor, which includes a drain selection gate TSG) at its drain terminal. The source selection transistor BSG310 and the drain selection transistor TSG312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each storage string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselection voltage (e.g., 0 V) ​​to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselection voltage (e.g., 0 V) ​​to a corresponding BSG 310 via one or more BSG lines 315.

[0062] like Figure 3b As shown in , the memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and the unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by the read and program operations. In some embodiments, in combination with the previous Figure 3a, multiple memory cells are isolated by an upper selection gate isolation structure and a gate isolation structure, and multiple memory cells between the upper selection gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, and each memory cell row is parallel to the gate isolation structure and the upper selection gate isolation structure.

[0063] refer to Figure 3a , Figure 3b Each memory cell 306 in the plurality of memory cells is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 via a corresponding selection transistor (such as the top selection transistor (TSG) 312).

[0064] Figure 4 FIG. 3 is a cross-sectional schematic diagram of an exemplary memory cell array 301 including a memory string 308 using NAND as an example according to some aspects of the present application. Figure 4 As shown, the NAND memory cell array 301 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 that are alternately stacked in sequence, and a channel structure that vertically penetrates the gate layers 411 and the insulating layers 412, wherein the channel structure is coupled with each gate layer to form a memory cell, and the channel structure is coupled with a plurality of gate layers in the stacked structure 410 to form a memory string 308. The gate layers 411 and the insulating layers 412 may be alternately stacked, and two adjacent gate layers 411 are separated by a layer of insulating layer 412.

[0065] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0066] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0067] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0068] Return to reference Figure 3b , the peripheral circuit 302 may be coupled to the memory cell array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include Figure 5 Additional peripheral circuits not shown.

[0069] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 can store the program data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306, and amplify the small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512, and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0070] The row decoder / word line driver 508 may be configured to be controlled by the control logic 512 and select / deselect the memory block 304 of the memory cell array 301 and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cell 306 coupled to the (one or more) selected word lines 318. The voltage generator 510 may be configured to be controlled by the control logic 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 301.

[0071] The control logic 512 may be coupled to each of the other parts in the peripheral circuits described above, and is configured to control the operation of each of the other parts in the peripheral circuits. The register 514 may be coupled to the control logic 512, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic 512, and act as a control buffer to buffer control commands received from a host system (not shown) and relay them to the control logic 512, and to buffer status information received from the control logic 512 and relay them to the host system. The interface 516 may also be coupled to the column decoder / bit line driver 506 via the data bus 518, and act as a data I / O interface and a data buffer to buffer data and relay them to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0072] As mentioned above, in NAND type memory, a single-bit storage cell (SLC) has fast read and write speed, high reliability, and long service life, but small storage capacity, and a multi-bit storage cell (MLC, TLC, QLC, PLC) has large storage capacity and low cost, but slow read and write speed; in other words, when a single-bit storage cell (SLC) and a multi-bit storage cell (MLC, TLC, QLC, PLC) perform read operations respectively, there is a large gap in read performance between the two, that is, there is a large gap in read access performance of the memory system to the two; among them, when the memory system reads data in a single-bit storage cell, the reading speed is fast, the reading time is short, and the data access performance is high; comparatively, when the memory system reads data in a multi-bit storage cell, the reading speed is slow, the reading time is long, the data access performance is low, and the user experience is poor.

[0073] Considering that the storage blocks of the memory device in SLC mode are faster to read and write and more durable, some storage blocks in the memory device with multi-bit storage units such as MLC, TLC, QLC or PLC are configured to be accessed in SLC mode as a cache (which may be called SLC cache, or SLC cache) for caching data. When the memory device starts to write data, it can be written to the SLC cache first. Later, when the space configured as the SLC cache is full or about to be full, the data in the SLC cache needs to be moved to the MLC, TLC, QLC or PLC to release the SLC cache space. It should be noted that the process of moving data in the SLC cache to the MLC, TLC, QLC or PLC can also be called a flush operation or refresh behavior.

[0074] The Write Booster module is a new feature introduced in the UFS2.2 and UFS3.1 specifications. It improves the write performance of UFS by using the aforementioned SLC cache write method. The functions of Write Booster are as follows: Figure 6 As shown. UFS Write Booster is widely used in current electronic devices, such as mobile phones. It provides the host system with the opportunity to configure the Write Boost size and control the refresh behavior, but different vendors currently have different understandings of this function, and therefore have different driver designs. This will make the design of the firmware (FW) unable to adapt to different types of drive logic. Since the driver can only change the refresh behavior when the memory system enters the idle state, the memory system has no chance to control the refresh behavior when the memory system input / output (I / O) is severely overloaded. In addition, the Flush granularity in some implementations is very small, such as the A SLC VB size. Frequent refresh behavior not only affects the write amplification factor (WAF), but also affects power consumption.

[0075] Based on one or more of the above problems, the embodiments of the present application provide a memory system, an electronic device and an operation method thereof, a host system, and a storage medium. The memory system includes: a memory device, including a first storage area and a second storage area, the first storage area includes a plurality of first storage units that store data in a single-bit mode, and the second storage area includes a plurality of second storage units that store data in a multi-bit mode; a memory controller, coupled to the memory device, and configured to: transfer the data stored in the first storage area to the second storage area according to a preset transfer mode based on the current storage space of the first storage area and at least one adjustment threshold.

[0076] Figure 7 A schematic diagram of the structure of an electronic device is shown. Figure 7As shown, the electronic device 100 includes a host system 108 and a memory system 102; the memory system 102 is connected to the host system 102, and the host system 102 can be an electronic device such as a personal computer or a mobile terminal. Among them, the host system 108 may include a controller unit 1081, an interface 1082 and a memory unit 1083; the controller unit 1081 is used to implement various calculations, controls, etc., the interface 1082 is used to implement the instruction interaction between the host system 108 and the memory system 102, and the memory unit 1083 is used to implement the storage of various intermediate variables and global variables, etc. The various components of the host system are coupled together through the first bus 1080. The first bus 1080 is used to realize the connection and communication between these components. In addition to the data bus, the first bus 1080 may also include a power bus, a control bus and a status signal bus. However, for the sake of clarity, in Figure 7 Various buses are labeled as a first bus 1080 .

[0077] The memory system 102 may include: a memory controller 106 and a memory device 104. The memory controller 106 is used to control the memory device 104 to perform operations such as reading, writing, and erasing. The memory controller 106 and the memory device 104 may also be coupled in any suitable manner. The memory controller 106 may include a host interface (I / F) 1061, a memory interface (I / F) 1062, a control unit 1063, an error correction module 1064, a data buffer 1067, and a second bus 1060. Among them, the host interface 1061 is a connection interface between the host 108 and the memory controller 106. The host interface 1061 allows the host and the memory controller to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1062 is a connection interface between the memory controller 106 and the memory device 104. The memory interface 1062 is used to realize data transmission between the memory controller 106 and the memory device 104. The control unit 1063 is used to control the memory system 106 as a whole. In some specific embodiments, the control unit 1063 is, for example, a central processing unit (CPU), a microprocessor (MCU), etc. The error correction module 1064 may further include an encoding unit 1065 and a decoding unit 1066; the encoding unit 1065 is used to encode the data to be stored to obtain the check data, and the decoding unit 1066 is used to decode the check data to detect and correct possible erroneous data during the data transmission process. The buffer 1067 is used to cache data.

[0078] The memory device 104 may include: a plurality of storage blocks 1041, and the plurality of storage blocks 1041 may be divided into a first storage area and a second storage area. The first storage area includes a plurality of first storage units, and the second storage area includes a plurality of second storage units; wherein the number of storage bits of the first storage unit is less than the number of storage bits of the second storage unit, that is, the storage capacity used by the first storage unit is less than the storage capacity used by the second storage unit, in other words, the first storage area includes a plurality of first storage units that store data in a unit mode, and the second storage area includes a plurality of second storage units that store data in a multi-bit mode. It can be understood that the read and write speed of the first storage unit is greater than the read and write speed of the second storage unit. Exemplarily, the first storage units in the first storage area are all configured as single-bit storage units (SLC) by multi-bit storage units, and the second storage units in the second storage area remain as ordinary multi-bit storage units (for example, MLC, TLC, QLC, PLC, etc.).

[0079] Here, the current storage space of the first storage area can be understood as the total storage space of the first storage area minus the space used by the stored data. The number of adjustment thresholds may include one or more, and the one or more adjustment thresholds may be used as trigger boundaries for different transfer modes. Different transfer modes correspond to different transfer frequencies and / or transfer data volumes.

[0080] In some embodiments, the at least one adjustment threshold includes multiple ones; the memory controller is configured to: determine a transfer mode for transferring data stored in the first storage area to the second storage area based on a size relationship between the current storage space of the first storage area and the total space and the multiple adjustment thresholds, and different transfer modes correspond to different transfer frequencies and / or transfer data volumes.

[0081] Here, the multiple adjustment thresholds may be percentages. The ratio of the current storage space of the first storage area to the total space is calculated, the ratio is compared with the multiple adjustment thresholds, and the transfer mode is determined according to the comparison result.

[0082] In some embodiments, the multiple adjustment thresholds include a first adjustment threshold corresponding to a first proportion, a second adjustment threshold corresponding to a second proportion, and a third adjustment threshold corresponding to a third proportion, the first proportion is less than the second proportion, and the second proportion is less than the third proportion; the memory controller is configured to: when the current storage space of the first storage area accounts for less than or equal to the first proportion of the total space, use a first transfer mode to transfer at least part of the data stored in the first storage area to the second storage area at a first frequency; when the current storage space of the first storage area accounts for more than the first proportion but less than the second proportion of the total space, use a second transfer mode to transfer part of the data stored in the first storage area to the second storage area at a second frequency; when the current storage space of the first storage area accounts for more than the third proportion of the total space, use a third transfer mode to transfer at most part of the data stored in the first storage area to the second storage area at a third frequency; wherein the first frequency corresponding to the first transfer mode is greater than the second frequency corresponding to the second transfer mode, and the second frequency corresponding to the second transfer mode is greater than the third frequency corresponding to the third transfer mode.

[0083] Here, the relationship between the first proportion, the second proportion and the third proportion is that the first proportion < the second proportion < the third proportion, and the specific values ​​of the first proportion, the second proportion and the third proportion can be adjusted according to actual conditions. In some specific embodiments, the first proportion ranges from 20% to 40%, the second proportion ranges from 60% to 80%, and the third proportion ranges from 90% to 100%. Exemplarily, the first proportion is 30%, the second proportion is 70%, and the third proportion is 90%.

[0084] It can be understood that the first transfer mode corresponds to a scenario in which the current storage space of the first storage area accounts for less than or equal to the first proportion to the total space, that is, the current storage space of the first storage area is already insufficient, and the first frequency and / or the amount of transferred data corresponding to the first transfer mode are relatively large; the second transfer mode corresponds to a scenario in which the current storage space of the first storage area accounts for more than the first proportion and less than the second proportion to the total space, that is, the current storage space of the first storage area is used normally, and the second frequency and / or the amount of transferred data corresponding to the first transfer mode are both normal; the third transfer mode corresponds to a scenario in which the current storage space of the first storage area accounts for more than the third proportion to the total space, that is, the current storage space of the first storage area is relatively abundant, and the third frequency and / or the amount of transferred data corresponding to the third transfer mode are relatively small, or even 0.

[0085] It should be noted that, when the current storage space of the first storage area accounts for a greater proportion of the total space than the second proportion and is less than the third proportion, the second transfer mode can be further subdivided, that is, the transfer frequency and / or data transfer amount of the second transfer mode can be subdivided. Exemplarily, the data transfer amount corresponding to the current storage space of the first storage area accounts for a greater proportion of the total space than the first proportion and is less than the second proportion is set to be greater than the second proportion and less than the third proportion.

[0086] In some specific embodiments, the first transfer mode is to continuously transfer data when the storage memory system is in an idle state until all data is transferred or the storage memory system exits the idle state; the second transfer mode is to transfer a portion of the data when the storage memory system is in an idle state; and the third transfer mode is to stop transferring data.

[0087] It should be noted that the data transfer from the first storage area to the second storage area (refresh operation) in this application is completed when the memory system is in an idle state. Generally, the memory system enters the idle state after a period of time without a host system access request, but at this time, the memory control and memory devices inside the memory system can still perform some operations to improve storage performance, such as bad block management, garbage collection, and wear leveling.

[0088] Here, the first transfer mode can also be called a forced refresh mode. In this mode, once the memory system enters the idle state, it starts to execute the refresh operation (that is, the data in the first storage area is transferred to the second storage area) until the memory system exits the idle state or the data execution of the refresh operation is completed, that is, all data in the first storage area is transferred to the second storage area.

[0089] Here, the second transfer mode can also be called a fragment refresh mode. In this mode, after the memory system enters the idle state, it starts to perform a refresh operation. When the refresh operation reaches a preset data amount, the memory system continues to be in the idle state but does not perform a refresh operation. The preset data amount here can be adjusted according to actual conditions. For example, after the memory system enters the idle state each time, 30% of the current total data amount in the first storage area is refreshed and transferred to the second storage area.

[0090] Here, the third transfer mode may also be referred to as a stop refresh mode. In this mode, after the memory system enters an idle state, no refresh operation is performed and the idle state is maintained to save power.

[0091] In some specific embodiments, Figure 8As shown, the host system can send the adjustment thresholds, such as three adjustment thresholds, to the memory system by means of instructions. Two flags are set in the firmware of the memory system, and the two flags can correspond to the aforementioned forced refresh mode and fragmented refresh mode respectively. When the current storage space of the first storage area is larger than the adjustment threshold and satisfies the forced refresh mode, the flag corresponding to the forced refresh mode is enabled, and the forced refresh mode is turned on; when the current storage space of the first storage area is larger than the adjustment threshold and satisfies the fragmented refresh mode, the flag corresponding to the fragmented refresh mode is enabled, and the fragmented refresh mode is turned on; when the current storage space of the first storage area is larger than the adjustment threshold and satisfies the stop refresh mode, the flags corresponding to the forced refresh mode and the fragmented refresh mode are disabled, and the stop refresh mode is turned on.

[0092] In some embodiments, at least one adjustment threshold includes two, in which case the division of the corresponding transfer modes can be relatively simple. In some specific embodiments, the two adjustment thresholds correspond to a range of 60%-80%, 20%-40%, exemplified by 70%, 30%, and the corresponding transfer modes can be the aforementioned fragment refresh mode and stop refresh mode. When the current storage space of the first storage area is greater than or equal to 70%, the fragment refresh mode is enabled; when the current storage space of the first storage area is less than 30%, the stop refresh mode is enabled.

[0093] In some embodiments, at least one adjustment threshold includes one, and in this case, the division of the corresponding transfer mode can be relatively simple. In some specific embodiments, the one adjustment threshold corresponds to a proportion range of 50-70%, exemplified as 60%, and the corresponding transfer mode can be the aforementioned fragment refresh mode and stop refresh mode. When the current storage space of the first storage area is greater than or equal to 60%, the fragment refresh mode is enabled; when the current storage space of the first storage area is less than 60%, the stop refresh mode is enabled.

[0094] It can be understood that, for the memory system side, one or more adjustment thresholds can be obtained through instructions or the like, and the ratio of the current storage space of the first storage area to the total space can be periodically obtained, and the ratio can be compared with the one or more adjustment thresholds obtained above, and based on the comparison result, it is decided to enable or disable the flags corresponding to different transfer modes, thereby achieving adjustment of different transfer modes.

[0095] It should be noted that, in the embodiments of the present application, corresponding adjustment thresholds and transfer modes can be set according to requirements, and the above are only some examples and are not used to limit the adjustment thresholds and transfer modes in the embodiments of the present application. It is understandable that the more adjustment thresholds are set, the more complex the setting of the corresponding transfer mode is.

[0096] The aforementioned memory system determines and switches the adjustment mode according to the size relationship between the current storage space of the first storage area and the adjustment threshold value, which can be called an automatic refresh mode or an automatic adjustment mode. The memory system switches the adjustment mode according to the specified adjustment mode sent by the host system, which can be called a passive refresh mode or a passive adjustment mode. In some specific embodiments, the automatic refresh mode and the passive refresh mode can be switched by instructions or the like to obtain better compatibility.

[0097] In some embodiments, the memory controller is specifically configured to: receive a first instruction, the first instruction instructing the storage memory system to enter an automatic adjustment mode; in response to the first instruction, receive a second instruction, the second instruction including the at least one adjustment threshold; and obtain the current storage space of the first storage area according to a preset period.

[0098] In some embodiments, the memory controller is further configured to: receive a third instruction, the third instruction instructing the storage memory system to enter a passive adjustment mode; after the third instruction, receive a fourth instruction, the fourth instruction instructing to transfer the data stored in the first storage area to the second storage area according to a specified transfer mode; in response to the fourth instruction, transfer the data stored in the first storage area to the second storage area according to the specified transfer mode.

[0099] Here, the first instruction instructs the storage memory system to enter the automatic adjustment mode, and the second instruction is used to transfer one or more adjustment thresholds from the host system to the memory system. The third instruction instructs the storage memory system to enter the passive adjustment mode, and the fourth instruction is used to transfer the specified transfer mode to the storage memory system, and the memory system directly transfers the data in the first storage area to the data in the second storage area according to the transfer mode specified by the host system.

[0100] Here, acquiring the current storage space of the first storage area according to a preset period can be understood as adjusting the transfer mode according to a preset period, that is, the switching of the transfer mode is adjusted according to a preset period. In some specific embodiments, the preset period here may include 100ms-2s, exemplarily 1s.

[0101] In other embodiments, each time the memory system enters an idle state, the current storage space acquisition and transfer mode are switched.

[0102] It can be understood that switching the transfer mode according to the preset period can avoid the memory system entering the idle state too frequently (for example, 10ms) resulting in too frequent transfer mode modifications and smaller refresh granularity; switching the transfer mode according to the preset period can avoid the memory system having a large amount of traffic on the input and output interfaces, and there is no chance or it takes too long (for example, 3s) to enter the idle state, resulting in no chance or a relatively delayed change of the refresh mode, which makes the reading and writing speed of the memory device slow down when the current storage space of the first storage space is insufficient.

[0103] In some embodiments, the memory controller is configured to: control the memory device to read the data stored in the first storage area according to a preset transfer mode, and write the read data into the second storage area.

[0104] In some specific embodiments, when the data stored in the first storage area is transferred to the second storage area, the data twisting can be implemented inside the memory device, exemplarily, it can be implemented by a copyback read instruction (Copyback Read) and a copyback write instruction (Copyback Rrogram).

[0105] In some specific embodiments, when the data stored in the first storage area is transferred to the second storage area, the data twisting can be implemented between the memory device and the memory controller. Specifically, the data stored in the first storage area in the memory device can be fed back to the memory controller after the read operation, and then written from the memory controller to the second storage area in the memory device.

[0106] An embodiment of the present application further proposes a host system, comprising: a memory unit; an interface; a controller unit, configured to: use the interface to send a first instruction, the first instruction instructing the memory system to enter an automatic adjustment mode; the memory system comprises a memory device, the memory device comprises a first storage area and a second storage area, the first storage area comprises a plurality of first storage units that store data in a single-bit mode, the second storage area comprises a plurality of second storage units that store data in a multi-bit mode; after sending the first instruction, send a second instruction, the second instruction comprises at least one adjustment threshold, the at least one adjustment threshold and the current storage space of the first storage area provide a basis for a transfer mode of transferring at least part of the data stored in the first storage area to the second storage area.

[0107] In some embodiments, the controller unit is configured to: send a third instruction, wherein the third instruction instructs the storage memory system to enter a passive adjustment mode; after sending the third instruction, send a fourth instruction, wherein the fourth instruction instructs the data stored in the first storage area to be transferred to the second storage area according to a specified transfer mode.

[0108] Here, for the host system side, the driver can be modified to skip the refresh check of all first storage areas in the driver code. At the same time, there is no need to modify a large number of codes related to refresh operations. Only two flags protocols need to be added to achieve refresh adjustment of different transfer modes.

[0109] An embodiment of the present application also proposes an electronic device, comprising: a host system and a memory system coupled to the host system; wherein the memory system comprises a memory device, the memory device comprises a first storage area and a second storage area, the first storage area comprises a plurality of first storage units storing data in a unit mode, and the second storage area comprises a plurality of second storage units storing data in a multi-bit mode; the host system is configured to: send a first instruction; the memory system is configured to: receive the first instruction, and enter an automatic adjustment mode in response to the first instruction; the host system is further configured to: send a second instruction after the first instruction, the second instruction comprising at least one adjustment threshold; the memory system is further configured to: receive the second instruction; obtain the current storage space of the first storage area; and transfer the data stored in the first storage area to the second storage area according to a preset mode based on the current storage space of the first storage area and the at least one adjustment threshold.

[0110] Here, the memory system determines and switches the adjustment mode according to the size relationship between the current storage space of the first storage area and the adjustment threshold. Fig.9A The host system notifies the memory system to enter the automatic adjustment mode through a first instruction, and sends one or more adjustment thresholds to the memory system through a second instruction. The memory controller in the memory system periodically obtains the current storage space of the first storage area of ​​the memory device, and after the memory device feeds back the current storage space of the first storage area each time, compares the current storage space of the first storage area with the one or more adjustment thresholds, determines the current transfer mode according to the comparison result, and controls the memory device to transfer data according to the current transfer mode.

[0111] In some embodiments, the host system is further configured to: send a third instruction; the memory system is further configured to: receive the third instruction, and enter a passive adjustment mode in response to the third instruction; the host system is further configured to: send a fourth instruction after sending the third instruction; the memory system is further configured to: in response to the fourth instruction, transfer the data stored in the first storage area to the second storage area according to a specified transfer mode.

[0112] Here, the memory system switches the adjustment mode according to the specified adjustment mode sent by the host system. Fig. 9B The host system notifies the memory system to enter the passive adjustment mode through the third instruction, and sends the specified transfer mode to the memory system through the fourth instruction. The memory controller in the memory system controls the memory device to transfer data according to the current transfer mode.

[0113] An embodiment of the present application further proposes an electronic device, comprising: a host system and a memory system coupled to the host system; wherein the memory system comprises a memory device, the memory device comprises a first storage area and a second storage area, the first storage area comprises a plurality of first storage units that store data in a unit mode, and the second storage area comprises a plurality of second storage units that store data in a multi-bit mode; the host system is configured to: send a fifth instruction; the memory system is configured to: receive the fifth instruction, and in response to the fifth instruction, feedback the current storage space of the first storage area; the host system is further configured to: receive the current storage space of the first storage area, obtain at least one adjustment threshold; determine a transfer mode for transferring at least part of the data stored in the first storage area to the second storage area according to the current storage space of the first storage area and the at least one adjustment threshold; send a sixth instruction; the memory system is configured to: receive the sixth instruction, and in response to the sixth instruction, transfer at least part of the data stored in the first storage area to the second storage area according to the determined transfer mode.

[0114] Different from the aforementioned electronic device, here, the execution subject corresponding to the adjustment mode is determined to be the host system according to the size relationship between the current storage space of the first storage area and the adjustment threshold. That is to say, the memory system feeds back the current storage space of the first storage area in the memory device to the host system, and the host system does not need to send the adjustment threshold to the memory system. Instead, after the host system obtains the adjustment threshold, it compares the current storage space of the first storage area with the adjustment threshold, determines the transfer mode according to the comparison result, and sends the determined transfer mode to the memory system.

[0115] For example, Fig. 9CThe host system notifies the memory system to enter the automatic adjustment mode through the fifth instruction. The memory controller in the memory system periodically obtains the current storage space of the first storage area of ​​the memory device in response to the fifth instruction, and feeds back the current storage space of the first storage area fed back by the memory device to the host system each time, compares the current storage space of the first storage area with the obtained one or more adjustment thresholds, determines the current transfer mode according to the comparison result, and sends the currently determined transfer mode to the memory controller through the sixth instruction. The memory controller controls the memory device to transfer data according to the current transfer mode.

[0116] It can be understood that the data transfer scheme of the embodiment of the present application periodically queries the current remaining space of the first storage area and periodically switches the transfer mode. Each time the current remaining space of the first storage area is queried, the previously saved query results are queried first, and new queries are only performed on the updated local area. This can avoid polling the entire memory space of the first memory area each time the idle state is entered, thereby reducing the software polling overhead.

[0117] At the same time, the data transfer scheme of the embodiment of the present application can avoid the frequent transfer mode modification and smaller refresh granularity caused by the memory system entering the idle state too frequently (for example, 10ms) by switching the transfer mode according to the preset cycle, thereby achieving the effect of increasing the refresh granularity and saving power consumption. And switching the transfer mode according to the preset cycle can improve the problem that there is no opportunity or a relatively delayed change of the refresh mode due to the large flow of the input and output interface of the memory system, and there is no opportunity or it takes too long to enter the idle state, so that the read and write speed of the memory device slows down when the current storage space of the first storage space is insufficient.

[0118] An embodiment of the present application also proposes an operating method of a memory system, wherein the memory system includes: a memory device, wherein the memory device includes a first storage area and a second storage area, wherein the first storage area includes a plurality of first storage units that store data in a single-bit mode, and the second storage area includes a plurality of second storage units that store data in a multi-bit mode; the operating method includes: transferring the data stored in the first storage area to the second storage area according to a preset transfer mode based on the current storage space of the first storage area and at least one adjustment threshold.

[0119] In some embodiments, the at least one adjustment threshold includes multiple ones; based on the current storage space of the first storage area and at least one adjustment threshold, at least part of the data stored in the first storage area is transferred to the second storage area according to a preset transfer frequency, including: based on the size relationship between the current storage space of the first storage area to the total space and the multiple adjustment thresholds, determining the transfer mode for transferring the data stored in the first storage area to the second storage area, different transfer modes correspond to different transfer frequencies and / or transfer data amounts.

[0120] In some embodiments, the multiple adjustment thresholds include a first adjustment threshold corresponding to a first proportion, a second adjustment threshold corresponding to a second proportion, and a third adjustment threshold corresponding to a third proportion, the first proportion is less than the second proportion, and the second proportion is less than the third proportion; the transfer mode for transferring at least part of the data stored in the first storage area to the second storage area according to the size relationship between the proportion of the current storage space of the first storage area to the total space and the multiple adjustment thresholds includes: when the current storage space of the first storage area to the total space accounts for less than or equal to the first proportion, using the first transfer mode to transfer at least part of the data stored in the first storage area to the second storage area according to a first frequency; when the current storage space of the first storage area to the total space accounts for more than the first proportion and less than the second proportion, using the second transfer mode to transfer part of the data stored in the first storage area to the second storage area according to a second frequency; when the current storage space of the first storage area to the total space accounts for more than the third proportion, using the third transfer mode to transfer at most part of the data stored in the first storage area to the second storage area; wherein the first frequency corresponding to the first transfer mode is greater than the second frequency corresponding to the second transfer mode, and the second frequency corresponding to the second transfer mode is greater than the third frequency corresponding to the third transfer mode.

[0121] In some embodiments, the method further includes: receiving a first instruction, the first instruction instructing the storage memory system to enter an automatic adjustment mode; in response to the first instruction, receiving a second instruction, the second instruction including the at least one adjustment threshold; and obtaining the current storage space of the first storage area according to a preset period.

[0122] In some embodiments, the method further includes: receiving a third instruction, wherein the third instruction instructs the storage memory system to enter a passive adjustment mode; after the third instruction, receiving a fourth instruction, wherein the fourth instruction instructs the data stored in the first storage area to be transferred to the second storage area according to a specified transfer mode; and in response to the fourth instruction, transferring the data stored in the first storage area to the second storage area according to the specified transfer mode.

[0123] In some embodiments, transferring at least part of the data stored in the first storage area to the second storage area according to a preset transfer mode includes: reading the data stored in the first storage area according to the preset transfer mode, and writing the read data to the second storage area.

[0124] It should be noted that the operation method of the memory system in the above embodiment can be understood by referring to the specific implementation scheme of the transfer mode switching described in the memory system in the above embodiment.

[0125] An embodiment of the present application also proposes an operating method of a host system, which is coupled to the memory system, and the method includes: sending a first instruction, the first instruction instructing the memory system to enter an automatic adjustment mode; the memory system includes a memory device, the memory device includes a first storage area and a second storage area, the first storage area includes a plurality of first storage units that use a single-bit mode to store data, and the second storage area includes a plurality of second storage units that use a multi-bit mode to store data; after sending the first instruction, sending a second instruction, the second instruction includes at least one adjustment threshold, the at least one adjustment threshold and the current storage space of the first storage area provide a basis for a transfer mode of transferring data stored in the first storage area to the second storage area.

[0126] In some embodiments, the method further includes: sending a third instruction, wherein the third instruction instructs the storage memory system to enter a passive adjustment mode; after sending the third instruction, sending a fourth instruction, wherein the fourth instruction instructs at least part of the data stored in the first storage area to be transferred to the second storage area according to a specified transfer mode.

[0127] It should be noted that the operation method of the host system in the above embodiment can be understood by referring to the specific implementation scheme of the transfer mode switching described in the host system in the above embodiment.

[0128] The present application also provides an operating method of an electronic device, wherein the electronic device includes a host system and a memory system coupled to the host system; wherein the memory system includes a memory device, the memory device includes a first storage area and a second storage area, the first storage area includes a plurality of first storage units that use a single-bit mode to store data, and the second storage area includes a plurality of second storage units that use a multi-bit mode to store data; Figure 7 and Fig. 10A FIG. 9 is a schematic flow chart of a method for operating an electronic device according to an embodiment of the present disclosure, wherein the method for operating the electronic device comprises the following steps:

[0129] Step S1001: the host system sends a first instruction;

[0130] Step S1003: the memory system receives the first instruction, and enters an automatic adjustment mode in response to the first instruction;

[0131] Step S1005: the host system sends a second instruction after the first instruction, where the second instruction includes at least one adjustment threshold;

[0132] Step S1007: the memory system receives the second instruction; obtains the current storage space of the first storage area according to a preset cycle; and transfers the data stored in the first storage area to the second storage area according to a preset transfer mode based on the current storage space of the first storage area and the at least one adjustment threshold.

[0133] In some embodiments, the method further includes: the host system sends a third instruction; the memory system receives the third instruction and enters a passive adjustment mode in response to the third instruction; after sending the third instruction, the host system sends a fourth instruction; and in response to the fourth instruction, the memory system transfers the data stored in the first storage area to the second storage area according to a specified transfer mode.

[0134] The present application also provides an operating method of an electronic device, the electronic device comprising: a host system and a memory system coupled to the host system; wherein the memory system comprises a memory device, the memory device comprises a first storage area and a second storage area, the first storage area comprises a plurality of first storage units that store data in a single-bit mode, and the second storage area comprises a second storage unit that stores data in a multi-bit mode; Figure 7 and Fig. 10B , Fig. 10B A schematic flow chart of another method for operating an electronic device provided in an embodiment of the present disclosure, wherein the method for operating the electronic device comprises the following steps:

[0135] Step S1002: the host system sends a fifth instruction;

[0136] Step S1004: the memory system receives the fifth instruction, and in response to the fifth instruction, feeds back the current storage space of the first storage area;

[0137] Step S1006: the host system receives the current storage space of the first storage area and obtains at least one adjustment threshold; determines the transfer frequency of transferring the data stored in the first storage area to the second storage area according to the current storage space of the first storage area and the at least one adjustment threshold; and sends a sixth instruction;

[0138] Step S1008: the memory system receives the sixth instruction, and in response to the sixth instruction, transfers the data stored in the first storage area to the second storage area according to the determined transfer mode.

[0139] The embodiment of the present application further proposes a storage medium, on which executable instructions are stored. When the executable instructions are executed, the steps of the method described in the embodiment of the present application can be implemented.

[0140] In an embodiment of the present application, the read and write speed of the first storage area of ​​the memory device in the memory system is greater than the read and write speed of the second storage area, and the memory control in the memory system determines a transfer mode for transferring at least part of the data in the first storage area to the second storage area according to the size relationship between the current storage space of the first memory and at least one adjustment threshold. In an embodiment of the present application, the transfer mode is flexibly adjusted according to the size relationship between the remaining storage space of the first memory and the adjustment threshold, which can better adapt to different application scenarios and take into account both lower power consumption and better read and write performance.

[0141] In some embodiments, the memory system includes a universal flash storage device (UFS) or a solid state drive (SSD). The memory device includes a NAND type memory.

[0142] An embodiment of the present application further provides a storage medium having executable instructions stored thereon. When the executable instructions are executed by an electronic device, the steps of the operating method of the electronic device described in the above embodiment of the present application can be implemented.

[0143] In some specific embodiments, the storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface storage, an optical disk, or a compact disc read-only memory (CD-ROM); it can also be various devices including one or any combination of the above-mentioned memory devices.

[0144] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment.

[0145] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, such as in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or code portions).

[0146] As an example, the executable instructions may be deployed to be executed on one electronic device, or on multiple electronic devices located at one site, or on multiple electronic devices distributed at multiple sites and interconnected by a communication network.

[0147] In some specific embodiments, reference Fig.11 , Fig.11A schematic diagram of the composition structure of a storage medium provided in an embodiment of the present application; wherein the storage medium includes a first storage medium corresponding to the host system 108, a second storage medium corresponding to the memory system 102, and a third storage medium corresponding to the electronic device; when the executable instruction is executed by the host system, the first storage medium can be used to implement the steps of the operating method of the host system described in the above embodiment of the present application; when the executable instruction is executed by the memory system, the second storage medium can be used to implement the steps of the operating method of the memory system described in the above embodiment of the present application; when the executable instruction is executed by the electronic device, the third storage medium can be used to implement the steps of the operating method of the electronic device described in the above embodiment of the present application.

[0148] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. The above-mentioned sequence numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0149] The methods disclosed in several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0150] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A memory system, characterized in that: include: A memory device, comprising a first storage area and a second storage area, wherein the first storage area comprises a plurality of first storage units that store data in a single-bit mode, and the second storage area comprises a plurality of second storage units that store data in a multi-bit mode; a memory controller coupled to the memory device and configured to: The data stored in the first storage area is transferred to the second storage area according to a preset transfer mode according to the current storage space of the first storage area and at least one adjustment threshold.

2. The memory system according to claim 1, wherein: The at least one adjustment threshold comprises a plurality of; The memory controller is configured to: Based on the relationship between the current storage space ratio of the first storage area to the total space and the multiple adjustment thresholds, a transfer mode for transferring the data stored in the first storage area to the second storage area is determined, and different transfer modes correspond to different transfer frequencies and / or transfer data volumes.

3. The memory system according to claim 2, wherein: The multiple adjustment thresholds include a first adjustment threshold corresponding to a first proportion, a second adjustment threshold corresponding to a second proportion, and a third adjustment threshold corresponding to a third proportion, the first proportion is smaller than the second proportion, and the second proportion is smaller than the third proportion; The memory controller is configured to: When the current storage space of the first storage area accounts for less than or equal to the first proportion of the total space, at least part of the data stored in the first storage area is transferred to the second storage area at a first frequency using a first transfer mode; When the current storage space of the first storage area accounts for a larger proportion of the total space than the first proportion and is smaller than the second proportion, using a second transfer mode to transfer part of the data stored in the first storage area to the second storage area at a second frequency; When the current storage space of the first storage area accounts for a larger proportion of the total space than the third proportion, at most part of the data stored in the first storage area is transferred to the second storage area at a third frequency using a third transfer mode; The first frequency corresponding to the first transfer mode is greater than the second frequency corresponding to the second transfer mode, and the second frequency corresponding to the second transfer mode is greater than the third frequency corresponding to the third transfer mode.

4. The memory system according to claim 3, characterized in that: The first transfer mode is to continuously transfer data when the storage memory system is in an idle state until all data is transferred or the storage memory system exits the idle state; the second transfer mode is to transfer a portion of the data when the storage memory system is in an idle state; and the third transfer mode is to stop transferring data.

5. The memory system according to claim 1, wherein: The memory controller is specifically configured as follows: receiving a first instruction, wherein the first instruction instructs the storage memory system to enter an automatic adjustment mode; In response to the first instruction, receiving a second instruction, wherein the second instruction includes the at least one adjustment threshold; and The current storage space of the first storage area is obtained according to a preset period.

6. The memory system according to claim 1, wherein: The memory controller is further configured to: receiving a third instruction, wherein the third instruction instructs the storage memory system to enter a passive adjustment mode; After the third instruction, receiving a fourth instruction, the fourth instruction instructing to transfer the data stored in the first storage area to the second storage area according to a specified transfer mode; In response to the fourth instruction, the data stored in the first storage area is transferred to the second storage area according to a specified transfer mode.

7. The memory system according to any one of claims 1 to 6, characterized in that: The memory controller is configured to: The memory device is controlled to read the data stored in the first storage area according to a preset transfer mode, and write the read data into the second storage area.

8. A host system, characterized in that: include: Memory unit; interface; The controller unit is configured to: send a first instruction through the interface, wherein the first instruction instructs the memory system to enter an automatic adjustment mode; wherein the memory system includes a memory device, the memory device includes a first storage area and a second storage area, the first storage area includes a plurality of first storage units that store data in a single-bit mode, and the second storage area includes a plurality of second storage units that store data in a multi-bit mode; After sending the first instruction, a second instruction is sent, wherein the second instruction includes at least one adjustment threshold, and the at least one adjustment threshold and the current storage space of the first storage area provide a basis for a transfer mode of transferring data stored in the first storage area to the second storage area.

9. The host system according to claim 8, characterized in that: The controller section is configured as: sending a third instruction, wherein the third instruction instructs the storage memory system to enter a passive adjustment mode; After sending the third instruction, a fourth instruction is sent, wherein the fourth instruction instructs to transfer the data stored in the first storage area to the second storage area according to a specified transfer mode.

10. An electronic device, characterized in that: include: A host system and a memory system coupled to the host system; wherein, The memory system comprises a memory device, the memory device comprises a first storage area and a second storage area, the first storage area comprises a plurality of first storage cells that store data in a single-bit mode, and the second storage area comprises a plurality of second storage cells that store data in a multi-bit mode; The host system is configured to: send a first instruction; The memory system is configured to: receive the first instruction, and enter an automatic adjustment mode in response to the first instruction; The host system is further configured to: send a second instruction after the first instruction, wherein the second instruction includes at least one adjustment threshold; The memory system is also configured to: receive the second instruction; obtain the current storage space of the first storage area; and transfer the data stored in the first storage area to the second storage area according to a preset mode based on the current storage space of the first storage area and the at least one adjustment threshold.

11. The electronic device according to claim 10, characterized in that: The host system is further configured to: send a third instruction; The memory system is further configured to: receive the third instruction, and enter a passive adjustment mode in response to the third instruction; The host system is further configured to: after sending the third instruction, send a fourth instruction; The memory system is further configured to: in response to the fourth instruction, transfer the data stored in the first storage area to the second storage area according to a specified transfer mode.

12. An electronic device, characterized in that: include: A host system and a memory system coupled to the host system; wherein, The memory system comprises a memory device, the memory device comprises a first storage area and a second storage area, the first storage area comprises a plurality of first storage cells that store data in a single-bit mode, and the second storage area comprises a plurality of second storage cells that store data in a multi-bit mode; The host system is configured to: send a fifth instruction; The memory system is configured to: receive the fifth instruction, and feedback a current storage space of the first storage area in response to the fifth instruction; The host system is further configured to: receive the current storage space of the first storage area, obtain at least one adjustment threshold; determine a transfer mode for transferring the data stored in the first storage area to the second storage area according to the current storage space of the first storage area and the at least one adjustment threshold; and send a sixth instruction; The memory system is configured to: receive the sixth instruction, and in response to the sixth instruction, transfer the data stored in the first storage area to the second storage area according to a determined transfer mode.

13. A method for operating a memory system, characterized in that: The memory system comprises: a memory device, the memory device comprises a first storage area and a second storage area, the first storage area comprises a plurality of first storage units that store data in a single-bit mode, and the second storage area comprises a plurality of second storage units that store data in a multi-bit mode; the operation method comprises: The data stored in the first storage area is transferred to the second storage area according to a preset transfer mode according to the current storage space of the first storage area and at least one adjustment threshold.

14. The operating method according to claim 13, characterized in that: The at least one adjustment threshold comprises a plurality of; The method further comprises: transferring at least part of the data stored in the first storage area to the second storage area at a preset transfer frequency according to the current storage space of the first storage area and at least one adjustment threshold, comprising: Based on the relationship between the current storage space ratio of the first storage area to the total space and the multiple adjustment thresholds, a transfer mode for transferring the data stored in the first storage area to the second storage area is determined, and different transfer modes correspond to different transfer frequencies and / or transfer data volumes.

15. The operating method according to claim 14, characterized in that: The multiple adjustment thresholds include a first adjustment threshold corresponding to a first proportion, a second adjustment threshold corresponding to a second proportion, and a third adjustment threshold corresponding to a third proportion, the first proportion is smaller than the second proportion, and the second proportion is smaller than the third proportion; The determining, according to a size relationship between a proportion of the current storage space of the first storage area to the total space and a plurality of the adjustment thresholds, a transfer mode for transferring the data stored in the first storage area to the second storage area comprises: When the current storage space of the first storage area accounts for less than or equal to the first proportion of the total space, at least part of the data stored in the first storage area is transferred to the second storage area at a first frequency using a first transfer mode; When the current storage space of the first storage area accounts for a larger proportion of the total space than the first proportion and is smaller than the second proportion, using a second transfer mode to transfer part of the data stored in the first storage area to the second storage area at a second frequency; When the current storage space of the first storage area accounts for a larger proportion of the total space than the third proportion, at most part of the data stored in the first storage area is transferred to the second storage area using the third transfer mode; The first frequency corresponding to the first transfer mode is greater than the second frequency corresponding to the second transfer mode, and the second frequency corresponding to the second transfer mode is greater than the third frequency corresponding to the third transfer mode.

16. The operating method according to claim 13, characterized in that: The method further comprises: receiving a first instruction, wherein the first instruction instructs the storage memory system to enter an automatic adjustment mode; In response to the first instruction, receiving a second instruction, wherein the second instruction includes the at least one adjustment threshold; and The current storage space of the first storage area is obtained according to a preset period.

17. The operating method according to claim 13, characterized in that: The method further comprises: receiving a third instruction, wherein the third instruction instructs the storage memory system to enter a passive adjustment mode; After the third instruction, receiving a fourth instruction, the fourth instruction instructing to transfer the data stored in the first storage area to the second storage area according to a specified transfer mode; In response to the fourth instruction, the data stored in the first storage area is transferred to the second storage area according to a specified transfer mode.

18. The operating method according to any one of claims 13 to 17, characterized in that: The transferring at least part of the data stored in the first storage area to the second storage area according to a preset transfer mode includes: The data stored in the first storage area is read according to a preset transfer mode, and the read data is written into the second storage area.

19. A method for operating an electronic device, characterized in that: The electronic device comprises a host system and a memory system coupled to the host system; wherein the memory system comprises a memory device, the memory device comprises a first storage area and a second storage area, the first storage area comprises a plurality of first storage units storing data in a single-bit mode, and the second storage area comprises a plurality of second storage units storing data in a multi-bit mode; the method comprises: The host system sends a first instruction; The memory system receives the first instruction, and enters an automatic adjustment mode in response to the first instruction; The host system sends a second instruction after the first instruction, wherein the second instruction includes at least one adjustment threshold; The memory system receives the second instruction; obtains the current storage space of the first storage area according to a preset cycle; and transfers the data stored in the first storage area to the second storage area according to a preset transfer mode based on the current storage space of the first storage area and the at least one adjustment threshold.

20. The operating method according to claim 19, characterized in that: The method further comprises: The host system sends a third instruction; The memory system receives the third instruction, and enters a passive adjustment mode in response to the third instruction; After sending the third instruction, the host system sends a fourth instruction; In response to the fourth instruction, the memory system transfers the data stored in the first storage area to the second storage area according to a specified transfer mode.

21. A method for operating an electronic device, characterized in that: The electronic device comprises: a host system and a memory system coupled to the host system; wherein the memory system comprises a memory device, the memory device comprises a first storage area and a second storage area, the first storage area comprises a plurality of first storage units storing data in a single-bit mode, and the second storage area comprises a second storage unit storing data in a multi-bit mode; the method comprises: The host system sends a fifth instruction; The memory system receives the fifth instruction, and in response to the fifth instruction, feeds back a current storage space of the first storage area; The host system receives the current storage space of the first storage area and obtains at least one adjustment threshold; determines the transfer frequency of transferring the data stored in the first storage area to the second storage area according to the current storage space of the first storage area and the at least one adjustment threshold; and sends a sixth instruction; The memory system receives the sixth instruction, and in response to the sixth instruction, transfers the data stored in the first storage area to the second storage area according to the determined transfer mode.

22. A storage medium, characterized in that: The storage medium stores executable instructions, and when the executable instructions are executed, the steps of the method described in any one of claims 13-21 can be implemented.

Images