Fpga chip data sorting method, fpga chip and electronic equipment

Abstract

The application relates to an FPGA chip data sorting method, an FPGA chip and electronic equipment. The FPGA chip is in communication connection with an extended memory, and the method comprises the following steps: obtaining to-be-sorted data, and writing the to-be-sorted data into the memory; reading the to-be-sorted data in the memory; respectively performing single sorting on the to-be-sorted data according to a preset sorting number; and outputting sorted ordered data in a specified range each time after each single sorting is completed. According to the scheme, the FPGA chip can be combined with the memory, the memory is used to cache to-be-sorted data, the problem of insufficient on-chip caching resources of the FPGA is solved, and therefore, fast sorting of a large amount of data in the FPGA chip is realized. The FPGA implementation logic of the method is simple, the sorting time consumption is less, and the stability of sorting is high.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a data sorting method for FPGA chips, FPGA chips, and electronic devices. Background Technology

[0002] In today's rapidly developing information technology landscape, data processing speed has become a key factor in system response time. Sorting algorithms are a fundamental and indispensable data processing operation in the field of computer science. By sorting, data can be arranged in a certain order, thereby reducing the time complexity of subsequent operations.

[0003] An FPGA (Field Programmable Gate Array) is a type of chip whose internal structure can be modified through programming. Due to its high flexibility and customizability, it plays a crucial role in many fields. Currently, most sorting algorithms implemented in FPGAs employ traditional sorting algorithms, such as insertion sort, selection sort, and bubble sort. These algorithms typically require allocating storage space for the data to be sorted within the FPGA chip, resulting in high time complexity, and also necessitate frequent comparisons and exchanges of the data. When dealing with large volumes of data, implementing sorting algorithms faces two main challenges: firstly, the limited storage resources of the FPGA chip may not be sufficient to cache all the data; secondly, frequent data comparisons and exchanges significantly increase the total sorting time. Based on these two challenges, sorting algorithms implementable in FPGA chips are only suitable for sorting small amounts of data; implementing sorting functionality becomes extremely difficult with large datasets. Summary of the Invention

[0004] To address or partially address the problems existing in related technologies, this application provides an FPGA chip data sorting method, an FPGA chip, and an electronic device, which can realize the rapid sorting of large amounts of data in an FPGA chip.

[0005] The first aspect of this application provides a data sorting method for an FPGA chip, wherein the FPGA chip is communicatively connected to an extended memory, the method comprising:

[0006] Obtain the data to be sorted and write the data to be sorted into the memory;

[0007] Read the data to be sorted from the memory;

[0008] The data to be sorted is sorted once according to a preset number of sorting steps;

[0009] After each sorting operation, output a specified range of sorted, ordered data.

[0010] Preferably, the single sorting of the to-be-sorted data according to the preset sorting times comprises:

[0011] For each single sorting, the number of occurrences of each data in the to-be-sorted data is counted to obtain an initial score of each data, and a score sequence is generated according to the initial score.

[0012] The storage value of each data is determined according to the score sequence, and the to-be-sorted data is sorted based on the storage value.

[0013] Preferably, the storage value of each data is determined according to the score sequence, and the to-be-sorted data is sorted based on the storage value.

[0014] The first n terms of each initial score in the score sequence are calculated in turn as the storage value of the data corresponding to the initial score.

[0015] Each data in the to-be-sorted data is read, and the storage value corresponding to the data is output; each time the data appears, the storage value corresponding to the data is reduced by one.

[0016] After the reading of the to-be-sorted data is completed, the final storage value of the to-be-sorted data is obtained.

[0017] The to-be-sorted data is sorted according to the final storage value.

[0018] Preferably, the score sequence generated according to the initial score comprises:

[0019] Each data is arranged in order of size, and the initial score of each data is arranged according to the arrangement order of each data to generate a score sequence corresponding to the initial score.

[0020] Preferably,

[0021] The preset sorting times are determined in the following manner:

[0022] The limit value of the data output by the FPGA chip each time is determined.

[0023] The preset sorting times are determined according to the number of to-be-sorted data and the limit value of the data output by the FPGA chip each time.

[0024] The output of the specified range of sorted ordered data each time after each single sorting is completed comprises:

[0025] After each single sorting is completed,

[0026] For the first output, a preset number of ranked ordered data located in the front or rear column is outputted, wherein the preset number does not exceed the limit value of the FPGA chip for each output data;

[0027] For the non-first output, a preset number of ranked ordered data located in the front or rear column is outputted in addition to the ordered data outputted last time.

[0028] Preferably, the memory comprises a dynamic random memory DDR.

[0029] The second aspect of the present application provides an FPGA chip, which is in communication connection with an extended memory, and the chip comprises:

[0030] a writing module, configured to acquire to-be-ordered data and write the to-be-ordered data into the memory;

[0031] a reading module, configured to read the to-be-ordered data in the memory;

[0032] a sorting module, configured to respectively perform single sorting on the to-be-ordered data according to a preset sorting number;

[0033] an output module, configured to output ordered data in a specified range after each single sorting is completed.

[0034] Preferably, the sorting module comprises:

[0035] a counting submodule, configured to count the number of occurrences of each data in the to-be-ordered data to obtain an initial score of each data and generate a score sequence according to the initial score for each single sorting;

[0036] a sorting submodule, configured to determine a storage value of each data according to the score sequence and sort the to-be-ordered data based on the storage value.

[0037] Preferably, the chip further comprises:

[0038] a limit value determining module, configured to determine the limit value of the FPGA chip for each output data;

[0039] a sorting number module, configured to determine the preset sorting number according to the number of the to-be-ordered data and the limit value of the FPGA chip for each output data;

[0040] The output module is further configured to: output, after each single sorting is completed, a preset number of sorted ordered data ranked in the front or the back for the first output, wherein the preset number does not exceed a limit value of data output by the FPGA chip each time; and output, for a non-first output, a preset number of sorted ordered data ranked in the front or the back in addition to the ordered data output last time.

[0041] The third aspect of the present application provides an electronic device, comprising:

[0042] a processor; and

[0043] a memory having executable code stored thereon, which, when executed by the processor, causes the processor to perform the method described above.

[0044] The technical scheme provided by the present application can have the following beneficial effects: the FPGA chip data sorting method provided by the embodiments of the present application, in which the FPGA chip is in communication connection with an extended memory, the method comprises the following steps: obtaining to-be-sorted data, writing the sorted data into the memory; reading the to-be-sorted data in the memory; sorting the to-be-sorted data, grouping the sorted data after the sorting is completed; and outputting the ordered data of each group in turn to obtain a final sorting result. The scheme of the present application can combine the FPGA chip with the extended memory, use the memory to cache the to-be-sorted data, solve the problem of insufficient on-chip cache resources of the FPGA, split a large amount of data sorting into a processing flow of multiple single sorting, and realize fast sorting of a large amount of data in the FPGA chip. The FPGA implementation logic of the method is simple, the sorting time is short, and the stability of the sorting is high.

[0045] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0046] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout the figures, and wherein:

[0047] Figure 1 is a flowchart of the FPGA chip data sorting method shown in the embodiments of the present application;

[0048] Figure 2 is another flowchart of the FPGA chip data sorting method shown in the embodiments of the present application;

[0049] Figure 3a is a schematic diagram of to-be-sorted data shown in the embodiments of the present application;

[0050] Figure 3b is a schematic diagram of a fractional number sequence according to an embodiment of the present application;

[0051] Figure 3c is a schematic diagram of a cumulative transformation of a fractional number sequence according to an embodiment of the present application;

[0052] Figure 3d is another schematic diagram of a fractional number sequence according to an embodiment of the present application;

[0053] Figure 3e is another schematic diagram of a fractional number sequence according to an embodiment of the present application;

[0054] Figure 3f is another schematic diagram of a fractional number sequence according to an embodiment of the present application;

[0055] Figure 3g is another schematic diagram of a fractional number sequence according to an embodiment of the present application;

[0056] Figure 4 is a schematic diagram of a structure of an FPGA chip according to an embodiment of the present application;

[0057] Figure 5 is another schematic diagram of a structure of an FPGA chip according to an embodiment of the present application;

[0058] Figure 6 is a schematic diagram of a structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0059] Embodiments of the present application will be described in more detail with reference to the drawings. Although the embodiments of the present application are shown in the drawings, it should be understood that the present application can be embodied in various forms without being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0060] The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in the present application and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0061] It should be understood that although the terms "first", "second", "third", etc. can be used in this application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information without departing from the scope of the application. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more features. In the description of the application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited.

[0062] When the data amount of the data to be sorted is large, there are two problems in the implementation of the sorting algorithm: on the one hand, the storage resources of the FPGA chip are limited and may not be sufficient to cache all the data to be sorted; on the other hand, frequent data comparison and exchange will greatly increase the total sorting time. Based on the above two problems, the sorting algorithm that can be implemented in the FPGA chip is only suitable for sorting a small amount of data, and when the data amount is large, the implementation of the sorting function is difficult.

[0063] In view of the above problems, the FPGA chip data sorting method provided in the embodiments of the application can combine the FPGA chip with the memory, use the memory to cache the data to be sorted, solve the problem of insufficient on-chip cache resources of the FPGA, split the sorting of a large amount of data into multiple single sorting processing procedures, and realize fast sorting of a large amount of data in the FPGA chip. The FPGA implementation logic of the method is simple, the sorting time is short, and the stability of the sorting is high.

[0064] The technical solutions of the embodiments of the application are described in detail below with reference to the drawings.

[0065] Figure 1 is a flowchart of the FPGA chip data sorting method shown in the embodiments of the application.

[0066] Referring to Figure 1 , the method comprises:

[0067] In step 101, the data to be sorted is obtained, and the data to be sorted is written into the memory.

[0068] In the embodiments of the application, the FPGA chip is in communication connection with the extended memory, and the two can interact with each other. The FPGA is a chip that can change the internal structure through programming and can be used for sorting data.

[0069] The FPGA chip obtains the data to be sorted through the bus, initiates a write request signal to the memory after receiving the data to be sorted, and caches the data to be sorted to the extended memory. Using the memory to cache the data to be sorted can solve the problem of insufficient on-chip cache resources of the FPGA.

[0070] The memory can be a dynamic random memory (DDR, Double Data Rate Synchronous Dynamic Random Access Memory). The FPGA chip is equipped with the DDR memory, and the read and write access of data is more efficient.

[0071] In step 102, the data to be sorted in the memory is read.

[0072] The FPGA chip reads the data to be sorted in the memory for initialization.

[0073] In step 103, the data to be sorted is sorted for a single time according to a preset sorting number.

[0074] The FPGA chip can use the counting sorting method to sort all data in the data to be sorted according to the data value size order. The main idea of counting sorting is to count the number of occurrences of each element and calculate the position of each element in the sorted array, so as to realize sorting.

[0075] Due to the limited on-chip resources of the FPGA, when the data amount of the data to be sorted is large, all the data to be sorted cannot be output at the same time after sorting. Therefore, the data to be sorted can be sorted for a single time according to a preset sorting number.

[0076] The data to be sorted for a single time according to a preset sorting number includes: for each single time sorting, counting the number of occurrences of each data in the data to be sorted to obtain the initial score of each data, and generating a score sequence according to the initial score; determining the storage value of each data according to the score sequence; and sorting the data to be sorted based on the storage value.

[0077] The preset sorting number is determined in the following manner: determining the limit value of data output by the FPGA chip each time; and determining the preset sorting number according to the number of data to be sorted and the limit value of data output by the FPGA chip each time.

[0078] Due to the limited RAM (Random Access Memory) storage resources on the FPGA chip, when the data amount of the data to be sorted is large, all the sorted data cannot be output at the same time. Therefore, the sorted data can be output in multiple times, and the limit value of data output by the FPGA chip each time can be determined. In an example, the limit value of data output by the FPGA chip each time is 2^15=32768.

[0079] The preset sorting times can be determined according to the number of the data to be sorted and the limit of the data output by the FPGA chip each time. For example, 130,000 data to be sorted need to be sorted from large to small, and the limit of the data output by the FPGA chip each time is 32768 due to the on-chip resource limitation of the FPGA chip, and the 130,000 data to be sorted can be sorted 4 times.

[0080] In step 104, the specified range of sorted ordered data is output each time after each single sorting is completed.

[0081] The specified range of sorted ordered data can be output each time after the single sorting of the data to be sorted is performed each time. For example, when the limit of the data output by the FPGA chip each time is 32768, the 130,000 data to be sorted can be sorted 4 times, the specified range of ordered data can be output each time after each single sorting is completed, the first 32768 largest data can be output after the first sorting, the first 32768 largest data of the remaining data except the data output in the first time can be output after the second sorting, the first 32768 largest data of the remaining data except the data output in the first and second times can be output after the third sorting, and the remaining data except the data output in the first, second and third times can be output after the fourth sorting. Then it is determined whether all the data are output, and if all the data are output, the sorting is completed, and the final sorting result is obtained.

[0082] The scheme of the embodiment of the application can be applied to the visual acceleration scene, the image processing scene, the data analysis scene, the neural network and other deep learning scenes based on the FPGA chip processing. In 5ms, the FPGA can complete the sorting of 100,000 data to be sorted, the sorting efficiency is high, and the time consumption is small.

[0083] The embodiment of the application provides an FPGA chip data sorting method, wherein the FPGA chip is in communication connection with an extended memory, the method comprises the following steps: obtaining data to be sorted, writing the sorted data into the memory; reading the data to be sorted in the memory; performing single sorting on the data to be sorted according to a preset sorting times; and outputting the specified range of sorted ordered data each time after each single sorting is completed. The scheme of the application can combine the FPGA chip with the memory, use the memory to cache the data to be sorted, solve the problem of insufficient on-chip cache resources of the FPGA, divide the sorting of a large amount of data into a processing flow of multiple single sorting, and realize the fast sorting of a large amount of data in the FPGA chip. The FPGA implementation logic of the method is simple, the sorting time consumption is small, and the stability of the sorting is high.

[0084] Figure 2 FIG. 4 is another flowchart of the FPGA chip data sorting method according to an embodiment of the application.

[0085] In the embodiment of the present application, the FPGA chip is in communication connection with the extended DDR memory and can interact data.

[0086] Referring to Figure 2 The method comprises the following steps:

[0087] In step 201, the data to be sorted is acquired and written into the DDR memory.

[0088] In step 202, the data to be sorted in the DDR memory is read.

[0089] Steps 201 and 202 are similar to steps 101 and 102, and the description of steps 101 and 102 can be referred to, and thus will not be repeated here.

[0090] In step 203, the number of occurrences of each data in the data to be sorted is counted for each single sorting, the initial score of each data is obtained, and the score sequence is generated according to the initial score.

[0091] For each single sorting, the counting sorting method is used to sort the data to be sorted. For all data to be sorted, the number of occurrences of each data in the data to be sorted can be counted first, and the number of occurrences of each data is taken as the initial score of the data, denoted as score. Taking the data to be sorted {1, 1, 3, 3} as an example, the number of occurrences of data 0 is 0, the score of data 0 is 0; the number of occurrences of data 1 is 2, the score of data 1 is 2; the number of occurrences of data 2 is 0, the score of data 2 is 0; the number of occurrences of data 3 is 2, the score of data 3 is 2, and then the score sequence is generated according to the initial score.

[0092] In an optional embodiment of the present application, step 203 comprises:

[0093] The data is arranged in order of size, and the initial score of each data is arranged according to the arrangement order of each data, to generate the score sequence corresponding to the initial score.

[0094] The data is arranged in order of size, and the initial score of each data is arranged according to the arrangement order of each data, to generate the score sequence corresponding to the initial score. Taking the data to be sorted {1, 1, 3, 3} as an example, the data to be sorted can be stored in the RAM resource on the FPGA chip, such as Figure 3aAs shown in the figure, in the to-be-sorted data {1, 1, 3, 3}, two data 1 are stored in the address addr1, two data 3 are stored in the address addr3, the number of occurrence of data 0 is 0, the score of data 0 is 0; the number of occurrence of data 1 is 2, the score of data 1 is 2; the number of occurrence of data 1 is 0, the score of data 1 is 0; the number of occurrence of data 3 is 2, the score of data 3 is 2, and the corresponding score sequence is {0, 2, 0, 2}. The score sequence is stored in the RAM resource on the FPGA chip, as shown in the figure Figure 3b As shown in the figure, the score sequence of the to-be-sorted data {1, 1, 3, 3} is {0, 2, 0, 2}, the first score 0 in the score sequence is stored in the address addr0, the second score 2 is stored in the address addr1, the third score 0 is stored in the address addr2, and the fourth score 2 is stored in the address addr3.

[0095] In step 204, the storage value of each data is determined according to the score sequence, and the to-be-sorted data is sorted based on the storage value.

[0096] The score sequence is accumulated and deformed, the storage value of each data in the to-be-sorted data is calculated, and the to-be-sorted data is sorted according to the size of the storage value.

[0097] In an optional embodiment of the present application, step 204 includes:

[0098] In step S11, the first n terms of each initial score in the score sequence are calculated in sequence as the storage value of the data corresponding to the initial score.

[0099] The score sequence is accumulated and deformed, the storage value of each data in the to-be-sorted data is calculated, and the to-be-sorted data is sorted according to the size of the storage value. Figure 3c As shown in the figure, the score sequence of the to-be-sorted data {1, 1, 3, 3} is {0, 2, 0, 2}, the first score 0 in the score sequence is stored in the address addr0, the second score 2 is stored in the address addr1, the third score 0 is stored in the address addr2, and the fourth score 2 is stored in the address addr3.

[0100] In sub-step S12, each data in the data to be sorted is read, and the storage value corresponding to the data is output; each time the data appears, the storage value corresponding to the data is reduced by one.

[0101] The data to be sorted is re-traversed, and each data in the data to be sorted is read, and the storage value corresponding to the data is output. Taking the data to be sorted {1, 1, 3, 3} as an example, the first read data is the first data 1, the storage value 2 corresponding to the data 1 is output, and the storage value 2 corresponding to the data 1 is reduced by 1 to obtain 1, as shown in FIG. 2a, the storage value in the address addr1 becomes 1; continue to read the data to be sorted, the second read data is the second data 1, the storage value 1 corresponding to the data 1 is output, and the storage value 1 corresponding to the data 1 is reduced by 1 to obtain 0, as shown in FIG. 2b, the storage value in the address addr1 becomes 0; continue to read the data to be sorted, the third read data is the third data 3, the storage value 4 corresponding to the data 3 is output, and the storage value 4 corresponding to the data 3 is reduced by 1 to obtain 3, as shown in FIG. 2c, the storage value in the address addr3 becomes 3; continue to read the data to be sorted, the fourth read data is the fourth data 3, the storage value 3 corresponding to the data 3 is output, and the storage value 3 corresponding to the data 3 is reduced by 1 to obtain 2, as shown in FIG. 2d, the storage value in the address addr3 becomes 2. Figure 3d Figure 3e Figure 3f Figure 3g

[0102] After the data to be sorted is read, the final storage value of the data to be sorted is obtained in sub-step S13.

[0103] After all the data to be sorted is read, the final storage value of the data to be sorted can be obtained, taking the data to be sorted {1, 1, 3, 3} as an example, after all the data to be sorted is read, the final storage value is {2, 1, 4, 3}, wherein the final storage value of the first data 1 is 2; the final storage value of the second data 1 is 1; the final storage value of the third data 3 is 4; and the final storage value of the fourth data 3 is 3. By default, the final storage value of the data in the earlier position is higher.

[0104] The data to be sorted is sorted according to the final storage value in sub-step S14.

[0105] Taking the data to be sorted {1, 1, 3, 3} as an example, after all the data to be sorted is read, the final storage value is {2, 1, 4, 3}, wherein the final storage value of the first data 1 is 2; the final storage value of the second data 1 is 1; the final storage value of the third data 3 is 4; and the final storage value of the fourth data 3 is 3. According to the size of the final storage value, the data to be sorted is sorted to obtain the sorted data {3, 3, 1, 1}.

[0106] ​​​​In step 205, after each single sorting is completed, for the first output, the preset number of sorted ordered data ranked in the front or the back is output, wherein the preset number does not exceed the limit value of data output by the FPGA chip each time; for the non-first output, the preset number of sorted ordered data ranked in the front or the back is output in addition to the ordered data output last time.

[0107] After each single sorting is completed, the ordered data of the limit value of data output by the FPGA chip each time can be output, in order to output all data faster, the preset number can be the same as the limit value of data output by the FPGA chip each time. The output order can be the ranking order from large to small according to the score or the ranking order from small to large according to the score. In the case of the first output, that is, the first sorting of the data to be sorted, if the output is in the ranking order from large to small according to the score, the preset number of sorted ordered data ranked in the front can be output; if the output is in the ranking order from large to small according to the score, the preset number of sorted ordered data ranked in the back can be output. In an example, if 130,000 data to be sorted is sorted from large to small, due to the on-chip resource limitation of the FPGA chip, the limit value of data output by the FPGA chip each time is 32,768 data, according to the number of data to be sorted and the limit value of data output by the FPGA chip each time, it can be determined that the preset sorting times is 4, and the output is in the ranking order from large to small according to the score, in the first sorting, that is, the first sorting of all data to be sorted (130,000 data to be sorted), the ranking range of the sorted data is 130,000 ~ 97,233.

[0108] In the case of non-first output, that is, 2 times or more sorting of the data to be sorted, in addition to the ordered data output last time, the sorted ordered data of a preset number of ranks in the front or rear column can be output. In an example, if 130,000 data to be sorted is sorted from large to small, due to the on-chip resource limitation of the FPGA chip, the limit of the FPGA chip for outputting data each time is 32,768 data, and the data is output in the order of the ranking from large to small. In the first sorting, that is, the first sorting of all data to be sorted (130,000 data to be sorted), the sorted ranking range of the output data is 130,000-97,233; in the second sorting, that is, the second sorting of all data to be sorted (130,000 data to be sorted), in addition to the first output data, the sorted ranking range of the output data is 97,232-64,465; in the third sorting, that is, the third sorting of all data to be sorted (130,000 data to be sorted), in addition to the first and second output data, the sorted ranking range of the output data is 64,464-31,697; in the fourth sorting, that is, the fourth sorting of all data to be sorted (130,000 data to be sorted), in addition to the first, second and third output data, the sorted ranking range of the output data is 31,696-1.

[0109] In step 206, it is judged whether all data is output, if yes, it goes to step 207; if no, it returns to step 204.

[0110] In step 207, the sorting is completed, and the final sorting result is obtained.

[0111] If all data is output, the sorting is completed, and the final sorting result is obtained, if there is still data not output, it returns to step 204, and the data is sorted again.

[0112] The FPGA chip data sorting method provided in the embodiments of the present application solves the problem of insufficient on-chip cache resources of the FPGA chip by combining the counting sorting algorithm with the extended DDR memory, splits the sorting of a large amount of data into a plurality of single sorting processing procedures, realizes the fast sorting of a large amount of data in the FPGA chip, and adopts the counting sorting algorithm, so that the data sorting logic is simple, has stable sorting, low time complexity, low space complexity and other characteristics, and does not need to frequently compare and exchange the data to be sorted, so that the sorting time is less.

[0113] Corresponding to the foregoing application function implementation method embodiments, the present application also provides an FPGA chip, an electronic device and corresponding embodiments.

[0114] Figure 4 FIG. 1 is a structural schematic diagram of an FPGA chip according to an embodiment of the present application.

[0115] In the embodiment of the application, the FPGA chip is in communication connection with the memory and can interact with data.

[0116] Referring to Figure 4 The chip comprises:

[0117] The write module 410 is configured to acquire the to-be-sequenced data and write the to-be-sequenced data into the memory.

[0118] The FPGA chip acquires the to-be-sequenced data through the bus, initiates a write request signal to the memory after receiving the to-be-sequenced data, and thus caches the to-be-sequenced data to the memory.

[0119] The read module 420 is configured to read the to-be-sequenced data in the memory.

[0120] The FPGA chip reads the to-be-sequenced data in the memory for initialization.

[0121] The sequencing module 430 is configured to perform single sequencing on the to-be-sequenced data according to a preset sequencing number.

[0122] The FPGA chip can adopt the counting sorting method to sequence all data in the to-be-sequenced data according to the data value size order. Since the on-chip resource of the FPGA is limited, when the data amount of the to-be-sequenced data is large, all to-be-sequenced data cannot be outputted simultaneously after sequencing, and thus the to-be-sequenced data can be sequentially sequenced according to the preset sequencing number.

[0123] The output module 440 is configured to output the sequenced ordered data in a specified range each time after each single sequencing is completed.

[0124] After each single sequencing is performed on the to-be-sequenced data, the sequenced ordered data in a specified range can be outputted each time.

[0125] The sequencing module 430 comprises:

[0126] The statistical submodule is configured to count the number of occurrences of each data in the to-be-sequenced data for each single sequencing, obtain the initial score of each data, and generate a score sequence according to the initial score.

[0127] The sequencing submodule is configured to determine the storage value of each data according to the score sequence and sequence the to-be-sequenced data based on the storage value.

[0128] The chip further comprises:

[0129] The limit value determination module is configured to determine the limit value of data outputted by the FPGA chip each time.

[0130] The sorting frequency module is configured to determine the preset sorting frequency according to the number of the data to be sorted and the limit of the data output by the FPGA chip each time.

[0131] The output module is further configured to: for the first output, output the sorted ordered data of the preset number of ranks in the front or rear column after each single sorting is completed, wherein the preset number is not more than the limit of the data output by the FPGA chip each time; and for the non-first output, output the sorted ordered data of the preset number of ranks in the front or rear column in addition to the ordered data output last time.

[0132] The sorting sub-module is further configured to sequentially calculate the first n terms of each score in the score sequence as the storage value of the data corresponding to the score, read each data in the data to be sorted, output the storage value corresponding to the data, and decrease the storage value corresponding to the data by one each time the data appears, and obtain the final storage value of the data to be sorted after the reading of the data to be sorted is completed, and sort the data to be sorted according to the final storage value.

[0133] The counting sub-module is further configured to sequentially arrange each data in size order, and generate the score sequence corresponding to the initial score according to the arrangement order of each data.

[0134] Figure 5 is another structural schematic diagram of the FPGA chip shown in the embodiments of the present application. The FPGA chip is divided into a PL (Programmable Logic, programmable logic) and a PS (Processing System, processing system), the PL is connected with an HP (High-Performance, high performance) in the PS, the PL includes a sorting circuit, a read-write control circuit, a VDMA (Video Direct Memory Access, video direct memory access), an AXI-SmartConnect master-slave interconnection module, and the FPGA chip is in communication connection with a memory.

[0135] The embodiments of the present application provide an FPGA chip in communication connection with an extended memory, and solve the problem of insufficient on-chip cache resources of the FPGA through a method of combining the counting sorting algorithm with the memory, realize fast sorting of a large amount of data in the FPGA chip, and adopt the counting sorting algorithm, so that the data sorting logic is simple, stable sorting, low time complexity, low space complexity and other characteristics are achieved, and the sorting time is less.

[0136] As to the apparatus in the above embodiments, the specific manners in which various modules perform operations have been described in detail in the embodiments of the method, and will not be described herein in detail.

[0137] Figure 6 FIG. 1 is a structural schematic diagram of an electronic device according to an embodiment of the present application.

[0138] Referring to FIG. 6, Figure 6 The electronic device 600 includes a memory 610 and a processor 620.

[0139] The processor 620 can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gates or transistor logic, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can be any conventional processor.

[0140] The memory 610 can include various types of storage units, such as a system memory, a read-only memory (ROM), and a permanent storage device. Among them, the ROM can store static data or instructions required by the processor 620 or other modules of the computer. The permanent storage device can be a read-write storage device. The permanent storage device can be a non-volatile storage device that does not lose stored instructions and data even after the computer is powered off. In some embodiments, the permanent storage device uses a mass storage device (such as a magnetic or optical disk, a flash memory) as a permanent storage device. In some other embodiments, the permanent storage device can be a removable storage device (such as a floppy disk, an optical drive). The system memory can be a read-write storage device or a volatile read-write storage device, such as a dynamic random access memory. The system memory can store some or all instructions and data required by the processor during runtime. In addition, the memory 610 can include a combination of any computer-readable storage media, including various types of semiconductor storage chips (such as DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), magnetic disks and / or optical disks. In some embodiments, the memory 610 can include a read and / or write removable storage device, such as a compact disc (CD), a read-only digital versatile disc (such as DVD-ROM, double-layer DVD-ROM), a read-only Blu-ray disc, an ultra-density optical disc, a flash memory card (such as an SD card, a min SD card, a Micro-SD card, etc.), a magnetic floppy disk, etc. The computer-readable storage medium does not include a carrier wave and a transient electronic signal transmitted through a wireless or wired transmission.

[0141] The executable code stored on the memory 610, when processed by the processor 620, can cause the processor 620 to perform part or all of the above-mentioned methods.

[0142] In addition, the method according to the present application can also be implemented as a computer program or computer program product, which includes computer program code instructions for performing part or all of the steps of the above-mentioned methods of the present application.

[0143] Alternatively, the present application can also be implemented as a computer readable storage medium (or non-transitory machine readable storage medium or machine readable storage medium) having stored executable code (or computer program or computer instruction code) which, when executed by a processor of an electronic device (or server, etc.), causes the processor to perform part or all of the steps of the above-mentioned methods according to the present application.

[0144] The above has described the embodiments of the present application, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles of the embodiments, practical application or improvement of the technology in the market, or to enable other ordinary skilled in the art to understand the embodiments disclosed herein.

Claims

1. A data sorting method for an FPGA chip, characterized in that, The FPGA chip is communicatively connected to an extended memory, and the method includes: Obtain the data to be sorted and write the data to be sorted into the memory; Read the data to be sorted from the memory; The data to be sorted is sorted once according to a preset number of sorting steps; After each sorting operation, output a specified range of sorted, ordered data. The step of sorting the data to be sorted in a single operation according to a preset number of sorting operations includes: For each single sorting operation, the frequency of each data point in the unsorted data is counted to obtain an initial score for each data point, and a score sequence is generated based on the initial scores. Calculate the sum of the first n terms of each initial score in the fraction sequence, and use it as the storage value of the data corresponding to the initial score; Read each piece of data from the unsorted data and output the corresponding storage value; decrement the storage value of the data by one each time the data appears. After the data to be sorted is read, the final stored value of the data to be sorted is obtained; The unsorted data is sorted according to the final stored value.

2. The method according to claim 1, characterized in that, The step of generating a fraction sequence based on the initial fraction includes: Arrange the data in order of size, and arrange the initial scores of the data according to the order of arrangement to generate a score sequence corresponding to the initial scores.

3. The method according to claim 1, characterized in that, The preset number of sorting iterations is determined in the following manner: Determine the limit value of the data output by the FPGA chip each time; The preset number of sorting times is determined based on the quantity of data to be sorted and the limit of data output by the FPGA chip each time. The step of outputting a specified range of sorted, ordered data after each single sorting operation includes: After each single sorting operation is completed For the first output, a preset number of sorted data ranked at the top or bottom are output, wherein the preset number does not exceed the limit of the data output by the FPGA chip each time; For non-first outputs, in addition to the ordered data from the previous output, output a preset number of sorted ordered data that rank at the top or bottom.

4. The method according to claim 1, characterized in that, The memory includes dynamic random access memory (DDR).

5. An FPGA chip, characterized in that, The FPGA chip is communicatively connected to an extended memory, and the chip includes: The writing module is used to acquire data to be sorted and write the data to be sorted into the memory; A reading module is used to read the data to be sorted from the memory; The sorting module is used to sort the data to be sorted one by one according to a preset number of sorting steps. The output module is used to output a specified range of sorted data after each sorting cycle. The sorting module includes: The statistics submodule is used to count the number of times each data appears in the data to be sorted for each single sorting, obtain the initial score of each data, and generate a score sequence based on the initial score; The sorting submodule is used to calculate the sum of the first n terms of each score in the score sequence, and store the sum as the corresponding data value; read each data in the data to be sorted and output the corresponding storage value; decrement the storage value of the data each time it appears; after reading the data to be sorted, obtain the final storage value of the data to be sorted, and sort the data according to the final storage value.

6. The chip according to claim 5, characterized in that, The chip also includes: A limit determination module is used to determine the limit value of the data output by the FPGA chip each time. The sorting count module is used to determine the preset sorting count based on the quantity of data to be sorted and the limit of data output by the FPGA chip each time. The output module is also used to output a preset number of sorted ordered data ranked at the top or bottom of the column for the first output after each single sorting is completed, wherein the preset number does not exceed the limit of the data output by the FPGA chip each time; for non-first outputs, in addition to the ordered data output in the previous output, output a preset number of sorted ordered data ranked at the top or bottom of the column.

7. An electronic device, characterized in that, include: processor; as well as A memory having executable code stored thereon, which, when executed by the processor, causes the processor to perform the method as described in any one of claims 1-4.

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