Gigabit Ethernet engineering module division method and system

Abstract

The invention belongs to the technical field of network protocol transmission, and discloses a gigabit Ethernet engineering module division method and system. According to the method, the gigabit Ethernet engineering system is decomposed into a plurality of sub-modules according to obtained function requirement information of the gigabit Ethernet engineering system, and the sub-modules are further continuously decomposed into sub-modules of the next level until the design requirement of the gigabit Ethernet engineering is met. According to the method, codes have better reusability, repeated work among multiple designs can be reduced, repetition is avoided, the working efficiency is improved, the clock domains of different modules are relatively independent, and the boundary among the cross-clock-domain designs is clearer.

Description

Technical Field

[0001] The invention belongs to the technical field of network protocol transmission, and in particular relates to a method and system for dividing Gigabit Ethernet engineering modules. Background Art

[0002] Modular design is an important method for designing complex digital systems. It is beneficial to the division of labor, testing, reading, maintenance and reuse of complex designs. Module division is very important. It is related to whether the ability of project members to collaborate in design can be maximized. More importantly, it directly determines the integration of design, the time and efficiency of implementation, and reuse. Module division is very important. It is related to whether the ability of project members to collaborate in design can be maximized. More importantly, it directly determines the integration of design, the time and efficiency of implementation.

[0003] Through the above analysis, the problems and defects of the prior art are as follows: the module division in the engineering module division of the Gigabit Ethernet protocol design in the prior art is unreasonable and the module division is redundant. Summary of the invention

[0004] To overcome the problems existing in the related art, the disclosed embodiments of the present invention provide a Gigabit Ethernet engineering module partitioning method and system, and specifically relate to a Gigabit Ethernet UDP protocol code implementation module partitioning method based on FPGA.

[0005] The technical solution is as follows: a Gigabit Ethernet engineering module division method, according to the obtained functional requirement information of the Gigabit Ethernet engineering system, decomposes the Gigabit Ethernet engineering system into multiple sub-modules, and the sub-modules are further decomposed into sub-modules of the next level until the Gigabit Ethernet engineering design requirements are met; specifically, the following steps are included:

[0006] S1, according to engineering requirements, obtain information to achieve different functional requirements;

[0007] S2, building a hardware system structure, and obtaining peripheral devices that need to be added in addition to the FPGA based on the information obtained to achieve different functional requirements;

[0008] S3, based on the hardware system structure after adding the interface conversion module, the PC instruction system is designed, and the FPGA is used to configure the registers of the peripheral devices to obtain the improved hardware system structure;

[0009] S4, based on the acquired hardware system structure, according to the actual situation, add, supplement or split independent corresponding modules on the MAC IP core module side in the FPGA according to the data flow direction, complete the data interaction between the FPGA and the PHY and PC, and merge and simplify the modules with the same functions;

[0010] S5, based on the result of adding, supplementing or splitting independent corresponding modules according to the data flow direction on the MAC IP core module side, the operation rate matching between the modules inside the FPGA is determined.

[0011] In step S1, different functional requirements include:

[0012] (1) The packet data generated and sent inside the FPGA;

[0013] (2) Implement UDP protocol sending by adding MAC protocol header, IP protocol header, and UDP protocol header;

[0014] (3) When the FPGA receives the UDP message sent by the PC, it needs to parse the protocol header information layer by layer, first parse out the MAC header, then the IP header, and UDP header, and finally obtain the user data;

[0015] (4) FPGA periodically sends ARP protocol request messages;

[0016] (5) The FPGA receives the ARP protocol reply message from the PC, parses the source MAC address, and packages and sends the obtained MAC address as the destination MAC address in the outgoing packet data.

[0017] In step S2, a hardware system structure is constructed, including:

[0018] PC, used to transmit the sent data to PHY via Gigabit Ethernet cable;

[0019] PHY, used to modulate the data sent by the PC and send the modulated data to the FPGA;

[0020] FPGA, used to complete FCS check on the modulated data sent through the MAC IP core module;

[0021] Button, used to trigger the start of MAC IP core module initialization;

[0022] Arrange an interface conversion module on the FPGA peripheral interface to convert the interface timing of the peripheral device into a universal interface timing, or convert the universal interface timing into the interface timing of the peripheral device;

[0023] The interface conversion module corresponding to the button is the button debounce detection module; the interface conversion module corresponding to the PHY is the MACIP core module.

[0024] In step S3, designing the PC instruction system includes: building an instruction system including commands, addresses and data in the PC, and deploying a register parsing module to change the value of a corresponding register according to the commands, addresses and data.

[0025] In step S3, the peripheral device performs register configuration, including: register configuration of the MAC IP core module, in which a register configuration table module, a register read and write configuration module, and a peripheral configuration interface timing conversion module are configured; the MAC IP core module configuration interface and the peripheral configuration interface timing conversion module both use the Avalon protocol for external interfaces.

[0026] In step S4, the data flow direction includes the data flow direction of the sending side, and an independent corresponding module is added from the data flow direction of the sending side; specifically:

[0027] a) According to the data transmission requirements, a data generation module is added inside the FPGA to generate the transmission data to be sent;

[0028] b) Receive and send data, and add UDP header module, IP header, and MAC header in sequence according to the UDP protocol message transmission requirements; complete the complete UDP protocol message, and send the UDP protocol message to the MAC IP core module, and the MAC IP core module sends the sending data to PHY and PC in sequence,

[0029] Among them, the UDP header module adds the UDP protocol header module;

[0030] IP header module, add IP protocol header module;

[0031] MAC header module, add MAC protocol header module;

[0032] c) At the same time, in order to periodically send ARP protocol request messages, add an ARP request message module to send the ARP protocol request message to the MAC IP core module;

[0033] ARP protocol request messages are generated periodically, and a timing module is added.

[0034] Furthermore, the data flow direction includes a receiving side data flow direction, and an independent corresponding module is added from the receiving side data flow direction, including:

[0035] 1) The message output by the MAC IP core module is checked by the added MAC header parsing module. If it is correct, the UDP message and ARP reply message are output. If it is wrong, the packet is discarded;

[0036] 2) After being processed by the MAC header parsing module, the output is the correct IP message. The IP header is checked by the added IP header parsing module. If it is correct, the message is output. If it is wrong, the packet is discarded;

[0037] 3) After being processed by the MAC header parsing module, the output is a correct ARP reply message. At this time, the ARP reply message parsing module is added to parse the ARP message to obtain the address of the MAC IP core module of the sender. At the same time, the result of the ARP message parsing is sent to the data generation module;

[0038] 4) The same principle as step 1) and step 2) is used. The output UDP message is checked for the UDP header by the added UDP header parsing module. The message data parsed by the UDP header parsing module is the correct user data sent by the PC and is output.

[0039] In step S4, in the split independent corresponding modules, for those involving multiple inputs and one output, FIFO is used. When optimizing the modules, the generated user data and timed ARP request messages cannot be output to the MAC IP core module at the same time. The message sending scheduling module is used to complete the scheduling of multiple inputs and one output, whether to send the UDP message sent by the packaging module or the ARP request message.

[0040] In step S5, the determination of the operation rate matching between modules inside the FPGA is performed, including:

[0041] On the sending side:

[0042] (i) When sending a message, the data packaging module needs time to calculate the checksum and length information of each protocol header, set up a FIFO between the data generation module and the data packaging module, and set up an RDY signal;

[0043] (ii) The data packaging module and the ARP request message sending module are sent to the message sending scheduling module at the same time. The message sending scheduling module cannot respond at the same time. FIFO buffer. For emergencies, FIFO overflows. A FIFO is set between the data packaging module and the ARP request message timing sending module and an RDY signal is set;

[0044] On the receiving side: The receiving side modules have rate matching, and no FIFO and RDY signals are set.

[0045] Another object of the present invention is to provide a Gigabit Ethernet engineering module division system, the system implements the Gigabit Ethernet engineering module division method, the system comprising:

[0046] Functional requirement analysis module, used to obtain information on achieving different functional requirements based on engineering requirements;

[0047] Construct a hardware system structure block diagram module to obtain peripheral devices that need to be added in addition to the FPGA based on the information obtained to achieve different functional requirements;

[0048] The improved hardware system structure acquisition module is used to design the PC instruction system based on the hardware system structure after adding the interface conversion module, and to configure the registers of the peripheral devices of the FPGA to obtain the improved hardware system structure;

[0049] Add, supplement or split modules to obtain the improved hardware system structure and, based on the actual situation, add, supplement or split independent corresponding modules on the MAC IP core module side in the FPGA according to the data flow direction to complete the data interaction between the FPGA and the PHY and PC; at the same time, merge and simplify modules with the same functions;

[0050] The rate matching module is used to determine the running rate matching between modules inside the FPGA based on the result of adding, supplementing or splitting independent corresponding modules according to the data flow direction on the MAC IP core module side.

[0051] In combination with all the above technical solutions, the beneficial effects of the present invention are as follows: the present invention provides a Gigabit Ethernet module division method, which involves many protocols and many divided modules, wherein the protocols may be MAC protocol, ARP protocol, IP protocol and UDP protocol. The code of the present invention has better readability, and it is easier to understand the designed functions and the flow between data, and it is easier to implement. The code of the present invention has better reusability, can reduce the duplication of multiple designs, avoid duplication, and improve work efficiency. The clock domains of different modules of the present invention are relatively independent, making the boundaries between cross-clock domain designs clearer. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the present disclosure;

[0053] Figure 1 1. It is a diagram of a method for dividing Gigabit Ethernet engineering modules provided by an embodiment of the present invention;

[0054] Figure 2 It is a block diagram of the hardware system structure provided by the embodiment of the present invention;

[0055] Figure 3 This is a block diagram after adding an interface conversion module provided by an embodiment of the present invention;

[0056] Figure 4 It is a schematic diagram of the peripheral device after register configuration provided by the embodiment of the present invention;

[0057] Figure 5 It is a principle diagram of adding independent corresponding modules from the data flow direction of the sending side and the data flow direction of the receiving side provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0058] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific implementation disclosed below.

[0059] Embodiment 1, the Gigabit Ethernet engineering module division method provided by the embodiment of the present invention, when designing a system, first analyzes according to the system functional requirements, and then decomposes the complex system into multiple sub-modules, and these sub-modules can be further decomposed into lower-level sub-modules until the design requirements are met. Modular design can improve the readability of the code, make the design ideas clearer, facilitate the division of labor and independent testing of large-scale designs, and help maintain and reuse design files.

[0060] Specifically include the following:

[0061] S1, according to engineering requirements, obtain information to achieve different functional requirements;

[0062] The different functional requirements include:

[0063] (1) The packet data generated and sent inside the FPGA;

[0064] (2) Implement UDP protocol sending by adding MAC protocol header, IP protocol header, and UDP protocol header;

[0065] (3) When the FPGA receives the UDP message sent by the PC, it needs to parse the protocol header information layer by layer, first parse out the MAC header, then the IP header, the UDP header, and finally obtain the user data;

[0066] (4) FPGA periodically sends ARP protocol request messages;

[0067] (5) The FPGA receives the ARP protocol reply message from the PC, parses the source MAC address, and packages and sends the obtained MAC address as the destination MAC address in the outgoing packet data.

[0068] S2, building a hardware system structure, and obtaining peripheral devices that need to be added in addition to the FPGA based on the information obtained to achieve different functional requirements;

[0069] Through analysis, it is concluded that the communication between FPGA and PC is in the form of Gigabit Ethernet, and the signal output by FPGA needs to be modulated into a Gigabit Ethernet signal. The present invention selects the external PHY chip RTL8211 to realize this communication modulation function.

[0070] Similarly, the data sent by the PC is transmitted through the Gigabit Ethernet cable and needs to be demodulated by the PHY before being output to the FPGA. For the convenience of design, the calculation of the FCS check in the message data sent by the FPGA is handed over to the MAC IP core to complete. Similarly, the FCS check of the message data sent by the PC is also completed by the MAC IP core. In order to verify the design in the early stage, consider adding a button as the start condition to trigger the initialization of the MAC IP core. Construct a hardware system structure block diagram, such as Figure 2 shown.

[0071] Exemplarily, each peripheral interface in the hardware system structure block diagram corresponds to an interface conversion module. The function of the interface conversion module is to convert the interface timing of the peripheral device into a general interface timing, or to convert the general interface timing into the peripheral device interface timing, so that other modules inside the FPGA no longer need to worry about the timing of the peripheral interface.

[0072] Among them, the interface conversion module corresponding to the button is the button debounce detection module; the interface conversion module corresponding to the PHY is the MAC IP core module; after adding the interface conversion module, the frame Figure 3 shown.

[0073] S3, based on the hardware system structure after adding the interface conversion module, the PC instruction system is designed, and the FPGA is used to configure the registers of the peripheral devices to obtain the improved hardware system structure;

[0074] The instruction system design includes:

[0075] The host computer, such as PC, ARM, DSP or other devices, only involves one interface, but there are many instructions or command functions to be sent, so an instruction system is needed. The instruction system must involve commands, addresses and data. In this case, there will be a "register parsing module" to change the value of the corresponding register according to the command, address and data.

[0076] The peripheral device register configuration includes: the MAC IP core module in the present invention involves register configuration. Register configuration is performed using a register configuration table module + a register read / write configuration module + a peripheral configuration interface timing conversion module; since the MAC IP configuration interface uses the Avalon protocol, the external interface of the peripheral configuration interface timing conversion module should also be Avalon, and the internal interface should be a standard interface. The schematic diagram after the peripheral device register configuration is as follows Figure 4 The peripheral device includes a MAC IP core module;

[0077] S4, based on the acquired hardware system structure, according to the actual situation, add, supplement or split independent corresponding modules on the MAC IP core module side in the FPGA according to the data flow direction, complete the data interaction between the FPGA and the PHY and PC, and merge and simplify the modules with the same functions;

[0078] The data flow direction includes the data flow direction on the sending side and the data flow direction on the receiving side;

[0079] Exemplarily, from the data flow direction of the sending side, adding independent corresponding modules includes:

[0080] a) According to the data transmission requirements, a data generation module is added inside the FPGA to generate the transmission data to be sent;

[0081] b) Receive and send data, and add UDP header module, IP header, and MAC header in sequence according to the UDP protocol message transmission requirements; complete the complete UDP protocol message, and send the UDP protocol message to the MAC IP core module, and the MAC IP core module sends the sending data to PHY and PC in sequence,

[0082] Among them, the UDP header module needs to add the UDP protocol header module;

[0083] IP header module, you need to add IP protocol header module;

[0084] MAC header module, you need to add MAC protocol header module;

[0085] c) At the same time, in order to periodically send ARP protocol request messages, add an ARP request message module to send the ARP protocol request message to the MAC IP core module;

[0086] Since ARP protocol request messages need to be generated periodically, a timing module needs to be added.

[0087] Exemplarily, from the data flow direction of the receiving side, adding an independent corresponding module includes:

[0088] The FPGA receives the UDP message or ARP reply message sent by the PC demodulated by the PHY, and after the MAC IP core module verifies the FCS, it parses out the correct or incorrect UDP message and ARP reply message; specifically, it includes:

[0089] 1) The message output by the MAC IP core module is checked by the added MAC header parsing module. If it is correct, the UDP message and ARP reply message are output. If it is wrong, the packet is discarded;

[0090] 2) After being processed by the MAC header parsing module, the output is the correct IP message. The IP header is checked by the added IP header parsing module. If it is correct, the message is output. If it is wrong, the packet is discarded;

[0091] 3) After being processed by the MAC header parsing module, the output is a correct ARP reply message. At this time, the ARP reply message parsing module is added to parse the ARP message to obtain the address of the MAC IP core module of the sender. At the same time, the result of the ARP message parsing can be sent to the data generation module;

[0092] 4) The same principle as step 1) and step 2), the output UDP message is checked by the added UDP header parsing module, and the message data parsed by the UDP header parsing module is the correct user data sent by the PC end, which can be output. Specifically, the principle of adding independent corresponding modules from the data flow direction of the sending side and the data flow direction of the receiving side is as follows Figure 5 shown.

[0093] For example, modules with mutually exclusive functions, related data flows, and consistent interfaces are merged and simplified;

[0094] Another exemplary embodiment is that in the splitting of independent corresponding modules, for multiple inputs and one output, FIFO (First Input First Output, meaning "first in, first out", is a way of data processing and organization) is used. The data flow of the present invention involves the problem of multiple inputs and one output. When optimizing the module, the generated user data and the timed ARP request message cannot be output to the MAC IP core module at the same time. At this time, the message sending scheduling module is used to complete the scheduling of multiple inputs and one output, whether to send the UDP message sent by the packaging module or the ARP request message.

[0095] S5, based on the result of adding, supplementing or splitting independent corresponding modules according to the data flow direction on the MAC IP core module side, the operation rate matching between the modules inside the FPGA is determined.

[0096] To determine whether the rate matching problem is involved and whether an RDY signal or FIFO is required, first consider whether the RDY signal is required on the interface that communicates with the peripheral device. The communication between the peripheral PHY chip and the FPGA is processed by the MAC IP core module. The timing MAC IP core module has been completed, so there is no need to set the RDY signal. Then consider the case where the operating rates between the modules inside the FPGA do not match, and consider the direction of the data flow:

[0097] Sending side:

[0098] (i) When sending a message, the data packaging module requires time (calculating the checksum, length and other information of each protocol header), so a FIFO is set between the data generation module and the data packaging module, and an RDY signal is set.

[0099] (ii) The data packaging module and the ARP request message sending module are sent to the message sending scheduling module at the same time. The message sending scheduling module cannot respond at the same time and requires FIFO for buffering. Considering that the FIFO will overflow in emergencies, it is necessary to set up FIFO and RDY signal between the data packaging module and the ARP request message timing sending module.

[0100] Receiving side:

[0101] The receiving side has rate matching between modules, and there is no need to set FIFO and RDY signals. So far, the module division of the Gigabit network project has been completed step by step according to the module division steps. In specific practice, it is necessary to split or increase or decrease functional modules at any time according to the adjustment of the internal signals of the FPGA.

[0102] Embodiment 2, the present invention also provides a Gigabit Ethernet engineering module partitioning system, the system comprising:

[0103] Functional requirement analysis module, used to obtain information on achieving different functional requirements based on engineering requirements;

[0104] Construct a hardware system structure block diagram module to obtain peripheral devices that need to be added in addition to the FPGA based on the information obtained to achieve different functional requirements;

[0105] The improved hardware system structure acquisition module is used to design the PC instruction system based on the hardware system structure after adding the interface conversion module, and to configure the registers of the peripheral devices of the FPGA to obtain the improved hardware system structure;

[0106] Add, supplement or split modules to obtain the improved hardware system structure and, based on the actual situation, add, supplement or split independent corresponding modules on the MAC IP core module side in the FPGA according to the data flow direction to complete the data interaction between the FPGA and the PHY and PC; at the same time, merge and simplify modules with the same functions;

[0107] The rate matching module is used to determine the running rate matching between modules inside the FPGA based on the result of adding, supplementing or splitting independent corresponding modules according to the data flow direction on the MAC IP core module side.

[0108] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0109] Since the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present invention, their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0110] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated in one processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment.

[0111] An embodiment of the present invention further provides a computer device, which includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor implements the steps in any of the above-mentioned method embodiments when executing the computer program.

[0112] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0113] An embodiment of the present invention further provides an information data processing terminal, which, when executed on an electronic device, provides a user input interface to implement the steps in the above method embodiments. The information data processing terminal is not limited to mobile phones, computers, and switches.

[0114] An embodiment of the present invention further provides a server, which is used to provide a user input interface to implement the steps in the above method embodiments when executed on an electronic device.

[0115] An embodiment of the present invention provides a computer program product. When the computer program product runs on an electronic device, the electronic device can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0116] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the camera / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a disk or an optical disk.

[0117] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for dividing Gigabit Ethernet engineering modules, characterized in that: The method decomposes the Gigabit Ethernet engineering system into multiple sub-modules according to the obtained functional requirement information of the Gigabit Ethernet engineering system, and the sub-modules are further decomposed into sub-modules of the next level until the Gigabit Ethernet engineering design requirements are met; The following steps are involved: S1, according to engineering requirements, obtain information to achieve different functional requirements; S2, building a hardware system structure, and obtaining peripheral devices that need to be added in addition to the FPGA based on the information obtained to achieve different functional requirements; S3, based on the hardware system structure after adding the interface conversion module, the PC instruction system is designed, and the FPGA is used to configure the registers of the peripheral devices to obtain the improved hardware system structure; S4, based on the acquired hardware system structure, according to the actual situation, add, supplement or split independent corresponding modules on the MAC IP core module side in the FPGA according to the data flow direction, complete the data interaction between the FPGA and the PHY and PC, and merge and simplify the modules with the same functions; S5, based on the result of adding, supplementing or splitting independent corresponding modules according to the data flow direction on the MAC IP core module side, the operation rate matching between the modules inside the FPGA is determined.

2. The Gigabit Ethernet engineering module division method according to claim 1, characterized in that: In step S1, different functional requirements include: (1) The packet data generated and sent inside the FPGA; (2) Implement UDP protocol sending by adding MAC protocol header, IP protocol header, and UDP protocol header; (3) When the FPGA receives the UDP message sent by the PC, it needs to parse the protocol header information layer by layer, first parse out the MAC header, then the IP header, and UDP header, and finally obtain the user data; (4) FPGA periodically sends ARP protocol request messages; (5) The FPGA receives the ARP protocol reply message from the PC, parses the source MAC address, and packages and sends the obtained MAC address as the destination MAC address in the outgoing packet data.

3. The Gigabit Ethernet engineering module division method according to claim 1, characterized in that: In step S2, a hardware system structure is constructed, including: PC, used to transmit the sent data to PHY via Gigabit Ethernet cable; PHY, used to modulate the data sent by the PC and send the modulated data to the FPGA; FPGA, used to complete FCS check on the modulated data sent through the MAC IP core module; Button, used to trigger the start of MAC IP core module initialization; Arrange an interface conversion module on the FPGA peripheral interface to convert the interface timing of the peripheral device into a universal interface timing, or convert the universal interface timing into the interface timing of the peripheral device; The interface conversion module corresponding to the button is the button debounce detection module; the interface conversion module corresponding to the PHY is the MAC IP core module.

4. The Gigabit Ethernet engineering module division method according to claim 1, characterized in that: In step S3, designing the PC instruction system includes: building an instruction system including commands, addresses and data in the PC, and deploying a register parsing module to change the value of a corresponding register according to the commands, addresses and data.

5. The Gigabit Ethernet engineering module division method according to claim 1, characterized in that: In step S3, the peripheral device performs register configuration, including: register configuration of the MAC IP core module, in which a register configuration table module, a register read and write configuration module, and a peripheral configuration interface timing conversion module are configured; the MAC IP core module configuration interface and the peripheral configuration interface timing conversion module both use the Avalon protocol for external interfaces.

6. The Gigabit Ethernet engineering module division method according to claim 1, characterized in that: In step S4, the data flow direction includes the data flow direction of the sending side, and an independent corresponding module is added from the data flow direction of the sending side; specifically: a) According to the data transmission requirements, a data generation module is added inside the FPGA to generate the transmission data to be sent; b) Receive and send data, and add UDP header module, IP header, and MAC header in sequence according to the UDP protocol message transmission requirements; complete the complete UDP protocol message, and send the UDP protocol message to the MAC IP core module, and the MAC IP core module sends the sending data to PHY and PC in sequence, Among them, the UDP header module adds the UDP protocol header module; IP header module, add IP protocol header module; MAC header module, add MAC protocol header module; c) At the same time, in order to periodically send ARP protocol request messages, an ARP request message module is added to send the ARP protocol request message to the MAC IP core module; ARP protocol request messages are generated periodically, and a timing module is added.

7. The method for dividing Gigabit Ethernet engineering modules according to claim 6, characterized in that: The data flow direction includes the receiving side data flow direction, and an independent corresponding module is added from the receiving side data flow direction, including: 1) The message output by the MAC IP core module is checked by the added MAC header parsing module. If it is correct, the UDP message and ARP reply message are output. If it is wrong, the packet is discarded; 2) After being processed by the MAC header parsing module, the output is the correct IP message. The IP header is checked by the added IP header parsing module. If it is correct, the message is output. If it is wrong, the packet is discarded; 3) After being processed by the MAC header parsing module, the output is a correct ARP reply message. At this time, the ARP reply message parsing module is added to parse the ARP message to obtain the address of the MAC IP core module of the sender. At the same time, the result of the ARP message parsing is sent to the data generation module; 4) The same principle as step 1) and step 2) is used. The output UDP message is checked for the UDP header by the added UDP header parsing module. The message data parsed by the UDP header parsing module is the correct user data sent by the PC and is output.

8. The method for dividing Gigabit Ethernet engineering modules according to claim 1, characterized in that: In step S4, in the split independent corresponding modules, for those involving multiple inputs and one output, FIFO is used. When optimizing the modules, the generated user data and timed ARP request messages cannot be output to the MAC IP core module at the same time. The message sending scheduling module is used to complete the scheduling of multiple inputs and one output, whether to send the UDP message sent by the packaging module or the ARP request message.

9. The method for dividing Gigabit Ethernet engineering modules according to claim 1, characterized in that: In step S5, the determination of the running rate matching between modules inside the FPGA is performed, including: On the sending side: (i) When sending a message, the data packaging module needs time to calculate the checksum and length information of each protocol header, set up a FIFO between the data generation module and the data packaging module, and set up an RDY signal; (ii) The data packaging module and the ARP request message sending module are sent to the message sending scheduling module at the same time. The message sending scheduling module cannot respond at the same time. FIFO buffer. For emergencies, FIFO overflows. A FIFO is set between the data packaging module and the ARP request message timing sending module and an RDY signal is set; On the receiving side: The receiving side modules have rate matching, and no FIFO and RDY signals are set.

10. A Gigabit Ethernet engineering module partitioning system, characterized in that: The system implements the Gigabit Ethernet engineering module division method according to any one of claims 1 to 9, and the system comprises: Functional requirement analysis module, used to obtain information on achieving different functional requirements based on engineering requirements; Construct a hardware system structure block diagram module to obtain peripheral devices that need to be added in addition to the FPGA based on the information obtained to achieve different functional requirements; The improved hardware system structure acquisition module is used to design the PC instruction system based on the hardware system structure after adding the interface conversion module, and to configure the registers of the peripheral devices of the FPGA to obtain the improved hardware system structure; Add, supplement or split modules to obtain the improved hardware system structure and, based on the actual situation, add, supplement or split independent corresponding modules on the MAC IP core module side in the FPGA according to the data flow direction to complete the data interaction between the FPGA and the PHY and PC; at the same time, merge and simplify modules with the same functions; The rate matching module is used to determine the running rate matching between modules inside the FPGA based on the result of adding, supplementing or splitting independent corresponding modules according to the data flow direction on the MAC IP core module side.

Images