GPU instruction optimization method and device, equipment and storage medium

Abstract

The invention provides a GPU instruction optimization method and device, equipment and a storage medium, and the method comprises the steps: initializing an instruction set and a hash table in an NIR optimization stage; initializing a function pointer, and obtaining a current function according to the function pointer; initializing a basic block pointer according to the current function, and obtaining a current basic block according to the basic block pointer; initializing an NIR instruction pointer according to the current basic block, and obtaining a current instruction according to the NIR instruction pointer; according to whether the current instruction is a jump instruction, adding the current instruction into an instruction set and a hash table; and in an emit assembly instruction stage, performing instruction optimization according to the instruction set and the hash table. According to the method, in the emit assembly instruction stage, instruction optimization is carried out according to the instruction set and the hash table, the number of NIR and the number of assembly instructions are reduced, and then the register pressure is reduced.

Description

Technical Field

[0001] The present application relates to the field of GPU compiler technology, and in particular to a GPU instruction optimization method, device, equipment, and storage medium. Background Art

[0002] The GLSL (OpenGL Shading Language) compiler is a tool that converts high-level shader code into machine code or an intermediate representation that can be executed by the GPU (Graphics Processing Unit).

[0003] The GLSL compiler framework is as follows Figure 1 As shown, it is usually divided into three main parts: front end, middle end and back end.

[0004] 1. Front-end: responsible for lexical analysis, syntax analysis, and semantic analysis, and generating intermediate code (NIR).

[0005] 2. Mid-end: Perform various optimization operations on the generated intermediate code, including constant folding, dead code elimination, and loop unrolling.

[0006] 3. Backend: responsible for converting the optimized intermediate code into machine code of the target platform.

[0007] For NIR descent, conversion, and some heuristic algorithms, the GLSL compiler will increase the number of assembly instructions due to the increase in the number of NIRs, thereby increasing the register pressure. Summary of the invention

[0008] In order to solve one of the above technical defects, the present application provides a GPU instruction optimization method, device, equipment, and storage medium.

[0009] In a first aspect of the present application, a method for optimizing GPU instructions is provided, the method comprising:

[0010] In the NIR optimization phase, the instruction set and hash table are initialized; the function pointer is initialized, and the current function is obtained according to the function pointer; the basic block pointer is initialized according to the current function, and the current basic block is obtained according to the basic block pointer; the NIR instruction pointer is initialized according to the current basic block, and the current instruction is obtained according to the NIR instruction pointer; according to whether the current instruction is a jump instruction, the current instruction is added to the instruction set and hash table;

[0011] In the emit assembly instruction stage, instruction optimization is performed based on the instruction set and hash table.

[0012] Optionally, depending on whether the current instruction is a jump instruction, the current instruction is added to the instruction set and the hash table, including:

[0013] If the current instruction is a jump instruction, the source operand of the current instruction is obtained to determine whether the source operand is a static single assignment type; if it is a static single assignment type, the current instruction is added to the instruction set and hash table according to the relationship between the parent instruction of the source operand and the current instruction; if it is not a static single assignment type, the next instruction is processed;

[0014] If the current instruction is not a jump instruction, the next instruction is processed.

[0015] Optionally, according to the relationship between the parent instruction of the source operand and the current instruction, the current instruction is added to the instruction set and the hash table, including:

[0016] Determine whether the parent instruction of the source operand is the previous instruction of the current instruction, and whether the parent instruction of the source operand is a conditional instruction;

[0017] If the parent instruction of the source operand is the previous instruction of the current instruction, and the parent instruction of the source operand is a conditional instruction, determine whether the destination operand of the parent instruction of the source operand is only used in the current instruction; if it is only used in the current instruction, determine that the current instruction is an optimized instruction, add the current instruction to the instruction set, and add the instruction pair consisting of the current instruction and the parent instruction of the source operand to the hash table; if it is not only used in the current instruction, proceed to the next instruction processing;

[0018] If the parent instruction of the source operand is not the previous instruction of the current instruction, or the parent instruction of the source operand is not a conditional instruction, the next instruction is processed.

[0019] Optionally, performing next instruction processing includes:

[0020] Determine whether the current instruction is the last instruction of the current basic block;

[0021] If it is not the last instruction, the NIR instruction pointer is pointed to the next instruction, and the step of obtaining the current instruction according to the NIR instruction pointer and subsequent steps are repeated;

[0022] If it is the last instruction, determine whether the current basic block is the last basic block of the current function; if it is not the last basic block, point the basic block pointer to the next basic block, and repeat the steps of obtaining the current basic block according to the basic block pointer and subsequent steps; if it is the last basic block, when the current function is the last function in the shader program, end the NIR optimization phase; when the current function is not the last function in the shader program, point the function pointer to the next function, and repeat the steps of obtaining the current function according to the function pointer and subsequent steps.

[0023] Optionally, the instruction set is used to store the conditional instructions of the NIR, and the hash table is used to store <jump instruction, conditional instruction> pairs;

[0024] Instruction optimization based on instruction sets and hash tables, including:

[0025] When generating an alu instruction, if the alu instruction to be generated is in the instruction set, the conditional instruction corresponding to the alu instruction to be generated is obtained according to the hash table;

[0026] If the corresponding conditional instruction is successfully obtained, the instruction is optimized according to the corresponding conditional instruction.

[0027] Optionally, instruction optimization is performed according to corresponding conditional instructions, including:

[0028] Set the corresponding conditional code in the GPU instruction set architecture according to the corresponding conditional instruction;

[0029] Generate two source operands corresponding to the GPU instruction according to the two source operands in the corresponding conditional instruction;

[0030] Modify the swizzle values ​​of the corresponding two source operands according to the corresponding conditional instructions;

[0031] Generate a merged BRANCH instruction based on the corresponding two source operands, target location, and condition code.

[0032] Optionally, after obtaining the conditional instruction corresponding to the alu instruction to be generated according to the hash table, the method further includes:

[0033] If the corresponding conditional instruction fails to be obtained, the BRANCH instruction is directly generated.

[0034] In a second aspect of the present application, a GPU instruction optimization device is provided, the device comprising:

[0035] The NIR optimization phase processing module is used to initialize the instruction set and hash table in the NIR optimization phase; initialize the function pointer, and obtain the current function according to the function pointer; initialize the basic block pointer according to the current function, and obtain the current basic block according to the basic block pointer; initialize the NIR instruction pointer according to the current basic block, and obtain the current instruction according to the NIR instruction pointer; add the current instruction to the instruction set and hash table according to whether the current instruction is a jump instruction;

[0036] The emit assembly instruction stage processing module is used to optimize instructions according to the instruction set and hash table in the emit assembly instruction stage.

[0037] In a third aspect of the present application, an electronic device is provided, including:

[0038] Memory;

[0039] Processor; and

[0040] Computer programs;

[0041] The computer program is stored in the memory and is configured to be executed by the processor to implement the method as described in the first aspect above.

[0042] In a fourth aspect of the present application, a computer-readable storage medium is provided, on which a computer program is stored; the computer program is executed by a processor to implement the method described in the first aspect above.

[0043] The present application provides a method, device, equipment, and storage medium for GPU instruction optimization. In the NIR optimization stage, the method initializes an instruction set and a hash table; initializes a function pointer, and obtains the current function according to the function pointer; initializes a basic block pointer according to the current function, and obtains the current basic block according to the basic block pointer; initializes a NIR instruction pointer according to the current basic block, and obtains the current instruction according to the NIR instruction pointer; adds the current instruction to the instruction set and hash table according to whether the current instruction is a jump instruction; and optimizes instructions according to the instruction set and hash table in the emit assembly instruction stage. The method of the present application optimizes instructions according to the instruction set and hash table in the emit assembly instruction stage, reduces the number of NIRs and the number of assembly instructions, and thereby reduces register pressure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0045] Figure 1 A schematic diagram of the framework of an existing GLSL compiler;

[0046] Figure 2 A flowchart of a GPU instruction optimization method provided in an embodiment of the present application;

[0047] Figure 3 A schematic diagram of a process flow of a NIR optimization stage provided in an embodiment of the present application;

[0048] Figure 4 A schematic diagram of a process of merging CMP and BRANCH provided in an embodiment of the present application;

[0049] Figure 5 A schematic diagram of the structure of a GPU instruction optimization device provided in an embodiment of the present application;

[0050] Figure 6A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0052] In the process of implementing the present application, the inventors found that when performing reduction, conversion and some heuristic algorithms on NIR, the GLSL compiler will increase the register pressure due to the increase in the number of NIRs and the increase in the number of assembly instructions.

[0053] In response to the above problems, an embodiment of the present application provides a GPU instruction optimization method, device, equipment, and storage medium. In the NIR optimization stage, the method initializes the instruction set and hash table; initializes the function pointer, and obtains the current function according to the function pointer; initializes the basic block pointer according to the current function, and obtains the current basic block according to the basic block pointer; initializes the NIR instruction pointer according to the current basic block, and obtains the current instruction according to the NIR instruction pointer; adds the current instruction to the instruction set and hash table according to whether the current instruction is a jump instruction; and optimizes the instruction according to the instruction set and hash table in the emit assembly instruction stage. The method of the present application optimizes the instruction according to the instruction set and hash table in the emit assembly instruction stage, reduces the number of NIRs and the number of assembly instructions, and thereby reduces the register pressure.

[0054] The BRANCH instruction is one of the common operation operators in the GPU. The BRANCH instruction often appears together with the CMP instruction for conditional jumps. The GPU instruction optimization method provided in this embodiment is based on the GPU instruction set architecture and is specifically optimized for this instruction so that it can be merged with the CMP instruction.

[0055] For example, when there are two consecutive instructions as follows:

[0056] 1)CMP.ge r1.z r1.y c1.y-1

[0057] 2)BRANCH.not r1.z 10

[0058] 3) Through the GPU instruction optimization method provided in this embodiment, the above instruction is converted into an instruction BRANCH.ger1.y c1.y 10 in the GPU.

[0059] The optimization work of the GPU instruction optimization method provided in this embodiment mainly focuses on the NIR optimization stage and the emit assembly instruction stage. Figure 2 The implementation process of the GPU instruction optimization method provided in this embodiment is as follows:

[0060] 201, in the NIR optimization stage, initialize the instruction set and hash table. Initialize the function pointer, and obtain the current function according to the function pointer. Initialize the basic block pointer according to the current function, and obtain the current basic block according to the basic block pointer. Initialize the NIR instruction pointer according to the current basic block, and obtain the current instruction according to the NIR instruction pointer. Add the current instruction to the instruction set and hash table according to whether the current instruction is a jump instruction.

[0061] The instruction set is used to store the conditional instructions of NIR, and the hash table is used to store <jump instruction, conditional instruction> pairs.

[0062] Among them, according to whether the current instruction is a jump instruction (such as whether it is a nir_if instruction, where the nir_if instruction corresponds to the BRANCH instruction of the GPU), the implementation process of adding the current instruction to the instruction set and the hash table is:

[0063] If the current instruction is a jump instruction (such as a nir_if instruction), obtain the source operand of the current instruction and determine whether the source operand is a static single assignment type. If it is a static single assignment type, add the current instruction to the instruction set and hash table based on the relationship between the parent instruction of the source operand and the current instruction. If it is not a static single assignment type, proceed to the next instruction.

[0064] Among them, according to the relationship between the parent instruction of the source operand and the current instruction (i.e., the jump instruction), the process of adding the current instruction to the instruction set and the hash table is:

[0065] Determine whether the parent instruction of the source operand is the previous instruction of the current instruction (ie, the jump instruction), and whether the parent instruction of the source operand is a conditional instruction (ie, determine whether the parent instruction is the previous instruction of the jump instruction and is a conditional instruction).

[0066] If the parent instruction of the source operand is the previous instruction of the current instruction, and the parent instruction of the source operand is a conditional instruction, determine whether the destination operand of the parent instruction of the source operand is only used in the current instruction. If it is only used in the current instruction, determine that the current instruction is an optimized instruction, add the current instruction to the instruction set, and add the instruction pair consisting of the current instruction and the parent instruction of the source operand to the hash table. If it is not only used in the current instruction, proceed to the next instruction processing.

[0067] If the parent instruction of the source operand is not the previous instruction of the current instruction, or the parent instruction of the source operand is not a conditional instruction, the next instruction is processed.

[0068] If the current instruction is not a jump instruction (such as not a nir_if instruction), the next instruction is processed.

[0069] The process of processing the next instruction is as follows:

[0070] Determines whether the current instruction is the last instruction of the current basic block.

[0071] If it is not the last instruction, the NIR instruction pointer is pointed to the next instruction, and the step of obtaining the current instruction according to the NIR instruction pointer and subsequent steps are repeated.

[0072] If it is the last instruction, determine whether the current basic block is the last basic block of the current function. If it is not the last basic block, point the basic block pointer to the next basic block, and repeat the steps of obtaining the current basic block according to the basic block pointer and subsequent steps. If it is the last basic block, when the current function is the last function in the shader program, end the NIR optimization phase. When the current function is not the last function in the shader program, point the function pointer to the next function, and repeat the steps of obtaining the current function according to the function pointer and subsequent steps.

[0073] Step 201 is the process of finding opportunities to merge CMP instructions and BRANCH instructions, that is, in the NIR optimization stage, a hash table is constructed by executing step 201 to find opportunities for merging, and then step 202 can be executed to merge CMP instructions and BRANCH instructions according to the hash table in the emit assembly instruction stage.

[0074] See also Figure 3 , the implementation process of step 201 (ie, the process of the NIR optimization stage) is described again.

[0075] 301, initialize the instruction set and hash table.

[0076] That is, an instruction set is initialized to store the conditional instructions of NIR, and a hash table is used to store <jump instruction, conditional instruction> pairs.

[0077] 302, initialize the function pointer.

[0078] That is, initialize the function pointer for traversal function.

[0079] 303, obtaining the current function according to the function pointer.

[0080] That is, get the current function according to the function pointer.

[0081] 304, initialize the basic block pointer according to the current function.

[0082] That is, the basic block pointer is initialized according to the current function for traversing the basic block.

[0083] 305, obtaining the current basic block according to the basic block pointer.

[0084] That is, get the current basic block according to the basic block pointer.

[0085] 306, initialize the NIR instruction pointer according to the current basic block.

[0086] That is, the NIR instruction pointer is initialized according to the current basic block to traverse the NIR instructions.

[0087] 307, obtain the current instruction according to the NIR instruction pointer.

[0088] That is, get the current instruction according to the NIR instruction pointer.

[0089] 308, determine whether the current instruction is a nir_if instruction. If it is a nir_if instruction (i.e., the current instruction is a jump instruction), proceed to step 309. If it is not a nir_if instruction (i.e., the current instruction is not a jump instruction), proceed to step 315 to determine whether there is a next instruction and process the next instruction, i.e., enter the instruction loop traversal process.

[0090] Among them, the nir_if instruction corresponds to the BRANCH instruction of the GPU.

[0091] 309, obtain the source operand of the current instruction.

[0092] The current NIR instruction is nir_if, and the corresponding source operand will be obtained according to the NIR instruction.

[0093] 310, determine whether the source operand is a static single assignment type. If it is a static single assignment type, proceed to step 311 to optimize for the static single assignment case; if it is not a static single assignment type, proceed to step 315 to determine whether there is a next instruction and process the next instruction, that is, enter the instruction loop traversal process.

[0094] 311, find the instruction that defines the source operand according to the source operand, that is, the parent instruction of the source operand.

[0095] 312, determine whether the parent instruction of the source operand is the previous instruction of the current instruction (i.e., the jump instruction), and whether the parent instruction of the source operand belongs to the conditional instruction (i.e., determine whether the parent instruction is the previous instruction of the jump instruction and belongs to the conditional instruction). If the parent instruction of the source operand is the previous instruction of the current instruction (i.e., the jump instruction), and the parent instruction of the source operand belongs to the conditional instruction, then continue to step 313, if the parent instruction of the source operand is not the previous instruction of the current instruction (i.e., the jump instruction), or the parent instruction of the source operand does not belong to the conditional instruction, then continue to step 315, so as to determine whether there is a next instruction, and perform the next instruction processing, that is, enter the instruction loop traversal process.

[0096] 313, determine whether the destination operand of the parent instruction of the source operand is only used in the current instruction (ie, the jump instruction).

[0097] That is, it is determined whether the destination operand of the conditional instruction is only used in the current jump instruction. After the instruction fusion, the destination operand of the conditional instruction will no longer be assigned a register. If the operand is also used in other instructions, it will cause an error. Therefore, if the operand is also used in instructions other than the current jump instruction, it will no longer be processed. If it is not only used in the current instruction (i.e., the jump instruction), it will jump to step 315 to determine whether there is a next instruction and process the next instruction, that is, enter the instruction loop traversal process. If it is only used in the current instruction (i.e., the jump instruction), continue to step 314.

[0098] 314, determine that the current instruction is an optimized instruction, add the current instruction to the instruction set, and add the instruction pair consisting of the current instruction and the parent instruction of the source operand to the hash table.

[0099] If it is only used in the current instruction, it means that the current jump instruction can be merged, so it is an optimized instruction. It is added to the instruction set initialized in step 301, and the <jump instruction, conditional instruction> instruction pair is added to the hash table.

[0100] 315, determine whether the current instruction is the last instruction of the current basic block. If it is not the last instruction, continue to step 316, if it is the last instruction, continue to step 317 and enter the basic block loop process.

[0101] 316, point the NIR instruction pointer to the next instruction, repeat the step of obtaining the current instruction according to the NIR instruction pointer and the subsequent steps (ie, step 307 and subsequent steps), and continue to execute the next instruction.

[0102] 317, determine whether the current basic block is the last basic block of the current function. If it is not the last basic block, jump to step 318, if it is the last basic block, continue to step 319 and enter the function loop process.

[0103] 318, point the basic block pointer to the next basic block, repeat the step of obtaining the current basic block according to the basic block pointer and subsequent steps (ie, step 305 and subsequent steps), and continue to process the next basic block.

[0104] 319, determine whether the current function is the last function in the shader program, if the current function is the last function in the shader program, end the NIR optimization phase. If the current function is not the last function in the shader program, proceed to step 320.

[0105] 320, point the function pointer to the next function, repeat the step of obtaining the current function according to the function pointer and the subsequent steps (ie, step 303 and subsequent steps), and continue to process the next function.

[0106] 202, in the emit assembly instruction stage, instruction optimization is performed according to the instruction set and the hash table.

[0107] Specifically, the process of instruction optimization based on the instruction set and hash table is as follows:

[0108] When generating an alu instruction, if the alu instruction to be generated is in the instruction set, the conditional instruction corresponding to the alu instruction to be generated is obtained according to the hash table.

[0109] If the corresponding conditional instruction is obtained successfully, the instruction optimization is performed according to the corresponding conditional instruction. If the corresponding conditional instruction is obtained unsuccessfully, the BRANCH instruction is directly generated.

[0110] Among them, the process of instruction optimization according to the corresponding conditional instructions is:

[0111] 1. Set the corresponding conditional code in the GPU instruction set architecture according to the corresponding conditional instruction.

[0112] 2. Generate two source operands corresponding to the GPU instruction according to the two source operands in the corresponding conditional instruction.

[0113] 3. Modify the swizzle values ​​of the corresponding two source operands according to the corresponding conditional instructions.

[0114] 4. Generate the merged BRANCH instruction based on the corresponding two source operands, target location, and condition code.

[0115] In the assembly instruction generation stage, a specific merging process can be performed when generating a BRANCH instruction through step 202. That is, when outputting a nir_if statement in the instruction stage, a CMP instruction and a BRANCH.NZ instruction to be output are merged into a BRANCH instruction using corresponding condition codes and comparison operands.

[0116] See also Figure 4 , the implementation process of step 202 (ie, the process of merging CMP and BRANCH) is described again.

[0117] 401, when generating an alu instruction, determine whether the alu instruction to be generated is in the instruction set. If the alu instruction to be generated is in the instruction set, execute step 402. If the alu instruction to be generated is not in the instruction set, generate the alu instruction normally.

[0118] Conditional instructions belong to alu instructions in NIR. When generating alu instructions in the instruction generation stage, if the alu instruction currently to be generated is a conditional instruction in the set created in 201, it will not be generated, otherwise the alu instruction will be generated normally.

[0119] 402, obtain the conditional instruction corresponding to the alu instruction to be generated according to the hash table. If the corresponding conditional instruction is obtained successfully, execute step 403, if the corresponding conditional instruction is obtained unsuccessfully, no optimization is required, the merge optimization process is terminated, and the BRANCH instruction is directly generated.

[0120] 403, setting a corresponding condition code in the GPU instruction set architecture according to the corresponding conditional instruction.

[0121] 404 , generating two source operands corresponding to the GPU instruction according to the two source operands in the corresponding conditional instruction.

[0122] The negation operation in the conditional instruction has only one source operand, but NIR itself can merge the jump instruction negation operation. Therefore, there will be no negation operation in the related CMP and BRANCH merged conditional codes in the GPU instruction optimization method provided in this embodiment, and the corresponding two source operands of the GPU instruction can be directly generated according to the two source operands in the conditional instruction.

[0123] 405, modify the swizzle values ​​of the corresponding two source operands according to the corresponding conditional instruction.

[0124] The swizzle value of the source operand in the GPU instruction set architecture is processed according to the swizzle value of the destination operand. Therefore, it is necessary to modify the swizzle values ​​of the two source operands according to the swizzle value of the destination operand of the conditional instruction.

[0125] 406 , generate a merged BRANCH instruction according to the corresponding two source operands, the target location, and the condition code.

[0126] That is, a merged BRANCH instruction is generated based on two source operands, the target instruction position of the jump (ie, the target position), and the condition code.

[0127] The GPU instruction optimization method provided in this embodiment mainly involves the NIR (intermediate code) stage and the emit assembly instruction stage (i.e., the target code generation stage). By combining the characteristics of the GPU instruction set architecture, the NIR is reduced, converted, and some heuristic algorithms are used to reduce register pressure, etc., thereby reducing the number of NIRs and the number of assembly instructions. For example, by converting the NIR instructions and downgrading the complexity of the NIR instructions, the use of GPU registers by the NIR instructions can be reduced, thereby reducing the number of NIR codes, the number of GPU registers used, and the number of assembly instructions, thereby improving the performance of the GPU. The GPU instruction optimization method provided in this embodiment can improve the performance of the compiler and ensure efficient execution of the code.

[0128] The GPU instruction optimization method provided in this embodiment is to initialize a set for storing NIR conditional instructions and a hash table for storing <jump instruction, conditional instruction> pairs when the compiler is built. The function pointer is initialized to traverse the function, and then the current function is obtained according to the function pointer, and then the basic block pointer is initialized according to the current function to traverse the basic block. The NIR instruction pointer is initialized according to the current basic block to traverse the NIR instruction, and the nir_if instruction is converted into the BRANCH instruction of the GPU. And for the static single assignment type, the static single assignment is converted into the instruction of the source operand.

[0129] The GPU instruction optimization method provided in this embodiment combines the CMP instruction and the BRANCH instruction according to the optimized hash table constructed in the early stage at the emit assembly instruction stage. The GPU instruction optimization method provided in this embodiment combines the characteristics of the GPU instruction set architecture to merge adjacent CMP and BRANCH instructions into two corresponding source operands that directly generate the GPU instruction according to the two source operands in the conditional instruction. For example, the GPU instruction optimization method provided in this embodiment combines the characteristics of the GPU instruction set architecture at the emit assembly instruction stage to modify the swizzle value of the two source operands according to the swizzle value of the destination operand, and generates the merged BRANCH instruction in combination with the conditional code.

[0130] The GPU instruction optimization method provided in this embodiment is a GLSL compiler performance optimization method based on the merging of CMP instructions and subsequent BRANCH instructions. GPU compiler optimization technology is crucial to improving program performance. The GPU instruction optimization method provided in this embodiment can effectively improve the execution efficiency and resource utilization of the compiled program by adopting a variety of optimization technologies such as local optimization, global optimization, loop optimization, and register allocation optimization.

[0131] The GPU instruction optimization method provided in this embodiment is suitable for GPU applications that require strong rendering, such as 3D games, film and television animation, 4K video encoding and decoding, engineering modeling simulation, etc., whose underlying code may contain a large number of conditional jump instructions. By merging instructions, it is possible to reduce the number of instructions on GPU hardware (such as domestic JM9 series GPUs) and increase the operating performance of the hardware.

[0132] This embodiment provides a GPU instruction optimization method. In the NIR optimization stage, an instruction set and a hash table are initialized; a function pointer is initialized, and a current function is obtained according to the function pointer; a basic block pointer is initialized according to the current function, and a current basic block is obtained according to the basic block pointer; a NIR instruction pointer is initialized according to the current basic block, and a current instruction is obtained according to the NIR instruction pointer; according to whether the current instruction is a jump instruction, the current instruction is added to the instruction set and the hash table; in the emit assembly instruction stage, instruction optimization is performed according to the instruction set and the hash table, thereby reducing the number of NIRs and the number of assembly instructions, thereby reducing register pressure.

[0133] Based on the same inventive concept of the GPU instruction optimization method, this embodiment provides a GPU instruction optimization device, see Figure 5 , the device comprises:

[0134] The NIR optimization phase processing module 501 is used to initialize the instruction set and hash table in the NIR optimization phase. Initialize the function pointer and obtain the current function according to the function pointer. Initialize the basic block pointer according to the current function and obtain the current basic block according to the basic block pointer. Initialize the NIR instruction pointer according to the current basic block and obtain the current instruction according to the NIR instruction pointer. Add the current instruction to the instruction set and hash table according to whether the current instruction is a jump instruction.

[0135] The emit assembly instruction stage processing module 502 is used to optimize instructions according to the instruction set and the hash table at the emit assembly instruction stage.

[0136] Among them, according to whether the current instruction is a jump instruction, the current instruction is added to the instruction set and the hash table, including:

[0137] If the current instruction is a jump instruction, obtain the source operand of the current instruction and determine whether the source operand is a static single assignment type. If it is a static single assignment type, add the current instruction to the instruction set and hash table based on the relationship between the parent instruction of the source operand and the current instruction. If it is not a static single assignment type, proceed to the next instruction.

[0138] If the current instruction is not a jump instruction, the next instruction is processed.

[0139] According to the relationship between the parent instruction of the source operand and the current instruction, the current instruction is added to the instruction set and the hash table, including:

[0140] Determine whether the parent instruction of the source operand is the previous instruction of the current instruction, and whether the parent instruction of the source operand is a conditional instruction.

[0141] If the parent instruction of the source operand is the previous instruction of the current instruction, and the parent instruction of the source operand is a conditional instruction, determine whether the destination operand of the parent instruction of the source operand is only used in the current instruction. If it is only used in the current instruction, determine that the current instruction is an optimized instruction, add the current instruction to the instruction set, and add the instruction pair consisting of the current instruction and the parent instruction of the source operand to the hash table. If it is not only used in the current instruction, proceed to the next instruction processing.

[0142] If the parent instruction of the source operand is not the previous instruction of the current instruction, or the parent instruction of the source operand is not a conditional instruction, the next instruction is processed.

[0143] The next instruction processing includes:

[0144] Determines whether the current instruction is the last instruction of the current basic block.

[0145] If it is not the last instruction, the NIR instruction pointer is pointed to the next instruction, and the step of obtaining the current instruction according to the NIR instruction pointer and subsequent steps are repeated.

[0146] If it is the last instruction, determine whether the current basic block is the last basic block of the current function. If it is not the last basic block, point the basic block pointer to the next basic block, and repeat the steps of obtaining the current basic block according to the basic block pointer and subsequent steps. If it is the last basic block, when the current function is the last function in the shader program, end the NIR optimization phase. When the current function is not the last function in the shader program, point the function pointer to the next function, and repeat the steps of obtaining the current function according to the function pointer and subsequent steps.

[0147] The instruction set is used to store the conditional instructions of NIR, and the hash table is used to store <jump instruction, conditional instruction> pairs.

[0148] Instruction optimization based on instruction sets and hash tables, including:

[0149] When generating an alu instruction, if the alu instruction to be generated is in the instruction set, the conditional instruction corresponding to the alu instruction to be generated is obtained according to the hash table.

[0150] If the corresponding conditional instruction is successfully obtained, the instruction is optimized according to the corresponding conditional instruction.

[0151] Among them, instruction optimization is performed according to corresponding conditional instructions, including:

[0152] The corresponding conditional code in the GPU instruction set architecture is set according to the corresponding conditional instruction.

[0153] Generate two source operands corresponding to the GPU instruction according to the two source operands in the corresponding conditional instruction.

[0154] Modify the swizzle values ​​of the corresponding two source operands according to the corresponding conditional instruction.

[0155] Generate a merged BRANCH instruction based on the corresponding two source operands, target location, and condition code.

[0156] After obtaining the conditional instruction corresponding to the alu instruction to be generated according to the hash table, it also includes:

[0157] If the corresponding conditional instruction fails to be obtained, the BRANCH instruction is directly generated.

[0158] The device provided by this embodiment initializes the instruction set and the hash table in the NIR optimization stage through the NIR optimization stage processing module; initializes the function pointer, and obtains the current function according to the function pointer; initializes the basic block pointer according to the current function, and obtains the current basic block according to the basic block pointer; initializes the NIR instruction pointer according to the current basic block, and obtains the current instruction according to the NIR instruction pointer; adds the current instruction to the instruction set and the hash table according to whether the current instruction is a jump instruction; and optimizes the instructions according to the instruction set and the hash table in the emit assembly instruction stage through the emit assembly instruction stage processing module, thereby reducing the number of NIRs and the number of assembly instructions, thereby reducing the register pressure.

[0159] Based on the same inventive concept of the GPU instruction optimization method, this embodiment provides an electronic device, the electronic device such as Figure 6 As shown, it includes: a memory 601, a processor 602, and a computer program.

[0160] The computer program is stored in the memory 601 and is configured to be executed by the processor 602 to implement the above-mentioned GPU instruction optimization method.

[0161] Specifically,

[0162] In the NIR optimization phase, the instruction set and hash table are initialized. The function pointer is initialized and the current function is obtained according to the function pointer. The basic block pointer is initialized according to the current function and the current basic block is obtained according to the basic block pointer. The NIR instruction pointer is initialized according to the current basic block and the current instruction is obtained according to the NIR instruction pointer. Depending on whether the current instruction is a jump instruction, the current instruction is added to the instruction set and hash table.

[0163] In the emit assembly instruction stage, instruction optimization is performed based on the instruction set and hash table.

[0164] Optionally, depending on whether the current instruction is a jump instruction, the current instruction is added to the instruction set and the hash table, including:

[0165] If the current instruction is a jump instruction, obtain the source operand of the current instruction and determine whether the source operand is a static single assignment type. If it is a static single assignment type, add the current instruction to the instruction set and hash table based on the relationship between the parent instruction of the source operand and the current instruction. If it is not a static single assignment type, proceed to the next instruction.

[0166] If the current instruction is not a jump instruction, the next instruction is processed.

[0167] Optionally, according to the relationship between the parent instruction of the source operand and the current instruction, the current instruction is added to the instruction set and the hash table, including:

[0168] Determine whether the parent instruction of the source operand is the previous instruction of the current instruction, and whether the parent instruction of the source operand is a conditional instruction.

[0169] If the parent instruction of the source operand is the previous instruction of the current instruction, and the parent instruction of the source operand is a conditional instruction, determine whether the destination operand of the parent instruction of the source operand is only used in the current instruction. If it is only used in the current instruction, determine that the current instruction is an optimized instruction, add the current instruction to the instruction set, and add the instruction pair consisting of the current instruction and the parent instruction of the source operand to the hash table. If it is not only used in the current instruction, proceed to the next instruction processing.

[0170] If the parent instruction of the source operand is not the previous instruction of the current instruction, or the parent instruction of the source operand is not a conditional instruction, the next instruction is processed.

[0171] Optionally, performing next instruction processing includes:

[0172] Determines whether the current instruction is the last instruction of the current basic block.

[0173] If it is not the last instruction, the NIR instruction pointer is pointed to the next instruction, and the step of obtaining the current instruction according to the NIR instruction pointer and subsequent steps are repeated.

[0174] If it is the last instruction, determine whether the current basic block is the last basic block of the current function. If it is not the last basic block, point the basic block pointer to the next basic block, and repeat the steps of obtaining the current basic block according to the basic block pointer and subsequent steps. If it is the last basic block, when the current function is the last function in the shader program, end the NIR optimization phase. When the current function is not the last function in the shader program, point the function pointer to the next function, and repeat the steps of obtaining the current function according to the function pointer and subsequent steps.

[0175] Optionally, the instruction set is used to store conditional instructions of the NIR, and the hash table is used to store <jump instruction, conditional instruction> pairs.

[0176] Instruction optimization based on instruction sets and hash tables, including:

[0177] When generating an alu instruction, if the alu instruction to be generated is in the instruction set, the conditional instruction corresponding to the alu instruction to be generated is obtained according to the hash table.

[0178] If the corresponding conditional instruction is successfully obtained, the instruction is optimized according to the corresponding conditional instruction.

[0179] Optionally, instruction optimization is performed according to corresponding conditional instructions, including:

[0180] The corresponding conditional code in the GPU instruction set architecture is set according to the corresponding conditional instruction.

[0181] Generate two source operands corresponding to the GPU instruction according to the two source operands in the corresponding conditional instruction.

[0182] Modify the swizzle values ​​of the corresponding two source operands according to the corresponding conditional instruction.

[0183] Generate a merged BRANCH instruction based on the corresponding two source operands, target location, and condition code.

[0184] Optionally, after obtaining the conditional instruction corresponding to the alu instruction to be generated according to the hash table, the method further includes:

[0185] If the corresponding conditional instruction fails to be obtained, the BRANCH instruction is directly generated.

[0186] The electronic device provided by this embodiment, on which the computer program is executed by the processor to optimize instructions according to the instruction set and the hash table at the emit assembly instruction stage, thereby reducing the number of NIRs and the number of assembly instructions, thereby reducing register pressure.

[0187] Based on the same inventive concept of the GPU instruction optimization method, this embodiment provides a computer-readable storage medium, and a computer program is stored thereon. The computer program is executed by a processor to implement the above-mentioned GPU instruction optimization method.

[0188] Specifically,

[0189] In the NIR optimization phase, the instruction set and hash table are initialized. The function pointer is initialized and the current function is obtained according to the function pointer. The basic block pointer is initialized according to the current function and the current basic block is obtained according to the basic block pointer. The NIR instruction pointer is initialized according to the current basic block and the current instruction is obtained according to the NIR instruction pointer. Depending on whether the current instruction is a jump instruction, the current instruction is added to the instruction set and hash table.

[0190] In the emit assembly instruction stage, instruction optimization is performed based on the instruction set and hash table.

[0191] Optionally, depending on whether the current instruction is a jump instruction, the current instruction is added to the instruction set and the hash table, including:

[0192] If the current instruction is a jump instruction, obtain the source operand of the current instruction and determine whether the source operand is a static single assignment type. If it is a static single assignment type, add the current instruction to the instruction set and hash table based on the relationship between the parent instruction of the source operand and the current instruction. If it is not a static single assignment type, proceed to the next instruction.

[0193] If the current instruction is not a jump instruction, the next instruction is processed.

[0194] Optionally, according to the relationship between the parent instruction of the source operand and the current instruction, the current instruction is added to the instruction set and the hash table, including:

[0195] Determine whether the parent instruction of the source operand is the previous instruction of the current instruction, and whether the parent instruction of the source operand is a conditional instruction.

[0196] If the parent instruction of the source operand is the previous instruction of the current instruction, and the parent instruction of the source operand is a conditional instruction, determine whether the destination operand of the parent instruction of the source operand is only used in the current instruction. If it is only used in the current instruction, determine that the current instruction is an optimized instruction, add the current instruction to the instruction set, and add the instruction pair consisting of the current instruction and the parent instruction of the source operand to the hash table. If it is not only used in the current instruction, proceed to the next instruction processing.

[0197] If the parent instruction of the source operand is not the previous instruction of the current instruction, or the parent instruction of the source operand is not a conditional instruction, the next instruction is processed.

[0198] Optionally, performing next instruction processing includes:

[0199] Determines whether the current instruction is the last instruction of the current basic block.

[0200] If it is not the last instruction, the NIR instruction pointer is pointed to the next instruction, and the step of obtaining the current instruction according to the NIR instruction pointer and subsequent steps are repeated.

[0201] If it is the last instruction, determine whether the current basic block is the last basic block of the current function. If it is not the last basic block, point the basic block pointer to the next basic block, and repeat the steps of obtaining the current basic block according to the basic block pointer and subsequent steps. If it is the last basic block, when the current function is the last function in the shader program, end the NIR optimization phase. When the current function is not the last function in the shader program, point the function pointer to the next function, and repeat the steps of obtaining the current function according to the function pointer and subsequent steps.

[0202] Optionally, the instruction set is used to store conditional instructions of the NIR, and the hash table is used to store <jump instruction, conditional instruction> pairs.

[0203] Instruction optimization based on instruction sets and hash tables, including:

[0204] When generating an alu instruction, if the alu instruction to be generated is in the instruction set, the conditional instruction corresponding to the alu instruction to be generated is obtained according to the hash table.

[0205] If the corresponding conditional instruction is successfully obtained, the instruction is optimized according to the corresponding conditional instruction.

[0206] Optionally, instruction optimization is performed according to corresponding conditional instructions, including:

[0207] The corresponding conditional code in the GPU instruction set architecture is set according to the corresponding conditional instruction.

[0208] Generate two source operands corresponding to the GPU instruction according to the two source operands in the corresponding conditional instruction.

[0209] Modify the swizzle values ​​of the corresponding two source operands according to the corresponding conditional instruction.

[0210] Generate a merged BRANCH instruction based on the corresponding two source operands, target location, and condition code.

[0211] Optionally, after obtaining the conditional instruction corresponding to the alu instruction to be generated according to the hash table, the method further includes:

[0212] If the corresponding conditional instruction fails to be obtained, the BRANCH instruction is directly generated.

[0213] The computer-readable storage medium provided in this embodiment has a computer program thereon which is executed by a processor to optimize instructions according to an instruction set and a hash table at the emit assembly instruction stage, thereby reducing the number of NIRs and the number of assembly instructions, thereby reducing register pressure.

[0214] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. The scheme in the embodiments of the present application can be implemented in various computer languages, for example, object-oriented programming language Java and literal scripting language JavaScript, etc.

[0215] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0216] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0217] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0218] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0219] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A GPU instruction optimization method, characterized in that: The method comprises: In the NIR optimization stage, the instruction set and hash table are initialized; the function pointer is initialized, and the current function is obtained according to the function pointer; the basic block pointer is initialized according to the current function, and the current basic block is obtained according to the basic block pointer; the NIR instruction pointer is initialized according to the current basic block, and the current instruction is obtained according to the NIR instruction pointer; according to whether the current instruction is a jump instruction, the current instruction is added to the instruction set and hash table; In the emit assembly instruction stage, instruction optimization is performed based on the instruction set and hash table.

2. The method according to claim 1, characterized in that The adding the current instruction to the instruction set and the hash table according to whether the current instruction is a jump instruction comprises: If the current instruction is a jump instruction, the source operand of the current instruction is obtained, and it is determined whether the source operand is a static single assignment type; if it is a static single assignment type, the current instruction is added to the instruction set and the hash table according to the relationship between the parent instruction of the source operand and the current instruction; if it is not a static single assignment type, the next instruction is processed; If the current instruction is not a jump instruction, the next instruction processing is performed.

3. The method according to claim 2, characterized in that The adding the current instruction to the instruction set and the hash table according to the relationship between the parent instruction of the source operand and the current instruction comprises: Determine whether the parent instruction of the source operand is the previous instruction of the current instruction, and whether the parent instruction of the source operand is a conditional instruction; If the parent instruction of the source operand is the previous instruction of the current instruction, and the parent instruction of the source operand is a conditional instruction, determine whether the destination operand of the parent instruction of the source operand is only used in the current instruction; if it is only used in the current instruction, determine that the current instruction is an optimized instruction, add the current instruction to the instruction set, and add an instruction pair consisting of the current instruction and the parent instruction of the source operand to the hash table; if it is not only used in the current instruction, proceed to the next instruction processing; If the parent instruction of the source operand is not the previous instruction of the current instruction, or the parent instruction of the source operand is not a conditional instruction, the next instruction processing is performed.

4. The method according to claim 2 or 3, characterized in that: The performing next instruction processing comprises: Determine whether the current instruction is the last instruction of the current basic block; If it is not the last instruction, the NIR instruction pointer is pointed to the next instruction, and the step of obtaining the current instruction according to the NIR instruction pointer and subsequent steps are repeatedly executed; If it is the last instruction, determine whether the current basic block is the last basic block of the current function; if it is not the last basic block, point the basic block pointer to the next basic block, and repeat the step of obtaining the current basic block according to the basic block pointer and subsequent steps; if it is the last basic block, when the current function is the last function in the shader program, end the NIR optimization stage; when the current function is not the last function in the shader program, point the function pointer to the next function, and repeat the step of obtaining the current function according to the function pointer and subsequent steps.

5. The method according to claim 1, characterized in that The instruction set is used to store the conditional instructions of NIR, and the hash table is used to store <jump instruction, conditional instruction> pairs; The instruction optimization according to the instruction set and the hash table includes: When generating an alu instruction, if the alu instruction to be generated is in the instruction set, obtaining a conditional instruction corresponding to the alu instruction to be generated according to the hash table; If the corresponding conditional instruction is successfully obtained, instruction optimization is performed according to the corresponding conditional instruction.

6. The method according to claim 5, characterized in that The performing instruction optimization according to the corresponding conditional instruction includes: Setting a corresponding conditional code in the GPU instruction set architecture according to the corresponding conditional instruction; Generate two source operands corresponding to the GPU instruction according to the two source operands in the corresponding conditional instruction; Modify the swizzle values ​​of the corresponding two source operands according to the corresponding conditional instruction; Generate a merged BRANCH instruction based on the corresponding two source operands, target location, and condition code.

7. The method according to claim 5, characterized in that After obtaining the conditional instruction corresponding to the alu instruction to be generated according to the hash table, the method further includes: If the corresponding conditional instruction fails to be obtained, the BRANCH instruction is directly generated.

8. A GPU instruction optimization device, characterized in that: The device comprises: The NIR optimization phase processing module is used to initialize the instruction set and the hash table in the NIR optimization phase; initialize the function pointer, and obtain the current function according to the function pointer; initialize the basic block pointer according to the current function, and obtain the current basic block according to the basic block pointer; initialize the NIR instruction pointer according to the current basic block, and obtain the current instruction according to the NIR instruction pointer; add the current instruction to the instruction set and the hash table according to whether the current instruction is a jump instruction; The emit assembly instruction stage processing module is used to optimize instructions according to the instruction set and hash table in the emit assembly instruction stage.

9. An electronic device, characterized in that: include: Memory; processor; as well as Computer programs; The computer program is stored in the memory and is configured to be executed by the processor to implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: A computer program is stored thereon; the computer program is executed by a processor to implement the method according to any one of claims 1 to 7.

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