Memory access method and apparatus, electronic device, and chip

Abstract

The application provides a memory access method and device, electronic equipment and chip. The method comprises the following steps: determining a corresponding physical address according to a logical address to be accessed by a first processor; the physical address indicates at least one storage unit in a memory pool; at least two memory groups are arranged in the memory pool; any storage unit comprises storage areas in the at least two memory groups; and the storage areas in the storage unit are sequentially accessed according to the sorting order of the at least two memory groups. Compared with parallel memory access in the related art, the memory access of the application supports parallel access of at most a number of processors in the memory groups in the memory pool, and each processor can access the storage areas in the storage unit in different memory groups, thereby improving the parallelism of memory access, and further improving the memory access efficiency and performance in a multi-processor system.

Description

Technical Field

[0001] This application relates to the field of digital circuit design technology, and in particular to a memory access method, apparatus, electronic device and chip. Background Technology

[0002] Currently, in multi-processor systems, multiple processors take turns using a single bus port through arbitration to access the memory pool. In related technologies, when multiple processors take turns using a single bus port to access the memory pool, the system only supports one processor accessing the memory at a time. This leads to low access efficiency and severely limits the system's processing power and efficiency. Summary of the Invention

[0003] This application aims to at least partially address one of the technical problems in the related art.

[0004] To address this, this application proposes a memory access method, apparatus, electronic device, and chip. The method determines the corresponding physical address based on the logical address to be accessed by a first processor. The physical address indicates at least one storage unit in a memory pool, which contains at least two memory groups. Each storage unit includes storage areas within at least two memory groups. The method sequentially accesses the storage areas within each memory group of any storage unit according to the sorting order of the at least two memory groups. This supports parallel access by up to the number of processors in the memory pool's memory groups, and each processor can access storage areas within different memory groups in a storage unit, improving the parallelism of memory access and thus enhancing memory access efficiency and performance in a multiprocessor system.

[0005] One embodiment of this application proposes a memory access method, including:

[0006] The corresponding physical address is determined based on the logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in the memory pool, the memory pool is provided with at least two memory groups, and any storage unit includes the storage area within the at least two memory groups;

[0007] The storage regions within each of the memory groups are accessed sequentially in any of the memory cells according to the sorting order of the at least two memory groups.

[0008] Another embodiment of this application proposes a memory access device, including:

[0009] The first determining module is used to determine the corresponding physical address based on the logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in a memory pool, the memory pool is provided with at least two memory groups, and any one of the storage units includes a storage area within the at least two memory groups;

[0010] The first access module is configured to sequentially access the storage area within each of the memory groups in any of the memory cells, according to the sorting order of the at least two memory groups.

[0011] Another embodiment of this application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the method described in the foregoing aspect.

[0012] Another embodiment of this application proposes a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in the foregoing aspect.

[0013] Another embodiment of this application proposes a chip including processing circuitry configured to perform the method described in one aspect above.

[0014] Another embodiment of this application proposes a computer program product having a computer program stored thereon, which, when executed by a processor, implements the method described in the foregoing aspect.

[0015] The memory access method, apparatus, electronic device, and chip proposed in this application determine the corresponding physical address based on the logical address to be accessed by the first processor. The physical address indicates at least one storage unit in a memory pool, which contains at least two memory groups. Each storage unit includes storage areas within at least two memory groups. Storage areas within each memory group of any storage unit are accessed sequentially according to the sorting order of the at least two memory groups. Compared to parallel memory access in related technologies, the memory access method of this application supports parallel access by up to the number of processors in the memory pool's memory groups, and each processor can access storage areas within different memory groups in a storage unit, improving the parallelism of memory access and thus enhancing memory access efficiency and performance in multiprocessor systems.

[0016] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0017] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0018] Figure 1 This application provides a schematic diagram of a multiprocessor accessing memory.

[0019] Figure 2 This is a flowchart illustrating a memory access method provided in an embodiment of this application.

[0020] Figure 3 This application provides a schematic diagram of the structure of a storage unit in a memory pool.

[0021] Figure 4 A schematic diagram of another storage unit in a memory pool provided in this application;

[0022] Figure 5 A flowchart illustrating another memory access method provided in an embodiment of this application;

[0023] Figure 6 A flowchart illustrating another memory access method provided in an embodiment of this application;

[0024] Figure 7 A schematic diagram of another storage unit in a memory pool provided in this application;

[0025] Figure 8 A flowchart illustrating another memory access method provided in an embodiment of this application;

[0026] Figure 9 A flowchart illustrating another memory access method provided in an embodiment of this application;

[0027] Figure 10 This is a schematic diagram of the structure of a memory access device provided in an embodiment of this application;

[0028] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0029] Figure 12 This is a schematic diagram of the structure of a chip proposed in an embodiment of this application. Detailed Implementation

[0030] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0031] In related technologies, when multiple processors take turns using a single bus port to access the memory pool via arbitration, the system only supports one processor accessing the memory. For example... Figure 1 As shown, in a system with three processors, processor M1 needs to write data, while processors M2 and M3 need to read data. When only one set of ports is designed for the memory pool—one for writing data and one for reading data—and the memory pool has no other special design, then at any given time, only one of the three processors (M1, M2, and M3) can access memory to read or write data, and it cannot support more than two processors accessing memory in parallel.

[0032] Because it cannot support more than two processors accessing memory in parallel, the access efficiency is low, and the system's processing power and efficiency are severely limited.

[0033] The memory access methods, apparatus, electronic devices, and chips of this application are described below with reference to the accompanying drawings.

[0034] Figure 2 This is a flowchart illustrating a memory access method provided in an embodiment of this application.

[0035] As one implementation, the memory access method of this application embodiment can be configured in a memory access device, which can be applied to any electronic device so that the electronic device can perform memory access functions.

[0036] Among them, electronic devices can be any device with computing capabilities, such as mobile terminals, which can be hardware devices with various operating systems, touch screens and / or displays, such as mobile phones, tablets, personal digital assistants, wearable devices, etc.

[0037] As another implementation, the memory access method of this application embodiment can also be executed by a chip with processing capabilities. The chip includes a central processing unit (CPU), an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), a system on a chip (SOC), a reduced instruction set computer (RISC), etc., which will not be listed here.

[0038] like Figure 2As shown, the method may include the following steps:

[0039] Step 201: Determine the corresponding physical address based on the logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in the memory pool, the memory pool is provided with at least two memory groups, and any storage unit includes storage areas within at least two memory groups.

[0040] The first processor can be the processor among multiple processors in a shared memory pool that needs to access the memory pool.

[0041] In this embodiment of the application, at least two memory groups can be set in the memory pool. Each memory group can be a single-port memory group or a pseudo-dual-port memory group. The port type of the memory group can be selected and determined according to actual needs.

[0042] In one possible implementation of this application, the number of memory groups set in the memory pool can be determined based on the total number of processors in the shared memory pool.

[0043] As one possible implementation, when the total number of processors in the shared memory pool is n, the number of memory groups set in the memory pool is m, where the value of m is determined by an exponential function with the target value as the base, and both m and n are positive integers, with m being greater than n.

[0044] The target value can be preset, such as 2 or 3, and this application does not impose any restrictions on it.

[0045] As an example, assuming the total number of processors in the shared memory pool is 3 and the target value is 2, then the number of memory groups set in the memory pool can be 2. 2 1; Assuming the total number of processors in the shared memory pool is 6, and the target value is 2, then the number of memory groups set in the memory pool can be 2. 3 indivual.

[0046] In this embodiment of the application, a storage unit can be used as the basic unit of memory allocation to manage and allocate the storage area in the memory pool. The number of storage units in the memory pool can be, but is not limited to, one. When at least two memory groups are set in the memory pool, any storage unit can include the storage area within the at least two memory groups.

[0047] As an example, suppose a memory pool contains 1024 storage units and is divided into 8 memory groups. Each storage unit includes the storage area within those 8 memory groups. For instance, suppose there is a storage unit 'a', and its location in the memory pool is as follows: Figure 3 As shown.

[0048] In the embodiments of this application, a physical address can be used to indicate at least one storage unit in a memory pool. It should be noted that this application does not limit the number of storage units indicated by a physical address.

[0049] In this embodiment, the corresponding physical address can be determined based on the logical address to be accessed by the first processor. As an example, the corresponding physical address can be determined based on the mapping relationship between the logical address to be accessed by the first processor and that logical address.

[0050] Step 202: Access the memory regions within each memory group in any memory cell sequentially according to the sorting order of at least two memory groups.

[0051] In the embodiments of this application, each of the at least two memory groups in the memory pool can have a corresponding sorting order, so that the storage area in any memory cell located in each memory group can be accessed sequentially according to the sorting order of each memory group in the memory pool.

[0052] Still with Figure 3 To illustrate, suppose there is a memory cell 'a' in a memory pool, and the memory pool has 8 memory groups. According to the sorting order, the memory groups are bank0, bank1, bank2, bank3, bank4, bank5, bank6, and bank7. Then, the storage areas in memory cell 'a' within each memory group can be accessed sequentially according to the above order. That is, the storage area in bank0 of memory cell 'a' is accessed first, then the storage area in bank1, then the storage area in bank2, then the storage area in bank3, and so on.

[0053] It should be noted that when the number of memory groups in the memory pool is m, the memory pool can support parallel access by up to m processors, ensuring that each memory group is accessed by different processors. For example, when the number of memory groups in the memory pool is 8, it can support parallel access by up to 8 processors; and when the number of memory groups in the memory pool is 16, it can support parallel access by up to 16 processors. Therefore, parallel access by more than two processors can be achieved, improving access efficiency.

[0054] In one possible implementation of this application, when the physical address indicates that there are multiple storage units in the memory pool, the storage areas in the corresponding storage units within each memory group can be accessed sequentially according to the sorting order of the multiple storage units and the sorting order of at least two memory groups.

[0055] As an example, suppose the physical address indicates that the memory pool contains memory cells a and b, and the memory pool is configured with memory group 1 and memory group 2. The sorting order of the memory cells is memory cell b, then memory cell a, and the sorting order of the memory groups is memory group 1, then memory group 2. Then, following the sorting order of the memory groups, the memory regions within memory cell b that are within their respective memory groups are accessed sequentially first, followed by the memory regions within memory cell a that are within their respective memory groups. This maintains the atomicity and consistency of memory accesses, contributing to the orderly management of memory and the consistency of data.

[0056] Optionally, the storage area within each memory group in any memory cell can be at least two rows of storage areas. As an example, assuming that the size of each memory cell in the memory pool is 2KB, the number of memory groups set in the memory pool is 8, the bit width of each memory group is 128 bits, and the width of each memory cell is the same as the bit width of the memory group (128 bits), then the storage area of ​​each memory cell within each memory group is 16 rows of storage areas, which is 8 * 16 * 128 bits = 2048 bytes = 2KB.

[0057] It should be noted that the number of row storage areas included in the storage areas within each memory group in the above-mentioned storage unit is only exemplary. In practical applications, it can be set as needed, and this application does not impose any restrictions on it.

[0058] In one possible implementation of this application, if the storage area in any memory cell within each memory group is at least two rows of storage areas, for any memory cell, at least two rows of storage areas in each memory group can be accessed sequentially according to the sorting order of at least two memory groups.

[0059] As an example, such as Figure 4As shown, assuming there is a storage unit a, and the memory banks are ordered as bank0, bank1, bank2, and bank3 respectively, the storage area of ​​storage unit a within each of the above memory banks is 4 rows of storage area. The storage area of ​​each memory bank can be accessed sequentially according to the order of the memory banks. That is, according to the above order, the 4 rows of storage area of ​​storage unit a in bank0 are accessed first, then the 4 rows of storage area of ​​storage unit a in bank1 are accessed, then the 4 rows of storage area of ​​storage unit a in bank2 are accessed, and finally the 4 rows of storage area of ​​storage unit a in bank3 are accessed.

[0060] In the memory access method of this application embodiment, a corresponding physical address is determined based on the logical address to be accessed by the first processor. The physical address indicates at least one storage unit in a memory pool, and the memory pool is provided with at least two memory groups. Each storage unit includes storage areas within at least two memory groups. Storage areas within each memory group of any storage unit are accessed sequentially according to the sorting order of the at least two memory groups. Compared to parallel memory access in related technologies, the memory access method of this application supports parallel access by up to the number of processors in the memory pool's memory groups, and each processor can access storage areas within different memory groups in the storage unit, improving the parallelism of memory access and thus improving the memory access efficiency and performance in a multiprocessor system.

[0061] It is understandable that when the first processor accesses a memory region within a memory bank, multiple processors may access the same memory bank. In this case of access conflicts, this application also proposes a memory access method.

[0062] Based on the above embodiments, Figure 5 A flowchart illustrating another memory access method provided in this application embodiment is shown below. Figure 5 As shown, the method may further include the following steps:

[0063] Step 501: When accessing the first target memory group in at least two memory groups, if there is an access conflict with at least one second processor, determine the priority of the first processor and the second processor.

[0064] In this embodiment of the application, any memory group in the memory pool may have a corresponding arbitrator. Thus, when the first processor accesses the first target memory group among at least two memory groups, if there is an access conflict with at least one second processor, the priority of the first processor and the second processor can be determined by the arbitrator corresponding to the first target memory group.

[0065] In one embodiment of this disclosure, the priority between the first processor and the second processor can be determined according to a preset processor priority rule. Exemplarily, the priority between the first processor and the second processor can be set using a fixed-priority arbitrator. Exemplarily, the priority between the first processor and the second processor can be set using a round-robin priority arbitrator.

[0066] It should be noted that this application does not limit the number of second processors that have access conflicts with the first processor.

[0067] Step 502: Access the first target memory group in order of priority.

[0068] As an example, the first processor and the second processor can be sorted according to their priority, so that each processor can access the first target memory group in turn according to the corresponding sorting order.

[0069] As one possible implementation, when a high-priority processor in the first processor and at least one second processor accesses the first target memory group, access by a low-priority processor can be blocked; and when the high-priority processor completes its access, access by the low-priority processor to the first target memory group is allowed.

[0070] Therefore, when the first target memory group is accessed by a high-priority processor among the first processor and at least one second processor, access to the low-priority processor is blocked. This ensures that the access of the high-priority processor is not interfered with. Then, when the high-priority processor completes its access, the access block on the low-priority processor is released, and the low-priority processor is allowed to access the first target memory group. This can effectively solve the performance degradation problem caused by resource conflicts and maintain the stability and efficiency of the system.

[0071] In the memory access method of this application embodiment, when accessing a first target memory group among at least two memory groups, if there is an access conflict with at least one second processor, the priority of the first processor and the second processor is determined by an arbitrator corresponding to the first target memory group; the first target memory group is then accessed sequentially according to priority. By resolving access conflicts through an arbitrator based on priority rules, it is possible to ensure that shared resources in a multiprocessor system are accessed in an orderly and efficient manner, thereby improving system performance and stability.

[0072] Based on the above embodiments of this application, Figure 6 A flowchart illustrating another memory access method provided in this application embodiment is shown below. Figure 6 As shown, the method includes the following steps:

[0073] Step 601: Determine the corresponding physical address based on the logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in the memory pool, the memory pool is provided with at least two memory groups, and any storage unit includes storage areas within at least two memory groups.

[0074] The execution process of step 601 can be found in any embodiment of this application, and will not be described in detail here.

[0075] Step 602: For any memory cell, determine the access order of each row of memory areas in the memory cell according to the sorting of at least two rows of memory areas in each memory group.

[0076] As one possible implementation, for any given storage cell, the access order of each row of storage areas in the storage cell can be determined based on the sorting of at least two rows of storage areas within each memory group and the sorting order of each memory group.

[0077] As an example, such as Figure 7 As shown, assuming there is a storage unit a, and the memory banks are ordered as bank0, bank1, bank2, and bank3, the storage area in storage unit a that is located within each of the memory banks consists of two rows of storage areas. The two rows of storage areas in bank0 are ordered as row 01 and row 02, the two rows of storage areas in bank1 are ordered as row 11 and row 12, the two rows of storage areas in bank2 are ordered as row 21 and row 22, and the two rows of storage areas in bank3 are ordered as row 31 and row 32. Based on the order of at least two rows of storage areas in each memory bank within the storage unit, and the order of the memory banks, the access order of each row of storage areas in the storage unit can be determined as: row 01, row 11, row 21, row 31, row 02, row 12, row 22, and row 32.

[0078] Step 603: If the target row storage area to be accessed is determined based on the access order, the target row storage area in each memory group is accessed sequentially according to the sorting order of at least two memory groups.

[0079] The target row storage area can be any row storage area within a storage unit.

[0080] In the memory access method of this application embodiment, for any memory cell, the access order of each row of memory areas in the memory cell is determined according to the sorting of at least two corresponding rows of memory areas within each memory group; if the target row of memory areas to be accessed is determined based on the access order, the target row of memory areas in each memory group is accessed sequentially according to the sorting order of at least two memory groups. By determining the access order, orderly control of the access process is achieved, which helps to improve the performance stability and reliability of multiprocessing systems.

[0081] In the case where the physical address also indicates a second target memory group among at least two memory groups, in order to clearly illustrate how the memory regions in any memory cell located within each memory group are accessed sequentially according to the sorting order of at least two memory groups in the above embodiments of this application, this application also proposes a memory access method.

[0082] Based on the above embodiments of this application, Figure 8 A flowchart illustrating another memory access method provided in this application embodiment is shown below. Figure 8 As shown, the method includes the following steps:

[0083] Step 801: Determine the corresponding physical address based on the logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in the memory pool, the memory pool is provided with at least two memory groups, and any storage unit includes storage areas within at least two memory groups.

[0084] The execution process of step 801 can be found in any embodiment of this application, and will not be described in detail here.

[0085] Optionally, the logical address is carried in the write instruction.

[0086] In the case where a logical address is carried in a write instruction, in order to clearly explain how the corresponding physical address is determined based on the logical address to be accessed by the first processor, in one possible implementation of this application embodiment, in response to the write instruction, a free storage unit is allocated from the storage unit list according to the size of the data block to be written carried in the write instruction; and the physical address is determined based on the logical address and the encoding of the allocated storage unit.

[0087] The storage unit list can be a data structure such as a queue or a linked list, and the storage unit list can be used to indicate the free storage units in the storage pool.

[0088] In this context, it's understandable that each storage unit in the storage pool can have a corresponding code to uniquely identify it. For example, during circuit initialization, 0, 1, 2, 3... can be used sequentially as the codes for each storage unit.

[0089] In this embodiment of the application, in response to a write instruction, a free storage unit can be allocated from the storage unit list according to the size of the data block to be written carried by the write instruction.

[0090] To clearly illustrate how free storage units are allocated from the storage unit list based on the size of the data block to be written carried by the write instruction, as one possible implementation, in response to a write instruction, the number of storage units to be allocated can be determined based on the size of the data block to be written carried by the write instruction and the size of each storage unit; and free storage units are allocated from the storage unit list based on the number of storage units to be allocated.

[0091] As an example, suppose the storage unit list uses a first-in-first-out queue to store free storage units. The size of the data block to be written carried by the write instruction is 6KB, and the size of each storage unit is 2KB. Then, based on the size of the data block to be written carried by the write instruction, it can be determined that the number of storage units to be allocated is 3. Based on this number, the first 3 storage units in the first-in-first-out queue are allocated.

[0092] In related technologies, the allocation of storage space for different business data to be written is fixed, and cannot be allocated on demand, or can only be statically configured through registers, lacking flexibility and resulting in underutilization of memory resources. This application, however, determines the allocated storage unit based on the size of the data block to be written, enabling dynamic request and allocation of the required storage space according to actual needs, thus ensuring efficient utilization of memory resources.

[0093] In this embodiment, the physical address can be determined based on the logical address and the encoding of the allocated memory unit. As an example, the physical address can be generated based on the logical address carried by the write instruction and the encoding of the allocated memory unit; for example, the encoding of the memory group to be accessed in at least two memory groups is determined according to bits [2:0] in the logical address carried by the write instruction, and the physical address is generated according to the determined encoding of the memory group to be accessed and the encoding of the allocated memory unit.

[0094] In one possible implementation of this application, after allocating a free storage unit from the storage unit list according to the size of the data block to be written carried by the write instruction, the correspondence between the allocated storage unit and the logical address can be saved.

[0095] When a logical address is carried in a read instruction, in order to clearly explain how the corresponding physical address is determined based on the logical address to be accessed by the first processor, as a possible implementation, in response to the read instruction, the corresponding code is queried based on the logical address carried in the read instruction; wherein, the correspondence between the logical address and the code is stored when allocating the memory unit; the physical address is determined based on the logical address and the code.

[0096] The encoding can be used to uniquely identify the storage unit.

[0097] It is understood that the storage space of any storage unit can be released. Therefore, in one possible implementation of this application embodiment, when at least one storage unit is released, the status of at least one storage unit can be updated from occupied to free in the storage unit list. This updates the status of the storage unit so that its availability can be determined subsequently, maintaining the continuous and efficient operation of the system.

[0098] Step 802: For any memory cell, according to the sorting order of at least two memory groups, starting from the second target memory group, sequentially access the memory areas in each memory group within the memory cell.

[0099] As an example, for memory cell a, assuming the sorting order of each memory group is bank0, bank1, bank2, bank3, and the physical address also indicates the second target memory group as bank1, then starting from bank1, the memory areas in memory cell a located in bank1, bank2, and bank3 can be accessed sequentially according to the sorting order of each memory group.

[0100] In the memory access method of this application embodiment, for any memory cell, the storage areas within each memory group are accessed sequentially, starting from the second target memory group, according to the sorting order of at least two memory groups. This further optimizes the access process to the storage areas within each memory group, improving the flexibility and targeting of the access process, and helping to ensure data consistency and accuracy during access.

[0101] In the case where the physical address also indicates a third target memory group and a fourth target memory group in at least two memory groups, in order to clearly illustrate how the memory regions in any memory cell located in each memory group are accessed sequentially according to the sorting order of at least two memory groups in the above embodiments of this application, this application also proposes a memory access method.

[0102] Based on the above embodiments of this application, Figure 9 A flowchart illustrating another memory access method provided in this application embodiment is shown below. Figure 9 As shown, the method includes the following steps:

[0103] Step 901: Determine the corresponding physical address based on the logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in the memory pool, the memory pool is provided with at least two memory groups, and any storage unit includes storage areas within at least two memory groups.

[0104] The execution process of step 901 can be found in any embodiment of this application, and will not be described in detail here.

[0105] Step 902: For any memory cell, according to the sorting order of at least two memory groups, starting from the third target memory group and ending at the fourth target memory group, sequentially access the memory areas in each memory group within the memory cell.

[0106] As an example, for memory cell a, assuming the sorting order of each memory group is bank0, bank1, bank2, bank3, and the physical address indicates the third target memory group as bank0 and the fourth target memory group as bank2, then starting from bank1 and using bank2 as the middle power, the memory areas in memory cell a located in bank0, bank1, and bank2 can be accessed sequentially according to the sorting order of each memory group.

[0107] In one possible implementation of this application, when the storage area in each memory group of a storage cell is at least two rows of storage areas, and the physical address also indicates the first row of storage areas in the third target memory group and the second row of storage areas in the fourth target memory group of any storage cell, for that storage cell, the first row of storage areas in the third target memory group of the storage cell can be taken as the starting point, and the second row of storage areas in the fourth target memory group of the storage cell can be taken as the ending point; according to the sorting order of each memory group, the access order of each row of storage areas in the storage cell is determined according to the starting point and the ending point, and each row of storage areas is accessed sequentially according to the access order.

[0108] As an example, still using Figure 7To illustrate, assume there exists a memory cell a, and the memory banks are ordered as bank0, bank1, bank2, and bank3. The memory area within memory cell a that falls within each of these memory banks is a two-row storage area. In bank0, the two rows are rows 01 and 02; in bank1, rows 11 and 12; in bank2, rows 21 and 22; and in bank3, rows 31 and 32. Also assume the physical address indicates that memory cell a contains a third target... Given that the first row of storage area 11 in memory bank 1 and the second row of storage area 22 in the fourth target memory bank 2 in memory cell a, the row 11 in bank 1 of memory cell a can be taken as the starting point and the row 22 in bank 2 of memory cell a can be taken as the ending point. According to the sorting order of each memory bank, based on the starting point and the ending point, the access order of each row of storage area in the memory cell can be determined as: row 11, row 21, row 31, row 02, row 12, row 22, and each row of storage area can be accessed in sequence according to this access order.

[0109] In the memory access method of this application embodiment, for any storage unit, the storage areas within each memory group are accessed sequentially, starting from the third target memory group and ending at the fourth target memory group, according to the sorting order of at least two memory groups. This further optimizes the access process to the storage areas within each memory group, improving the flexibility and targeting of the access process, and helping to ensure data consistency and accuracy during access.

[0110] To implement the above embodiments, this application also proposes a memory access device.

[0111] Figure 10 This is a schematic diagram of a memory access device provided in an embodiment of this application.

[0112] like Figure 10 As shown, the device may include:

[0113] The first determining module 1001 is used to determine the corresponding physical address based on the logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in the memory pool, the memory pool is provided with at least two memory groups, and any storage unit includes storage areas within at least two memory groups.

[0114] The first access module 1002 is used to sequentially access the storage area within each memory group in any memory cell according to the sorting order of at least two memory groups.

[0115] Furthermore, in one implementation of this application embodiment, the apparatus may further include:

[0116] The second determining module is used to determine the priority of the first processor and the second processor when accessing the first target memory group in at least two memory groups, if there is an access conflict with at least one second processor.

[0117] The second access module accesses the first target memory group sequentially according to priority.

[0118] In one implementation of this application, the second access module is used for:

[0119] When a high-priority processor in the first processor and at least one second processor accesses the first target memory group, access to the low-priority processor is blocked.

[0120] Once a high-priority processor has completed its access, a low-priority processor is allowed to access the first target memory group.

[0121] In one implementation of this application, the storage area within each memory group in any storage cell consists of at least two rows of storage areas; the first access module 1002 is used for:

[0122] For any given memory cell, determine the access order of each row of memory areas in the memory cell according to the order of at least two rows of memory areas that are located in any memory group.

[0123] If the target row storage area to be accessed is determined based on the access order, the target row storage area in each memory group is accessed sequentially according to the sorting order of at least two memory groups.

[0124] In one implementation of this application, the storage area within each memory group in any storage cell consists of at least two rows of storage areas; the first access module 1002 is used for:

[0125] For any given memory cell, sequentially access at least two rows of memory areas in each memory group according to the sorting order of at least two memory groups.

[0126] In one implementation of this application, the physical address further indicates a second target memory group; the first access module 1002 is used for:

[0127] Following the sorting order of at least two memory groups, starting with the second target memory group, sequentially access the storage regions within each memory group in any memory cell.

[0128] In one implementation of this application, the physical address further includes a third target memory group and a fourth target memory group; the first access module 1002 is used for:

[0129] For any memory cell, following the sorting order of at least two memory groups, starting with the third target memory group and ending with the fourth target memory group, sequentially access the memory regions within each memory group in the memory cell.

[0130] In one implementation of this application, the logical address is carried in the write instruction; the first determining module 1001 is used for:

[0131] In response to a write command, a free storage unit is allocated from the storage unit list based on the size of the data block to be written carried by the write command.

[0132] The physical address is determined based on the logical address and the encoding of the allocated storage unit.

[0133] In one implementation of this application, the logical address is carried in the read instruction; the first determining module 1001 is used for:

[0134] In response to a read command, the corresponding code is queried based on the logical address; the correspondence between the logical address and the code is stored when the memory unit is allocated.

[0135] The physical address is determined based on the logical address and the encoding.

[0136] In one implementation of this application, the apparatus may further include: an update module, configured to:

[0137] In response to the release of at least one storage unit, the status of at least one storage unit in the storage unit list is updated from occupied to free.

[0138] In one implementation of this application, when the total number of processors in the shared memory pool is n, the number of memory groups set in the memory pool is m, where the value of m is determined by an exponential function with the target value as the base, and both m and n are positive integers, with m being greater than n.

[0139] This application proposes a memory access device in which a corresponding physical address is determined based on the logical address to be accessed by a first processor. The physical address indicates at least one storage unit in a memory pool, the memory pool having at least two memory groups, and any storage unit including storage areas within at least two memory groups. Storage areas within each memory group of any storage unit are accessed sequentially according to the sorting order of the at least two memory groups. Compared to parallel memory access in related technologies, the memory access method of this application supports parallel access by up to the number of processors in the memory pool's memory groups, and each processor can access storage areas within different memory groups in the storage unit, improving the parallelism of memory access and thus enhancing the memory access efficiency and performance in a multiprocessor system.

[0140] To implement the above embodiments, this application also proposes a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the method described in the foregoing method embodiments.

[0141] To implement the above embodiments, this application also proposes a computer program product having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method described in the foregoing method embodiments.

[0142] To implement the above embodiments, this application also proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the method described in the foregoing method embodiments.

[0143] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. For example, the electronic device 1100 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0144] Reference Figure 11 The electronic device 1100 may include one or more of the following components: processing component 1102, memory 1104, power component 1106, multimedia component 1108, audio component 1110, input / output (I / O) interface 1112, sensor component 1114, and communication component 1116.

[0145] Processing component 1102 typically controls the overall operation of electronic device 1100, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 1102 may include one or more processors 1120 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 1102 may include one or more modules to facilitate interaction between processing component 1102 and other components. For example, processing component 1102 may include a multimedia module to facilitate interaction between multimedia component 1108 and processing component 1102.

[0146] Memory 1104 is configured to store various types of data to support the operation of electronic device 1100. Examples of such data include instructions for any application or method operating on electronic device 1100, contact data, phonebook data, messages, pictures, videos, etc. Memory 1104 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0147] Power component 1106 provides power to various components of electronic device 1100. Power component 1106 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 1100.

[0148] Multimedia component 1108 includes a screen that provides an output interface between the electronic device 1100 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 1108 includes a front-facing camera and / or a rear-facing camera. When the electronic device 1100 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0149] Audio component 1110 is configured to output and / or input audio signals. For example, audio component 1110 includes a microphone (MIC) configured to receive external audio signals when electronic device 1100 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 1104 or transmitted via communication component 1116. In some embodiments, audio component 1110 also includes a speaker for outputting audio signals.

[0150] I / O interface 1112 provides an interface between processing component 1102 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0151] Sensor assembly 1114 includes one or more sensors for providing state assessments of various aspects of electronic device 1100. For example, sensor assembly 1114 may detect the on / off state of electronic device 1100, the relative positioning of components such as the display and keypad of electronic device 1100, changes in position of electronic device 1100 or a component of electronic device 1100, the presence or absence of user contact with electronic device 1100, the orientation or acceleration / deceleration of electronic device 1100, and temperature changes of electronic device 1100. Sensor assembly 1114 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 1114 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 1114 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0152] Communication component 1116 is configured to facilitate wired or wireless communication between electronic device 1100 and other devices. Electronic device 1100 can access wireless networks based on communication standards, such as WiFi, 4G, or 5G, or combinations thereof. In one exemplary embodiment, communication component 1116 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 1116 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0153] In an exemplary embodiment, the electronic device 1100 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, microprocessors, or other electronic components to perform the methods described above.

[0154] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 1104 including instructions, which can be executed by a processor 1120 of an electronic device 1100 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0155] To implement the above embodiments, this application also proposes a chip, including: the chip includes a processing circuit configured to perform the methods provided in the foregoing embodiments.

[0156] Figure 12 This is a schematic diagram of the structure of a chip according to an embodiment of this application. See also... Figure 12 The diagram shown is a schematic representation of the structure of chip 1200, but it is not limited to this.

[0157] Chip 1200 includes processing circuitry 1201, which is configured to perform any of the above methods.

[0158] In some embodiments, chip 1200 further includes one or more interface circuits 1202. Optionally, the interface circuit 1202 is connected to memory 1203, and the interface circuit 1202 can be used to receive signals from memory 1203 or other devices, and the interface circuit 1202 can be used to send signals to memory 1203 or other devices. For example, the interface circuit 1202 can read instructions stored in memory 1203 and send the instructions to processing circuit 1201.

[0159] In some embodiments, the interface circuit 1202 performs at least one of the communication steps such as sending and / or receiving in the above method, while the processing circuit 1201 performs other steps.

[0160] In some embodiments, the terms interface circuit, interface, transceiver pin, transceiver, etc., can be used interchangeably.

[0161] In some embodiments, chip 1200 further includes one or more memories 1203 for storing instructions. Optionally, all or part of the memories 1203 may be located outside of chip 1200.

[0162] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0163] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0164] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0165] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0166] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0167] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it includes one or a combination of the steps of the method embodiments.

[0168] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0169] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A memory access method, characterized by, The method comprises: determining a corresponding physical address according to a logical address to be accessed by a first processor; wherein the physical address indicates at least one storage unit in a memory pool, the memory pool is provided with at least two memory groups, any of the storage units comprises storage areas in the at least two memory groups, and any of the memory groups is a single-port memory group or a pseudo double-port memory group; sequentially accessing the storage areas in the storage units in the respective memory groups according to a sorting order of the at least two memory groups.

2. The method of claim 1, wherein, The method further comprises: when accessing a first target memory group in the at least two memory groups, determining priorities of the first processor and at least one second processor if there is an access conflict between the first processor and the second processor; sequentially accessing the first target memory group according to the priorities.

3. The method of claim 2, wherein, The sequentially accessing the first target memory group according to the priorities comprises: blocking access of a low-priority processor when a high-priority processor in the first processor and the at least one second processor accesses the first target memory group; allowing the low-priority processor to access the first target memory group when the high-priority processor finishes the access.

4. The method according to any one of claims 1 to 3, characterized in that, The storage areas in the respective memory groups in any of the storage units are at least two rows of storage areas; The sequentially accessing the storage areas in the storage units in the respective memory groups according to the sorting order of the at least two memory groups comprises: for any of the storage units, determining an access order of the rows of storage areas in the storage unit according to a sorting of the at least two rows of storage areas in the storage unit in any of the memory groups; and when it is determined that a target row of storage areas needs to be accessed according to the access order, sequentially accessing the target row of storage areas in the respective memory groups according to the sorting order of the at least two memory groups.

5. The method according to any one of claims 1 to 3, characterized in that, The storage areas in the respective memory groups in any of the storage units are at least two rows of storage areas; The sequentially accessing the storage areas in the storage units in the respective memory groups according to the sorting order of the at least two memory groups comprises: for any of the storage units, sequentially accessing the at least two rows of storage areas in the respective memory groups according to the sorting order of the at least two memory groups.

6. The method of any one of claims 1-3, wherein, The physical address further indicates a second target memory group; The sequentially accessing the storage areas in the storage units in the respective memory groups according to the sorting order of the at least two memory groups comprises: sequentially accessing the storage areas in the storage units in the respective memory groups according to the sorting order of the at least two memory groups, starting from the second target memory group.

7. The method of any one of claims 1-3, wherein, The physical address further comprises a third target memory group and a fourth target memory group; The sequentially accessing the storage areas in the storage units in the respective memory groups according to the sorting order of the at least two memory groups comprises: For any one of the storage units, in the order of the at least two memory banks, starting from the third target memory bank and ending at the fourth target memory bank, sequentially access the storage regions in the storage unit within each of the memory banks.

8. The method of any one of claims 1-3, wherein, The logical address is carried in a write instruction; and the corresponding physical address is determined according to the logical address to be accessed by the first processor, including: In response to the write instruction, according to the size of the data block to be written carried by the write instruction, allocate an idle storage unit from the storage unit list; Based on the logical address and the encoding of the allocated storage unit, determine the physical address.

9. The method of claim 8, wherein, The logical address is carried in a read instruction; and the corresponding physical address is determined according to the logical address to be accessed by the first processor, including: In response to the read instruction, query the corresponding encoding according to the logical address; wherein the corresponding relationship between the logical address and the encoding is stored when the storage unit is allocated; Based on the logical address and the encoding, determine the physical address.

10. The method of claim 8, wherein, The method further comprises: In response to the release of the at least one storage unit, update the state of the at least one storage unit from occupied to idle in the storage unit list.

11. The method of any one of claims 1-3, wherein, In the case that the total number of processors sharing the memory pool is n, the number of memory banks provided in the memory pool is m, wherein the value of m is determined by an exponential function with a target value as the base number, and m and n are both positive integers, and m is greater than n.

12. A memory access device, comprising: Comprise: The first determination module is configured to determine the corresponding physical address according to the logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in the memory pool, and the memory pool is provided with at least two memory banks, and any one of the storage units comprises storage regions within the at least two memory banks, wherein any one of the memory banks is a single-port memory bank or a pseudo double-port memory bank; The first access module is configured to sequentially access the storage regions in any one of the storage units within each of the memory banks in the order of the at least two memory banks.

13. An electronic device, comprising: The computer program is executed by the processor to implement the method of any one of claims 1-12.

14. A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the method of any one of claims 1-12.

15. A chip, characterized by The chip comprises processing circuitry, and the processing circuitry is configured to execute the method of any one of claims 1-12.

16. A computer program product, characterised in that, The computer program is executed by the processor to implement the method of any one of claims 1-12.

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