DSP (Digital Signal Processor) multi-accounting power division method, device and equipment and storage medium

Abstract

The invention discloses a DSP multi-core computing power division method, device and equipment and a storage medium, and relates to the technical field of data processing, the method comprises the steps that a single RTOS system is created for a DSP, and the single RTOS system only comprises one RTOS, one set of audio frame and one set of audio topology; carrying out audio topology definition and identification so as to identify an I / O task and an algorithm task of the audio topology as different core operation; and defining an inter-core data interface to realize inter-core communication and data sharing, and carrying out consistency maintenance operation on inter-core data. Through the single RTOS system design, the code space occupation is reduced, the code maintenance complexity is reduced, and the deployment and operation complexity is reduced.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a DSP multi-core computing power partitioning method, device, equipment and storage medium. Background Art

[0002] In the design of digital signal processing chips, especially audio DSP (Digital Signal Processor), multiple cores are usually designed to provide computing power expansion. In practice, this type of embedded processor core is often designed as multiple instances, that is, the design of a core is repeated multiple times, and communication is carried out through inter-core interrupts. Multiple cores store shared data through non-hardware consistent storage.

[0003] See also Figure 1 As shown, in the current audio DSP solution based on the above design, an independent RTOS (Real Time Operate System) will run on each DSP core and the algorithms will be statically distributed on different cores. The establishment of the entire data flow of the algorithm depends on the division and coordination of the application data flow, and the related data exchange will also vary depending on the application scenario. A significant disadvantage of this design is that an RTOS needs to compile multiple RTOS instances and load and execute them according to the memory distribution. Based on the above limitations, each core needs to run an audio framework instance and provide a pre-divided audio topology diagram to ensure that each core completes a complete function.

[0004] It can be seen that the existing audio DSP design scheme has the following problems: (1) Multiple independent RTOS instances will cause the code running space to grow exponentially with the number of cores; (2) Multiple independent RTOS instances will cause the overall address space to be statically divided into multiple blocks, causing the link script to be different in each instance, introducing maintenance complexity; (3) Multiple independent RTOS instances need to cooperate with the deployment and operation of multiple audio framework instances; (4) Multiple independent ROTS instances also require static division of the topology; (5) The static division of the audio topology requires that the interaction between multiple cores must be deeply integrated into the interaction format and content between the components in the topology, and the interaction information of different components is different. Summary of the invention

[0005] The present application provides a DSP multi-core computing power partitioning method, device, equipment and storage medium, which reduces code space occupancy, reduces the complexity of code maintenance, and reduces the complexity of deployment and operation through a single RTOS system design.

[0006] In a first aspect, an embodiment of the present application provides a DSP multi-core computing power partitioning method, the DSP multi-core computing power partitioning method comprising: Creating a single RTOS system for the DSP, wherein the single RTOS system includes only one RTOS, one audio framework, and one audio topology; Define and identify the audio topology to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores; Define inter-core data interfaces to achieve inter-core communication and data sharing, and perform consistency maintenance operations on inter-core data.

[0007] In combination with the first aspect, in one implementation, The RTOS is used to implement task scheduling on multiple cores of DSP; The audio framework is used to implement the operation and scheduling of audio components in the audio topology on the multi-core of DSP.

[0008] In combination with the first aspect, in one implementation, the audio topology definition and identification to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores specifically includes: An audio topology is defined and audio components in the audio topology are identified, so that an I / O task in the audio topology is identified as executable on one core of the DSP and an algorithm task is identified as executable on another core of the DSP.

[0009] In conjunction with the first aspect, in one implementation, defining an inter-core data interface to implement inter-core communication and data sharing specifically includes: Define the inter-core data interface to aggregate all the core input and output data and input and output dependent data into a standard data structure definition; Inter-core communication and data sharing are achieved through inter-core interrupts and shared memory.

[0010] In conjunction with the first aspect, in one implementation, the operation of maintaining consistency of inter-core data specifically includes: Configure the code and data in the DSP to be cacheable; Increase the consistency of RTOS shared resources and inter-core data.

[0011] In a second aspect, an embodiment of the present application provides a DSP multi-core computing power partitioning device, wherein the DSP multi-core computing power partitioning device comprises: A creation module, which is used to create a single RTOS system for the DSP, wherein the single RTOS system only includes one RTOS, a set of audio frameworks, and a set of audio topologies; An identification module, which is used to define and identify the audio topology, so as to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores; The execution module is used to define the inter-core data interface to achieve inter-core communication and data sharing, and perform consistency maintenance operations on inter-core data.

[0012] In conjunction with the second aspect, in one implementation, The RTOS is used to implement task scheduling on multiple cores of DSP; The audio framework is used to implement the operation and scheduling of audio components in the audio topology on the multi-core of DSP.

[0013] In conjunction with the second aspect, in one implementation, the audio topology definition and identification is performed to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores, specifically including: An audio topology is defined and audio components in the audio topology are identified, so that an I / O task in the audio topology is identified as executable on one core of the DSP and an algorithm task is identified as executable on another core of the DSP.

[0014] In a third aspect, an embodiment of the present application provides a DSP multi-core computing power partitioning device, wherein the DSP multi-core computing power partitioning device includes a processor, a memory, and a DSP multi-core computing power partitioning program stored in the memory and executable by the processor, wherein when the DSP multi-core computing power partitioning program is executed by the processor, the steps of the above-mentioned DSP multi-core computing power partitioning method are implemented.

[0015] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a DSP multi-core computing power partitioning program is stored. When the DSP multi-core computing power partitioning program is executed by a processor, the steps of the above-mentioned DSP multi-core computing power partitioning method are implemented.

[0016] The beneficial effects brought by the technical solution provided in the embodiments of the present application include: Through the design of a single RTOS system, the code space occupancy is reduced and the complexity of code maintenance is reduced. On this basis, the shared data structure processing part and cache consistency operation extension of the multi-core operating system are provided, and the complexity of deployment and operation is reduced by providing a unique audio framework. At the same time, based on the unique audio topology, the division of the audio topology on multiple cores adopts a simple and unified data format and content, and the two cores achieve information interaction through simple data encapsulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the structure designed for multiple independent RTOS; Figure 2 This is a flowchart of the DSP multi-core computing power division method for this application; Figure 3A schematic diagram of a single RTOS system designed for this application; Figure 4 This is a functional module diagram of the DSP multi-core computing power partitioning device of this application; Figure 5 This is a schematic diagram of the hardware structure of the DSP multi-core computing power partitioning device for this application. DETAILED DESCRIPTION

[0018] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0019] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0020] On the first aspect, the embodiment of the present application provides a DSP multi-core computing power division method to solve the problems existing after adopting a single RTOS system, such as lack of local consistent storage, code and data in external memory far away from the CPU (Central Processing Unit) core, and reduced shared data access efficiency. It adopts local cache and adds cache consistency maintenance operations, and adopts independent multi-core requirements. It divides applications and allocates computing power according to audio services, places audio I / O (Input / Output) and audio algorithms on different cores, and provides a simple and standard data encapsulation interface as a data interaction method between CPU cores.

[0021] In one embodiment, referring to Figure 2 , Figure 2 This is a flowchart of the DSP multi-core computing power division method of this application. Figure 2 As shown in the figure, the DSP multi-core computing power division method includes: S1: creating a single RTOS system for the DSP, wherein the single RTOS system includes only one RTOS, one audio framework, and one audio topology; Specifically, the single RTOS system design of this application can be found in Figure 3 As shown in the figure, it only contains an RTOS, an audio framework and an audio topology. In the figure, Core 0 represents one of the cores of the DSP, Core 1 represents another core of the DSP, IPI represents inter-processor interrupt, and Shared Memory represents shared memory.

[0022] For the RTOS in the single RTOS system design, the RTOS is used to implement task scheduling on the multi-core of the DSP. For tasks, it includes DMA (Direct Memory Access, DMA) transmission, algorithm operation, parameter adjustment, etc.; the audio framework is used to implement the operation and scheduling of audio components in the audio topology on the multi-core of the DSP. The audio framework refers to a set of software frameworks that establish audio topology, transmit audio data streams, and schedule audio data streams according to application requirements. Specifically, for the single RTOS system design, in the software part, it includes an RTOS, an audio framework, an audio topology and multi-core partition configuration, inter-core data interface definition and inter-core communication mechanism. For the audio topology and multi-core partition configuration, it is a representation of the partition of audio components on the multi-core and the construction of data streams, as well as the software partition configuration, for example, placing I / O tasks on core Core 0 and algorithm tasks on core Core 1.

[0023] S2: define and identify the audio topology to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores; Further, in one embodiment, the audio topology is defined and identified to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores, specifically including: defining the audio topology and identifying the audio components in the audio topology to identify the I / O tasks in the audio topology as being runnable by one core of the DSP and the algorithm tasks as being runnable by another core of the DSP. The audio topology refers to connecting the audio components through input-output relationships, thereby providing a network topology, and the audio data stream transmits data according to the topology.

[0024] Specifically, the computing power is divided on multiple cores, the audio topology is defined, and the audio components in the audio topology are identified. For example, the I / O tasks in the audio topology are identified as executable by core 0, and the algorithm tasks in the audio topology are identified as executable by core 1.

[0025] S3: Define the inter-core data interface to achieve inter-core communication and data sharing, and perform consistency maintenance operations on inter-core data.

[0026] Furthermore, in one embodiment, an inter-core data interface is defined to achieve inter-core communication and data sharing, specifically including: defining an inter-core data interface to aggregate all input and output data of the core and input and output dependent data into a standard data structure definition; achieving inter-core communication and data sharing through inter-core interrupts and shared memory.

[0027] Specifically, inter-core data sharing settings are performed. By defining the inter-core data interface, all input and output and input and output dependent data are aggregated into a standard data structure definition. At the same time, inter-core communication and data sharing are achieved through inter-core interrupts and shared memory.

[0028] Furthermore, in one embodiment, the consistency maintenance operation of the inter-core data is performed, specifically including: configuring the code and data in the DSP to be cacheable; adding the consistency operation of the RTOS shared resources, and the consistency operation of the inter-core data.

[0029] Specifically, consistency maintenance is performed, the code and data in the DSP are configured to be cacheable, and consistency operations of RTOS shared resources are increased, and consistency operations of inter-core application shared data, that is, inter-core data, are increased.

[0030] This application is based on the RTOS system design, adding a multi-core operating system shared data structure processing part and cache consistency operation extension; based on a set of audio topology static partitioning computing power and a simplified inter-core communication design, the data flow boundaries between different cores are clearly defined; a simple input and output data sharing and handshake mechanism is defined between the two cores, and the two cores perform cache consistency maintenance operations to solve the problem of multi-core shared data.

[0031] The DSP multi-core computing power division method of the embodiment of the present application reduces the code space occupancy and the complexity of code maintenance through a single RTOS system design, and on this basis provides a multi-core operating system shared data structure processing part and cache consistency operation extension, and reduces the complexity of deployment and operation by providing a unique audio framework. At the same time, based on a unique audio topology, and the division of the audio topology on multiple cores adopts a simple and unified data format and content, information interaction is achieved between the two cores through simple data encapsulation.

[0032] In a second aspect, an embodiment of the present application also provides a DSP multi-core computing power division device.

[0033] In one embodiment, referring to Figure 4 , Figure 4 This is a functional module diagram of the DSP multi-core computing power division device of this application. Figure 4 As shown, the DSP multi-core computing power division device includes: a creation module, an identification module, and an execution module.

[0034] The creation module is used to create a single RTOS system for DSP, and the single RTOS system only includes one RTOS, a set of audio frameworks and a set of audio topologies; the identification module is used to define and identify the audio topology to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores; the execution module is used to define the inter-core data interface to achieve inter-core communication and data sharing, and perform consistency maintenance operations on inter-core data.

[0035] For the RTOS in the single RTOS system design, the RTOS is used to implement task scheduling on the multi-core of the DSP. For tasks, it includes DMA (Direct Memory Access, DMA) transmission, algorithm operation, parameter adjustment, etc.; the audio framework is used to implement the operation and scheduling of audio components in the audio topology on the multi-core of the DSP. The audio framework refers to a set of software frameworks that establish audio topology, transmit audio data streams, and schedule audio data streams according to application requirements. Specifically, for the single RTOS system design, in the software part, it includes an RTOS, an audio framework, an audio topology and multi-core partition configuration, inter-core data interface definition and inter-core communication mechanism. For the audio topology and multi-core partition configuration, it is a representation of the partition of audio components on the multi-core and the construction of data streams, as well as the software partition configuration, for example, placing I / O tasks on core Core 0 and algorithm tasks on core Core 1.

[0036] In the present application, the RTOS is used to implement task scheduling on the multi-core of the DSP; the audio framework is used to implement the operation and scheduling of audio components in the audio topology on the multi-core of the DSP.

[0037] In this application, the audio topology is defined and identified to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores, specifically including: An audio topology is defined and audio components in the audio topology are identified, so that an I / O task in the audio topology is identified as executable on one core of the DSP and an algorithm task is identified as executable on another core of the DSP.

[0038] In this application, the inter-core data interface is defined to achieve inter-core communication and data sharing, including: Define the inter-core data interface to aggregate all the core input and output data and input and output dependent data into a standard data structure definition; Inter-core communication and data sharing are achieved through inter-core interrupts and shared memory.

[0039] In this application, the consistency maintenance operation of inter-core data includes: Configure the code and data in the DSP to be cacheable; Increase the consistency of RTOS shared resources and inter-core data.

[0040] This application reduces the code space occupancy and the complexity of code maintenance through a single RTOS system design, and on this basis provides a multi-core operating system shared data structure processing part and cache consistency operation extension, and reduces the complexity of deployment and operation by providing a unique audio framework. At the same time, based on a unique audio topology, and the division of the audio topology on multiple cores uses a simple and unified data format and content, information interaction is achieved between the two cores through simple data encapsulation.

[0041] In a third aspect, an embodiment of the present application provides a DSP multi-core computing power partitioning device, which may be a personal computer (PC), a laptop computer, a server, or other device with data processing capabilities.

[0042] Reference Figure 5 , Figure 5 The hardware structure diagram of the DSP multi-core computing power partitioning device involved in the embodiment of the present application is shown in FIG. In the embodiment of the present application, the DSP multi-core computing power partitioning device may include a processor, a memory, a communication interface, and a communication bus.

[0043] The communication bus may be of any type and is used to interconnect the processor, the memory, and the communication interface.

[0044] The communication interface includes input / output (I / O) interface, physical interface and logical interface, etc., which are used to realize the interconnection of devices inside the DSP multi-core computing power partitioning device, and the interface used to realize the interconnection between the DSP multi-core computing power partitioning device and other devices (such as other computing devices or user devices). This interface is usually an internal chip interface, such as AXI, AHB, APB, etc.

[0045] The memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0046] The processor may be a general-purpose processor, and the general-purpose processor may call the DSP multi-core computing power partitioning program stored in the memory and execute the DSP multi-core computing power partitioning method provided in the embodiment of the present application. For example, the general-purpose processor may be a central processing unit (CPU) or a dedicated processor for digital signal processing. The method executed when the DSP multi-core computing power partitioning program is called may refer to the various embodiments of the DSP multi-core computing power partitioning method of the present application, and will not be described in detail here.

[0047] Those skilled in the art will understand that Figure 5 The hardware structure shown in the figure does not constitute a limitation on the present application, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0048] In a fourth aspect, an embodiment of the present application also provides a computer-readable storage medium.

[0049] The computer-readable storage medium of the present application stores a DSP multi-core computing power partitioning program, wherein when the DSP multi-core computing power partitioning program is executed by a processor, the steps of the DSP multi-core computing power partitioning method as described above are implemented.

[0050] Among them, the method implemented when the DSP multi-core computing power partitioning program is executed can refer to the various embodiments of the DSP multi-core computing power partitioning method of this application, and will not be repeated here.

[0051] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. The terms "first", "second" and "third" are used to distinguish different objects, etc., and do not represent a sequence, nor do they limit "first", "second" and "third" to different types.

[0052] In the description of the embodiments of the present application, "exemplary", "for example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary", "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary", "for example" or "for example" is intended to present related concepts in a specific way.

[0053] In the description of the embodiments of the present application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; the “and / or” in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, “multiple” refers to two or more than two.

[0054] In some processes described in the embodiments of the present application, multiple operations or steps that appear in a specific order are included, but it should be understood that these operations or steps may not be executed in the order in which they appear in the embodiments of the present application or in parallel, and the sequence number of the operation is only used to distinguish the different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed in sequence or in parallel, and these operations or steps may be combined.

[0055] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD) as described above, and includes a number of instructions for a terminal device to execute the methods described in each embodiment of the present application.

[0056] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A DSP multi-core computing power partitioning method, characterized in that: The DSP multi-core computing power division method includes: Creating a single RTOS system for the DSP, wherein the single RTOS system includes only one RTOS, one audio framework, and one audio topology; Define and identify the audio topology to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores; Define inter-core data interfaces to achieve inter-core communication and data sharing, and perform consistency maintenance operations on inter-core data.

2. A DSP multi-core computing power partitioning method as claimed in claim 1, characterized in that: The RTOS is used to implement task scheduling on multiple cores of DSP; The audio framework is used to implement the operation and scheduling of audio components in the audio topology on the multi-core of DSP.

3. A DSP multi-core computing power division method as claimed in claim 1, characterized in that: The audio topology definition and identification is performed to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores, specifically including: An audio topology is defined and audio components in the audio topology are identified, so that an I / O task in the audio topology is identified as executable on one core of the DSP and an algorithm task is identified as executable on another core of the DSP.

4. A DSP multi-core computing power partitioning method as claimed in claim 1, characterized in that: Defining the inter-core data interface to achieve inter-core communication and data sharing specifically includes: Define the inter-core data interface to aggregate all the core input and output data and input and output dependent data into a standard data structure definition; Inter-core communication and data sharing are achieved through inter-core interrupts and shared memory.

5. A DSP multi-core computing power partitioning method as claimed in claim 1, characterized in that: The operation of maintaining consistency of inter-core data specifically includes: Configure the code and data in the DSP to be cacheable; Increase the consistency of RTOS shared resources and inter-core data.

6. A DSP multi-core computing power division device, characterized in that: The DSP multi-core computing power division device comprises: A creation module, which is used to create a single RTOS system for the DSP, wherein the single RTOS system only includes one RTOS, a set of audio frameworks, and a set of audio topologies; An identification module, which is used to define and identify the audio topology, so as to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores; The execution module is used to define the inter-core data interface to achieve inter-core communication and data sharing, and perform consistency maintenance operations on inter-core data.

7. A DSP multi-core computing power division device as claimed in claim 6, characterized in that: The RTOS is used to implement task scheduling on multiple cores of DSP; The audio framework is used to implement the operation and scheduling of audio components in the audio topology on the multi-core of DSP.

8. A DSP multi-core computing power division device as claimed in claim 6, characterized in that: The audio topology definition and identification is performed to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores, specifically including: An audio topology is defined and audio components in the audio topology are identified, so that an I / O task in the audio topology is identified as executable on one core of the DSP and an algorithm task is identified as executable on another core of the DSP.

9. A DSP multi-core computing power partitioning device, characterized in that: The DSP multi-core computing power partitioning device includes a processor, a memory, and a DSP multi-core computing power partitioning program stored in the memory and executable by the processor, wherein when the DSP multi-core computing power partitioning program is executed by the processor, the steps of the DSP multi-core computing power partitioning method as described in any one of claims 1 to 5 are implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a DSP multi-core computing power partitioning program, wherein when the DSP multi-core computing power partitioning program is executed by a processor, the steps of the DSP multi-core computing power partitioning method according to any one of claims 1 to 5 are implemented.

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