Method and system for media error recovery

Abstract

The invention relates to a method and system for media error recovery. In some aspects, a method may include identifying, by one or more processors, a presence of an error in a plurality of data storage units within a range of data storage units of an error bitmap of a redundant array of independent disks (RAID). The method may include generating, by the one or more processors, a parity RAID request format PRRQ frame that identifies the range of data storage units, where at least one data storage unit has an error, the range of data storage units identified at least among the plurality of data storage units. The method may include communicating, by the one or more processors, the PRRQ frame to a controller, the controller configured to restore data within the range of data storage units of the plurality of data storage units in response to the PRRQ frame.

Description

Technical Field

[0001] The present disclosure relates generally to the field of recovery in the event of media errors. Background Art

[0002] A media error can be an indication of a physical problem on the hard disk, which can occur when performing input / output (I / O) operations. The hard disk reports a media error when it is unable to perform read and write operations on a physical block of data. The controller of a redundant array of independent disks (RAID) can intervene to recover blocks with media errors. Summary of the invention

[0003] In a RAID system, a media error may refer to an error or failure that occurs on an individual disk within a RAID array. Media errors may include bad sectors, read and write failures, or any other problem that may affect the integrity or availability of data stored on the disks. To detect media errors within the input / output (I / O) range, a RAID system employs a bitmap. A bitmap may be a data structure that uses a series of bits to represent the state or condition of certain data storage units, such as sectors within an I / O range. An error bitmap may refer to a data structure or representation used to track and manage errors or anomalies within a larger system, such as a file, network, or computer memory. An error bitmap may include multiple individual bits, where each bit corresponds to a specific element, event, or condition within the monitored system.

[0004] Typically, media errors detected within an I / O range (e.g., within a 64K range that is subject to an I / O operation or a series of I / O operations) can be maintained by the RAID in a bitmap. The bitmap can be designed to cover a specific sector range (e.g., within a 64K range). Each bit in the bitmap corresponds to a sector within the range, indicating whether the sector is error-free or whether it has a media error. Depending on the design of the RAID system, the bitmap can be organized in a way that one bit represents one sector or multiple bits can represent a group of sectors.

[0005] When a media error occurs in any sector within the I / O range, the corresponding bit in the bitmap is marked or set to indicate the presence of an error. This allows the RAID system to identify and locate the affected sector without having to perform a complete scan or read operation on every sector within the range. Through the bitmap, the RAID system can track and manage media errors within the I / O range. This information allows the implementation of appropriate error handling and recovery strategies. For example, the RAID system can initiate processes such as data reconstruction, error correction, or disk replacement to ensure the integrity and reliability of the stored data.

[0006] A physical storage device, such as a hard disk drive (HDD), a solid-state drive (SSD), a hybrid drive (which combines features of an HDD and an SSD), or a network attached storage device (NAS) drive, can support multiple storage units. An HDD uses magnetic storage devices to read and write data on a rotating platter. An SSD utilizes flash memory to provide data access speeds, enhanced endurance, and lower power consumption. A hybrid drive combines features of both an HDD and an SSD, for example, a hybrid drive may include one or more HDDs and one or more SSDs to provide a balance between storage capacity and improved performance. A NAS system includes an HDD or SSD that is used as a storage medium; RAM and a processor, such as a CPU; and a network interface, such as an Ethernet port, for connecting the NAS to a local area network (LAN) or a wide area network (WAN).

[0007] The storage unit in the HDD may refer to, for example, a disk that may be independent. Each independent disk (or storage device) may include multiple stripes. A stripe is a unit of data or a data segment to be stored on an individual disk. Multiple stripes are multiple data segments, for example, stripes may be stored across multiple disks. A data segment or stripe may include a separate data storage unit into which data is striped or divided and distributed across multiple disks of a RAID system. Stripes may be distributed across multiple disks in a systematic manner. By spreading data segments across multiple drives, a RAID system allows parallel data retrieval and storage, resulting in faster read and write speeds.

[0008] Each stripe may include multiple data storage units, such as blocks. A block or logical block address (LBA) may refer to the smallest unit in a file system. In some embodiments, an LBA (which may have a size of, for example, 4K) may be the smallest unit of data stored on a device.

[0009] The storage unit in SDD may refer to, for example, a semiconductor-based memory unit. The memory unit may be arranged in an organized grid, forming data organization and data manipulation in SSD. Data may be divided into data segments that may be distributed across the SSD in the array. Each segment may contain multiple data storage units, such as pages.

[0010] A controller or processor, for example, with executable instructions in firmware, hardware, or software, may scan the error bitmap and begin issuing rebuild requests to recover bad blocks containing media errors. For example, when creating a RAID-5 using three drives with a 64K stripe size, the host may issue a read request for the first 16 LBAs. Therefore, media errors identified in the hard drive are reported to the controller (which may be, for example, a RAID controller). The back-end local message index (BKMID) is an index assigned to a disk block written to a RAID array. For example, the BKMID may be used to send I / O to a disk. After the I / O is completed, the I / O status may be obtained from the BKMID. When a BKMID is issued to perform a read operation and the drive fails to retrieve data due to a media error on the block, the drive reports a media error using sense data. According to the SCSI and Advanced Technology Attachment (ATA) standards, sense data may provide additional error information for storage devices. The sense data may contain key-value pairs that provide details about the error type, location, recovery options, etc. When a BKMID failure occurs, the RAID controller can identify the error information by referring to the error status and sensing data available in the BKMID. The RAID controller can report the error back to the RAID system.

[0011] The firmware of the RAID controller records the bad LBA in the error bitmap and submits a reconstruction request to the RAID controller using a parity RAID request format (PRRQ) frame of the parity volume to recover the data of each bad block. A parity volume may refer to a logical disk that contains parity blocks and is used to provide redundancy and fault tolerance. Typically, for the first erroneous LBA (or block) with offset 1, for example, the PRRQ request frame will fill "OffsetInRow" with 1 and "NumberOfBlocks" with 1. The PRRQ request is submitted to the RAID controller to perform a reconstruction of the first erroneous LBA.

[0012] A rebuild request is typically sent to recover one bad block. When the RAID controller rebuilds the data, a command indicating the completion of the PRRQ request is sent back to the firmware of the RAID controller. The controller's firmware may update the frame with an "OffsetInRow" set to the next bad block (e.g., block 2) and issue a new rebuild request (PRRQ) to the RAID controller. This process continues until all identified bad blocks with media errors are recovered. Typically, the number of media errors detected on the drive is equal to the number of rebuild requests issued to recover the bad block data.

[0013] A system of one or more computers may be configured to perform specific operations or actions by virtue of having software, firmware, hardware, or a combination thereof installed on the system, which, in operation, causes the system to perform the actions. One or more computer programs may be configured to perform specific operations or actions by virtue of containing instructions that, when executed by a data processing device, causes the device to perform the actions.

[0014] In one general aspect, a method may include identifying, by one or more processors, the presence of errors in a plurality of data storage units within a range of data storage units of an error bitmap of a redundant array of independent disks (RAID). The method may also include generating, by the one or more processors, a parity RAID request format (PRRQ) frame, wherein the PRRQ frame identifies the range of data storage units, wherein at least one data storage unit has an error, and wherein the range of data storage units is identifiable at least among the plurality of data storage units. The method may further include communicating, by the one or more processors, the PRRQ frame to a controller, wherein the controller is configured to recover data within the range of data storage units among the plurality of data storage units in response to the PRRQ frame. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the method.

[0015] Implementations may include the method, wherein the controller may be configured to recover the data within the range of the plurality of data storage units in response to no more than one PRRQ frame. Implementations of the method may include generating, by the one or more processors, the PRRQ frame to include a first field identifying an offset for identifying a location of a first data storage unit in the plurality of data storage units within the range of data storage units and a second field identifying the number of data storage units within the range of data storage units. Implementations may include the method, wherein the range of data storage units is in a data segment on a storage device of the RAID. Implementations may include the method, wherein the error is absent in at least one data storage unit within the range of data storage units. Implementations may include the method, wherein the error is absent in two or more non-subsequent first data storage units within a range of data storage units between two or more non-subsequent second data storage units. Implementations may include the method, wherein the error bitmap of the plurality of data storage units may identify a cluster of errors on a single storage device of the RAID. Implementations may include the method, wherein the error is a media error. Implementations of the described technology may include hardware, methods or processes, or computer tangible media.

[0016] In one general aspect, a circuit system may include one or more processors configured to identify the presence of errors in a plurality of data storage units within a range of data storage units of an error bitmap of a redundant array of independent disks (RAID). Implementations may include the one or more processors configured to generate a parity RAID request format (PRRQ) frame, wherein the PRRQ frame may identify the range of data storage units, wherein at least one data storage unit has an error, and wherein the range of data storage units is identifiable at least among the plurality of data storage units. Implementations may include the one or more processors configured to communicate the PRRQ frame to a controller, wherein the controller is configured to recover data within the range of data storage units among the plurality of data storage units in response to the PRRQ frame. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of a method.

[0017] Implementations may include the circuit system, wherein the controller is configured to recover the data within the range of the plurality of data storage units in response to no more than one PRRQ frame. Implementations may include the circuit system, wherein the one or more processors are further configured to generate the PRRQ frame to include a first field identifying an offset for identifying a location of a first data storage unit in the plurality of data storage units within the range of data storage units and a second field identifying the number of data storage units within the range of data storage units. Implementations may include the circuit system, wherein the range of data storage units is in a data segment on a storage device of the RAID. Implementations may include the circuit system, wherein the error is absent in at least one data storage unit within the range of data storage units. Implementations may include the circuit system, wherein the error is absent in two or more non-subsequent first data storage units within a range of data storage units between two or more non-subsequent second data storage units. Implementations may include the circuit system, wherein the error bitmap of the plurality of data storage units may identify clusters of errors on a single storage device of the RAID. Implementations of the described technology may include hardware, methods or processes, or computer tangible media.

[0018] In one general aspect, a system may include one or more processors configured to identify the presence of errors in a plurality of data storage units within a range of data storage units of an error bitmap of a redundant array of independent disks (RAID). The one or more processors may be configured to generate a parity RAID request format (PRRQ) frame, wherein the PRRQ frame may identify the range of data storage units, wherein at least one data storage unit has an error, and wherein the range of data storage units is identifiable at least among the plurality of data storage units. The one or more processors may be configured to communicate the PRRQ frame to a controller, wherein the controller is configured to recover data within the range of data storage units among the plurality of data storage units in response to the PRRQ frame. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of a system.

[0019] Embodiments may include the system, wherein the controller is configured to recover the data within the range of the plurality of data storage units in response to no more than one PRRQ frame. Embodiments may include the system, wherein the one or more processors are further configured to generate the PRRQ frame to include a first field identifying an offset for identifying a location of a first data storage unit in the plurality of data storage units within the range of data storage units and a second field identifying the number of data storage units within the range of data storage units. Embodiments may include the system, wherein the range of data storage units is in a data segment on a storage device of the RAID. Embodiments may include the system, wherein the error is absent in at least one data storage unit within the range of data storage units. Embodiments may include the system, wherein the error is absent in two different groups of data storage units within the range of data storage units. Embodiments may include the system, wherein the error bitmap of the plurality of data storage units identifies a cluster of errors on a single storage device of the RAID. Embodiments may include the system, wherein the error is a media error. Implementations of the described technology may include hardware, methods or processes, or computer tangible media. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present disclosure is described in conjunction with the accompanying drawings, which are not necessarily drawn to scale:

[0021] Figure 1 is a block diagram depicting a computing system according to at least some embodiments of the present disclosure;

[0022] Figure 2 is a block diagram depicting details of a controller according to at least some embodiments of the present disclosure;

[0023] Figure 3 is a flow chart depicting a data recovery method according to at least some embodiments of the present disclosure;

[0024] Figure 4 is a block diagram depicting details of using data structures according to at least some embodiments of the present disclosure;

[0025] Figure 5 is a block diagram depicting details of a drive having a media error in accordance with at least some embodiments of the present disclosure;

[0026] Figure 6 is a block diagram depicting details of one drive of a cluster having a media error in accordance with at least some embodiments of the present disclosure;

[0027] Figure 7 is a block diagram depicting details of two drives having media errors in accordance with at least some embodiments of the present disclosure;

[0028] Fig. 8A is a block diagram depicting an embodiment of a computing environment including one or more access points in communication with one or more wireless devices or stations; and

[0029] Figure 8B and 8C is a block diagram depicting an embodiment of a computing device that may be used in conjunction with the methods and systems described herein. DETAILED DESCRIPTION

[0030] Typically, RAID architectures provide mechanisms for detecting, mitigating, and recovering from media errors. For example, in error detection, RAID systems typically utilize techniques such as checksum or parity information to detect errors within a data block. When a cluster of media errors is encountered, the error detection mechanism will identify the damaged sector by comparing the calculated checksum or parity to the expected value.

[0031] To mitigate the effects of media errors, RAID systems may employ various levels of redundancy, such as RAID 1 (mirrored redundancy), RAID 5, or RAID 6 (parity-based redundancy). Redundancy may involve storing multiple copies of data and distributing parity information across different drives. When a cluster encounters a media error, redundancy allows the RAID system to use the redundant information to rebuild the damaged data. When the RAID system identifies the affected sectors within the cluster, it may initiate a recovery process. This process typically involves rebuilding the lost or damaged data using the redundant information available within the RAID array. The recovery process may vary depending on the RAID level employed and the specific algorithms and techniques used by the RAID controller.

[0032] In some embodiments, the RAID system may have three arms: Arm 0, Arm 1, and a parity information drive ( Figure 5 ). In some embodiments, in RAID 3, RAID 4, and RAID 5, parity information may be distributed across all data drives in the RAID array. In some embodiments, parity information may be stored, for example, on one drive where a parity sum of all block data is written. Parity may be used to detect errors in the storage system. In some embodiments, at least some stripes of parity information on a drive may contain parity blocks that store XOR (exclusive OR) values ​​of corresponding blocks from other drives (e.g., Arm 0 and Arm 1). For example, adding a checksum to the data may be used, which may detect errors during data transfer. For example, adding a single bit of data to the end of a block of data may ensure that the number of bits in the block is even or odd. In Figure 5 In the example shown in FIG. 1 , blocks 1, 2, 3, and 5-11 in Arm 0 have media errors (e.g., blocks 1, 2, 3, and 5-11 are bad blocks in Arm 0). No blocks in Arm 1 have media errors, so bad blocks 1, 2, 3, and 5-11 in Arm 0 can be recovered from good blocks in Arm 1. Typically, for ten recoverable bad blocks within a stripe (e.g., blocks 1, 2, 3, and blocks 5-11 in Arm 0), ten rebuild requests are issued to recover the ten bad blocks. Each PRRQ rebuild request sent by the RAID controller may generate a back-end I / O (BKIO) to read from other arms (e.g., Arm 1) and perform an XOR operation to recover the data in Arm 0.

[0033] Typically, the recovery process locks regions of a block, causing delays for I / O operations involving the same row of the block. As a result, host I / Os experience longer delays, potentially leading to resource starvation or extended wait times.

[0034] When the firmware of a RAID controller spends more time performing media error recovery processing, other firmware operations may be negatively impacted. Recovery time increases in proportion to the number of media errors detected on a drive. When clusters of media errors are encountered on a drive, the recovery time may significantly impact the overall performance of the RAID controller. For example, an error bitmap may identify clusters of media errors on a drive simultaneously or within a short period of time. A cluster of media errors may refer to multiple consecutive or closely located sectors on a drive. For example, if Figure 6 , a cluster of blocks 1 through 11 has media errors. This cluster of errors can occur due to various factors, such as physical damage to the disk surface, manufacturing defects, wear and tear from use, degradation over time, or environmental conditions. A cluster of media errors can have a significant impact on data integrity and RAID array performance.

[0035] refer to Figure 1 , details of a computing system 100 capable of implementing data recovery will be described according to at least some embodiments of the present disclosure. The computing system 100 is shown to include a host system 104, a controller 108 (e.g., a SCSI controller, a SAS controller, a RAID controller, etc.), and a storage array 112 having a plurality of storage devices (or disk drives) 136a to N therein. Each disk drive 136a to N may have one or more arms. An arm is a device for forming a RAID array. An arm may be a storage device, such as a hard disk drive or a solid-state drive, which is configured with other arms to provide data redundancy and improved performance. In a RAID array, data may be distributed across multiple arms. If one arm fails, data may still be accessed from the remaining arms. Different RAID levels provide different combinations of redundancy and performance. The storage array 112 may include a combination of Fig. 8A and 8B Any or all components of the computer system 800 described herein may be executed in conjunction with Fig. 8A and 8B Any or all of the functions of the computer system 800 described herein may be implemented. The system 100 may utilize any type of data storage architecture. The specific architecture (e.g., RAID architecture) depicted and described herein should not be construed as limiting the embodiments of the present disclosure. However, it should be understood that if the system is implemented using a RAID architecture, any type of RAID scheme (e.g., RAID-0, RAID-1, RAID-2, ..., RAID-5, RAID-6, etc.) may be employed.

[0036] In a RAID-0 (also referred to as RAID level 0) scheme, data blocks are stored sequentially across one or more of the storage devices 136a to N without redundancy. This effectively means that no data block is a copy of another data block, and no parity block is to be recovered from a failure of a storage device 136. On the other hand, a RAID-1 (also referred to as RAID level 1) scheme uses one or more of the storage devices 136a to N for storing data blocks and an equal number of additional mirror devices for storing copies of the stored data blocks. Higher level RAID schemes may further divide data into bits, bytes, or blocks for storage across multiple storage devices 136a to N. One or more of the storage devices 136a to N may also be used to store error correction or parity information.

[0037] A single unit of storage may be spread across multiple devices 136a to N, and such a unit of storage may be referred to as a stripe. A stripe may include related data written to the multiple devices 136a to N and parity information written to the parity storage devices 136a to N. In a RAID-5 (also referred to as RAID level 5) scheme, the stored data is divided into blocks for storage across multiple devices 136a to N, with a single parity block for each stripe distributed across the multiple devices 136a to N in a particular configuration. This scheme may be compared to a RAID-6 (also referred to as RAID level 6) scheme, in which dual parity blocks are determined for one stripe and distributed across each of the multiple devices 136a to N in the array 112.

[0038] A controller in a RAID system may refer to a hardware device or a software program or a combination thereof that manages the drives, such as, for example, hard disk drives (HDDs) or solid-state drives (SSDs), arranged in a storage array in such a way that the drives operate as logical units. A RAID controller may be located between the operating system and the storage drives. A RAID controller may be hardware-based or software-based. A hardware RAID controller may be a separate physical card installed in an expansion slot on a server or computer motherboard. A hardware RAID controller may include a processor and memory that offloads RAID-related tasks from the main system CPU. A software RAID controller uses the server main CPU and is managed by the operating system without the need for a separate card.

[0039] For example, one of the functions of the controller 108 is to make the multiple storage devices 136 a-N in the array 112 appear to the host system 104 as a single high-capacity or higher-capacity disk drive than any individual storage device. Thus, the controller 108 may be configured to automatically distribute data supplied from the host system 104 (potentially with parity information) across the multiple storage devices 136 a-N without exposing the manner in which the data is actually distributed to the host system 104.

[0040] In the depicted embodiment, the host system 104 is shown as including a processor 116, an interface 120, and a memory 124. It should be appreciated that the host system 104 may omit some of the listed components or include additional components without departing from the scope of the present disclosure. The host system 104 may include a processor 116, an interface 120, and a memory 124. Fig. 8A and 8B Any or all components of the computer system 800 described herein may be executed in conjunction with Fig. 8A and 8B800. In some embodiments, host system 104 corresponds to a user computer, a laptop computer, a workstation, a server, a collection of servers, etc. Thus, host system 104 may or may not be designed to receive input directly from a human user.

[0041] The processor 116 of the host system 104 may include a microprocessor, a central processing unit (CPU), a collection of microprocessors, etc. The memory 124 may be designed to store instructions that, when executed by the processor 116, enable the functionality of the host system 104. The memory 124 may also store data that is ultimately written to the storage array 112 by the host system 104. The memory 124 may further be used to store data retrieved from the storage array 112. The memory 124 device may include, but is not limited to, volatile or non-volatile computer memory (e.g., flash memory, RAM, DRAM, ROM, EEPROM, etc.).

[0042] The interface 120 of the host system 104 enables the host system 104 to communicate with the controller 108 via the host interface 128 of the controller 108. In some embodiments, the interface 120 and the host interface 128 may be of the same or similar type (e.g., utilizing a common protocol, a common communication medium, etc.) so that commands issued by the host system 104 can be received at the controller 108 and data retrieved by the controller 108 can be transmitted back to the host system 104. The interfaces 120, 128 may correspond to parallel or serial computer interfaces that utilize wired or wireless communication channels. The interfaces 120, 128 may include hardware that implements such wired or wireless communications. The communication protocol used between the host system 104 and the controller 108 may correspond to any type of known host or memory control protocol. Non-limiting examples of protocols that may be used between the interfaces 120, 128 include SAS, SATA, SCSI, Fibre Channel (FC), iSCSI, Ethernet ATA, InfiniBand, etc.

[0043] The controller 108 may provide the host system 104 with the ability to present the entire storage array 112 as a single large data storage device. Any known mechanism may be used to accomplish this task. The controller 108 may help manage the storage devices 136a to N (which may be hard disk drives, solid state drives, or a combination thereof) to operate as a logical unit. In some embodiments, the controller 108 may be physically incorporated into the host device 104 as a peripheral component interconnect (PCI) expansion (e.g., PCI Express (PCI-e)) card or the like. In such scenarios, the controller 108 may be referred to as a RAID adapter.

[0044] Without departing from the scope of the present disclosure, the storage devices 136a to N in the storage array 112 may be of similar types or may be of different types. The storage devices 136a to N may be co-located with each other, or may be physically located in different geographic locations. The nature of the storage interface 132 may depend on the type of storage devices 136a to N used in the storage array 112 and the required capabilities of the array 112. The storage interface 132 may correspond to a virtual interface or an actual interface. As with other interfaces described herein, the storage interface 132 may include serial or parallel interface technology. Examples of the storage interface 132 include, but are not limited to, SAS, SATA, SCSI, FC, iSCSI, Ethernet ATA, InfiniBand, and the like.

[0045] Reference Figure 2 , additional details of the controller 108 will be described according to at least some embodiments of the present disclosure. The controller 108 may include a combination of Fig. 8A and 8B Any or all components of the computer system 800 described herein may be executed in conjunction with Fig. 8A and 8B 1. The computer system 800 of claim 1 may be a computer system that is configured to store and retrieve data from a plurality of disk drives in a RAID array. The computer system 800 of claim 1 may be a computer system that is configured to store and retrieve data from a plurality of disk drives in a RAID array. The computer system 800 of claim 1 may be a computer system that is configured to store and retrieve data from a plurality of disk drives in a RAID array. The computer system 800 of claim 1 may be a computer system that is configured to store and retrieve data from a plurality of disk drives in a RAID array. The computer system 800 of claim 1 may be a computer system that is configured to store and retrieve data from a plurality of disk drives in a RAID array. The computer system 800 of claim 1 may be a computer system that is configured to store and retrieve data from a plurality of disk drives in a RAID array. The computer system 800 of claim 1 may be a computer system that is configured to store and retrieve data from a plurality of disk drives in a RAID array. The computer system 800 of claim 1 may be a computer system that is configured to store and retrieve data from a plurality of disk drives in a RAID array.

[0046] The processor 204 of the controller 108 executes instructions and performs the calculations required for data recovery. The processor 204 may include an integrated circuit (IC) chip or multiple IC chips, a CPU, a microprocessor, etc. The controller 108 utilizes a memory 208 to store data, instructions, and intermediate results during the recovery process, facilitating efficient data manipulation and reconstruction. The processor 204 may be configured to execute instructions in the memory 208, which is shown to include a host I / O manager 232, a buffer manager 248, a cache manager 252, a RAID manager 256, and a SAS manager 260. In addition, in conjunction with performing caching or buffering functions, the processor 204 may utilize a buffer memory 220, one or more internal scatter gather lists (ISGLs) 224, and a cache frame anchor 228. The host I / O manager 232 is shown to include multiple subroutines, including but not limited to a host message unit 236, a command extraction unit 240, and a completion engine 244. Internal scatter gather list (ISGL) 224 refers to a data structure used for efficient data transfer between devices (eg, in a storage system or a network interface).

[0047] Each of the components (e.g., host I / O manager 232, buffer manager 248, cache manager 252, RAID manager 256, and SAS manager 260) may correspond to a different functional block operating in their own local memory, loading global memory (e.g., global buffer memory 220 or memory 208) as needed. Each of these different functional blocks may be accelerated by a different hardware thread without departing from the scope of the present disclosure.

[0048] Memory 208 may be volatile and non-volatile in nature. As indicated above, memory 208 may include any hardware component or collection of hardware components capable of storing instructions and communicating those instructions to processor 204 for execution. Non-limiting examples of memory 208 include RAM, ROM, flash memory, EEPROM, variations thereof, combinations thereof, and the like. Similarly, buffer memory 220 may be volatile or non-volatile in nature. Buffer memory 220 may be configured for multiple reads and writes, and may be adapted for fast access by processor 204. Controller 108 utilizes buffer memory 220 to temporarily store data during the recovery process, ensuring efficient read and write operations. Controller 108 interacts with ISGL 224, which provides efficient data storage and retrieval capabilities, facilitating the recovery process. Within cache memory, controller 108 uses cache frame anchor 228 as a reference point for storing and retrieving data during the recovery process.

[0049] The instructions stored in the memory 208 are shown as different instruction sets, but it should be understood that the instructions can be combined into a smaller number of instruction sets without departing from the scope of the present disclosure. The host I / O manager 232, when executed, enables the processor 204 to manage I / O commands received from the host system 104 and facilitate higher-level communications with the host system 104. In some embodiments, the host I / O manager 232 may utilize a host message unit 236 to process incoming messages received from the host system 104. As a non-limiting example, the controller 108 may receive messages from the host system 104 in an NPI protocol. The host message unit 236 may take the message received from the host system 104 and pass the content of the message to the command extraction unit 240. The command extraction unit 240 may be configured to determine whether a particular command in the message can be accelerated (e.g., can be passed to a particular functional block to facilitate hardware acceleration). If it is determined that the command can be accelerated, the command extraction unit 240 may implement a hardware acceleration process and generate an appropriate local message ID (LMID) representing all information received from the host system 104 (in the command). The LMID effectively represents a command received from the host system 104, but in a different format that can be understood by the managers 248, 252, 256, 260. In some embodiments, the command extraction unit 240 can route various commands (such as LMIDs) to one or more of the buffer manager 248, cache manager 252, RAID manager 256, and SAS manager 260. The routing of the command may depend on the type of command and the function to be performed. The completion engine of the host I / O manager 232 may be responsible for reporting to the host system 104 that the I / O command has been completed by the controller 108.

[0050] The RAID manager 256 and the SAS manager 260 may include instructions that, when executed, enable the processor 204 to communicate with the storage array 112 of the storage devices 136 therein. In some embodiments, the RAID manager 256 and the SAS manager 260 may receive commands directly from the host I / O manager 232 (if caching is not required), or they may receive commands from the cache manager 252 after appropriate caching processes have been performed. When invoked, the RAID manager 256 and the SAS manager 260 may enable the processor 204 to complete read or write commands and exchange data with the storage array 112.

[0051] The host I / O manager 232 oversees I / O operations between the host system 104 and the controller 108, ensuring proper data transfer and command handling. Incoming messages or commands from the host system are received by the host messaging unit 236, which relays them to the appropriate components within the controller 108. The command extraction unit 240 of the controller 108 extracts the relevant commands from the incoming messages and prepares them for execution. After executing the command, the completion engine 244 manages its completion and sends the corresponding response back to the host system 104 ( Figure 1 ), providing status updates. The buffer manager 248 of the controller 108 allocates and manages the buffer memory 220 to store data during read and write operations, ensuring efficient data handling. The cache manager 252 oversees the management and utilization of the cache memory (including data caching, eviction policy, and cache coherency) to optimize data access during recovery. The RAID manager 256 oversees the overall management and operation of the RAID system 100, including error recovery and data reconstruction. The SAS manager 260 handles the Serial Attached SCSI (SAS) protocol, facilitating communication between the controller 108 and the disk drives during the recovery process. Other protocols may include Serial ATA (SATA), Non-Volatile Memory Express (NVMe), Fibre Channel (FC), Internet Small Computer System Interface (iSCSI), InfiniBand, Fibre Channel over Ethernet (FCoE), Parallel Advanced Technology Attachment (PATA), etc.

[0052] The software driver 212 facilitates communication between the controller 108 and the host system operating system to enable data transfer and command execution. The driver 212 may include firmware, hardware, software, or a combination thereof that enables the processor 204 to use other hardware components in the controller 108. For example, different drivers 212 may be provided to support the functionality of the interfaces 128, 132. As another example, a separate driver 212 may be provided to support the functionality of the buffer memory 220. The driver 212 may execute low-level routines that allow the processor 204 to communicate with other hardware components and respond to commands received from the processor 204.

[0053] The power supply 216 supplies power to the controller 108 and the disk drives 136a to N, ensuring their operation during the recovery process. The power supply 216 may include hardware components that provide the power required to operate the processor 204 and other components to the controller 108. As an example, the power supply 216 may correspond to a power converter that receives AC power from an external source (e.g., an electrical outlet) and converts the AC power to DC power that can be used by other hardware components of the controller 108. In some embodiments, the power supply 216 may correspond to an internal power source (e.g., a battery bank, a capacitor bank, etc.) that provides power to the hardware components of the controller 108.

[0054] refer to Figure 3 , additional details of data structure 300 will be described according to at least some embodiments of the present disclosure. Data structure 300 can be used to recover data in a bad block. Figure 3 The data structure 300 is shown as having a particular layout or organization, but it should be understood that the data structure 300 can be configured in any number of ways without departing from the scope of the present disclosure. The data structure 300 can correspond to a data structure created and managed by one of the components in the memory 208.

[0055] Various sections of data structure 300 may be used to store data that enables controller 208 to utilize variable stripe sizes, thereby taking advantage of different workloads where different types of commands require different amounts of memory and processing power.

[0056] The data structure 300 is shown to include a function identification field, an operation code field (opcode), a hardware (HW) context, a device disposition, a parent LMID field and a next LMID field, a tag field and a message tag field, a next LMID identification field, a counter or coefficient index field, an internal scatter gather list (ISGL) skip count or offset field (row offset), a stride field, a RowMod field, a stripe or row number field, a second stripe or row number field, a number of blocks to be restored field, a leading ISGL or extended LMID field, and a control tag field. In some embodiments, the data structure 300 may include an MSI index field, a logical drive (LD) number field, a VF_ID field, an MPI tag field, a reserved field, an arm field, an arm offset field, a data HSGL or RSGL ID field, a primary reference tag field, a primary application tag mask, a primary application tag field, an extended tag field, an extended ID field, and a buffer descriptor field (not shown). Some or all of these fields may be used in conjunction with performing a recovery process, determining where to start a recovery process, determining where to end a recovery process, and the like. Data structure 300 is particularly helpful in enabling certain managers (e.g., cache manager 252 and buffer manager 248) to communicate with each other and coordinate their efforts with respect to performing recovery procedures.

[0057] The stripe or stripe number field may store data identifying the stripe or stripe for which data structure 300 is used. In some embodiments, the stripe or stripe field may uniquely identify a stripe or stripe. In some embodiments, the stripe or stripe field may identify a memory location (e.g., a starting location) of a stripe or stripe of data stored in storage device 136. For example, the stripe or stripe field may store a number that has been assigned to a particular stripe or stripe of data.

[0058] The tag fields (tag and message tag) may store information describing the memory location of a tag or an identifier of a tag associated with data structure 300. Various types of tags may be used to identify the type of data stored in conjunction with data structure 300, and the tag extension field may be used to identify that type of data.

[0059] The LD ID field may contain an identifier or multiple identifiers of a logical disk used to store data. A logical disk may be identified by a memory location or by some alias used in the naming scheme of logical disks managed by controller 108.

[0060] The Span field may store a value describing the number of data blocks spanned by a particular data set.The Extension ID field may store information that uniquely identifies an extension frame from among other extension frames.

[0061] A local message ID (LMID) may refer to a unique identifier assigned to an individual message within a system. LMIDs are used as a means of identifying and tracking messages as they traverse through the system, allowing efficient message routing, processing, and synchronization. If an error or failure occurs during message transmission or processing, the local message ID may be utilized for error detection, recovery, and resynchronization. By referencing the local message ID, components of the controller 108 may identify and handle messages that have encountered an error or require retransmission. The parent LMID refers to the identifier of the RAID array or logical unit in which a media error occurred, used as a reference for the recovery process. In a RAID system with multiple logical units or arrays, the next LMID represents the identifier of the logical unit. The data structure 300 may correspond to an LMID used to communicate data between various managers or modules of the controller 108. LMIDs may refer to local message IDs, for example, unique identifiers assigned to individual messages within a communication system. In some embodiments, the LMID may correspond to a recovery LMID used to facilitate a hardware-based recovery process or routine.

[0062] RAID controller 108 initiates and coordinates the recovery process using opcodes representing specific operations or commands, indicating the components involved accordingly. Various tags are associated with components or operations within system 100 to provide specific attributes or properties to guide the recovery process. Message tags associated with error notifications and recovery commands provide specific attributes or properties related to errors and subsequent operations. Hardware context contains information about the current state of hardware components involved in the recovery process, assisting in decision making and data manipulation.

[0063] Figure 4 4 is a flowchart depicting a data recovery method 400 according to some embodiments. The method 400 may be performed by the system 100, in combination with Fig. 8A and 8BThe computer system 800 described herein or any other computing device described herein executes (execute / perform) or is otherwise implemented. In short, the method 400 can be implemented to perform a reconstruction operation of multiple blocks using a single request. The error bitmap is used to track the status of individual blocks within the range of blocks on the disk 136a to N. The error bitmap can be a data structure of the size of the bitmap corresponding to the entire range of blocks on the disk. Each bit in the bitmap represents the status of the corresponding block on the disk. A "1" in the bitmap can indicate that the corresponding block is in an error state, and a "0" can indicate that the block does not have an error. The error bitmap can indicate whether each block is in an error state. When the disk 136a to N or a portion of the disk 136a to N becomes faulty, the error bitmap facilitates identification of which specific blocks are affected, and the system 100 can use redundancy to recover the lost data. In order to identify the presence of errors in multiple blocks within the range of blocks within the error bitmap of the RAID array 112, the following operations can be performed: monitoring and reporting, error bitmap analysis, and identification of affected blocks.

[0064] For example, the RAID controller 108 may monitor the status of the disks 136a to N in the RAID array 112. When an error occurs on one or more of the disks 136a to N, the error is reported to the RAID management system (e.g., the controller 108). The RAID controller 108 may access and scan the error bitmap to identify bits that are set to "1" indicating the presence of an error. Since the error bitmap represents a block range, a series of consecutive "1"s may point to a failed segment on a particular disk.

[0065] At step 402, the method 400 may include scanning an error bitmap. In some embodiments, when the RAID system builds the error bitmap, the firmware of the RAID controller 108 may scan and identify whether the identified error block can be recovered from other arms. In some embodiments, the disk drives 136a to N detect a media error on one of its arms. The disk drives 136a to N send an error notification to the RAID controller 108 via the storage interface 132. The RAID manager 256 of the controller 108 receives the error notification from the disk drives 136a to N. The RAID manager 256 analyzes the error and identifies the parent logical multiplier ID (parent LMID) associated with the disk drive 136a to N having the media error.

[0066] At step 404, method 400 may include filling a PRRQ frame. In some embodiments, the firmware of RAID controller 108 may identify a range of recoverable bad blocks in a stripe. For example, based on the error notification and the parent LMID, RAID manager 256 may initiate a recovery process.

[0067] At step 406, method 400 may include submitting a rebuild request for multiple blocks. In some embodiments, the firmware of RAID controller 108 may issue no more than one PRRQ request to rebuild all bad blocks. RAID manager 256 sends a recovery command to host message unit 236. Host message unit 236 forwards the recovery command to command extraction unit 240. Command extraction unit 240 extracts the recovery command from the incoming message. Processor 204 receives the extracted recovery command from command extraction unit 240.

[0068] At step 408, according to some embodiments, method 400 may include restoring data. For example, processor 204 executes the extracted restore command received from command extraction unit 240. Processor 204 communicates with individual disk drives 136a to N in RAID array 112 through storage interface 132 to retrieve data required for data reconstruction. Processor 204 uses buffer manager 248 to allocate and manage buffer memory for temporary storage during the restore process. The method begins when buffer manager 248 receives an allocate buffer command. This command may be received in the form of an LMID or multiple LMIDs.

[0069] The processor 204 utilizes the cache manager 252 to handle data caching and eviction policies to optimize data access during recovery. The command (e.g., LMID) may be received at the cache manager 252 from the host I / O manager 232 or the buffer manager 248. The ISGL received along with the LMID may also be loaded at this stage of the recovery process. The method 400 may include obtaining the starting row and number of blocks from the LMID, and the arm offset from the LMID. This information is used to calculate the starting LBA, the number of rows from the starting row spanned by the I / O command, the number of extensions per stripe, the extension index, and the starting buffer segment index. In some embodiments, the starting stripe and number of blocks are obtained directly from the command LMID. The starting LBA is calculated from the first recoverable LBA of the stripe. The number of stripes required from the first recoverable LBA is calculated from the number of blocks required to accommodate the I / O command. The number of extensions per stripe is calculated by dividing the stripe size by the number of buffer segments in the extension. The extension index is calculated by dividing the first arm offset by the number of buffer segments in the extension.

[0070] The processor 204 uses the data retrieved from the working drive and the parity information (in the case of RAID 5 or RAID 6) to reconstruct the data lost due to the media error. The processor 204 performs data verification to ensure the accuracy of the reconstructed data. The processor 204 writes the reconstructed data back to the appropriate disk drives in the RAID array through the storage interface 132. The RAID manager 256 verifies the successful write-back and corrects any inconsistencies or errors in the RAID array 112. The RAID manager 256 notifies the completion engine 244 of the status of the recovery process and any error corrections made. The completion engine 244 sends the status update back to the host messaging unit 236. The host messaging unit 236 relays the status update to the host I / O manager 232. The host I / O manager 232 notifies the host system 104 of the completion of the recovery process and the success of the error correction.

[0071] Figure 5 1 is a block diagram depicting details of a system 500 in which one of the drives has a media error according to at least some embodiments of the present disclosure. In some embodiments, a media error on a single drive may be identified by the controller 108. In some embodiments, the firmware of the controller 108 may create a rebuild request using a PRRQ frame. A PRRQ frame is a data structure used to facilitate the implementation of parity RAID technology in a computer storage system. Parity RAID is a data protection method that enhances the reliability and fault tolerance of a storage device by distributing data and parity information across multiple disks. PRRQ frames are commonly used in storage protocols designed to coordinate and manage RAID operations, such as Small Computer System Interface (SCSI) and Serial ATA (SATA). Other protocols may include Non-Volatile Memory Express (NVMe), Fibre Channel (FC), Internet Small Computer System Interface (iSCSI), InfiniBand, Fibre Channel over Ethernet (FCoE), Parallel Advanced Technology Attachment (PATA), etc. PRRQ frames are used as a standardized format for issuing RAID-specific requests to a RAID controller or RAID array.

[0072] The PRRQ frame may include information related to the RAID operation, including but not limited to the following: the type of RAID operation requested, such as read, write, rebuild, or parity calculation; RAID level; source and destination addresses; data payload (the actual data to be written to or read from the RAID array); and parity information used for RAID calculations (e.g., for RAID 5 and RAID 6). The PRRQ frame enables communication between the host system and the RAID controller or RAID array, facilitating efficient management and coordination of RAID functionality. When the host system needs to perform a RAID operation, it constructs a PRRQ frame with parameters and sends it to the RAID controller through an appropriate storage protocol. The RAID controller interprets the PRRQ frame, performs the requested RAID operation, and may return relevant information (e.g., operation results or status updates) to the host system.

[0073] In some embodiments, the PRRQ frame may have the following parameters: OffsetInRow and NumberOfBlocks. Figure 5 In the case described in , the "OffsetInRow" field may be set to 1 (e.g., the first bad block, which is block 1). The number of blocks may be set to the sum of 1 and the difference between the last bad block (e.g., block 11) and the first bad block (e.g., block 1). Therefore, the "NumberOfBlocks" to be rebuilt may be set to eleven blocks (e.g., 1+11-1). In some embodiments, the firmware of the controller 108 may issue no more than one PRRQ request to rebuild all bad blocks 1 to 3 and blocks 5 to 11. Figure 5 , block 4 has no media errors, but it can be rebuilt with no more than one PRRQ request along with bad blocks 1 to 3 and blocks 5 to 11. The user can save time by using no more than one PRRQ request instead of using two separate PRRQ requests: a first PRRQ request for rebuilding bad blocks 1 to 3 and a second PRRQ request for rebuilding bad blocks 5 to 11.

[0074] In some embodiments, there may be no error in two or more non-subsequent blocks within a block range between two or more non-subsequent blocks. For example, in Arm 0, there may be no error in two non-contiguous blocks 4 and 8 ( Figure 51). In some embodiments, the firmware of controller 108 may issue no more than one PRRQ request to rebuild all bad blocks 1 to 3, bad blocks 5 to 7, and bad blocks 9 to 11. Blocks 4 and 8 may not have media errors, but they may be rebuilt with no more than one PRRQ request along with bad blocks 1 to 3, bad blocks 5 to 7, and bad blocks 9 to 11. The user can save time by using no more than one PRRQ request instead of three separate PRRQ requests: a first PRRQ request for rebuilding bad blocks 1-3, a second PRRQ request for rebuilding bad blocks 5-7, and a third PRRQ request for rebuilding bad blocks 9-11.

[0075] Figure 6 1 is a block diagram depicting details of a system 600 in which one of the drives has a cluster of media errors according to at least some embodiments of the present disclosure. In some embodiments, a cluster of errors on a single drive may be identified by the controller 108. In some embodiments, the firmware of the controller 108 may create a rebuild request using a PRRQ frame with the following parameters: OffsetInRow and NumberOfBlocks. For example, the "OffsetInRow" field may be set to 1 (e.g., the first bad block, which is block 1). The number of blocks may be set to the sum of 1 and the difference between the last bad block (e.g., block 11) and the first bad block (e.g., block 1). Therefore, the "NumberOfBlocks" to be rebuilt may be set to eleven blocks (e.g., 1+11-1). In some embodiments, the firmware of the controller 108 may issue no more than one PRRQ request to rebuild all bad blocks 1 to 11. The system 100 described herein may improve RAID controller media error recovery time because the system 100 may allow a user to take advantage of hardware support to perform rebuild operations for multiple blocks in no more than one PRRQ request.

[0076] Figure 7is a block diagram depicting details of a system 700 in which two drives have media errors in accordance with at least some embodiments of the present disclosure. In some embodiments, in addition to more than one arm with media errors, there may also be one or more blocks (e.g., Block 7) with media errors in all drives (e.g., Arm 0 and Arm 1) for recovery information. If not all errors are recoverable, the firmware of the controller 108 may separate the range of I / O for recovery and submit a PRRQ frame to rebuild the recoverable blocks.

[0077] For example, the firmware of the controller 108 may issue two PRRQ requests using the same PRRQ frame to rebuild all recoverable bad blocks 1 to 6 and 8 to 11. In some embodiments, the firmware of the controller 108 may create a first rebuild request using a PRRQ frame with the following parameters: OffsetInRow and NumberOfBlocks. The "OffsetInRow" field may be set to 1 (e.g., the first bad block, which is block 1). The number of blocks may be set to the sum of 1 and the difference between the last recoverable bad block (e.g., block 6) and the first recoverable bad block (e.g., block 1). Therefore, the "NumberOfBlocks" to be rebuilt using the first rebuild request may be set to six blocks (e.g., 1+6-1).

[0078] When the first reconstruction is complete, a second reconstruction request may be issued using the same PRRQ frame with the following parameters: OffsetInRow and NumberOfBlocks. The "OffsetInRow" field may be set to 8 (e.g., bad block 8). The number of blocks may be set to the sum of 1 and the difference between the last recoverable bad block (e.g., block 11) and the first recoverable bad block (e.g., block 8). Therefore, the "NumberOfBlocks" to be rebuilt with the second reconstruction request may be set to four blocks (e.g., 1+11-8). Therefore, two PRRQ requests using the same PRRQ frame are used to reconstruct all recoverable bad blocks 1 to 6 and 8 to 11.

[0079] System 100 can allow a significant reduction in the number of rebuild requests submitted to the hardware. Due to the smaller number of rebuild requests submitted to the hardware, hardware resource utilization is reduced. For example, for a logical drive (LD) of an arm with a 256K stripe size and a cluster with ten media errors, only one rebuild request can be issued, which can account for 10% of the typical number of rebuild requests submitted to typical hardware that does not utilize system 100. In some embodiments, the host I / O that needs to be restored can complete the reconstruction of the bad block at a faster rate. The recovery time can be reduced, and the firmware of the controller 108 can handle more recovery on a row (or multiple rows) during a given period. In some embodiments, no matter how the number of recoverable bad blocks in the stripe, only a single rebuild request is sufficient to restore all recoverable bad blocks. Therefore, a significant reduction in the processing time of the firmware of the controller 108 can be achieved, allowing the CPU to perform other operations.

[0080] The following IEEE standards (including any draft versions of such standards) are hereby incorporated by reference in their entirety and become part of the present disclosure for all purposes: IEEE 802.3, IEEE 802.11x, IEEE 802.11ad, IEEE 802.11ah, IEEE 802.11aj, IEEE 802.16 and 802.16a, and IEEE 802.11ac. In addition, although the present disclosure may refer to aspects of these standards, the present disclosure is in no way limited by these standards.

[0081] Having discussed specific embodiments of the present solution, it may be helpful to describe aspects of the operating environment and associated system components (eg, hardware elements) in conjunction with the methods and systems described herein. Fig. 8A , depicting an embodiment of a network environment. The network may include, or communicate with, one or more storage area networks (SANs), security adapters, or Ethernet converged network adapters (CNAs). In short, the network environment includes a communication system, which includes one or more network devices 806, one or more client devices 802, and network hardware components 892. In some embodiments, the network device 806 may be an access point (AP). In some embodiments, the client device 802 may be a wireless communication device. For example, the client device 802 may include a laptop computer 802, a tablet computer 802, a personal computer 802, a wearable device 802, a vehicle 802 (e.g., a car, a drone, a smart vehicle, a robotic unit, etc.), a video game console 802, a cellular telephone device 802, a smart television 802, an Internet of Things (IoT) device 802, and any other electronic device 802 capable of wireless communication. Reference Figure 8B and 8CDetails of embodiments of client device 802 and network device 806 are described in greater detail. In one embodiment, the network environment may be an ad hoc network environment, an infrastructure wireless network environment, a wired network coupled to a wireless network, a subnet environment, or a combination of the foregoing.

[0082] The network device 806 may be operably coupled to the network hardware 892 via a local area network connection. The network hardware 892, which may include one or more routers, gateways, switches, bridges, modems, system controllers, appliances, etc., may provide a local area network connection for the communication system. Each network device 806 may have an associated antenna or antenna array to communicate with client devices in its area. Client devices may register with a particular network device 806 to receive services from the communication system (e.g., via SU-MIMO or MU-MIMO configuration). For direct connections (i.e., point-to-point communications), some client devices may communicate directly via assigned channels and communication protocols. Some client devices 802 may be mobile or relatively static relative to the network device 806.

[0083] In some embodiments, the network device 806 includes a device or module (including a combination of hardware and software) that enables the connection of the client device 802 to a wired or wireless network. The network device 806 is oriented to wired connections and is also designed to support wireless connections. The configuration and design of the network device 806 implement the communication between the network device 806 and the controller and storage device established by the wired link. In some embodiments, the network device 806 can be connected to a router (e.g., via a wired network) as a standalone device. In other embodiments, the network device 806 can be a component of a router. The network device 806 can provide access to the network to multiple devices. The network device 806 can, for example, be connected to a wired Ethernet connection and use a radio frequency link to provide a wireless connection for other devices 802 to utilize that wired connection. The network device 806 can be constructed and configured to support standards for sending and receiving data using one or more radio frequencies. Those standards and the frequencies they use can be defined by IEEE (e.g., IEEE 802.11 standards). The network device 806 can be configured and used to support public Internet hotspots and on an internal network for extending the Wi-Fi signal range of the network.

[0084] In some embodiments, the network device 806 may be used for an in-home or in-building wireless network (e.g., IEEE 802.11, Bluetooth, ZigBee, any other type of radio frequency based network protocol or variations thereof). Each of the client devices 802 may include a built-in radio or be coupled to a radio. Such client devices 802 and network devices 806 may operate in accordance with various aspects of the present disclosure as presented herein to enhance performance, reduce cost or size, and enhance broadband applications. Each client device 802 may have the ability to act as a client node that seeks access to resources (e.g., data and connections to networked nodes such as servers) via one or more network devices.

[0085] The network connection may include any type or form of network, and may include any of the following: a point-to-point network, a broadcast network, a telecommunications network, a data communications network, or a computer network. The topology of the network may be a bus, a star, or a ring network topology. The network may be any such network topology known to those of ordinary skill in the art and capable of supporting the operations described herein. In some embodiments, different types of data may be transmitted via different protocols. In other embodiments, the same type of data may be transmitted via different protocols.

[0086] The client device 802 and the network device 806 may be deployed as or executed on any type and form of computing device, such as a computer, network device, or appliance capable of communicating over any type and form of network and performing the operations described herein. Figure 8B and 8C A block diagram of a computing device 800 is depicted that can be used to practice embodiments of a client device 802 or a network device 806. Figure 8B and 8C As shown in FIG. 8 , each computing device 800 includes a central processing unit 821 and a main memory or main memory unit 822. Figure 8B As shown in FIG. 8 , computing device 800 may include storage device 828, installation device 816, network interface 818, I / O controller 823, display devices 824a to 824n, keyboard 826, and pointing device 827, such as a mouse. Storage device 828 may include, but is not limited to, an operating system or software. Figure 8C As shown in , each computing device 800 may also include additional optional elements, such as a memory port 803, a bridge 870, one or more input / output (I / O) devices 830a to 830n (generally referred to using reference numeral 830), and a cache memory 840 that communicates with the central processing unit 821.

[0087] "Circuitry" may refer to an interconnected arrangement of electronic components and paths that allow electrical signals to flow within a device, system, or application. In some embodiments, a single-component circuit system may be an electronic component that performs a specific function within an electronic system, such as a resistor, capacitor, or transistor. In some embodiments, multiple components working together in a circuit system may include coordination of various electronic components. In some embodiments, a circuit system may include hardware components, such as integrated circuits, transistors, resistors, capacitors, and connectors, as well as a combination of hardware and software or firmware elements that can operate together to perform various functions. Multiple components may include individual components, such as sensors, microcontrollers, memory modules, communication interfaces, or power management circuits, which are interconnected to form a functional system. For example, a circuit system may include a microcontroller or processor that executes software instructions to control the behavior of hardware components. For example, a circuit system processor may run programs that enable a device or system to perform various tasks such as data processing and communication. Components may not be physically contained within the same device, for example, components may be distributed across different devices connected by wired or wireless interfaces.

[0088] The central processing unit (CPU) 821 is any logic circuitry that responds to and processes instructions fetched from the main memory unit 822. In many embodiments, the central processing unit 821 is provided by a microprocessor unit, such as: a microprocessor unit manufactured by Intel Corporation of Mountain View, California; a microprocessor unit manufactured by International Business Machines of White Plains, New York; or a microprocessor unit manufactured by Advanced Micro Devices of Sunnyvale, California. The computing device 800 may be based on any of these processors or any other processor capable of operating as described herein. The CPU may be a programmable parallel processor.

[0089] Other programmable parallel processors may include graphics processing units (GPUs) and neural processors. A GPU is a programmable parallel processor that can perform complex calculations for graphics rendering and general computing tasks. A GPU consists of processing cores interconnected by a high-bandwidth memory interface and a bus system to achieve efficient parallel processing. The processing cores of a GPU may be equipped with dedicated arithmetic logic units and cache memory, allowing multiple computing threads to be executed simultaneously. In order to optimize the graphics rendering pipeline, a GPU may incorporate the following hardware components: a texture unit and a rasterizer. A GPU may use optimized algorithms and data parallel techniques to accelerate calculations, resulting in superior performance compared to conventional CPUs. A GPU may be programmed using graphics APIs and parallel computing frameworks to achieve scientific simulations, machine learning, and data analysis.

[0090] The main memory unit 822 may be one or more memory chips capable of storing data and allowing access to any storage location by the microprocessor 821, such as any type or variation of static random access memory (SRAM), dynamic random access memory (DRAM), ferroelectric RAM (FRAM), NAND flash or NOR flash, and solid-state drive (SSD). The main memory 822 may be based on any of the above memory chips, or any other available memory chip capable of operating as described herein. Figure 8B In the embodiment shown in FIG. 8 , processor 821 communicates with main memory 822 via system bus 850 (described in more detail below). Figure 8C An embodiment of a computing device 800 is depicted in which the processor communicates directly with the main memory 822 via the memory port 803. For example, in Figure 8C In the embodiment, the main memory 822 may be a DRAM.

[0091] Figure 8C An embodiment is depicted in which the main processor 821 communicates directly with the cache memory 840 via an auxiliary bus (sometimes referred to as a backside bus). In other embodiments, the main processor 821 communicates with the cache memory 840 using a system bus 850. The cache memory 840 typically has a faster response time than the main memory 822 and is provided by, for example, SRAM, BSRAM, or EDRAM. Figure 8C In the embodiment shown in , the processor 821 communicates with various I / O devices 830 via a local system bus 850. Various buses may be used to connect the central processing unit 821 to any of the I / O devices 830, such as a VESA VL bus, an ISA bus, an EISA bus, a Micro Channel Architecture (MCA) bus, a PCI bus, a PCI-X bus, a PCI Express bus, or a NuBus. For embodiments in which the I / O device is a video display 824, the processor 821 may communicate with the display 824 using an Advanced Graphics Port (AGP). Figure 8CAn embodiment of a computer or computer system 800 is depicted in which a main processor 821 can communicate directly with an I / O device 830b, such as via HYPERTRANSPORT, RAPIDIO, or INFINIBAND communication technology. Figure 8C Also depicted is an embodiment in which local buses are mixed with direct communications: processor 821 communicates with I / O device 830a using a local interconnect bus while communicating directly with I / O device 830b.

[0092] There may be a wide variety of I / O devices 830a to 830n in computing device 800. Input devices include keyboards, mice, track pads, track balls, microphones, dials, touch pads, touch screens, and drawing tablets. Output devices include video displays, speakers, inkjet printers, laser printers, projectors, and dye sublimation printers. I / O devices may be controlled by I / O controller 823, such as Figure 8B 800. The I / O controller may control one or more I / O devices, such as a keyboard 826 and a pointing device 827, such as a mouse or an optical pen. In addition, the I / O devices may also provide storage and installation media 816 for the computing device 800. In still other embodiments, the computing device 800 may provide a USB connection (not shown) to receive a handheld USB storage device, such as the USB flash drive line of devices manufactured by s Industry, Inc. of Los Alamitos, California.

[0093] Reference again Figure 8B , the computing device 800 may support any suitable installation device 816, such as a disk drive, CD-ROM drive, CD-R / RW drive, DVD-ROM drive, flash drive, tape drives of various formats, USB devices, hard drives, network interfaces, or any other device suitable for installing software and programs. The computing device 800 may further include a storage device, such as one or more hard drives or redundant arrays of independent disks (storage devices), for storing an operating system and other related software and for storing application software programs (e.g., any program or software 820 for implementing the systems and methods described herein (e.g., software 820 configured or designed for the systems and methods described herein)). In some embodiments, any of the installation devices 816 may be used as a storage device. In some embodiments, the operating system and software may be run from a bootable medium.

[0094] In addition, computing device 800 may include a network interface 818 that interfaces with network 804 through various connections, including, but not limited to, a standard telephone line, a LAN or WAN link (e.g., 802.11, T1, T3, 56 kb, X.25, SNA, DECNET), a broadband connection (e.g., ISDN, Frame Relay, ATM, Gigabit Ethernet, Ethernet over SONET), a wireless connection, or some combination of any or all of the above. The connection may be established using various communication protocols (e.g., TCP / IP, IPX, SPX, NetBIOS, Ethernet, ARCNET, SONET, SDH, Fiber Distributed Data Interface (FDDI), RS232, IEEE 802.11, IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, IEEE 802.11n, IEEE 802.11ac, IEEE802.11ad, CDMA, GSM, WiMax, and direct asynchronous connection). In one embodiment, computing device 800 communicates with other computing devices 800 via any type and form of gateway or tunneling protocol, such as Secure Sockets Layer (SSL) or Transport Layer Security (TLS). Network interface 818 may include a built-in network adapter, a network interface card, a PCMCIA network card, a cardbus network adapter, a wireless network adapter, a USB network adapter, a modem, or any other device suitable for interfacing computing device 800 to any type of network capable of communicating and performing the operations described herein.

[0095] In some embodiments, the computing device 800 may include or be connected to one or more display devices 824a to 824n. Thus, any of the I / O devices 830a to 830n and the I / O controller 823 may include any type or form of suitable hardware, software, or a combination of hardware and software to support, implement, or provide for the connection and use of display devices 824a to 824n by the computing device 800. For example, the computing device 800 may include any type or form of video adapter, video card, driver, and library to interface, communicate, connect, or otherwise use display devices 824a to 824n. In one embodiment, the video adapter may include multiple connectors to interface with the display devices 824a to 824n. In other embodiments, the computing device 800 may include multiple video adapters, each of which is connected to the display devices 824a to 824n. In some embodiments, any portion of the operating system of the computing device 800 may be configured to use multiple displays 824a to 824n. One of ordinary skill in the art will recognize and appreciate the various ways and embodiments in which the computing device 800 may be configured to have one or more display devices 824a - 824n .

[0096] In other embodiments, the I / O device 830 may be a bridge between the system bus 850 and an external communication bus, such as a USB bus, an Apple Desktop bus, an RS-232 serial connection, a SCSI bus, a FireWire bus, a FireWire 800 bus, an Ethernet bus, an AppleTalk bus, a Gigabit Ethernet bus, an Asynchronous Transfer Mode bus, a Fibre Channel bus, a serial Small Computer System Interface bus, a USB connection, or an HDMI bus.

[0097] Figure 8B and 8C A computing device or system 800 of the type depicted in the drawings may operate under the control of an operating system that controls the scheduling of tasks and access to system resources. The computing device 800 may run any operating system, such as any version of the MICROSOFT WINDOWS operating system, different versions of the Unix and Linux operating systems, any version of the MAC OS for Apple computers, any embedded operating system, any real-time operating system, any open source operating system, any proprietary operating system, any operating system for mobile computing devices, or any other operating system capable of running on a computing device and performing the operations described herein. Typical operating systems include, but are not limited to: Android produced by Google Inc.; WINDOWS 7 and 8 produced by Microsoft Corporation of Redmond, Washington; MAC OS produced by Apple Computer of Cupertino, California; WebOS produced by Research In Motion (RIM); OS / 2 produced by International Business Machines Corporation of Armonk, New York; and Linux, a freely available operating system distributed by Caldera Corp. of Salt Lake City, Utah, or any type and form of Unix operating system, etc.

[0098] The computer system 800 may be any networking device, storage device, workstation, phone, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone or other portable telecommunication device, media playback device, gaming system, mobile computing device, or any other type or form of computing, telecommunication or media device capable of communication. The computer system 800 has sufficient processor power and memory capacity to perform the operations described herein.

[0099] In some embodiments, the computing device 800 may have a different processor, operating system, and input device consistent with the device. For example, in one embodiment, the computing device 800 is a smart phone, a mobile device, a tablet computer, or a personal digital assistant. In yet other embodiments, the computing device 800 is an Android-based mobile device, an iPhone smartphone produced by Apple Computer, Inc. of Cupertino, California, or a handheld device or smart phone based on Blackberry or WebOS, such as a device manufactured by Research In Motion Limited. In addition, the computing device 800 may be any workstation, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone, any other computer, or other form of computing or telecommunications device that can communicate and has sufficient processor power and memory capacity to perform the operations described herein. In the context of the systems and methods disclosed herein, the aspects of the operating environment and components described above will become apparent.

[0100] It should be noted that certain paragraphs of the present disclosure may refer to terms (e.g., "first" and "second") related to device signals, data, inputs, channels, etc. for identification or distinction from one another or for other purposes. These terms are not intended to relate entities (e.g., first input and second input) only in time or according to sequence, although in some cases these entities may include such a relationship, nor do these terms limit the number of possible entities (e.g., devices) that may operate within a system or environment.

[0101] It should be understood that the system described above may provide a plurality of any one or each of the components. In addition, the system and method described above may be provided as one or more computer-readable programs or executable instructions, programmable circuits, or digital logic embodied on or in one or more articles of manufacture. The article of manufacture may be a floppy disk, hard disk, CD-ROM, flash memory card, PROM, RAM, ROM, ASIC, or tape. In general, the computer-readable program may be implemented in any programming language (e.g., LISP, PERl, C, C++, C#, PROLOG) or in any bytecode language (e.g., JAVA). The software program or executable instructions may be stored as object code on or in one or more articles of manufacture.

[0102] Although the above written description of the methods and systems enables one of ordinary skill in the art to make and use various embodiments of these methods and systems, one of ordinary skill in the art should understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiments, methods, and examples herein. Therefore, the methods and systems should not be limited by the above embodiments, methods, and examples, but should be limited by all embodiments and methods within the scope and spirit of the present disclosure.

Claims

1. A method comprising: identifying, by one or more processors, the presence of errors in a plurality of data storage units within a range of data storage units of an error bitmap of a redundant array of independent disks RAID; generating, by the one or more processors, a parity RAID request format PRRQ frame, the PRRQ frame identifying the range of data storage units, wherein at least one data storage unit has an error, the range of data storage units being identified at least among the plurality of data storage units; and The PRRQ frame is communicated, by the one or more processors, to a controller, the controller being configured to recover data within the range of data storage units of the plurality of data storage units in response to the PRRQ frame.

2. The method of claim 1, wherein the controller is configured to recover the data within the range of the plurality of data storage units in response to no more than one PRRQ frame.

3. The method according to claim 1, further comprising: The PRRQ frame is generated by the one or more processors to include a first field identifying an offset for identifying a location of a first data storage unit among the plurality of data storage units within the range of data storage units and a second field identifying a number of data storage units within the range of data storage units.

4. The method according to claim 1, wherein: The range of data storage units is in a data segment on a storage device of the RAID. The method of claim 1 , wherein the error is absent in at least one data storage cell within the range of data storage cells. 6 . The method of claim 5 , wherein the error is absent in two or more non-subsequent first data storage units within the range of data storage units between two or more non-subsequent second data storage units.

7. The method of claim 1, wherein the error bitmap of the plurality of data storage units identifies clusters of errors on a single storage device of the RAID. The method of claim 1 , wherein the error is a media error.

9. A circuit system configured to: identifying the presence of errors in a plurality of data storage units within a range of data storage units of an error bitmap of a redundant array of independent disks RAID; generating a parity RAID request format PRRQ frame, the PRRQ frame identifying the range of data storage units, wherein at least one data storage unit has an error, the range of data storage units being identified at least among the plurality of data storage units; and The PRRQ frame is communicated to a controller, the controller being configured to recover data within the range of data storage units of the plurality of data storage units in response to the PRRQ frame.

10. The circuit system of claim 9, wherein the controller is configured to recover the data within the range of the plurality of data storage units in response to no more than one PRRQ frame.

11. The circuit system of claim 9, further configured to: The PRRQ frame is generated to include a first field identifying an offset for identifying a location of a first data storage unit among the plurality of data storage units within the range of data storage units and a second field identifying a number of data storage units within the range of data storage units.

12. The circuit system of claim 9, wherein the range of data storage units is in a data segment on a storage device of the RAID.

13. The circuit system of claim 9, wherein the error is absent in at least one data storage cell within the range of data storage cells. 14 . The circuit system of claim 13 , wherein the error is absent in two or more non-subsequent first data storage cells within the range of data storage cells between two or more non-subsequent second data storage cells.

15. The circuit system of claim 9, wherein the error bitmap of the plurality of data storage cells identifies clusters of errors on a single storage device of the RAID.

16. A system comprising: One or more processors configured to: identifying the presence of errors in a plurality of data storage units within a range of data storage units of an error bitmap of a redundant array of independent disks RAID; generating a parity RAID request format PRRQ frame, the PRRQ frame identifying the range of data storage units, wherein at least one data storage unit has an error, the range of data storage units being identified at least among the plurality of data storage units; and The PRRQ frame is communicated to a controller, the controller being configured to recover data within the range of data storage units of the plurality of data storage units in response to the PRRQ frame.

17. The system of claim 16, wherein the controller is configured to recover the data within the range of the plurality of data storage units in response to no more than one PRRQ frame.

18. The system of claim 16, wherein the one or more processors are further configured to: The PRRQ frame is generated to include a first field identifying an offset for identifying a location of a first data storage unit among the plurality of data storage units within the range of data storage units and a second field identifying a number of data storage units within the range of data storage units.

19. The system of claim 16, wherein the range of data storage units is in a data segment on a storage device of the RAID.

20. The system of claim 16, wherein the error is absent in at least one data storage unit within the range of data storage units.

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