Memory device, memory system and operating method thereof

Abstract

An operating method of a memory system is provided. The method can comprise the following steps of: respectively reading target data stored in a target memory page by using a plurality of reading voltages; sequentially storing read data corresponding to the target data in a plurality of latches including a first latch and a second latch, respectively; performing a first error correction code (ECC) decoding operation on the first read data stored in the first latch; and when the first ECC decoding operation fails, performing a second ECC decoding operation on the second read data stored in the second latch.

Description

[0001] This application is a divisional application of the Chinese patent application with application number 201811534099.8 filed on December 14, 2018, entitled “Memory device, memory system and operating method thereof”. Technical Field

[0002] Various exemplary embodiments of the present invention generally relate to a memory device and a memory system using the same, and in particular, relate to a memory device and a memory system capable of improving and more efficiently reading target data corresponding to a host read request and an operating method thereof. Background Art

[0003] The paradigm of computing environment is developing towards ubiquitous computing, which provides people or users with the ability to use their or generally provided computing systems at any time and anywhere. In the era of ubiquitous computing, the demand for portable electronic devices such as mobile phones, digital cameras, and laptop computers is growing rapidly. The electronic devices generally include a memory system, wherein the memory system uses a memory device as a data storage device. The data storage device can be used as a primary memory or an auxiliary memory of the portable electronic device.

[0004] Because the data storage device using the memory device does not have a mechanical drive unit (e.g., a mechanical arm with a read / write head) compared to a hard disk device, the data storage device can have excellent stability and durability. Moreover, the data storage device can have a faster data access rate and low power consumption than a hard disk device. Non-limiting examples of data storage devices with such advantages include universal serial bus (USB) memory devices, memory cards of different interfaces, solid state drives (SSDs), etc. Summary of the invention

[0005] Various embodiments of the present invention relate to a memory device and a memory system using the memory device, the memory device being capable of performing improved and more efficient reading of target data corresponding to a host request. Various embodiments of the present invention relate to a method of operating a memory system for improving and more efficiently reading target data corresponding to a host read request.

[0006] According to an embodiment of the present disclosure, an operating method of a memory system may include: using multiple read voltages to respectively read target data stored in a target memory page; sequentially storing read data corresponding to the target data in a plurality of latches including a first latch and a second latch, respectively; performing a first error correction code (ECC) decoding operation on the first read data stored in the first latch; and when the first ECC decoding operation fails, performing a second ECC decoding operation on the second read data stored in the second latch.

[0007] According to an embodiment of the present disclosure, a memory system may include: a memory device, comprising: a read / write circuit, including multiple latches in a page buffer; and a control circuit, which is suitable for controlling the read / write circuit to use multiple read voltages to respectively read target data stored in a target memory page, and sequentially store read data corresponding to the target data in multiple latches including a first latch and a second latch, respectively; and a controller, which is suitable for performing a first ECC decoding operation on first read data stored in the first latch; and when the first ECC decoding operation fails, performing a second ECC decoding operation on second read data stored in the second latch.

[0008] According to an embodiment of the present disclosure, a memory device may include: a read / write circuit, including multiple latches in a page buffer; and a control circuit, which is suitable for controlling the read / write circuit to use multiple read voltages to read target data stored in a target memory page respectively, and sequentially store the read data corresponding to the target data in multiple latches including a first latch and a second latch respectively.

[0009] According to an embodiment of the present disclosure, a memory system may include: a memory device; and a controller, wherein the memory device includes: a memory cell array including a target area for storing target data; an area buffer including, wherein a plurality of latches include a first latch and a second latch; and a control circuit adapted to: in response to a read command from the controller, sequentially read the target data using a plurality of read voltages; and sequentially store read data corresponding to the target data in the first latch and the second latch, wherein the controller loads the first read data stored in the first latch and performs a first decoding operation on the first read data, and wherein when the first decoding operation fails, the controller loads the second read data stored in the second latch and performs a second decoding operation on the second read data. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] These and other aspects and advantages of the present invention will become apparent to those skilled in the art from the following detailed description. This description is made herein with reference to the accompanying drawings, in which like reference numerals refer to like parts in the several views, wherein:

[0011] Figure 1 is a block diagram illustrating a data processing system including a memory system operably coupled to a host according to an embodiment of the present disclosure;

[0012] Figure 2 It is shown Figure 1A schematic diagram of an exemplary configuration of a memory device employed in the memory system shown;

[0013] Figure 3 Yes Description Figure 2 A circuit diagram of an exemplary configuration of a memory cell array of a memory block of a memory device shown in;

[0014] Figure 4 It is shown Figure 2 A schematic diagram of an exemplary three-dimensional structure of a memory device shown in;

[0015] Figure 5 is a block diagram illustrating a memory system according to an embodiment of the present disclosure;

[0016] Figure 6 is a flowchart illustrating an operating method of a memory system according to an embodiment of the present disclosure; and

[0017] Figures 7 to 15 is a diagram schematically showing an application example of a data processing system according to various embodiments of the present invention. DETAILED DESCRIPTION

[0018] The following describes in more detail various examples of the disclosure of the present invention with reference to the accompanying drawings. The present disclosure may be implemented in different other embodiments, forms and variations thereof, and should not be construed as being limited to the embodiments set forth herein. On the contrary, the described embodiments are provided so that the present invention will be complete and comprehensive and fully convey the present disclosure to those skilled in the art to which the present invention belongs or to which it relates. Throughout the present disclosure, the same figure numerals represent the same parts in the various figures and examples of the present disclosure. It is noted that references to "embodiments" do not necessarily relate to only one embodiment, and different references to "embodiments" are not necessarily the same embodiment.

[0019] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the spirit and scope of the present invention, the first element described below may also be referred to as the second element or the third element.

[0020] The accompanying drawings are not necessarily drawn to scale, and in some cases, the proportions may have been exaggerated in order to clearly illustrate the features of the embodiments. When an element is referred to as being connected or coupled to another element, it should be understood that the former may be directly connected or coupled to the latter, or the former may be electrically connected or coupled to the latter through an intermediate element therebetween.

[0021] It will be further understood that when an element is referred to as being “connected to” or “coupled to” another element, it can be directly on, connected to, or coupled to the other element, or one or more intervening elements may be present. Additionally, it will be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or one or more intervening elements may also be present.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0023] As used herein, the singular forms are intended to include the plural forms as well, and vice versa, unless the context clearly indicates otherwise.

[0024] It will be further understood that when the terms "include", "comprising", "including" and "comprising" are used in this specification, they specify the presence of the stated elements and do not exclude the presence or addition of one or more other elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0025] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meanings as those generally understood by ordinary technicians in the field to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be understood to have meanings consistent with their meanings in the context of this disclosure and the relevant field and will not be interpreted in an idealized or overly formal sense, unless so clearly defined herein.

[0026] In the following description, in order to provide a thorough understanding of the present invention, many specific details are set forth. The present invention can be implemented without some or all of these specific details. In other cases, in order to avoid unnecessarily obscuring the present invention, known process structures and / or processes are not described in detail.

[0027] It is also noted that in some cases, features or elements described in connection with one embodiment may be used alone or in combination with other features or elements of another embodiment, unless explicitly stated otherwise, as would be apparent to one skilled in the relevant art.

[0028] Figure 1 is a block diagram illustrating a data processing system 100 according to an embodiment of the present invention.

[0029] Reference Figure 1 , data processing system 100 may include a host 102 operably coupled to a memory system 110 .

[0030] For example, the host 102 may include, for example, portable electronic devices such as mobile phones, MP3 players, and laptop computers, or non-portable electronic devices such as desktop computers, game consoles, televisions (TVs), and projectors.

[0031] The memory system 110 may operate or perform a specific function or operation in response to a request from the host 102, and in particular, may store data to be accessed by the host 102. The memory system 110 may be used as a main memory system or an auxiliary memory system of the host 102. According to the protocol of the host interface, the memory system 110 may be implemented using any of various types of storage devices that may be electrically coupled to the host 102. Non-limiting examples of suitable storage devices include solid state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), reduced size MMCs (RS-MMCs) and micro MMCs, secure digital (SD) cards, mini SDs and micro SDs, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, standard flash memory (CF) cards, smart media (SM) cards, memory sticks, and the like.

[0032] The storage device of the memory system 110 may be implemented using volatile memory devices such as, for example, dynamic random access memory (DRAM) and static RAM (SRAM), and / or the storage device of the memory system 110 may be implemented using non-volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric RAM (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM or ReRAM), and flash memory.

[0033] The memory system 110 may include a controller 130 and a memory device 150. The memory device 150 may store data to be accessed by the host 102, and the controller 130 may control the data to be stored in the memory device 150.

[0034] The controller 130 and the memory device 150 may be integrated into a single semiconductor device, and the single semiconductor device may be included in various types of memory systems as exemplified above.

[0035] The memory system 110 may be configured as, for example, a part of a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional (3D) television, a smart TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configuring a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a telematics network, a radio frequency identification (RFID) device, or one of various components configuring a computing system.

[0036] The memory device 150 may be a nonvolatile memory device and may retain data stored therein even when power is not supplied. The memory device 150 may store data provided from the host 102 through a write operation and provide the data stored therein to the host 102 through a read operation. The memory device 150 may include a plurality of memory blocks 152 to 156, each of which may include a plurality of pages. Each page may include a plurality of memory cells electrically coupled to a plurality of word lines (WLs).

[0037] The controller 130 may control all operations such as a read operation, a write operation, a program operation, and an erase operation of the memory device 150. For example, the controller 130 may control the memory device 150 in response to a request from the host 102. The controller 130 may provide the host 102 with data read from the memory device 150, and / or may store data provided by the host 102 in the memory device 150.

[0038] Controller 130 may include a host interface (I / F) 132, a processor 134, an error correction code (ECC) unit 138, a power management unit (PMU) 140, a memory interface (I / F) 142, and a memory 144, all operably coupled via an internal bus.

[0039] The host interface 132 may process commands and data provided from the host 102, and may communicate with the host 102 through at least one of various interface protocols such as Universal Serial Bus (USB), MultiMediaCard (MMC), Peripheral Component Interconnect-Express (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0040] The ECC unit 138 may detect and correct errors in data read from the memory device 150 during a read operation. When the number of error bits is greater than or equal to a threshold number of correctable error bits, the ECC unit 138 may not correct the error bits but may output an error correction failure signal indicating a failure to correct the error bits.

[0041] The ECC unit 138 may perform error correction operations based on coded modulation such as low-density parity check (LDPC) codes, Bose-Chaudhri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis coded modulation (TCM), and block coded modulation (BCM), etc. The ECC unit 138 may include all or some of the circuits, modules, systems, or devices for performing error correction operations based on at least one of the above codes.

[0042] The PMU 140 may provide and manage power to the controller 130 .

[0043] The memory interface 142 may be used as an interface for processing commands and data transmitted between the controller 130 and the memory device 150 to allow the controller 130 to control the memory device 150 in response to a request sent by the host 102. In the case where the memory device 150 is a flash memory, particularly when the memory device 150 is a NAND flash memory, the memory interface 142 may generate a control signal for the memory device 150 under the control of the processor 134, and may process data input to or output from the memory device 150.

[0044] The memory 144 may be used as a working memory of the memory system 110 and the controller 130, and may store temporary data or transaction data for operating or driving the memory system 110 and the controller 130. The controller 130 may control the memory device 150 in response to a request from the host 102. The controller 130 may transfer data read from the memory device 150 to the host 102, and store data input through the host 102 in the memory device 150. The memory 144 may be used to store data required for the controller 130 and the memory device 150 to perform these operations.

[0045] The memory 144 may be implemented using a volatile memory. The memory 144 may be implemented using a static random access memory (SRAM) or a dynamic random access memory (DRAM). Figure 1 The memory 144 is illustrated as being provided inside the controller 130, but the present disclosure is not limited thereto. That is, the memory 144 may be located inside or outside the controller 130. For example, the memory 144 may be implemented by an external volatile memory having a memory interface that transfers data and / or signals transferred between the memory 144 and the controller 130.

[0046] The processor 134 may control the overall operation of the memory system 110. The processor 134 may drive or execute firmware to control the overall operation of the memory system 110. The firmware may be referred to as a flash translation layer (FTL).

[0047] The FTL may perform an operation as an interface between the host 102 and the memory device 150. The host 102 may transmit requests for write operations and read operations to the memory device 150 through the FTL.

[0048] The FTL can manage operations such as address mapping, garbage collection, and wear leveling. In particular, the FTL can store mapping data. Therefore, the controller 130 can map the logical address provided from the host 102 to the physical address of the memory device 150 through the mapping data. Due to the address mapping operation, the memory device 150 can perform operations like a normal device. In addition, through the address mapping operation based on the mapping data, when the controller 130 updates the data of a specific page, due to the characteristics of the flash memory device, the controller 130 can program the new data to another empty page and can invalidate the old data of the specific page. Further, the controller 130 can store the mapping data of the new data in the FTL.

[0049] The processor 134 may be implemented using a microprocessor or a central processing unit (CPU). The memory system 110 may include one or more processors 134 .

[0050] A management unit (not shown) may be included in the processor 134. The management unit may perform bad block management of the memory device 150. The management unit may find bad memory blocks contained in the memory device 150 that do not meet the requirements for further use, and perform bad block management on the bad memory blocks. When the memory device 150 is a flash memory such as a NAND flash memory, due to the characteristics of the NAND logic function, a programming failure may occur during a write operation, for example, during a programming operation. During the bad block management, data of a memory block or a bad memory block that has failed programming may be programmed into a new memory block. Bad blocks may seriously degrade the utilization efficiency of the memory device 150 having a 3D stacking structure and the reliability of the memory system 110, and therefore reliable bad block management is required.

[0051] Figure 2 is a schematic diagram showing the memory device 150 .

[0052] Reference Figure 2 , the memory device 150 may include a plurality of memory blocks BLOCK0 to BLOCKN-1, and each of the blocks BLOCK0 to BLOCKN-1 may include a plurality of pages, for example, 2M pages, and the number of pages may vary according to the circuit design. According to the number of bits that can be stored or expressed in each memory cell, the memory device 150 may include a plurality of memory blocks, such as a single-level cell (SLC) memory block and a multi-level cell (MLC) memory block. The SLC memory block may include a plurality of pages implemented using memory cells each capable of storing 1 bit of data. The MLC memory block may include a plurality of pages implemented using memory cells each capable of storing, for example, two or more bits of data. An MLC memory block including a plurality of pages implemented using memory cells each capable of storing 3 bits of data may be defined as a triple-level cell (TLC) memory block.

[0053] Figure 3 is a circuit diagram showing a memory block 330 in the memory device 150 .

[0054] Reference Figure 3 , the memory block 330 may correspond to any one of the plurality of memory blocks 152 to 156 included in the memory device 150 of the memory system 110 .

[0055] Reference Figure 3, the memory block 330 of the memory device 150 may include a plurality of cell strings 340 electrically connected to the bit lines BL0 to BLm-1, respectively. Each column of the cell string 340 may include at least one drain select transistor DST and at least one source select transistor SST. A plurality of memory cells or a plurality of memory cell transistors MC0 to MCn-1 may be electrically connected in series between the select transistors DST and SST. The individual memory cells MC0 to MCn-1 may be configured by a single-level cell (SLC) each of which may store 1 bit of information or by a multi-level cell (MLC) each of which may store multiple bits of data information. The strings 340 may be electrically connected to the corresponding bit lines BL0 to BLm-1, respectively. For reference, in Figure 3 In the figure, “DSL” denotes a drain select line, “SSL” denotes a source select line, and “CSL” denotes a common source line.

[0056] Although as an example, Figure 3 It is shown that the memory block 330 is composed of NAND flash memory cells, but it is noted that the memory block 330 of the memory device 150 according to the present embodiment is not limited to NAND flash memory. The memory block 330 can be implemented by a NOR flash memory, a hybrid flash memory in which at least two memory cells are combined, or a 1-NAND flash memory in which a controller is built into a memory chip. The operating characteristics of the semiconductor device can be applied not only to a flash memory device in which a charge storage layer is configured by a conductive floating gate, but also to a charge capture flash memory (CTF) in which a charge storage layer is configured by a dielectric layer.

[0057] The power supply circuit 310 of the memory device 150 may provide word line voltages such as a program voltage, a read voltage, and a pass voltage to be provided to each word line according to an operation mode and a voltage to be provided to, for example, a bulk of a well region in which a memory cell is formed. The power supply circuit 310 may perform a voltage generation operation under the control of a control circuit (not shown). The power supply circuit 310 may generate a plurality of variable read voltages to generate a plurality of read data, select one of the memory blocks or sectors of the memory cell array under the control of the control circuit, select one of the word lines of the selected memory block, and provide the word line voltage to the selected word line and unselected word lines.

[0058] The read and write (read / write) circuit 320 of the memory device 150 may be controlled by a control circuit and may be used as a sense amplifier or a write driver according to an operation mode. During a verification operation or a normal read operation, the read / write circuit 320 may be used as a sense amplifier for reading data from a memory cell array. During a programming operation, the read / write circuit 320 may be used as a write driver for driving a bit line according to data to be stored in the memory cell array. During a programming operation, the read / write circuit 320 may receive data to be stored in the memory cell array from a buffer (not shown) and drive the bit line according to the received data. The read / write circuit 320 may include a plurality of regional buffers 322 to 326 corresponding to columns (or bit lines) or column pairs (or bit line pairs), respectively, and each of the regional buffers 322 to 326 may include a plurality of latches (not shown).

[0059] Figure 4 is a schematic diagram showing a 3D structure of the memory device 150 .

[0060] Although Figure 4 Although a 3D structure is shown, the memory device 150 may be implemented as a two-dimensional (2D) or three-dimensional (3D) memory device. Figure 4 As shown, the memory device 150 may be implemented as a nonvolatile memory device having a 3D stacked structure. When the memory device 150 has a 3D structure, the memory device 150 may include a plurality of memory blocks BLK0 to BLKN-1, each of which has a 3D structure (or a vertical structure).

[0061] Figure 5 A memory system 110 is shown in accordance with an embodiment of the present invention.

[0062] Reference Figure 5 , the memory system 110 may include a controller 130 and a memory device 150. The memory device 150 may include a read and write (read / write) circuit 320, a memory cell array 330, a control circuit 510, and a data input / output (I / O) circuit 530. In operation, the controller 130 may provide data DATA, a command CMD, and an address ADDR to the memory device 150. The controller 130 may also receive data from the memory device 150 to transmit the data to the host 102 (see Figure 1 ). Data DATA, commands CMD and addresses ADDR can be transmitted through the same or different I / O buses.

[0063] Hereinafter, an operation method according to an embodiment is described. Figure 1The host 102 may send a read command for the target data to the memory system 110. The controller 130 may receive a read command for reading the target data and address information corresponding to the target data from the host 102. The controller 130 may control the memory device 150 to read the target data based on the received read command and address information.

[0064] For example, the control circuit 510 of the memory device may receive a read command and address information for target data from the controller 130. The control circuit 510 may control the power supply circuit 310 and the read / write circuit 320 (see Figure 3 and 5 ) to read the target data according to the received read command and address information. Figure 5 , but the power supply circuit 310 may apply an initial read voltage to the word line and the bit line based on the received address information to read the target data from the memory cell storing the target data. The read / write circuit 320 may read the target data using the initial read voltage applied from the power supply circuit 310 based on the read command and the address information. The read / write circuit 320 may store the read target data (hereinafter referred to as read data) in a page buffer included in the read / write circuit 320. Although in the described embodiment, the read / write circuit 320 includes a plurality of page buffers, the present invention is not limited thereto. Generally, the read / write circuit 320 may include a plurality of memory area buffers corresponding to a plurality of memory areas. The page buffer may include a plurality of internal latches. The read / write circuit 320 may store the read data in the internal latch of the page buffer in the read / write circuit 320. Then, the data I / O circuit 530 may output the read data stored in the internal latch to the controller 130.

[0065] The controller 130 may perform an error correction code (ECC) decoding operation on the read data output from the memory device 150. Specifically, although not in Figure 5 However, Figure 1The ECC unit 138 may perform an ECC decoding operation on the read data. At this time, the controller 130 may determine whether the read operation on the target data has been successfully performed based on the read data decoded by the ECC (hereinafter referred to as the decoded data). When the decoded data meets the preset success condition, for example, when the number of error bits of the ECC decoding operation is less than the preset number of error bits, the controller 130 may determine that the read operation on the target data has been successfully performed. When the decoded data does not meet the preset success condition, for example, when the number of error bits of the ECC decoding operation is greater than or equal to the preset number of error bits, the controller 130 may determine that the read operation on the target data has failed. Then, the controller 130 may change the read voltage and control the memory device 150 to re-read the target data based on the changed read voltage.

[0066] Specifically, the control circuit 510 may receive a command and address information for re-reading target data for which a read operation has failed, from the controller 130 .

[0067] In performing a re-read operation, the control circuit 510 may control the power supply circuit 310 to change the initial read voltage to a read voltage different from the initial read voltage. For example, the control circuit 510 may select the read voltage based on a read voltage table. The read voltage table may be stored in the control circuit 510. A plurality of read voltages may be stored in the read voltage table. The plurality of read voltages stored in the read voltage table may have a priority. For example, in various embodiments, the first to sixth read voltages may be stored in the read voltage table according to their priority. The control circuit 510 may control the power supply circuit 310 to sequentially apply the first to sixth read voltages to the memory cell having the address corresponding to the target data based on the priority of the first to sixth read voltages. Therefore, the power supply circuit 310 may sequentially apply the first to sixth read voltages to the word line and the bit line corresponding to the target data.

[0068] The read / write circuit 320 can sequentially read the target data by using the first to sixth read voltages applied sequentially, and store the read data in each latch. For example, when three latches are included in each of the page buffers included in the read / write circuit 320, the read / write circuit 320 can store the first read data in the first latch, the second read data in the second latch, and the third read data in the third latch. The first read data is obtained by reading the target data using the first read voltage. The second read data is obtained by reading the target data using the second read voltage. The third read data is obtained by reading the target data using the third read voltage. Then, when the first read data stored in the first latch is output to the controller 130 through the data I / O circuit 530, the read / write circuit 320 can store the fourth read data in the first latch. The fourth read data is obtained by reading the target data using the fourth read voltage. Based on the same principle, the fifth read data and the sixth read data can be stored in the second latch and the third latch, respectively. The operation of reading the read data and storing the read data in the respective latches of the corresponding page buffer may be performed regardless of the ECC decoding operation performed by the controller 130. That is, while the controller 130 performs the ECC decoding operation on the first read data, the read / write circuit 320 may store the fourth read data in the first latch.

[0069] In another example, the control circuit 510 may not use a read voltage table. For example, the control circuit 510 may sequentially change the read voltage in ascending or descending order, and control the power supply circuit 310 to apply multiple read voltages to addresses corresponding to target data. That is, the control circuit 510 may control the power supply circuit 310 to apply multiple voltages with a constant difference between them, that is, the read voltage table stored in the control circuit 510 is not required. As described above, the read / write circuit 320 can store the read data obtained by the multiple voltages in each latch.

[0070] The controller 130 may load the first read data stored in the first latch through the data I / O circuit 530. Then, the controller 130 may perform an ECC decoding operation on the loaded first read data and determine whether the first decoded data satisfies a preset success condition.

[0071] When the first decoded data satisfies the preset success condition, the controller 130 may end the read operation on the target data and output the first decoded data to the host 102. Then, the controller 130 may control the memory device 150 to perform a discharge operation on the target page having the stored target data so as to perform the next read operation. Specifically, the controller 130 may transmit a discharge command to the memory device 150, and the control circuit 510 may perform a discharge operation on the target page corresponding to the discharge command. The controller 130 may control the memory device 150 to set the first read voltage as a new read reference voltage.

[0072] When the first decoded data does not meet the preset success condition, the controller 130 may determine whether to reload the read data based on the preset number of times the ECC decoding operation is repeated (hereinafter referred to as the ECC decoding repetition number). For example, when the ECC decoding repetition number is set to 3 and the ECC decoding operation for the same target data has been performed three times, the controller 130 may not perform another read operation on the target data, but may determine that the target data is uncorrectable (also referred to herein as ECC uncorrectable data or simply uncorrectable ECC (UECC)). On the other hand, when the number of times the ECC decoding operation is repeated does not reach the ECC decoding repetition number, the controller 130 may load the read data from another latch instead of loading the read data from the latch that has loaded the target data, and perform the ECC decoding operation again.

[0073] Unlike the above example, when the number of times the ECC decoding operation is repeated reaches the ECC decoding repetition number, but the plurality of voltages written in the read voltage table are all used, the controller 130 may not perform a read operation on the target data, but determine that the target data is UECC. Then, the controller 130 may control the memory device 150 to perform a discharge operation on the target memory area, such as, for example, a page.

[0074] The read operation according to the present embodiment has been described based on the read operation performed after the initial read operation of reading the target data using the initial voltage fails. However, this is only an example, and the present embodiment is not limited thereto. In the present embodiment, after controlling the memory device 150 to read the target data using the initial read voltage, the controller 130 may control the memory device 150 to read the target data using a plurality of read voltages written in the read voltage table. Different from the above configuration, the controller 130 may control the memory device 150 to directly read the target data using a plurality of read voltages written in the read voltage table without using the initial read voltage.

[0075] Figure 6 FIG. 2 is a diagram showing a memory system according to an embodiment, for example Figure 5Flow chart of an operation method of the memory system 110. In the following, it is assumed that the initial read operation of the target data has failed, and the read operation of the target data is performed again. In addition, it is assumed that the read voltage table is stored in Figure 5 In the control circuit 510.

[0076] In step S601 , i latches storing read data and initial values ​​of j read voltages written in a read voltage table may be set.

[0077] In step S603, the control circuit 510 may control the power supply circuit 310 to apply the jth read voltage based on the read voltage table. The read / write circuit 320 may read the target data based on the applied jth read voltage.

[0078] In step S605 , the read / write circuit 320 may store the i-th read data in the i-th latch.

[0079] In step S607 , the control circuit 510 may determine whether the i-th latch is a latch having a last number in the page buffer corresponding to the target page having the stored target data.

[0080] When the i-th latch is not the latch with the last number in the page buffer (step S607 is “No”), in step S609, the values ​​of i and j may be added with “1”. Then, the control circuit 510 may perform steps S603 to S605 based on the values ​​of i and j in step S609.

[0081] When the i-th latch is the latch with the last number in the page buffer (“Yes” in step S607), in step S611, the value of i may be set to “1”, and the value of j may be set to a value obtained by adding the previous value of j to “1”. Then, the control circuit 510 may perform steps S603 to S605 based on the values ​​of i and j in step S611.

[0082] In step S613 , the controller 130 may load the read data stored in the i-th latch through the data I / O circuit 530 regardless of whether the operations of steps S607 to S611 are performed in the memory device 150 .

[0083] In step S615 , the controller 130 may perform an ECC decoding operation on the loaded data.

[0084] In step S617, the controller 130 may determine whether the ECC decoding operation on the decoded data satisfies a preset success condition. In other words, the controller 130 may determine whether the ECC decoding operation is successful.

[0085] When the ECC decoding operation satisfies the preset success condition ("Yes" in step S617), in step S619, the controller 130 may output the decoded data to the host 102. Although not shown, the controller 130 may control the memory device 150 to perform a discharge operation on the target page having the stored target data so as to perform the next read operation. In addition, the controller 130 may control the memory device 150 to set the read voltage to a new read reference voltage. The read voltage has been used when reading the read data corresponding to the decoded data.

[0086] When the ECC decoding operation does not meet the preset success condition (step S617 is "No"), in step S621, the controller 130 can determine whether to reload the read data based on the preset ECC decoding repetition number. The controller 130 can determine whether to reload the read data by comparing the number of times the current ECC decoding operation is repeated with the preset ECC decoding repetition number.

[0087] When the number of times the ECC decoding operation is repeated is greater than or equal to the preset ECC decoding repetition number (“Yes” in step S621 ), the controller 130 may determine that the target data is an uncorrectable ECC (UECC) in step S623 .

[0088] When the number of times the ECC decoding operation is repeated is less than the preset ECC decoding repetition number (step S621 is "No"), in step S625, the controller 130 may determine whether the i-th latch is a latch with a last number in the page buffer corresponding to the target page having the stored target data. In other words, the controller 130 may determine whether i is the last number.

[0089] When the i-th latch is the latch with the last number in the page buffer (“Yes” in step S625 ), the value of i may be set to “1” in step S627 . Then, the controller 130 may perform steps S613 to S617 based on the value of i in step S627 .

[0090] When the i-th latch is not the latch with the last number in the page buffer (step S625 is "No"), in step S629, the value of i may be set to a value obtained by adding "1" to the previous value of i. Then, the controller 130 may perform steps S613 to S617 based on the value of i in step S629.

[0091] As described above, the memory system 110 according to the present embodiment can efficiently perform a read operation.

[0092] In the following, reference will be made to Figures 7 to 15 The detailed description may include the above by reference Figures 1 to 6 The described memory device 150 and the memory system 110 of the controller 130 constitute a data processing system and an electronic device.

[0093] Figures 7 to 15 is a schematic diagram showing the Figures 1 to 6 Schematic diagram of an example of application of a data processing system.

[0094] Figure 7 is a diagram schematically illustrating an example of a data processing system including a memory system according to an embodiment. Figure 7 A memory card system including a memory system according to an embodiment is schematically shown.

[0095] Reference Figure 7 , the memory card system 6100 may include a memory controller 6120 , a memory device 6130 , and a connector 6110 .

[0096] More specifically, the memory controller 6120 may be connected to the memory device 6130 and access the memory device 6130. The memory device 6130 may be implemented by a volatile memory (NVM). As an example and not a limitation, the memory controller 6120 may be configured to control a read operation, a write operation, an erase operation, and a background operation for the memory device 6130. The memory controller 6120 may be configured to provide an interface between the memory device 6130 and a host (not shown), and / or drive firmware to control the memory device 6130. That is, the memory controller 6120 may correspond to the reference Figures 1 to 6 The controller 130 in the memory system 110 described above, and the memory device 6130 may correspond to the reference Figures 1 to 6 The memory device 150.

[0097] Therefore, if Figure 1 As shown, the memory controller 6120 may include a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction unit. The memory controller 6120 may further include Figure 1 The components described.

[0098] The memory controller 6120 can communicate with, for example, Figure 1 For example, as shown in FIG. Figure 1As described, the memory controller 6120 can communicate with external devices through one or more of the following various communication protocols: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (EDSI), Integrated Drive Circuit (IDE), FireWire, Universal Flash Memory (UFS), Wireless Fidelity (WI-FI or WIFI) WIFI and Bluetooth. Therefore, the memory system and data processing system according to the present embodiment can be applied to wired and / or wireless electronic devices, especially mobile electronic devices.

[0099] The memory device 6130 may be implemented by a volatile memory. For example, the memory device 6130 may be implemented by various nonvolatile memory devices such as erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin torque transfer magnetic RAM (STT-MRAM). The memory device 6130 may include a memory device such as a memory device 6130 shown in FIG. Figure 1 Multiple dies in the memory device 150.

[0100] The memory controller 6120 and the memory device 6130 may be integrated into a single semiconductor device. For example, the memory controller 6120 and the memory device 6130 may constitute a solid state drive (SSD) by being integrated into a single semiconductor device. Moreover, the memory controller 6120 and the memory device 6130 may construct memory cards such as PC cards (e.g., Personal Computer Memory Card International Association (PCMCIA)), standard flash memory (CF) cards, smart media cards (e.g., SM and SMC), memory sticks, multimedia cards (e.g., MMC, RS-MMC, micro MMC, and eMMC), secure digital (SD) cards (e.g., SD, mini SD, micro SD, and SDHC), and universal flash memory (UFS).

[0101] Figure 8 6200 is a diagram schematically illustrating another example of a data processing system including a memory system 6200 according to an embodiment.

[0102] Reference Figure 8 , the data processing system 6200 may include a memory device 6230 having one or more non-volatile memories (NVMs) and a memory controller 6220 for controlling the memory device 6230. The data processing system 6200 may be used as a reference Figure 1The storage medium described above, such as a memory card (CF, SD, micro SD, etc.) or a USB device. The memory device 6230 may correspond to Figures 1 to 6 The memory device 150 in the memory system 110 shown, and the memory controller 6220 may correspond to Figures 1 to 6 The controller 130 in the memory system 110 is shown.

[0103] The memory controller 6220 can control a read operation, a write operation, or an erase operation on the memory device 6230 in response to a request from the host 6210, and the memory controller 6220 may include one or more central processing units (CPUs) 6221, a buffer memory such as a random access memory (RAM) 6222, an error correction code (ECC) circuit 6223, a host interface 6224, and a memory interface such as an NVM interface 6225.

[0104] The CPU 6221 may control operations on the memory device 6230, such as a read operation, a write operation, a file system management operation, and a bad page management operation. The RAM 6222 may operate according to the control of the CPU 6221 and be used as a working memory, a buffer memory, or a cache memory. When the RAM 6222 is used as a working memory, data processed by the CPU 6221 may be temporarily stored in the RAM 6222. When the RAM 6222 is used as a buffer memory, the RAM 6222 may be used to buffer data transmitted from the host 6210 to the memory device 6230 or data transmitted from the memory device 6230 to the host 6210. When the RAM 6222 is used as a cache memory, the RAM 6222 may assist the memory device 6230 to operate at a high speed.

[0105] The ECC circuit 6223 may correspond to Figure 1 The ECC unit 138 of the controller 130 is shown. Figure 1 As described above, the ECC circuit 6223 may generate an error correction code (ECC) for correcting a fail bit or an error bit of the data provided from the memory device 6230. The ECC circuit 6223 may perform error correction encoding on the data provided to the memory device 6230, thereby forming data with a parity bit. The parity bit may be stored in the memory device 6230. The ECC circuit 6223 may perform error correction decoding on the data output from the memory device 6230. In this case, the ECC circuit 6223 may use the parity bit to correct the error. For example, as shown in FIG. Figure 1As described, the ECC circuit 6223 can correct errors using low-density parity-check (LDPC) codes, Bose-Chadhouli-Houchingham (BCH) codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), or coded modulation such as trellis coded modulation (TCM) or block coded modulation (BCM).

[0106] The memory controller 6220 may transmit data or signals to and / or receive data or signals from the host 6210 through the host interface 6224, and transmit data or signals to and / or receive data or signals from the memory device 6230 through the NVM interface 6225. The host interface 6224 may be connected to the host 6210 through a parallel advanced technology attachment (PATA) bus, a serial advanced technology attachment (SATA) bus, a small computing system interface (SCSI), a universal serial bus (USB), a high-speed peripheral component interconnect (PCIe), or a NAND interface. The memory controller 6220 may have a wireless communication function using a mobile communication protocol such as wireless fidelity (WiFi) or long-term evolution (LTE). The memory controller 6220 may be connected to an external device, such as the host 6210 or another external device, and then transmit data to and / or receive data from the external device. When the memory controller 6220 is configured to communicate with an external device through one or more of various communication protocols, the memory system and the data processing system according to the present embodiment may be applied to wired and / or wireless electronic devices or particularly mobile electronic devices.

[0107] Fig. 9 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment. Fig. 9 A solid state drive (SSD) to which the memory system according to the embodiment is applied is schematically shown.

[0108] Reference Fig. 9 , the SSD 6300 may include a controller 6320 and a memory device 6340 including a plurality of non-volatile memories (NVMs). The controller 6320 may correspond to Figure 1 The controller 130 in the memory system 110 and the memory device 6340 may correspond to Figure 1 A memory device 150 in a memory system.

[0109] More specifically, the controller 6320 may be connected to the memory device 6340 through a plurality of channels CH1 to CHi. The controller 6320 may include one or more processors 6321, an error correction code (ECC) circuit 6322, a host interface 6324, a buffer memory 6325, and a memory interface such as a non-volatile memory interface 6326.

[0110] The buffer memory 6325 may temporarily store data provided from the host 6310 or data provided from a plurality of flash memory NVMs included in the memory device 6340, or temporarily store metadata of the plurality of flash memory NVMs, for example, mapping data including a mapping table. The buffer memory 6325 may be implemented by a volatile memory such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a double data rate (DDR) SDRAM, a low power DDR (LPDDR) SDRAM, and a graphic RAM (GRAM), or a nonvolatile memory such as a ferroelectric RAM (FRAM), a resistive RAM (ReRAM), a spin transfer torque magnetic RAM (STT-MRAM), and a phase change RAM (PRAM). For the purpose of description, Fig. 9 The buffer memory 6325 is shown to exist inside the controller 6320 , but the buffer memory 6325 may be located or arranged outside the controller 6320 .

[0111] The ECC circuit 6322 may calculate an error correction code (ECC) value for data to be programmed into the memory device 6340 during a programming operation, perform an error correction operation on data read from the memory device 6340 based on the ECC value during a read operation, and perform an error correction operation on data recovered from the memory device 6340 during a failed data recovery operation.

[0112] The host interface 6324 may provide an interface function with an external device such as a host 6310 , and the nonvolatile memory interface 6326 may provide an interface function with a memory device 6340 connected through a plurality of channels.

[0113] In addition, applications are available Figure 1The data processing system, for example, a redundant array of independent disks (RAID) system, is implemented by using multiple SSDs 6300 of the memory system 110. The RAID system may include multiple SSDs 6300 and a RAID controller for controlling the multiple SSDs 6300. When the RAID controller performs a programming operation in response to a write command provided from the host 6310, the RAID controller may select one or more memory systems or SSDs 6300 in the SSDs 6300 according to multiple RAID levels, i.e., RAID level information of the write command provided from the host 6310, and output data corresponding to the write command to the selected SSDs 6300. In addition, when the RAID controller performs a read operation in response to a read command provided from the host 6310, the RAID controller may select one or more memory systems or SSDs 6300 in the SSDs 6300 according to multiple RAID levels, i.e., RAID level information of the read command provided from the host 6310, and provide data read from the selected SSDs 6300 to the host 6310.

[0114] Fig.10 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment. Fig.10 An embedded multimedia card (eMMC) 6400 to which the memory system according to the embodiment is applied is schematically illustrated.

[0115] Reference Fig.10 , the eMMC 6400 may include a controller 6430 and a memory device 6440 implemented by one or more NAND flash memories. The controller 6430 may correspond to Figure 1 The controller 130 in the memory system 110 and the memory device 6440 may correspond to Figure 1 The memory device 150 in the memory system 110.

[0116] More specifically, the controller 6430 may be connected to the memory device 6440 through a plurality of channels. The controller 6430 may include one or more cores 6432, a host interface (I / F) 6431, and a memory interface such as a NAND interface (I / F) 6433.

[0117] The kernel 6432 may control the operation of the eMMC 6400, and the host interface 6431 may provide an interface function between the controller 6430 and the host 6410. The NAND interface 6433 may provide an interface function between the memory device 6440 and the controller 6430. For example, the host interface 6431 may be used as a reference, for example. Figure 1 The host interface 6431 may be a parallel interface of the MMC interface. In addition, the host interface 6431 may be used as a serial interface, such as an ultra-high speed (UHS)-I and UHS-II interface.

[0118] Figures 11 to 14 is a diagram schematically illustrating other examples of a data processing system including a memory system according to an embodiment. Figures 11 to 14 A Universal Flash Storage (UFS) system to which the memory system according to the embodiment is applied is schematically illustrated.

[0119] Reference Figures 11 to 14 , the UFS systems 6500, 6600, 6700, 6800 may include hosts 6510, 6610, 6710, 6810, UFS devices 6520, 6620, 6720, 6820, and UFS cards 6530, 6630, 6730, 6830, respectively. The hosts 6510, 6610, 6710, and 6810 may be used as application processors for wired and / or wireless electronic devices or, in particular, mobile electronic devices, and the UFS devices 6520, 6620, 6720, and 6820 may be used as embedded UFS devices. The UFS cards 6530, 6630, 6730, and 6830 may be used as external embedded UFS devices or removable UFS cards.

[0120] The hosts 6510, 6610, 6710, 6810, UFS devices 6520, 6620, 6720, 6820, and UFS cards 6530, 6630, 6730, 6830 in each UFS system 6500, 6600, 6700, 6800 can communicate with external devices such as wired / wireless electronic devices or, in particular, mobile electronic devices through the UFS protocol. The UFS devices 6520, 6620, 6720, 6820, and UFS cards 6530, 6630, 6730, 6830 can communicate with external devices such as wired / wireless electronic devices or, in particular, mobile electronic devices through the UFS protocol. Figure 1 For example, in the UFS systems 6500, 6600, 6700, and 6800, the UFS devices 6520, 6620, 6720, and 6820 may refer to Figures 8 to 10 The data processing system 6200, SSD 6300 or eMMC 6400 described above can be implemented, and the UFS cards 6530, 6630, 6730, 6830 can refer to Figure 7 The described memory card system 6100 is implemented in the form of.

[0121] In addition, in the UFS systems 6500, 6600, 6700, and 6800, the hosts 6510, 6610, 6710, and 6810, the UFS devices 6520, 6620, 6720, and 6820, and the UFS cards 6530, 6630, 6730, and 6830 may communicate with each other through a UFS interface, for example, MIPI M-PHY and MIPI UniPro (Unified Protocol) in MIPI (Mobile Industry Processor Interface). In addition, the UFS devices 6520, 6620, 6720, 6820, and the UFS cards 6530, 6630, 6730, and 6830 may communicate with each other through various protocols such as Universal Serial Bus (USB), Flash Drive (UFD), Multimedia Card (MMC), Secure Digital (SD), Mini SD, and Micro SD in addition to the UFS protocol.

[0122] exist Fig.11 In the UFS system 6500 shown in , each of the host 6510, the UFS device 6520, and the UFS card 6530 may include UniPro. The host 6510 may perform a switching operation to communicate with at least one of the UFS device 6520 and the UFS card 6530. The host 6510 may communicate with the UFS device 6520 or the UFS card 6530 at the UniPro through a link layer switch such as an L3 switch. In this case, the UFS device 6520 and the UFS card 6530 may communicate with each other through a link layer switch at the UniPro of the host 6510. In the example, for ease of description, a configuration in which one UFS device 6520 and one UFS card 6530 are connected to the host 6510 has been illustrated. However, a plurality of UFS devices and UFS cards may be connected to the host 6410 in parallel or in a star form, and a plurality of UFS cards may be connected to the UFS device 6520 in parallel or in a star form, or connected to the UFS device 6520 in series or in a chain form. In this context, a star format refers to an arrangement in which a single device is coupled to multiple other devices or cards for centralized control.

[0123] exist Fig.12In the UFS system 6600 shown in , each of the host 6610, the UFS device 6620, and the UFS card 6630 may include UniPro, and the host 6610 may communicate with the UFS device 6620 or the UFS card 6630 through a switching module 6640 that performs a switching operation, for example, through a switching module 6640 that performs a link layer switching such as L3 switching at UniPro. The UFS device 6620 and the UFS card 6630 may communicate with each other through link layer switching at UniPro by the switching module 6640. In the example, for ease of description, a configuration in which one UFS device 6620 and one UFS card 6630 are connected to the switching module 6640 has been illustrated. However, a plurality of UFS devices and UFS cards may be connected to the switching module 6640 in parallel or in a star form, and a plurality of UFS cards may be connected to the UFS device 6620 in series or in a chain form.

[0124] exist Fig.13 In the UFS system 6700 shown in , each of the host 6710, the UFS device 6720, and the UFS card 6730 may include UniPro. The host 6710 may communicate with the UFS device 6720 or the UFS card 6730 through a switching module 6740 that performs a switching operation, for example, through a switching module 6740 that performs a link layer switching such as L3 switching at UniPro. In this case, the UFS device 6720 and the UFS card 6730 may communicate with each other through link layer switching at UniPro by the switching module 6740, and the switching module 6740 may be integrated into one module with the UFS device 6720 inside or outside the UFS device 6720. In the example, for ease of description, a configuration in which one UFS device 6720 and one UFS card 6730 are connected to the switching module 6740 has been illustrated. However, a plurality of modules each including the switching module 6740 and the UFS device 6720 may be connected to the host 6710 in parallel or in a star form, or connected to each other in series or in a chain form. In addition, a plurality of UFS cards may be connected to the UFS device 6720 in parallel or in a star form.

[0125] exist Fig.14In the UFS system 6800 shown in , each of the host 6810, the UFS device 6820, and the UFS card 6830 may include an M-PHY and a UniPro. The UFS device 6820 may perform an exchange operation to communicate with the host 6810 and the UFS card 6830. The UFS device 6820 may communicate with the host 6810 or the UFS card 6830 through an exchange operation between the M-PHY and UniPro modules for communicating with the host 6810 and an exchange operation between the M-PHY and UniPro modules for communicating with the UFS card 6830, for example, through a target identifier (ID) exchange operation. Here, the host 6810 and the UFS card 6830 may communicate with each other through a target ID exchange between the M-PHY and UniPro modules of the UFS device 6820. In an embodiment, for ease of description, a configuration in which one UFS device 6820 is connected to the host 6810 and one UFS card 6830 is connected to the UFS device 6820 has been exemplified. However, multiple UFS devices may be connected to the host 6810 in parallel or in a star form, or in series or in a chain form, and multiple UFS cards may be connected to the UFS device 6820 in parallel or in a star form, or in series or in a chain form.

[0126] Fig.15 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment. Fig.15 69 is a diagram schematically illustrating a user system 6900 to which the memory system according to the embodiment is applied.

[0127] Reference Fig.15 , the user system 6900 may include a user interface 6910 , a memory module 6920 , an application processor 6930 , a network module 6940 , and a storage module 6950 .

[0128] More specifically, the application processor 6930 may drive components included in the user system 6900 such as an operating system (OS), and include a controller, an interface, a graphic engine, etc. for controlling components included in the user system 6900. The application processor 6930 may be provided as a system on chip (SoC).

[0129] The memory module 6920 may be used as a main memory, a working memory, a buffer memory, or a cache memory of the user system 6900. The memory module 6920 may include a volatile random access memory (RAM) such as a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a double data rate (DDR) SDRAM, a DDR2 SDRAM, a DDR3 SDRAM, a LPDDR SDRAM, a LPDDR2 SDRAM, or a LPDDR3 SDRAM, or a non-volatile RAM such as a phase change RAM (PRAM), a resistive RAM (ReRAM), a magnetoresistive RAM (MRAM), or a ferroelectric RAM (FRAM). For example, the application processor 6930 and the memory module 6920 may be packaged and mounted based on a stacked package (POP).

[0130] The network module 6940 can communicate with an external device. For example, the network module 6940 can support not only wired communication, but also various wireless communication protocols, such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), global microwave access interoperability (WiMAX), wireless local area network (WLAN), ultra-wideband (UWB), Bluetooth, wireless display (WI-DI), so as to communicate with wired / wireless electronic devices, or in particular mobile electronic devices. Therefore, the memory system and data processing system according to an embodiment of the present invention can be applied to wired / wireless electronic devices. The network module 6940 can be included in the application processor 6930.

[0131] The storage module 6950 may store data, such as data received from the application processor 6930, and then may transmit the stored data to the application processor 6930. The storage module 6950 may be implemented by a nonvolatile semiconductor memory device, such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (ReRAM), a NAND flash memory, a NOR flash memory, and a 3D NAND flash memory, and may be provided as a removable storage medium such as a memory card or an external drive of the user system 6900. The storage module 6950 may correspond to the reference Figure 1 The memory system 110 described above. In addition, the storage module 6950 can be implemented as described above with reference to Figures 7 to 14 The SSD, eMMC and UFS mentioned above.

[0132] The user interface 6910 may include an interface for inputting data or commands to the application processor 6930 or for outputting data to an external device. For example, the user interface 6910 may include a user input interface such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric element, and a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, a light emitting diode (LED), a speaker, and a monitor.

[0133] In addition, when Figure 1 When the memory system 110 is applied to a mobile electronic device of the user system 6900, the application processor 6930 may control the operation of the mobile electronic device, and the network module 6940 may be used as a communication module for controlling wired and / or wireless communication with an external device. The user interface 6910 may display data processed by the processor 6930 on a display and / or touch module of the mobile electronic device or support a function of receiving data from a touch panel.

[0134] While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. A method for operating a memory system, comprising: reading target data stored in a target memory page based on a plurality of read voltages; storing first read data and second read data in a first latch and a second latch, respectively, the first read data and the second read data corresponding to target data read using read voltages of different levels among the plurality of read voltages; performing a first error correction code decoding operation, i.e., a first ECC decoding operation, on the first read data stored in the first latch, and storing third read data in the first latch while performing the first ECC decoding operation, the third read data corresponding to target data read using another read voltage of a different level among the plurality of read voltages; as well as When the first ECC decoding operation fails and the number of repeated ECC decoding operations is less than a preset ECC decoding repetition number, a second ECC decoding operation is performed on the second read data stored in the second latch, and the repeated ECC decoding operation includes the first ECC decoding operation and the second ECC decoding operation.

2. The operating method according to claim 1, further comprising: storing fourth read data in the second latch when performing the second ECC decoding operation, the fourth read data corresponding to target data read using another read voltage of a different level among the plurality of read voltages; as well as When the second ECC decoding operation fails and the number of repeated ECC decoding operations is less than a preset number of ECC decoding repetitions, a third ECC decoding operation is performed on the third read data stored in the first latch, and the repeated ECC decoding operation includes the first ECC decoding operation, the second ECC decoding operation and the third ECC decoding operation. 3 . The operating method according to claim 1 , wherein reading the target data comprises reading the target data using the plurality of read voltages written in a read voltage table stored in a control circuit. 4 . The operating method according to claim 1 , further comprising determining that the target data is uncorrectable when the number of times the ECC decoding operation is repeated is greater than or equal to the preset ECC decoding repetition number.

5. The operating method according to claim 1, further comprising: When the second ECC decoding operation is successful, performing a discharge operation on the target memory page; and The second read data is output to a host.

6. The operating method according to claim 1, further comprising: Using a preset initial read voltage to read the target data; storing initial read data corresponding to the target data in any one of the plurality of latches; as well as performing an initial ECC decoding operation on the initial read data; as well as When the initial ECC decoding operation fails, the memory device is controlled by the controller to read the target data using a read voltage.

7. The operating method according to claim 1, further comprising: loading the first read data stored in the first latch; as well as The second read data stored in the second latch is loaded.

8. A memory system comprising: A memory device, comprising: a read / write circuit including a plurality of latches in a page buffer; and a control circuit controlling the read / write circuit to respectively read target data stored in a target memory page using a plurality of read voltages having different levels, and storing first read data and second read data corresponding to the target data read using read voltages of different levels among the plurality of read voltages in the plurality of latches including the first latch and the second latch; and A controller, performing a first ECC decoding operation on the first read data stored in the first latch, and controlling the control circuit to store third read data in the first latch when performing the first ECC decoding operation, the third read data corresponding to target data read using another read voltage of a different level among the multiple read voltages; and performing a second ECC decoding operation on the second read data stored in the second latch when the first ECC decoding operation fails and the current number of repeated ECC decoding operations is less than a preset number of ECC decoding repetitions, the repeated ECC decoding operations including the first ECC decoding operation and the second ECC decoding operation.

9. The memory system of claim 8, wherein the controller: controlling the control circuit to store fourth read data in the second latch when performing the second ECC decoding operation, the fourth read data corresponding to target data read using another different level of a read voltage among the plurality of read voltages; and When the second ECC decoding operation fails and the number of repeated ECC decoding operations is less than a preset number of ECC decoding repetitions, a third ECC decoding operation is performed on the third read data stored in the first latch, and the repeated ECC decoding operation includes the first ECC decoding operation, the second ECC decoding operation and the third ECC decoding operation. 10 . The memory system of claim 8 , wherein the control circuit controls the read / write circuit to read the target data using the plurality of read voltages written in a read voltage table stored in the control circuit.

11. The memory system of claim 8, wherein when the number of times the ECC decoding operation is repeated is greater than or equal to the preset ECC decoding repetition number, the controller determines that the target data is an uncorrectable ECC error (UECC error). 12 . The memory system of claim 8 , wherein when the second ECC decoding operation is successful, the controller controls the memory device to perform a discharge operation on the target memory page and output the second read data to a host.

13. The memory system according to claim 8, wherein the control circuit controls the read / write circuit to read the target data using a preset initial read voltage, and stores initial read data corresponding to the target data in any one of the plurality of latches; and The controller performs an initial ECC decoding operation on the initial read data, and controls the memory device to read the target data using a read voltage when the initial ECC decoding operation fails. 14 . The memory system of claim 8 , wherein the controller loads first read data stored in the first latch, and loads second read data stored in the second latch.

15. A memory device comprising: a read / write circuit including a plurality of latches in a page buffer; as well as A control circuit controls the read / write circuit to respectively read target data stored in a target memory page using a plurality of read voltages having different levels, and respectively stores first read data and second read data corresponding to the target data read using read voltages having different levels among the plurality of read voltages in a plurality of latches including a first latch and a second latch. a controller that performs a first ECC decoding operation on the first read data stored in the first latch, and controls third read data to be stored in the first latch when performing the first ECC decoding operation, the third read data corresponding to target data read using a read voltage of a different level among the plurality of read voltages; And when the first ECC decoding operation fails and the current number of repeated ECC decoding operations is less than the preset ECC decoding repetition number, a second ECC decoding operation is performed on the second read data stored in the second latch, and the repeated ECC decoding operation includes the first ECC decoding operation and the second ECC decoding operation.

16. The memory device of claim 15, wherein the controller: controlling the control circuit to store fourth read data in the second latch when performing the second ECC decoding operation, the fourth read data corresponding to target data read using another different level of a read voltage among the plurality of read voltages; and When the second ECC decoding operation fails and the number of repeated ECC decoding operations is less than a preset number of ECC decoding repetitions, a third ECC decoding operation is performed on the third read data stored in the first latch, and the repeated ECC decoding operation includes the first ECC decoding operation, the second ECC decoding operation and the third ECC decoding operation. 17 . The memory device of claim 15 , wherein the control circuit controls the read / write circuit to read the target data using the plurality of read voltages written in a read voltage table stored in the control circuit.

18. The memory device of claim 15, wherein when a discharge command for the target memory page is received, the control circuit controls the read / write circuit to perform a discharge operation on the target memory page.

19. The memory device of claim 15, wherein the control circuit controls the read / write circuit to read the target data using a preset initial read voltage and stores initial read data corresponding to the target data in any one of the plurality of latches.

20. A memory system comprising: Memory device; as well as Controller, Wherein the memory device comprises: a memory cell array including a target area for storing target data; a region buffer comprising a plurality of latches, the plurality of latches comprising a first latch and a second latch; and Control circuit: In response to a read command from the controller, reading the target data using a plurality of read voltages having different levels; and storing first read data and second read data corresponding to target data read using read voltages of different levels among the plurality of read voltages in the first latch and the second latch, wherein the controller loads the first read data stored in the first latch, performs a first ECC decoding operation on the first read data, and controls the control circuit to store third read data in the first latch when performing the first ECC decoding operation, the third read data corresponding to target data read using another read voltage of a different level among the plurality of read voltages, The controller loads the second read data stored in the second latch, and performs a second ECC decoding operation on the second read data when the first decoding operation fails and the current number of repeated ECC decoding operations is less than a preset number of ECC decoding repetitions, wherein the repeated ECC decoding operation includes the first ECC decoding operation and the second ECC decoding operation.

21. The memory system of claim 20, wherein the controller: controlling the control circuit to store fourth read data in the second latch when performing the second ECC decoding operation, the fourth read data corresponding to target data read using another different level of a read voltage among the plurality of read voltages; and When the second ECC decoding operation fails and the number of repeated ECC decoding operations is less than a preset number of ECC decoding repetitions, a third ECC decoding operation is performed on the third read data stored in the first latch, and the repeated ECC decoding operation includes the first ECC decoding operation, the second ECC decoding operation and the third ECC decoding operation.

22. The memory system of claim 20, wherein the target area comprises a target page, and the area buffer comprises a page buffer.

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