Low-delay large-scale virtual channel DMA (Direct Memory Access) circuit based on FPGA (Field Programmable Gate Array)

Abstract

The invention provides an FPGA-based low-delay large-scale virtual channel DMA circuit, and relates to the technical field of integrated circuit design, the FPGA-based low-delay large-scale virtual channel DMA circuit is mainly composed of a data preprocessing module, a TLP packaging module, a Cell address generation module, a PCIe module and a PingPang memory structure module, real-time full acquisition can be carried out on all E1 link data of stm-16, the delay of a single 64K signal does not exceed 10ms, and the time delay of the single 64K signal does not exceed 10ms. According to the method and the system, the timeliness of data transmission is remarkably improved, the real-time requirement of a service is ensured to be met, an additional memory does not need to be designed for the FPGA, the occupation of hardware resources is reduced, the complexity of FPGA program control and the hardware design cost are reduced, the requirements of cache and implementation are fully considered, the characteristics of a CPU system are effectively utilized, and the method and the system have the advantages of being high in practicability and easy to popularize. The performance that the DMA controller writes the Mems and the performance that the host accesses the PingPang memory are improved, so that a single CPU processing thread can perform independent processing according to the E1 rate, and the parallel capability of multiple threads of the CPU is brought into full play.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and more specifically, particularly relates to a low-latency large-scale virtual channel DMA circuit based on FPGA. Background Art

[0002] In today's communications field, especially in SDH (Synchronous Digital Hierarchy) data acquisition systems, how to accurately transmit a large amount of business data to CPU memory efficiently and with low latency is a critical and challenging issue.

[0003] As a widely used communication standard, SDH faces many difficulties in data collection due to the diversity of services it carries and the complexity of its frame structure. In traditional data collection processing methods, CPU direct access mode or DMA mode is usually used. However, the CPU direct access mode will occupy a large number of CPU instruction cycles, increase the CPU burden, and has poor real-time and scalability, making it difficult to meet the needs of high-speed SDH collection systems.

[0004] Although the DMA transmission method can reduce the CPU communication load to a certain extent, the existing DMA controller has the problem of limited number of channels, often only dozens of channels, and is mainly designed for large-block data scenarios. It cannot cope with the thousands of channels required and strict real-time requirements in the SDH acquisition system.

[0005] With the continuous development of communication services, the requirements for SDH data acquisition are getting higher and higher. It not only needs to support a large number of channels, but also needs to ensure low-latency data transmission to ensure that the service quality is not affected. In this context, it is urgent to design a low-latency large-scale virtual channel DMA circuit that can meet the special needs of the SDH acquisition system. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a low-latency large-scale virtual channel DMA circuit based on FPGA to solve the above problems.

[0007] A low-latency large-scale virtual channel DMA circuit based on FPGA includes a data preprocessing module, a TLP packet module, a Cell address generation module, a PCIe module and a PingPang memory structure module, wherein the data preprocessing module is used to receive a high-speed asynchronous E1 data stream based on byte interleaving parsed from an SDH signal, the TLP packet module is used to receive front-end data input, encapsulate it in 64B units according to the E1 number of the line data, and then send it to the PCIe module for processing, and send a corresponding interrupt signal after a group of PingPang memory transmission is completed. The Cell address generation module is used to generate the TLP address of the current Cell through the software preset first address and the E1 number of the received line data. The address generation rule is: cell address = first address + stm_num + E1_num + offset. The PCIe module is used to provide the connection and transmission functions of the PCIe bus. The PingPang memory structure module is located in the CPU's memory and is managed by the driver. It is divided into two PingPang groups. The number of memory blocks in each group is configured according to the number of line stms. The memory block size is 64KB, which is logically divided into 64 1KB sub-memory blocks of equal length.

[0008] Preferably, the data preprocessing module converts the data mode of byte interleaving in the SDH signal into a data mode of interleaving in units of 64B.

[0009] Preferably, the TLP packet module uses 64B as the basic transmission unit, called a cell, to perform fixed-length packet transmission.

[0010] Preferably, the number of each group of memory blocks is consistent with the number of stm-1 in the SDH signal.

[0011] Preferably, the capacity of each sub-memory block is 1 kB, and one memory block is 64*1k=64 kB.

[0012] Preferably, after the cell is transferred to the designated memory via TLP, for the sub-memory blocks that are currently full, the newly arrived data will be written into another group of memory blocks, and when the first group of memory blocks is completely full, an interrupt signal is sent to the CPU.

[0013] Preferably, the PingPang memory structure module asynchronously parallelizes CPU interrupt processing and SDH data collection.

[0014] Preferably, the first address in the address generation rule in the Cell address generation module is pre-allocated by software, and the E1 address and offset are calculated by hardware according to certain rules.

[0015] Preferably, the DMA circuit can realize the real-time full acquisition of all E1 link data of STM-16, and the delay of a single 64K signal does not exceed 10ms.

[0016] Preferably, the DMA circuit has a smaller requirement on the host memory, requiring only about 2 MB of DMA core memory.

[0017] Compared with the prior art, the present invention has the following beneficial effects: 1. In the present invention, all E1 link data of stm-16 can be fully collected in real time, and the delay of a single 64K signal does not exceed 10ms, which significantly improves the timeliness of data transmission and ensures that the real-time requirements of the business are met.

[0018] 2. In the present invention, there is no need to design additional memory for FPGA, which reduces the occupation of hardware resources, and reduces the complexity of FPGA program control and hardware design cost.

[0019] 3. In the present invention, the host memory requirement is relatively small, and only about 2MB of DMA core memory is required (calculated based on a single-channel stm16), which reduces the system's memory overhead.

[0020] 4. In the present invention, the requirements of cacheline and mempage are fully considered, the characteristics of the CPU system are effectively utilized, and the performance of DMA controller writing Mem and host accessing PingPang memory is improved.

[0021] 5. In the present invention, a single CPU processing thread can be processed independently at the E1 rate, giving full play to the parallel capability of CPU multi-threading and improving the overall processing efficiency of the system.

[0022] 6. The present invention has good adaptability to STM-1, STM-16, and STM-64, and supports parallel streaming acquisition of multiple SDH signals, and can flexibly respond to communication scenario requirements of different scales and complexities.

[0023] 7. In the present invention, by adopting a ping-pong memory structure, CPU interrupt processing and SDH data collection are asynchronously parallelized, thereby avoiding the problem of line data loss and ensuring the real-time performance of CPU processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a circuit block diagram of the present invention. DETAILED DESCRIPTION

[0025] The following embodiments of the present invention are described in further detail in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0026] See also Figure 1 , the present invention provides a low-latency large-scale virtual channel DMA circuit based on FPGA, which is mainly composed of a data preprocessing module, a TLP packet module, a Cell address generation module, a PCIe module and a PingPang memory structure module; The data preprocessing module receives high-speed asynchronous E1 data streams based on byte interleaving parsed from the SDH signal. These data streams are high-speed and asynchronous, and need to be effectively processed to adapt to subsequent transmission and storage. The data preprocessing module organizes the data from the original 1B interleaving to 64B interleaving through high-speed cache transformation processing. Such a conversion helps to improve the transmission efficiency and processing convenience of data. In specific implementation, the data preprocessing module adopts a first-in-first-out (FIFO) cache mechanism. When the E1 data stream enters the module, it is first stored in the FIFO cache. Then, through a specific logic circuit, the data is rearranged and sorted in units of 64B. In this process, the byte order of the data needs to be adjusted and the integrity and accuracy of the data must be ensured. In order to ensure the real-time processing, the data preprocessing module adopts high-speed hardware logic implementation, which can complete the processing of each data unit within nanoseconds. At the same time, in order to cope with possible data congestion and loss, the module also sets up congestion detection and error handling mechanisms. When the FIFO buffer is close to full or a data error is detected, an alarm signal will be issued in time to suspend data input and perform corresponding error recovery operations.

[0027] The TLP packet module is responsible for receiving the front-end data input after being processed by the data preprocessing module. It encapsulates the data in 64B units according to the E1 number of the line data, and then sends the encapsulated data to the PCIe module for processing. At the same time, after a group of PingPang memory transmission is completed, the module will send a corresponding interrupt signal. During the packetization process, the TLP packetization module will add necessary header and tail information for each 64B data unit, including source address, destination address, data type, checksum, etc. This information helps the PCIe module to accurately identify and process data packets. In order to improve the packetization efficiency, the module adopts a pipeline working mode and can process the packetization operations of multiple data units at the same time. In addition, the TLP packetization module also has the functions of flow control and congestion avoidance. It monitors the load of the PCIe bus in real time and adjusts the packet rate according to the preset threshold to avoid bus congestion. When a group of PingPang memory transmission is completed, the module will send an interrupt signal to the system through a specific interrupt signal line to notify the CPU to perform corresponding processing.

[0028] The Cell address generation module is one of the key parts in the DMA circuit. It is responsible for generating accurate TLP addresses for each transmitted Cell. Through the software preset first address and the E1 number of the receiving line data, the TLP address of the current Cell is generated according to the specific address generation rule: cell address = first address + stm_num + E1_num + offset. In actual operation, the software will configure the first address for the address generation module when the system is initialized. When there is a new data Cell to be transmitted, the module will calculate the complete TLP address according to the STM number (stm_num) and E1 number (E1_num) to which the data belongs and the offset (offset). Among them, the STM number and E1 number are obtained by SDH signal analysis, and the offset is calculated according to the storage location and transmission order of the data in the memory. In order to improve the speed and accuracy of address generation, the Cell address generation module adopts hardware acceleration to complete the address calculation in a very short time through a dedicated address generation logic circuit. At the same time, in order to ensure the uniqueness and validity of the address, the module will also perform verification and error correction on the generated address.

[0029] The PCIe module provides the connection and transmission functions of the PCIe bus, and is responsible for transmitting the encapsulated TLP data packets to the CPU memory through the PCIe bus. The module supports multiple versions of the PCIe protocol and can adaptively select the appropriate transmission rate and number of channels according to the system configuration and hardware environment. During the data transmission process, the PCIe module will strictly follow the specifications of the PCIe protocol to perform data packaging, unpacking, flow control and error handling operations. In order to improve the reliability of data transmission, the PCIe module adopts a retransmission mechanism and error correction coding technology. When data packets are lost or errors occur during the transmission process, the module will automatically request the sender to retransmit and perform error correction decoding on the received data to ensure the integrity and accuracy of the data. In addition, the PCIe module also has power management and hot-swap support functions, which can dynamically adjust power consumption and adapt to the plug-in and unplug operations of hardware devices during system operation, improving the stability and scalability of the system.

[0030] The PingPang memory structure module is located in the CPU memory and is managed by the driver. It is divided into two groups, Ping and Pang, and the number of memory blocks in each group is configured according to the number of line STMs. Each memory block is 64KB in size and is logically divided into 64 1KB sub-memory blocks of equal length. During the data writing process, the data is written to the corresponding sub-memory block according to the usage of the current memory group and the E1 number of the data. When one group of memory blocks is full, it automatically switches to another group of memory blocks to continue writing, realizing the asynchronous parallel operation of CPU interrupt processing and SDH data collection. In order to improve the efficiency of memory access, the PingPang memory structure module adopts memory mapping technology to directly map the memory address to the CPU address space, so that the CPU can quickly and directly access the data in the memory. At the same time, in order to prevent memory access conflicts and data inconsistency problems, the module adopts synchronization mechanisms such as mutex locks and semaphores to strictly control and manage the read and write operations of the memory.

[0031] Data transmission process: Step 1: Data preprocessing: The high-speed asynchronous E1 data stream in the SDH signal enters the data preprocessing module. The module transforms the 1B interleaved data into 64B interleaved data through high-speed cache conversion, and the processed data is output to the TLP packet module; Step 2: TLP Packaging: The TLP Packaging module receives the pre-processed data, encapsulates it in 64B units according to the E1 number, forms a Cell, sends the Cell to the PCIe module, and sends an interrupt signal after a set of PingPang memory transmission is completed; Step 3: Cell address generation: The Cell address generation module generates a TLP address based on the software preset first address and the E1 number of the line data. The address includes the first address, stm_num, E1_num and offset; Step 4: PCIe transmission: The PCIe module receives the encapsulated Cell and the corresponding TLP address, and transmits the data to the PingPang memory structure module through the PCIe bus; Step 5: PingPang memory storage: The PingPang memory structure module stores data in the corresponding memory blocks and sub-memory blocks according to the TLP address. When one group of memory blocks is full, it switches to another group to continue storage and sends an interrupt signal to the CPU.

[0032] In order to verify the performance and function of the FPGA-based low-latency large-scale virtual channel DMA circuit of the present invention, a series of experiments and tests were carried out. The experimental environment was built using a development board with a high-performance FPGA chip, such as Xilinx's Virtex series or Altera's Stratix series, equipped with a high-speed PCIe interface card, supporting PCIeGen3x8 or higher specifications, connected to the SDH data source, providing real SDH signal input, using professional FPGA development tools, such as Xilinx Vivado or Altera Quartus Prime, installed with corresponding drivers and test software to control and monitor the running status of the DMA circuit, the test indicators and methods are as follows: (1) Delay test: Use high-precision time measurement equipment, such as oscilloscopes and logic analyzers, to measure the time delay from SDH signal input to data storage in the CPU memory. Test SDH signals of different sizes and types, including STM-1, STM-16 and STM-64, and calculate the average delay and maximum delay. (2) Data transfer efficiency test: By monitoring the bandwidth utilization and data throughput of the PCIe bus, the data transfer efficiency of the DMA circuit is evaluated. Tests are performed using different data transfer rates and load conditions to analyze performance under various conditions. (3) Memory requirement test: measure the actual occupancy of the host memory by the DMA circuit under different SDH signal configurations, compare the theoretical calculated value with the actual measured value, and verify the accuracy of the memory requirement; (4) Scalability test: gradually increase the number of channels and data flow of the SDH signal, observe the performance changes and stability of the DMA circuit, and test the overall performance and resource utilization of the system when multiple SDH signals are collected in parallel.

[0033] The test results and analysis are as follows: (1) Delay test results: Under the configuration of STM-16, the real-time collection delay of all E1 link data does not exceed 10ms, meeting the low delay requirement. As the scale of SDH signals increases, the delay increases slightly, but still remains within an acceptable range. (2) Data transmission efficiency test results: The bandwidth utilization of the PCIe bus can reach more than 80% under high load conditions, and the data throughput is stable. Under different transmission rates and load conditions, the DMA circuit can adaptively adjust the transmission strategy to maintain a high efficiency. (3) Memory requirement test results: The actual host memory requirement is consistent with the theoretical calculated value, which is about 2MB (calculated based on a single-channel STM-16), and the system resource usage is relatively small; (4) Scalability test results: When the number of SDH signal channels increases and the data flow increases, the DMA circuit can work normally without obvious performance degradation. When multiple SDH signals are collected in parallel, the system can effectively allocate resources and achieve efficient data transmission and processing.

[0034] The low-latency large-scale virtual channel DMA circuit based on FPGA of the present invention has significant advantages in the following scenarios: In the SDH data acquisition system, it can efficiently process a large amount of E1 channel data, ensure the real-time and reliability of the service, support the acquisition and transmission of SDH signals of different rates and formats, such as STM-1, STM-16 and STM-64, and has good compatibility and scalability; it is used for high-speed data transmission between servers and storage devices, improves the overall performance and efficiency of the data center, can cope with large-scale data traffic and complex business requirements in the data center, and reduce the delay and cost of data transmission; in the industrial automation control system, it realizes the rapid acquisition and processing of real-time data, ensures the precise control and stable operation of the system, adapts to the harsh electromagnetic interference and temperature changes in the industrial environment, and has high reliability and stability.

[0035] The low-latency large-scale virtual channel DMA circuit based on FPGA of the present invention effectively solves the problems of large number of channels and strict latency requirements faced by SDH acquisition systems through innovative design and optimization. Through actual experiments and tests, its superior performance in latency, data transmission efficiency, memory requirements and scalability has been verified. The circuit has broad application prospects in the fields of telecommunications, data centers, industrial control, etc., and can provide strong support for performance improvement and function optimization of related systems.

[0036] The embodiments of the present invention are given for the purpose of illustration and description, and are not intended to be exhaustive or to limit the invention to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments are selected and described in order to better illustrate the principles and practical applications of the present invention and to enable those of ordinary skill in the art to understand the present invention and thereby design various embodiments with various modifications suitable for specific uses.

Claims

1. A low-latency large-scale virtual channel DMA circuit based on FPGA, characterized in that: It includes data preprocessing module, TLP packet module, Cell address generation module, PCIe module and PingPang memory structure module; The data preprocessing module is used to receive the high-speed asynchronous E1 data stream based on byte interleaving parsed from the SDH signal; The TLP packet module is used to receive the front-end data input, encapsulate it in 64B units according to the E1 number of the line data, and then send it to the PCIe module for processing. At the same time, after a group of PingPang memory transmission is completed, the corresponding interrupt signal is sent; The cell address generation module is used to generate the TLP address of the current cell through the software preset first address and the E1 number of the received line data. The address generation rule is: cell address = first address + stm_num + E1_num + offset; The PCIe module is used to provide the connection and transmission functions of the PCIe bus; The PingPang memory structure module is located in the CPU's memory and is managed by the driver. It is divided into two PingPang groups. The number of memory blocks in each group is configured according to the number of line stms. The memory block size is 64KB, which is logically divided into 64 1KB sub-memory blocks of equal length.

2. A low-latency large-scale virtual channel DMA circuit based on FPGA as claimed in claim 1, characterized in that: The data preprocessing module converts the byte interleaving data pattern in the SDH signal into a data pattern interleaving in units of 64B.

3. A low-latency large-scale virtual channel DMA circuit based on FPGA as claimed in claim 1, characterized in that: The TLP packet module uses 64B as the basic transmission unit, called a cell, for fixed-length packet transmission.

4. A low-latency large-scale virtual channel DMA circuit based on FPGA as claimed in claim 1, characterized in that: The number of memory blocks in each group is consistent with the number of stm-1 in the SDH signal.

5. A low-latency large-scale virtual channel DMA circuit based on FPGA as claimed in claim 1, characterized in that: The capacity of each sub-memory block is 1kB, and a memory block is 64*1k=64kB.

6. A low-latency large-scale virtual channel DMA circuit based on FPGA as claimed in claim 1, characterized in that: When the cell is transferred to the specified memory through TLP, for the sub-memory block that is currently full, the new data will be written into another group of memory blocks. When the first group of memory blocks is completely full, an interrupt signal is sent to the CPU.

7. A low-latency large-scale virtual channel DMA circuit based on FPGA as claimed in claim 1, characterized in that: The PingPang memory structure module asynchronously parallelizes CPU interrupt processing and SDH data collection.

8. The low-latency large-scale virtual channel DMA circuit based on FPGA as claimed in claim 1, characterized in that: The first address in the address generation rule in the Cell address generation module is pre-allocated by software, and the E1 address and offset are calculated by hardware according to certain rules.

9. A low-latency large-scale virtual channel DMA circuit based on FPGA as claimed in claim 1, characterized in that: The DMA circuit can realize the real-time full acquisition of all E1 link data of STM-16, and the delay of a single 64K signal does not exceed 10ms.

10. The low-latency large-scale virtual channel DMA circuit based on FPGA as claimed in claim 1, characterized in that: The DMA circuit has a small requirement for host memory, requiring only about 2MB of DMA core memory.

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