An improved circuit structure for a USB-C interface device

Abstract

This invention discloses an improved circuit structure for a USB-C interface device. The structure includes a CPU, a USB-C protocol chip, a USB-C connector, a non-standard detection circuit module, and a power switch SW1. The USB-C protocol chip determines whether the insertion / removal is in master or slave mode by detecting the voltages CC1 and CC2 in the USB-C connector, and communicates with the CPU via an I2C signal bus. After a non-standard USB-C cable is inserted, the non-standard detection circuit module provides additional logic for determining the voltages CC1 and CC2 in the USB-C connector and outputs a non-standard detection control signal to control the opening and closing of the power switch SW1. This structure allows non-standard USB-C cables to be recognized by the USB-C protocol chip just like standard USB-C cables, avoiding the need for customers to remember which specific terminal devices these outwardly identical but internally incompatible USB-C cables can only be used with.

Description

Technical Field

[0001] This invention belongs to the field of communication products in the electronics industry, and relates to the functional application extension of the USB (Universal Serial Bus) communication interface protocol, especially an improved circuit structure of a USBC interface device. Background Technology

[0002] Currently available USB-C (USB Type-C, USB Type-C interface) protocol chips are designed according to the protocol defined by the USB Alliance and are promoted in various industries. The protocol stipulates that USB-C can supply power to external devices or supply power to the device itself through an external power source.

[0003] The power delivery function of USB-C is described below:

[0004] The logic diagram for the USBC power supply working mode is as follows: Figure 1 As shown:

[0005] USBC interconnection is performed with one device in master mode and the other device in slave mode.

[0006] The USB-C cable contains a CC (Configuration Channel) wire, which connects to either CC1 or CC2 on either end of the USB connector (the connection varies depending on whether the USB-C connector is reversed). Devices at both ends of the USB-C cable read the voltage values ​​on CC1 and CC2 to determine the status of the other device.

[0007] Main mode: Acts as a power port, supplying power externally. Connect pull-up resistors Rp to both CC1 and CC2 inside the USB-C connector, directing them to the power supply.

[0008] Slave mode: Receives power as a powered port. Connect both CC1 and CC2 to ground using pull-down resistors Rd.

[0009] Dual-port mode: When a device can operate in both master and slave modes, the two devices negotiate via the USB internal connection line CC to determine which device will act as the master and which as the slave. After negotiation, each device will set itself to master or slave mode, and connect pull-up resistors Rp or pull-down resistors Rd to ports CC1 and CC2.

[0010] If, on the master mode side, the voltage of one of the CC1 and CC2 pins is detected to be pulled low by the Rd divider, while the other of CC1 and CC2 remains high, it indicates that the other end is connected to a slave mode device. If the master mode device detects that the other pin of CC1 and CC2 is pulled low by the Ra divider, it indicates that an internal chip in this USB-C cable needs to supply power to the USB-C cable through this pin.

[0011] Similarly, when a device in slave mode detects that the voltage of one of the CC1 and CC2 pins has been pulled up to a voltage greater than 0V by Rp voltage divider, while the other of CC1 and CC2 remains at 0V, it indicates that the other end has been connected to a device in master mode.

[0012] When the master device detects that the other end of the USB-C cable has been connected to the slave device, it will turn on the power supply end to supply power to the slave device through the power supply circuit inside the USB-C cable. If no slave device is detected, the power supply will be disconnected.

[0013] When the slave device is not powered by its internal battery, it turns on the power supply switch to the internal circuitry after detecting a connection to the master device.

[0014] When the device is powered by its internal battery, it will turn on the battery charging switch after detecting the connection of the master device.

[0015] These identification operations are typically performed by proprietary USBC protocol chips.

[0016] Although the USBC protocol specifies the specifications and definitions of USBC cables, it cannot prevent many manufacturers from arbitrarily defining the internal resistance of USBC cables and designing their own terminal products based on this definition. This results in these USBC cables being incompatible with standard USBC terminal devices, causing users without USBC knowledge and experience to find that although the cables look exactly the same, they are not compatible with each other, causing confusion.

[0017] The usual practice for non-marking lines is as follows: Figure 2 As shown, an additional connection line connecting CC1 and CC2 was added. As a result, the voltages collected by the master and slave devices at the CC1 and CC2 ports are the same, causing the USBC protocol chip to be unable to recognize it according to the USBC protocol, thus making the non-standard USBC cable unable to be used normally on standard USBC devices. Summary of the Invention

[0018] To address the issue of non-standard USBC cables failing to function properly on standard USBC devices, this invention provides an improved circuit structure for USBC interface devices. This structure allows non-standard USBC cables to be recognized by the USBC protocol chip just like standard USBC cables, thus avoiding the need for customers to remember which specific terminal devices these outwardly identical but internally incompatible USBC cables can only be used with.

[0019] To achieve the above objectives, the present invention adopts the following technical solution:

[0020] In one embodiment of the present invention, an improved circuit structure for a USB-C interface device is proposed. The structure includes a CPU, a USB-C protocol chip, a USB-C connector, a non-standard detection circuit module, and a power switch SW1. The USB-C protocol chip determines whether the insertion or removal of the device is in master mode or slave mode by detecting the voltages CC1 and CC2 in the USB-C connector, and communicates with the CPU via the I2C signal bus. After the non-standard USB-C cable is inserted, the non-standard detection circuit module provides additional logic determination by detecting the voltages CC1 and CC2 in the USB-C connector, and outputs a non-standard detection control signal to control the opening and closing of the power switch SW1.

[0021] Furthermore, if a master mode device is inserted, the power switch SW1 is turned off, and the inserted master mode device provides voltage to the system. At this time, the internal system 5V_SYS voltage and the external USBC cable 5V_USBC voltage are combined to power the system. If a slave mode device is inserted, the power switch SW1 is turned off, and the internal system 5V_SYS voltage powers the external USBC interface device through the USBC connector interface. If the external USBC interface device is unplugged, the power switch SW1 is turned off, cutting off the connection between the internal system 5V_SYS voltage and the external USBC cable 5V_USBC voltage.

[0022] Furthermore, in the circuit of the power supply switch SW1, the internal system voltage 5V_SYS or the external USBC cable connection voltage 5V_USBC is established by providing a 4.7V detection voltage to the network gate through the body diode of the first PMOS transistor Q1 and the second PMOS transistor Q2, where the body diode voltage drop is 0.3V. When the external USBC interface device has no other power supply, the 5V_USBC connected by the external USBC cable provides the power supply voltage. At this time, the fourth NMOS transistor Q4 is turned off, and the third NMOS transistor Q3 is turned on by the voltage divider of the second resistor R2 and the third resistor R3, thereby turning on the first PMOS transistor Q1 and the second PMOS transistor Q2, and connecting the internal system voltage 5V_SYS with the external USBC cable. The 5V USBC voltage connection connected to the external USBC cable powers the external USBC interface device. At this time, the CPU takes over the CPU_control signal. When the CPU_control signal is set to low level, the fourth NMOS transistor Q4 is cut off and the third NMOS transistor Q3 is turned on, making the first PMOS transistor Q1 and the second PMOS transistor Q2 in the open state. When the CPU_control signal is set to high level, the fourth NMOS transistor Q4 is turned on and the third NMOS transistor Q3 is cut off, making the first PMOS transistor Q1 and the second PMOS transistor Q2 in the closed state, thus completing the function of the CPU_control signal controlling the opening and closing of the power supply switch SW1.

[0023] Furthermore, if the external USBC interface device is powered by another power source, causing the internal system voltage 5V_SYS to be established before the external USBC cable access voltage 5V_USBC, then the CPU controls the switching of the first PMOS transistor Q1 and the second PMOS transistor Q2.

[0024] Furthermore, after the non-standard USB-C cable is inserted, when the non-standard detection control signal is set to low level, the sixth NMOS transistor Q6 is turned off, and the fifth NMOS transistor Q5 is turned on by the voltage divider of the fifth resistor R5 and the seventh resistor R7, so that the first PMOS transistor Q1 and the second PMOS transistor Q2 are in the open state; when the non-standard detection control signal is set to high level, the sixth NMOS transistor Q6 is turned on, and the fifth NMOS transistor Q5 is turned off, so that the first PMOS transistor Q1 and the second PMOS transistor Q2 are in the closed state, thereby completing the function of controlling the opening and closing of the power supply switch SW1 by the non-standard detection control signal.

[0025] Furthermore, the USBC protocol chip is configured in dual-port detection mode. When no external USBC interface device is inserted, square waves are displayed on the CC1 and CC2 pins of the USBC connector. The square wave on the CC1 pin is low-pass filtered by the ninth resistor R9, the first capacitor C1, and the eighth resistor R8 to generate a voltage sufficient to turn on the seventh NMOS transistor Q7. The square wave on the CC2 pin is low-pass filtered by the tenth resistor R10, the second capacitor C2, and the eleventh resistor R11 to generate a voltage sufficient to turn on the eighth NMOS transistor Q8. The seventh NMOS transistor Q7 and the eighth NMOS transistor Q8 are connected in series. When a non-standard USBC cable is inserted, CC1 and CC2 are pulled up simultaneously, the sixth NMOS transistor Q6 is cut off, and the fifth NMOS transistor Q5 is turned on, thereby turning on the first PMOS transistor Q1 and the second PMOS transistor Q2, thus completing the non-standard logic detection function provided by the non-standard detection circuit module.

[0026] Beneficial effects:

[0027] This invention solves the problem of older products being unable to detect non-standard USBC cables. It eliminates the need to explain to customers which USBC cables are non-standard and cannot be used, and to require customers to purchase the corresponding standard protocol cables. This saves customers time and costs, while also improving product compatibility. Attached Figure Description

[0028] Figure 1 This is the logic diagram for the USB-C power supply operating mode;

[0029] Figure 2 This is a typical diagram of non-marked lines;

[0030] Figure 3 This is a circuit architecture diagram of the improved USBC interface device of this invention;

[0031] Figure 4 This is a detailed circuit diagram of the power supply switch SW1 of the present invention;

[0032] Figure 5 This is a detailed circuit diagram of the entire invention after superimposing non-standard detection logic. Detailed Implementation

[0033] The principles and spirit of the present invention will now be described with reference to several exemplary embodiments. It should be understood that these embodiments are provided merely to enable those skilled in the art to better understand and implement the present invention, and are not intended to limit the scope of the present invention in any way. Rather, these embodiments are provided to make this disclosure more thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art.

[0034] Those skilled in the art will recognize that embodiments of the present invention can be implemented as a system, apparatus, device, method, or computer program product. Therefore, this disclosure can be specifically implemented in the following forms: entirely hardware, entirely software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0035] According to an embodiment of the present invention, an improved circuit structure for a USBC interface device is proposed, which enables non-standard USBC cables to be recognized by the USBC protocol chip in the same way as standard USBC cables, thereby avoiding the need for customers to remember which specific terminal devices these outwardly identical but internally incompatible USBC cables can only be used with.

[0036] The principles and spirit of the present invention will be explained in detail below with reference to several representative embodiments.

[0037] Figure 3 This is a schematic diagram of the circuit structure of the improved USBC interface device of this invention. (See diagram below.) Figure 3 As shown, under normal circumstances, the USBC protocol chip determines whether a device is in master or slave mode by detecting the CC1 and CC2 voltages in the USBC connector, and communicates with the CPU via the I2C signal bus. If a master mode device is inserted, the power switch SW1 is turned off, and the inserted master mode device provides voltage to the system. At this time, the internal system 5V_SYS voltage and the external USBC cable's 5V_USBC voltage are combined to power the system simultaneously. If a slave mode device is inserted, the power switch SW1 is turned off, and the internal system 5V_SYS voltage powers the external USBC interface device through the USBC connector interface. If the external USBC interface device is unplugged, the power switch SW1 is turned off, cutting off the connection between the internal system 5V_SYS voltage and the external USBC cable's 5V_USBC voltage. A non-standard detection circuit module is added outside the standard USBC protocol chip. After a non-standard USBC cable is inserted, the non-standard detection circuit module provides additional logic determination by detecting the CC1 and CC2 voltages in the USBC connector and outputs a non-standard detection control signal to control the opening and closing of the power switch SW1.

[0038] The detailed circuit design of power switch SW1 is as follows: Figure 4 As shown:

[0039] Q1 and Q2 are PMOS transistors. Regardless of whether the internal system voltage 5V_SYS or the external USBC cable connection voltage 5V_USBC is established, a detection voltage of approximately 4.7V can be provided to the network gate through the body diodes of the first PMOS transistor Q1 and the second PMOS transistor Q2, where the body diode voltage drop is approximately 0.3V. When the external USBC interface device is not powered by any other power source, the 5V_USBC connection from the external USBC cable provides the power supply voltage. At this time, the fourth NMOS transistor Q4 is turned off, and the third NMOS transistor Q3 is turned on by the voltage divider formed by the second resistor R2 and the third resistor R3, thereby turning on the first PMOS transistor Q1 and the second PMOS transistor Q2, connecting the internal system voltage 5V_SYS with the external USBC cable. The 5V USBC voltage connection connected to the BC cable powers the external USBC interface device. At this time, the CPU (Central Processing Unit) takes over the CPU_control signal. When the CPU_control signal is set to low level, the fourth NMOS transistor Q4 is cut off and the third NMOS transistor Q3 is turned on, making the first PMOS transistor Q1 and the second PMOS transistor Q2 in the open state. When the CPU_control signal is set to high level, the fourth NMOS transistor Q4 is turned on and the third NMOS transistor Q3 is cut off, making the first PMOS transistor Q1 and the second PMOS transistor Q2 in the closed state, thus completing the function of the CPU_control signal controlling the opening and closing of the power supply switch SW1.

[0040] If the external USBC interface device is powered by another power source, causing the internal system voltage 5V_SYS to be established before the external USBC cable access voltage 5V_USBC, then the CPU controls the switching of the first PMOS transistor Q1 and the second PMOS transistor Q2.

[0041] The overall circuit design after superimposing non-standard detection logic is as follows: Figure 5 As shown:

[0042] First, resistors R1, R2, R3, and R4, along with PMOS transistors Q1, Q2, Q3, and Q4, are used to control the power supply switch SW1 via the CPU_control signal (see above for details). Then, resistors R5 and R7, along with NMOS transistors Q5 and Q6, are added to control the power supply switch SW1 via the non-standard detection control signal. Specifically, when the non-standard detection control signal is set to low, NMOS transistor Q6 is cut off, and NMOS transistor Q5 is turned on by the voltage divider formed by resistors R5 and R7, thus turning on PMOS transistors Q1 and Q2. When the non-standard detection control signal is set to high, NMOS transistor Q6 is turned on, and NMOS transistor Q5 is cut off, thus turning off PMOS transistors Q1 and Q2. Then, through resistors R8 (eighth), R9 (ninth), R10 (tenth), R11 (eleventh), C1 (first), C2 (second), Q7 (seventh), and Q8 (eighth), the non-standard logic detection function provided by the non-standard detection circuit module is completed. Specifically, the USB-C protocol chip is first configured in dual-port detection mode via software configuration. When no external USB-C interface device is inserted, a square wave is presented on the CC1 and CC2 pins of the USB-C connector. The square wave on the CC1 pin passes through resistor R9 (ninth), capacitor C1 (first), and Q8 (eighth). After low-pass filtering by resistor R8, a voltage sufficient to turn on the seventh NMOS transistor Q7 is generated; the square wave on pin CC2, after low-pass filtering by resistor R10, capacitor C2, and resistor R11, generates a voltage sufficient to turn on the eighth NMOS transistor Q8; the seventh NMOS transistor Q7 and the eighth NMOS transistor Q8 are connected in series; when a non-standard USB-C cable is inserted, CC1 and CC2 are pulled up simultaneously, the sixth NMOS transistor Q6 is turned off, and the fifth NMOS transistor Q5 is turned on, thereby turning on the first PMOS transistor Q1 and the second PMOS transistor Q2.

[0043] Figure 5 In this configuration, the third NMOS transistor Q3 and the fifth NMOS transistor Q5 are connected in parallel, and their turn-on processes are independent of each other. This parallel structure can achieve an "OR" logic output, allowing the CPU_control signal to independently control the opening and closing of the USBC power supply line when no external USBC interface device is plugged in, thus reserving space for potential future expansion applications.

[0044] This circuit improvement enables the terminal circuit to simultaneously use both standard and non-standard USBC cables to perform normal USBC port device insertion and removal detection.

[0045] It should be noted that although several modules of the improved circuit structure of the USBC interface device have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of the present invention, the features and functions of two or more modules described above can be embodied in a single module. Conversely, the features and functions of a single module described above can be further divided and embodied by multiple modules.

[0046] The main improvements of this invention are as follows:

[0047] 1. The power supply switch SW1 has been improved. The conventional design uses a diode to isolate 5V_SYS and 5V_USBC. This approach is only suitable for internal system voltages higher or lower than 5V. If the internal system voltage requirement is 5V, the voltage drop across the diode will prevent the required voltage from being met (typically, 5V is used as the system voltage in the final product due to overall design cost considerations). The improved design uses a PMOS switch, which can handle larger currents while the voltage drop is negligible.

[0048] 2. A simple resistor-capacitor integration circuit is used for voltage acquisition, and a MOS circuit is used for switching logic control. This not only effectively prevents voltage jitter during USBC cable insertion and removal, but also complements the USBC protocol chip's functionality, improving compatibility between standard and non-standard USBC cables on the same device. When detecting voltage, the duty cycle range of the square waves generated on CC1 and CC2 in the dual-port mode of the USBC protocol must be referenced. The maximum values ​​of the turn-on voltages of Q7 and Q8 must be considered, along with the jitter that may occur during insertion and removal and the human perception of delay, to comprehensively calculate the values ​​of each resistor and capacitor, and select the corresponding MOS.

[0049] When selecting components and setting parameters, you can refer to the following process to ensure that the circuit can function properly by avoiding the discrete characteristics of component parameters:

[0050] (1) Based on the cost principle, the cheapest NMOS is selected as the switch. At this time, 2N7002 can be selected as Q3, Q4, Q5, Q6, Q7, and Q8. The turn-on voltage Vgs required for its conduction is 1-2V. After reserving a 10% margin, 2.2V is selected as the turn-on voltage of Q7 and Q8. Therefore, the turn-on voltage of Q7 and Q8 is defined as 2.2V.

[0051] (2) Next, select PMOS as Q1 and Q2 according to the current required by the USBC interface device. If the current is required to be 3A, SI2323 can be selected.

[0052] (3) In dual-port mode, when a non-standard line is inserted, a square wave signal will appear on CC1 and CC2, with a duty cycle range of approximately 0.64-0.7. The larger the duty cycle, the higher the equivalent turn-on voltage. Here, the minimum duty cycle of 64% is selected.

[0053] (4) The USBC voltage range is defined as 4.75V-5.25V. The lower the USBC power supply voltage, the smaller the high level of the square wave output by CC1 and CC2, making it more difficult to enable Q7 and Q8. Therefore, the lowest power supply voltage of 4.75V is selected, and 4.5V is defined as the USBC power supply voltage after reserving a 5% margin. Under this condition, after the non-standard cable is inserted, the high level of the square wave output by the USBC protocol chip on CC1 and CC2 is about 4.25V, and the low level is about 0.39V. Therefore, the parameters of the square wave are defined as 4.25V for the high level and 0.39V for the low level.

[0054] (5) To avoid calculating the differential equations, the approximate calculation of the resistance and capacitance parameters is as follows:

[0055] Based on cost principles, capacitors C1 and C2 are selected as 1uF. According to the voltage rise time of the RC circuit t = RC = 1s (this time length does not affect the user's experience of plugging and unplugging USBC), R9 = R10 = 1M ohms are obtained.

[0056] The average voltage provided by the square wave is 4.25V * 64% + 0.39V * 36% = 2.87V, which serves as the charging voltage for capacitors C1 and C2. Discharge resistors R8 and R11 are also needed to ensure that capacitors C1 and C2 discharge quickly and return to normal operation when the USB-C device is unplugged. Based on the turn-on voltage of Q7 and Q8 (2.2V) and the charging voltage of 2.87V, the calculation is as follows: 2.2V * 1M ohm

[0057] / (2.87V-2.2V)=3.28M ohms, engineering selection R8=R11=3.6M ohms. With this circuit, the maximum turn-on time does not exceed 3s, and the discharge time does not exceed 1s, meeting customer experience requirements.

[0058] 3. Using more complex CPU software for detection and judgment would be too costly, while this circuit not only perfectly solves the requirements but also has a negligible cost.

[0059] While the spirit and principles of the invention have been described with reference to several specific embodiments, it should be understood that the invention is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined for benefit; such division is merely for ease of description. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0060] Regarding the limitation of the scope of protection of this invention, those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solution of this invention are still within the scope of protection of this invention.

Claims

1. An improved circuit structure for a USB-C interface device, characterized in that, The structure includes a CPU, a USB-C protocol chip, a USB-C connector, a non-standard detection circuit module, and a power switch SW1. The USB-C protocol chip determines whether the device is in master or slave mode by detecting the voltages CC1 and CC2 in the USB-C connector, and communicates with the CPU via the I2C signal bus. After a non-standard USB-C cable is inserted, the non-standard detection circuit module provides additional logic by detecting the voltages CC1 and CC2 in the USB-C connector, and outputs a non-standard detection control signal to control the opening and closing of the power switch SW1. The USB-C protocol chip is configured in dual-port detection mode; when no external USB-C interface device is inserted, the voltages CC1 and CC2 in the USB-C connector are detected. The square wave on pin 2 is in the form of a square wave. The square wave on pin CC1 is low-pass filtered by resistor R9, capacitor C1, and resistor R8 to generate a voltage sufficient to turn on the seventh NMOS transistor Q7. The square wave on pin CC2 is low-pass filtered by resistor R10, capacitor C2, and resistor R11 to generate a voltage sufficient to turn on the eighth NMOS transistor Q8. The seventh NMOS transistor Q7 and the eighth NMOS transistor Q8 are connected in series. When a non-standard USB-C cable is inserted, CC1 and CC2 are pulled up simultaneously, the sixth NMOS transistor Q6 is turned off, and the fifth NMOS transistor Q5 is turned on, thereby turning on the first PMOS transistor Q1 and the second PMOS transistor Q2, thus completing the non-standard logic detection function provided by the non-standard detection circuit module.

2. The improved circuit structure of the USB-C interface device according to claim 1, characterized in that, If a master mode device is inserted, power switch SW1 is turned off, and the inserted master mode device provides voltage to the system. At this time, the internal system 5V_SYS voltage and the external USBC cable 5V_USBC voltage are combined to power the system. If a slave mode device is inserted, power switch SW1 is turned off, and the internal system 5V_SYS voltage powers the external USBC interface device through the USBC connector. If the external USBC interface device is unplugged, power switch SW1 is turned off, cutting off the connection between the internal system 5V_SYS voltage and the external USBC cable 5V_USBC voltage.

3. The circuit structure of the improved USB-C interface device according to claim 1, characterized in that, In the circuit of power switch SW1, the internal system voltage 5V_SYS or the external USBC cable connection voltage 5V_USBC is established by providing a 4.7V detection voltage to the network gate through the body diode of the first PMOS transistor Q1 and the second PMOS transistor Q2, where the body diode voltage drop is 0.3V. When the external USBC interface device has no other power supply, the 5V_USBC connection from the external USBC cable provides the power supply voltage. At this time, the fourth NMOS transistor Q4 is turned off, and the third NMOS transistor Q3 is turned on by the voltage divider of the second resistor R2 and the third resistor R3, thereby turning on the first PMOS transistor Q1 and the second PMOS transistor Q2, and connecting the internal system voltage 5V_SYS with the external... The 5V USBC voltage connection connected to the USBC cable powers the external USBC interface device. At this time, the CPU takes over the CPU_control signal. When the CPU_control signal is set to low level, the fourth NMOS transistor Q4 is cut off and the third NMOS transistor Q3 is turned on, making the first PMOS transistor Q1 and the second PMOS transistor Q2 in the open state. When the CPU_control signal is set to high level, the fourth NMOS transistor Q4 is turned on and the third NMOS transistor Q3 is cut off, making the first PMOS transistor Q1 and the second PMOS transistor Q2 in the closed state, thus completing the function of the CPU_control signal controlling the opening and closing of the power supply switch SW1.

4. The improved circuit structure of the USB-C interface device according to claim 3, characterized in that, If the external USBC interface device is powered by another power source, causing the internal system voltage 5V_SYS to be established before the external USBC cable access voltage 5V_USBC, then the CPU controls the switching of the first PMOS transistor Q1 and the second PMOS transistor Q2.

5. The improved circuit structure of the USB-C interface device according to claim 3, characterized in that, When a non-standard USB-C cable is inserted, if the non-standard detection control signal is set to low, the sixth NMOS transistor Q6 is turned off, and the fifth NMOS transistor Q5 is turned on by the voltage divider of the fifth resistor R5 and the seventh resistor R7, causing the first PMOS transistor Q1 and the second PMOS transistor Q2 to be in the open state. If the non-standard detection control signal is set to high, the sixth NMOS transistor Q6 is turned on, and the fifth NMOS transistor Q5 is turned off, causing the first PMOS transistor Q1 and the second PMOS transistor Q2 to be in the closed state, thus completing the function of controlling the opening and closing of the power supply switch SW1 by the non-standard detection control signal.

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