Signal transmission device, server mainboard and server signal transmission system

Abstract

This application provides a signal transmission device, a server motherboard, and a server signal transmission system. The device includes a first processor and a second processor. The first processor generates target status information based on a first signal acquired from a first signal pin. The second processor determines a third signal pin from among multiple second signal pins that corresponds to the target information type of the target status information. The third signal pin is then used to send an indication signal corresponding to the operating status indicated by the target status information to a data center security control device. This application solves the problem of low signal transmission efficiency between the host processor and the data center security control device, thereby improving the signal transmission efficiency between them.

Description

Technical Field

[0001] This application relates to the field of computers, and more specifically, to a signal transmission device, a server motherboard, and a server signal transmission system. Background Technology

[0002] With the rise of big data and AI (Artificial Intelligence) fields, the market demand for servers with high computing performance is increasing. Data centers are also growing in scale. At the same time, there is a growing call for standardized data center management. Therefore, adopting a standardized modular design approach to accommodate the security management needs of different platforms, reduce redundant R&D resource investment, and accelerate product iteration has become an important development trend for data centers to adapt to changing needs and continuously upgrade. The DC-SCM (Data Center-ready Secure Control Module) project stems from this need. By configuring the DC-SCM circuit board, common management, security, and control functions can be separated from the motherboard and transferred to a smaller DC-SCM circuit board. The DC-SCM circuit board connects to the motherboard via a connector, and it can contain all the firmware states previously housed on the motherboard (BMC (Baseboard Management Controller), TPM (Trusted Platform Module), BootFlash, ROT (Root of Trust), etc.). In the current trend of modular design, DC-SCM faces incompatibility with traditional designs, posing a significant challenge to the smooth upgrade of hardware and software. In traditional designs, devices implementing management, security, and control functions have ample GPIO (General Purpose Input Output) resources on the motherboard. Hardware designs typically connect the status directly to these devices via GPIOs, allowing them to directly read GPIO states to determine their current hardware status. The motherboard's status is then directly transmitted to these devices via GPIOs, ensuring a secure and reliable acquisition of the motherboard's current state. However, with DC-SCM designs, the limited number of pins restricts the allocation of pins for devices with management, security, and control functions on the DC-SCM circuit board. This limits the devices' ability to obtain motherboard status information, leading to signal transmission failures for some devices. Summary of the Invention

[0003] This application provides a signal transmission device, a server motherboard, and a server signal transmission system to at least solve the problem of low signal transmission efficiency between host processors and data center security control devices in related technologies.

[0004] According to one embodiment of this application, a signal transmission device is provided, comprising:

[0005] A first processor and a second processor, wherein the first processor is configured with a plurality of first signal pins and a first transmission port, and the second processor is configured with a plurality of second signal pins and a second transmission port, the server includes: a host processor and an external socket for a data center security control device, wherein the plurality of first signal pins are used to be connected one-to-one with the signal pins of the host processor, the first transmission port is used to be connected to a target pin of the external socket, the second transmission port is used to be connected to a signal pin corresponding to the target pin on the external socket, and the plurality of second signal pins are used to be connected one-to-one with the signal pins of the data center security control device;

[0006] The first processor is configured to generate target status information based on a first signal acquired by the first signal pin, wherein the target status information is used to indicate the current operating status of the host processor; and transmit the target status information to the second processor through the first transmission port.

[0007] The second processor is configured to determine, among a plurality of second signal pins, a third signal pin corresponding to the target information type to which the target status information belongs; and to send an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin.

[0008] Optionally, the first processor is further configured to: detect level change information of each of the plurality of first signal pins; when the level change information indicates a change in the level value of a fourth signal pin among the plurality of first signal pins, detect the current first level value on the fourth signal pin, wherein the first signal includes the first level value; obtain a first pin identifier of the fourth signal pin among the plurality of first signal pins; and generate a first status message based on the first pin identifier and the first level value, wherein the first status message indicates the level output status of the host processor on the fourth signal pin, and the target status information includes the first status message.

[0009] Optionally, the first processor is further configured to: add the first pin identifier to the first field position in the initial status message corresponding to the host processor to obtain a second status message, wherein the first field position is the field position in the initial status message used to store the pin identifier of the pin that has undergone a level change; add the first level value to the second field position in the second status message to obtain a third status message, wherein the second field position is the field position in the second status message used to store the level value of the pin after the level change; add a status change field to the header position of the third status message to obtain the first status message, wherein the status change field is used to indicate that a level change has occurred on the signal pin of the host processor.

[0010] Optionally, the second processor is further configured to: detect the fields carried in the header of the initial message received in the second transmission port; if the field carried in the header is a state change field, determine the initial message as a first state message sent by the host processor, wherein the target state information includes the first state message, the state change field is used to indicate that a level change has occurred on the signal pin of the host processor, and the first state message carries information for indicating the level value on the signal pins among a plurality of the first signal pins where a level value change has occurred.

[0011] Optionally, the second processor is further configured to extract a first pin identifier carried in the first status message from a first field position in the first status message, and extract a first level value carried in the first status message from a second field position in the first status message, wherein the first status message carries information for indicating the level value of a signal pin among a plurality of first signal pins that has undergone a level value change, the target status information including the first status message, the first pin identifier for indicating the signal pin among a plurality of first signal pins that has undergone a level value change, and the first level value being the current level value of the signal pin among a plurality of first signal pins that has undergone a level value change; determine the target information type of the information transmitted on the first signal pin indicated by the first pin identifier; determine the third signal pin corresponding to the target information type from the information types with corresponding relationships and the plurality of second signal pins; and control the third signal pin to output the indication signal corresponding to the first level value.

[0012] Optionally, the first processor is configured with a third transmission port, and the second processor is configured with a fourth transmission port. The third transmission port is used to connect to a reference pin of the external socket, and the fourth transmission port is used to connect to a signal pin corresponding to the reference pin on the external socket.

[0013] The second processor is configured to generate target control information based on second signals acquired from multiple second signal pins, wherein the second signal is a signal output by the data center security control device for controlling the operating state of the host processor, and the target control information is used to characterize the operating state of the host processor to be switched; and transmit the target control information to the first processor through the fourth transmission port;

[0014] The first processor is configured to determine, from a plurality of first signal pins, a fifth signal pin corresponding to the target state type controlled by the target control information; and to send a state control instruction corresponding to the operating state indicated by the target control information to the host processor via the fifth signal pin.

[0015] Optionally, the second processor is further configured to locate the sixth signal pin that acquired the second signal from among a plurality of second signal pins; add the second pin identifier of the sixth signal pin to the third field position of the reference status message corresponding to the data center security control device, and add the second level value of the second signal to the fourth field position of the reference status message to obtain a fourth status message, wherein the third field position is the field position in the reference status message used to store the pin identifier of the pin that generated the signal, and the fourth field position is the field position in the reference status message used to store the pin level value; add an identifier field to the header position of the fourth status message to obtain a fifth status message, wherein the identifier field is used to indicate that the data center security control device has issued a control command to the host processor, and the target control information includes the fifth status message.

[0016] Optionally, the first processor is further configured to extract from the fifth status message a second pin identifier carried in the fifth status message and a second level value of the second signal, wherein the target control information includes the fifth status message, the second pin identifier is used to indicate the pin among a plurality of second signal pins that detects the second signal; determine the fifth signal pin corresponding to the target status type from the corresponding status types and the plurality of first signal pins; and control the fifth signal pin to output the status control command corresponding to the second level value.

[0017] According to another embodiment of this application, a server motherboard is provided, comprising:

[0018] The server motherboard is equipped with: a signal transmission device, a host processor, and an external socket for a data center security control device. The signal transmission device includes a first processor and a second processor. The first processor is configured with multiple first signal pins and a first transmission port. The second processor is configured with multiple second signal pins and a second transmission port. The multiple first signal pins are used to connect one-to-one with the signal pins of the host processor. The first transmission port is connected to a target pin of the external socket. The second transmission port is used to connect to the signal pin corresponding to the target pin on the external socket. The multiple second signal pins are used to connect one-to-one with the signal pins of the data center security control device.

[0019] The first processor is configured to generate target status information based on a first signal acquired by the first signal pin, wherein the target status information is used to indicate the current operating status of the host processor; and transmit the target status information to the second processor through the first transmission port.

[0020] The second processor is configured to determine, among a plurality of second signal pins, a third signal pin corresponding to the target information type to which the target status information belongs; and to send an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin.

[0021] According to another embodiment of this application, a server signal transmission system is provided, comprising:

[0022] The server is equipped with: a signal transmission device, a host processor, a data center security control device, and an external socket for the data center security control device. The signal transmission device includes a first processor and a second processor. The first processor is configured with multiple first signal pins and a first transmission port. The second processor is configured with multiple second signal pins and a second transmission port. The multiple first signal pins are used to connect one-to-one with the signal pins of the host processor. The first transmission port is connected to a target pin of the external socket. The second transmission port is used to connect to the signal pin corresponding to the target pin on the external socket. The multiple second signal pins are used to connect one-to-one with the signal pins of the data center security control device.

[0023] The first processor is configured to generate target status information based on a first signal acquired by the first signal pin, wherein the target status information is used to indicate the current operating status of the host processor; and transmit the target status information to the second processor through the first transmission port.

[0024] The second processor is configured to determine, among a plurality of second signal pins, a third signal pin corresponding to the target information type to which the target status information belongs; and to send an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin.

[0025] This application configures a first processor and a second processor, thereby configuring the first signal pin of the first processor to be connected one-to-one with the signal pin of the host processor, the first transmission port of the first processor to be connected to a target pin on the external socket of the data center security controller, the second transmission port of the second processor to be connected to the signal pin corresponding to the target pin on the external socket, and multiple second pins of the second processor to be connected one-to-one with the signal pins of the data center security controller. This achieves the connection of multiple signal pins of the host processor and multiple signal pins of the data center security control device through a single data transmission line via the first and second processors. Furthermore, the first processor generates target status information based on the first signal acquired from the first signal pin. The signal is transmitted to the second processor, which determines the third signal pin corresponding to the target information type from among multiple second signal pins. The second processor then sends an indication signal corresponding to the operating state indicated by the target status information to the data center security processor via the third signal pin. This achieves the transmission of status signals from multiple signal pins on the host processor to the data center security control device through a single transmission link. This process only requires one signal pin on the external socket of the data center security control device, avoiding the impact of insufficient signal pin configuration on signal transmission. Therefore, it can solve the problem of low signal transmission efficiency between the host processor and the data center security control device, thereby improving the signal transmission efficiency between them. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of a signal transmission device according to an embodiment of this application;

[0027] Figure 2 This is a schematic diagram of an optional status message according to an embodiment of this application;

[0028] Figure 3 This is a schematic diagram of an optional processor according to an embodiment of this application;

[0029] Figure 4 This is a schematic diagram of an optional bidirectional signal transmission according to an embodiment of this application. Detailed Implementation

[0030] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0032] This embodiment provides a signal transmission device. Figure 1 This is a schematic diagram of a signal transmission device according to an embodiment of this application, such as... Figure 1 As shown, the device includes:

[0033] A first processor and a second processor, wherein the first processor is configured with a plurality of first signal pins and a first transmission port, and the second processor is configured with a plurality of second signal pins and a second transmission port, the server includes: a host processor and an external socket for a data center security control device, wherein the plurality of first signal pins are used to be connected one-to-one with the signal pins of the host processor, the first transmission port is used to be connected to a target pin of the external socket, the second transmission port is used to be connected to a signal pin corresponding to the target pin on the external socket, and the plurality of second signal pins are used to be connected one-to-one with the signal pins of the data center security control device;

[0034] The first processor is configured to generate target status information based on a first signal acquired by the first signal pin, wherein the target status information is used to indicate the current operating status of the host processor; and transmit the target status information to the second processor through the first transmission port.

[0035] The second processor is configured to determine, among a plurality of second signal pins, a third signal pin corresponding to the target information type to which the target status information belongs; and to send an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin.

[0036] Through the above, by configuring the first processor and the second processor, and further configuring the first signal pin of the first processor to be connected one-to-one with the signal pin of the host processor, the first transmission port of the first processor to be connected to a target pin on the external socket of the data center security controller, the second transmission port of the second processor to be connected to the signal pin corresponding to the target pin on the external socket, and multiple second pins of the second processor to be connected one-to-one with the signal pins of the data center security controller, multiple signal pins of the host processor and multiple signal pins of the data center security control device are connected through a data transmission line via the first and second processors. The first processor then generates target status information based on the first signal acquired from the first signal pin. The signal is transmitted to the second processor, which determines the third signal pin corresponding to the target information type from among multiple second signal pins. The second processor then sends an indication signal corresponding to the operating state indicated by the target status information to the data center security processor via the third signal pin. This achieves the transmission of status signals from multiple signal pins on the host processor to the data center security control device through a single transmission link. This process only requires one signal pin on the external socket of the data center security control device, avoiding the impact of insufficient signal pin configuration on signal transmission. Therefore, it can solve the problem of low signal transmission efficiency between the host processor and the data center security control device, thereby improving the signal transmission efficiency between them.

[0037] Optionally, in this embodiment, the data center security control device deploys devices (including, but not limited to, BMC, TPM, Boot Flash, ROT, etc.) that enable server management, security, and control. To ensure simplified server motherboard design and server security, these devices, originally configured on the server motherboard, are moved to a smaller, general-purpose form factor module, thus encapsulating a data center security control device. This requires only one external socket on the server motherboard to connect the data center security control device to the server. In this embodiment, the data center security control device may be a DC-SCM (DatacenterSecure Control Module) circuit board, and the external socket may be a DC-SCM socket.

[0038] Optionally, in this embodiment of the application, the host processor may be, but is not limited to, the HOST of the server.

[0039] Optionally, in this embodiment, the first processor is a device that converts processor signals collected from multiple signal pins of a host processor connected to multiple first signal pins into status information that a second processor can recognize. This allows the host processor's status to be transmitted to the second processor via a single transmission link. This reduces the number of pins occupied by the external socket of the data center security control equipment when transmitting the host processor's status signals.

[0040] Optionally, in this embodiment, the second processor is a processor for identifying target status information and translating signals. That is, the second processor can identify the signal situation indicated by the target status information sent by the first processor, and convert the status signal output by the host processor carried in the target status information into an indication signal that the data center security control device can recognize, thereby realizing the transmission of the status signal output by the host processor to the data center security control device through the first processor and the second processor.

[0041] Optionally, in this embodiment of the application, the first processor can determine the first signal pin of the acquired first signal, and then generate indication information carrying the pin identifier of the signal pin that generated the first signal and the signal value of the first signal on the pin. The target state information includes the indication information. After receiving the indication information, the second processor can identify the state signal output of the host processor by recognizing the indication information.

[0042] Optionally, in this embodiment, in practical applications, the number of host processors deployed on the server motherboard can be multiple. To further optimize the issue of pin occupancy of external sockets when the server's host processor synchronizes signals with the data center security control equipment, multiple first sub-processors can be extended on the first processor. Each first sub-processor includes a first sub-transmission port and multiple first sub-signal pins. The N signal pins on the first processor can be connected to the first sub-transmission ports of the N first sub-processors. The multiple first sub-signal pins of each first sub-processor are connected one-to-one with the signal pins of the corresponding host processor. The first sub-processor is used to generate target status information based on the first sub-signal collected by the first sub-signal pins, wherein the target status information is used to indicate the current operating status of the host processor; the target status information is transmitted to the first processor through the first sub-transmission port, and the first processor recognizes that the target status information is transmitted by the first sub-transmission port and transmits the target status information to the second processor through the first transmission port.

[0043] Optionally, in this embodiment of the application, in practical applications, multiple data center security control devices may be deployed on the server. For example, different data center security control devices are used to perform corresponding management and control functions on the server. In order to further optimize the problem of the number of external socket pins occupied when the host processor of the server synchronizes signals to the data center security control device, multiple second sub-processors can be extended on the second processor. Each second sub-processor includes a second sub-transmission port and multiple second sub-signal pins. The N signal pins on the second processor can be connected to the second sub-transmission ports of the N second sub-processors. The multiple second sub-signal pins of each second sub-processor are connected one-to-one with the signal pins of the corresponding data center security control device. The second processor receives the target status information transmitted from the second transmission port. By identifying the target status information, it determines the data center security control device corresponding to the status signal of the host processor indicated by the target status information. Then, it sends the target status information to the second sub-processor through a second signal pin connected to the second sub-processor. The second sub-processor is used to determine a third signal pin from among multiple second sub-processor signal pins that corresponds to the target information type to which the target status information belongs. It then sends an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin.

[0044] As an optional embodiment, the first processor is further configured to: detect level change information of each of the plurality of first signal pins; when the level change information is used to indicate that the level value of a fourth signal pin among the plurality of first signal pins has changed, detect the current first level value on the fourth signal pin, wherein the first signal includes the first level value; obtain a first pin identifier of the fourth signal pin among the plurality of first signal pins; and generate a first status message based on the first pin identifier and the first level value, wherein the first status message is used to indicate the level output status of the host processor on the fourth signal pin, and the target status information includes the first status message.

[0045] Optionally, in this embodiment, the first processor is a component for connecting the DC-SCM socket and the host processor, used to transmit the changing state of the host processor to the DC-SCM circuit board, and is an intermediary component for signal transmission.

[0046] Optionally, in this embodiment, the first signal pin is connected one-to-one with the signal pins of the host processor. The first processor detects the level change of each first signal pin connected to the host processor. When the host processor state changes, that is, when the level of the first signal pin changes, the first processor detects the first signal pin with the changed level. The fourth signal pin is the first signal pin with the changed level. Simultaneously, the first processor detects and obtains the current first level value (the changed level value) and the first pin identifier on the fourth signal pin. The first pin identifier is the position identifier of the fourth pin among multiple first signal pins, determining which pin has experienced a level change. The first processor generates a first status message based on the first pin identifier and the first level value. The first status message indicates the level output state of the host processor on the fourth signal pin; that is, the first status message contains the position identifier information and level change information of the pin with the changed level.

[0047] Through the above, the first processor collects the level signals on each first signal pin, and then, after collecting changes in the level signals, converts the pin identifier of the collected first signal pin and the level value of the first signal into a status message, thereby ensuring the accuracy of the signal during transmission and avoiding incorrect signal identification by the second processor.

[0048] As an optional embodiment, the first processor is further configured to: add the first pin identifier to the first field position in the initial status message corresponding to the host processor to obtain a second status message, wherein the first field position is the field position in the initial status message used to store the pin identifier of the pin that has undergone a level change; add the first level value to the second field position in the second status message to obtain a third status message, wherein the second field position is the field position in the second status message used to store the level value of the pin after the level change; add a status change field to the header position of the third status message to obtain the first status message, wherein the status change field is used to indicate that a level change has occurred on the signal pin of the host processor.

[0049] Optionally, in this embodiment, after the first processor obtains the first level value and the first pin identifier, it adds the first pin identifier to the first field position in the initial status message to obtain the second status message. The initial status message is the initial status message corresponding to the host processor, used to represent the initial status information corresponding to the host processor. After obtaining the second message, the first processor adds the first level value to the second field position in the second message to obtain the third status message. The second field position is the field position in the second status message used to store the level value of the pin after a level change. Subsequently, the first processor adds a status change field to the third message header to obtain the first status message. The status change field is used to indicate that the level on the signal pin of the host processor has changed. Here, the status change field includes, but is not limited to, using field 0 to represent a change from high level to low level, and using field 1 to represent a change from low level to high level. The first status message can be encrypted using encryption methods, including but not limited to symmetric encryption and asymmetric encryption for more secure and reliable transmission.

[0050] Optionally, in this embodiment of the application, the status message may be, but is not limited to, a continuous string. Figure 2 This is a schematic diagram of an optional status message according to an embodiment of this application, such as... Figure 2 As shown, the status message is a continuous string, with each character having a different meaning. For example, the first character is the SYNC character, which indicates the signal enable status. When the host processor's GPIO TX is high by default, it is represented by the logic number 1. When the GPIO changes, the SYNC bit becomes 0. The second to second-to-last characters are pin identifier characters. In this embodiment, eight pins are used as an example: P0, P1, P2, P3, P4, P5, P6, P7, and P8. When a character is 0, it indicates that there is no change in the level signal of that pin. When a character is 1, it indicates that there is a change in the level signal of that pin. The last character of the string is the level value identifier, where VALUE represents the corresponding GPIO logic level value.

[0051] With the above configuration, the first processor processes the information on pin level changes and forms a status transmission message. This can securely transform multiple complex level state change information into a more secure, flexible, and compatible message format, improving the security of information transmission. The message can be flexibly configured and the transmitted information can be adjusted as needed, improving the flexibility of information transmission. The message can be extended with more status information and record more status information fields, enhancing the scalability of information transmission.

[0052] As an optional embodiment, the second processor is further configured to: detect the fields carried in the header of the initial message received in the second transmission port; if the field carried in the header is a state change field, determine the initial message as a first state message sent by the host processor, wherein the target state information includes the first state message, the state change field is used to indicate that a level change has occurred on the signal pin of the host processor, and the first state message carries information for indicating the level value on the signal pins where level changes have occurred among a plurality of the first signal pins.

[0053] Optionally, in this embodiment, the second processor is a component for connecting the DC-SCM socket and the data center security control device, for acquiring and parsing the first status message, obtaining target status information from the first status message, and sending the target status information to the corresponding data center security control device.

[0054] Optionally, in this embodiment, the second processor receives the initial message transmitted by the first processor and detects the fields carried in the header of the initial message. If the field carried in the header is detected to be a state change field, it can be determined that the received initial message is a first state message sent by the host processor, and a level change can be detected on the corresponding signal pin of the host processor. Conversely, if the field carried in the header does not contain a state change field, it indicates that no level change has occurred on the corresponding signal pin of the host processor.

[0055] By using the above processing methods, the second processor parses the fields carried in the header of the initial message to determine whether the signal pin level of the host processor has changed. This eliminates the need to process each field of every received initial message. Only when the message header carries status change information is the message further processed. Messages without status change fields are not processed, which improves the message processing and transmission speed and further enhances the response speed of the corresponding data center security control equipment.

[0056] As an optional embodiment, the second processor is further configured to extract a first pin identifier carried in the first status message from a first field position in the first status message, and extract a first level value carried in the first status message from a second field position in the first status message, wherein the first status message carries information for indicating the level value of a signal pin among a plurality of first signal pins that has undergone a level value change, the target status information including the first status message, the first pin identifier for indicating the signal pin among a plurality of first signal pins that has undergone a level value change, and the first level value being the current level value of the signal pin among a plurality of first signal pins that has undergone a level value change; determine the target information type of the information transmitted on the first signal pin indicated by the first pin identifier; determine the third signal pin corresponding to the target information type from the information types with corresponding relationships and the plurality of second signal pins; and control the third signal pin to output the indication signal corresponding to the first level value.

[0057] Optionally, in this embodiment, when the second processor determines that the field carried in the header of the received initial message is a state change field (i.e., after the received initial message is a first state message sent by the host processor), it extracts the first pin identifier from the first field position in the first state message and extracts the first level value carried in the first state message from the second field position. The first pin identifier is the position identifier of the signal pin of the host processor that has undergone a level change. Through this first pin identifier, the second controller can determine which parts of the host processor have changed state. The first level value is the level value of the signal pin of the host processor that has undergone a level change. Through the first level value, the second controller can determine how the corresponding part of the host processor has changed state. The second signal pin is connected to the data center security control equipment. After the second processor parses the first pin identifier, it can determine the second signal pin corresponding to the first pin identifier (i.e., the third signal pin) among the second signal pins connected to multiple data center security control devices. The second processor then controls the third signal pin to output an indication signal corresponding to the parsed first level value, and the device processes and reacts accordingly. The parsing process of the message fields by the second processor here includes, but is not limited to, the decryption process.

[0058] By using the above methods, the processing signals in a message can be parsed into indication signals for multiple corresponding devices, which not only improves the quality and speed of signal transmission, but also further enhances the response speed of multiple corresponding devices, greatly improving transmission efficiency.

[0059] As an optional embodiment, the first processor is configured with a third transmission port, and the second processor is configured with a fourth transmission port. The third transmission port is used to connect to a reference pin of the external socket, and the fourth transmission port is used to connect to a signal pin corresponding to the reference pin on the external socket.

[0060] The second processor is configured to generate target control information based on second signals acquired from multiple second signal pins, wherein the second signal is a signal output by the data center security control device for controlling the operating state of the host processor, and the target control information is used to characterize the operating state of the host processor to be switched; and transmit the target control information to the first processor through the fourth transmission port;

[0061] The first processor is configured to determine, from a plurality of first signal pins, a fifth signal pin corresponding to the target state type controlled by the target control information; and to send a state control instruction corresponding to the operating state indicated by the target control information to the host processor via the fifth signal pin.

[0062] Optionally, in this embodiment, the fourth transmission port may be the same as the second transmission port, changing from a two-wire transmission to a single-wire transmission, thus occupying fewer pins.

[0063] Optionally, in this embodiment, the third transmission port is configured on the first processor, and the fourth transmission port is configured on the second processor. The third transmission port is used to connect to a reference pin of the DC-SCM socket, and the fourth transmission port is used to connect to the signal pin corresponding to the reference pin on the DC-SCM socket. When the data center security control device is about to transmit a signal to the host processor, the second processor will collect the control information of the corresponding host processor of the data center security control device connected to it, and transmit the control information to the first processor through the fourth transmission port. The first processor receives the control information transmitted by the second processor, and determines the corresponding host signal pin (i.e., the fifth signal pin) in the control information from the signal pins of the host processor connected to it, and parses the control information to obtain the status command corresponding to the device control, and sends it to the corresponding host processor part through the fifth signal pin. The host processor can understand the operating status of the device and can control and change the operating status of the device. For example, if a device connected to the second processor is a fan, and the fan is currently stopped, the second processor connected to the fan will acquire the second signal that controls the fan's start and stop through the connected second signal pin. The second signal is the signal output by the fan that can control the operating state of the corresponding host processor. This signal can control the fan's start and stop. At this time, the signal indicates that the fan is stopped. The second processor will transmit the control information to the first processor. The first processor will parse the signal and find the corresponding pin of the host processor that controls the fan's start and stop. It will then send the fan's stop status information to the host processor through the corresponding pin. The host processor can then control and change the fan's operating state.

[0064] Optionally, in the embodiments of this application, the first processor and the second processor may be, but are not limited to, processors for transmitting GPIO signals. Figure 3 This is a schematic diagram of an optional processor according to an embodiment of this application, such as... Figure 3 As shown, the processor can be, but is not limited to, a functional module with GPIO signal conversion and transmission capabilities. Each GPIO module has three parts of peripheral pins: GPIO pins (i.e., signal pins, such as the first signal pin or the second signal pin) (GPIO1…GPIO1), GPIO TX (i.e., the first transmission port or the fourth transmission port), and GPIO RX (i.e., the second transmission port or the third transmission port).

[0065] GPIO1…GPION are general-purpose pins that can be used in ordinary peripheral circuit design.

[0066] GPIO TX is the GPIO status transmission pin. When the state of GPIO1 changes, GPIO TX sends the GPIO level data to the peer module through the protocol frame.

[0067] GPIO RX is the GPIO status receive pin. When the GPIO status of the peer changes, it receives the protocol frame and sets the corresponding GPIO status to the appropriate state.

[0068] As an optional embodiment, the second processor is further configured to locate the sixth signal pin that acquired the second signal from among a plurality of second signal pins; add the second pin identifier of the sixth signal pin to the third field position of the reference status message corresponding to the data center security control device, and add the second level value of the second signal to the fourth field position of the reference status message to obtain a fourth status message, wherein the third field position is the field position in the reference status message used to store the pin identifier of the pin that generated the signal, and the fourth field position is the field position in the reference status message used to store the pin level value; add an identifier field to the header position of the fourth status message to obtain a fifth status message, wherein the identifier field is used to indicate that the data center security control device has issued a control command to the host processor, and the target control information includes the fifth status message.

[0069] Optionally, in this embodiment, the sixth signal pin is the signal connection pin of the connected target device located and acquired by the second processor. The second processor adds the second pin identifier of the sixth signal pin (i.e., the location identifier of the target device signal connection pin) to the third field of the reference status message corresponding to the data center security control device, and adds the second level value (the current level value of the device) in the linked device status information (second signal) to the fourth field of the reference status message to obtain a fourth status message. An identifier field is added to the header of the fourth status message to obtain a fifth status message. The second controller transmits the fifth status message to the first controller through the fourth transmission port. The above message processing and transmission process includes, but is not limited to, symmetric encryption and asymmetric encryption.

[0070] The above method allows the status information of multiple devices to be written into the transmission message, transforming complex device status information into a simple and unified message for transmission, thereby improving the efficiency and speed of signal transmission.

[0071] As an optional embodiment, the first processor is further configured to extract from the fifth status message a second pin identifier carried in the fifth status message and a second level value of the second signal, wherein the target control information includes the fifth status message, the second pin identifier is used to indicate the pin among a plurality of second signal pins that detects the second signal; determine the fifth signal pin corresponding to the target status type from the corresponding status types and the plurality of first signal pins; and control the fifth signal pin to output the status control command corresponding to the second level value.

[0072] Optionally, in this embodiment of the application, the first processor receives the fifth status message transmitted by the second processor, extracts the second pin identifier and the second level value from the fifth status message, determines the signal pin of the host processor corresponding to the second pin identifier, and sends the second level value to the signal pin of the host processor. The host processor can then determine the transmitted device status and change the operating status of the corresponding device through control commands.

[0073] Through the above configuration and process, the information transmission process achieves a closed loop. The host processor can know the operating status of each device and can change the operating status of the device through the device in this application. Each connected device can also feed back the latest operating status to the host through the device in this application. This convenient closed-loop transmission mode can complete efficient signal communication with very few connection resources, which greatly improves the communication efficiency and speed between the device and the host.

[0074] As an alternative implementation, this paper proposes a GPIO pass-through scheme based on DC-SCM design. This scheme enables a smooth upgrade of traditional BMC designs through the interconnection of GPIO modules, taking the power status in a server design as an example. In traditional designs, the power status is directly connected to the BMC management chip AST2600 via GPIO. In the DC-SCM design, we achieve seamless software design upgrades by using GPIO pass-through between GPIO A (the second processor) and GPIO B (the first processor) modules for GPIO pass-through.

[0075] Figure 4 This is a schematic diagram of an optional bidirectional signal transmission according to an embodiment of this application, such as... Figure 4 As shown,

[0076] The motherboard's power status is indicated by Power Status B, where a high level indicates that the host is powered on, and a low level indicates that the host is powered off.

[0077] The BMC controls the power-on and power-off operation of the host by controlling Power Ctrl A. A high level on Power Ctrl A controls the host to power on, and a low level on Power Ctrl A controls the host to power off.

[0078] Step 1: With the HOST powered off, Power Status B is low, indicating a power-off state. GPIO module B synchronizes Power Status B to Power Status A of GPIO module A via GPIO TX. The BMC software running on the AST2600 detects that the HOST is powered off through the GPIO status.

[0079] Step 2: The BMC needs to control the host to power on. The BMC sets Power Ctrl A to a high level. GPIO module A transmits the state of Power Ctrl A to GPIO module B (Power Ctrl B) via GPIO TX. The host can then detect the change in the power control button state and control the host to power on.

[0080] Step 3: After the host powers on, Power Status B is set high, triggering the synchronization mechanism. GPIO module B transmits Power Status B to GPIO module A via GPIO TX, which in turn transmits Power Status A. Similarly, the BMC can directly obtain the host's power-on status through the GPIO status.

[0081] Step 4: The BMC controls the HOST to power down. The BMC sets Power Ctrl A to a low level. GPIO module A transmits the state of Power Ctrl A to GPIO module B (Power Ctrl B) via GPIOTX. The HOST can then detect the change in the power control button state and control the HOST to shut down.

[0082] Step 5: The HOST enters the power-off state. Power Status B is low, indicating the power-off state. GPIO module B synchronizes Power Status B to Power Status A of GPIO module A through GPIO TX. The BMC software detects that the HOST is in the power-off state through the GPIO status and completes the information loop.

[0083] Through the above embodiments, a GPIO pass-through scheme based on DC-SCM design is proposed. That is, the GPIO function is transmitted through a bidirectional GPIO expansion module, which simplifies BMC software design. In today's modular design, it can realize smooth upgrade of BMC software, improve software maintainability, reduce R&D cost investment, and has objective economic benefits.

[0084] Taking the Power Status / Power Ctrl as an example, after adopting the DC-SCM design, the existing BMC software needs to be modified to adapt to the new hardware architecture due to insufficient GPIO resources. After adopting this solution, the BMC software does not need to be upgraded and can directly reuse the design of the previous generation of products, which greatly shortens the server development cycle, realizes the smooth upgrade of the server software platform, and improves the competitiveness of server products.

[0085] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0086] This embodiment provides a server motherboard, on which are deployed a signal transmission device, a host processor, and an external socket for a data center security control device. The signal transmission device includes a first processor and a second processor. The first processor is configured with a plurality of first signal pins and a first transmission port. The second processor is configured with a plurality of second signal pins and a second transmission port. The plurality of first signal pins are used to connect one-to-one with the signal pins of the host processor. The first transmission port is connected to a target pin of the external socket. The second transmission port is used to connect to a signal pin corresponding to the target pin on the external socket. The plurality of second signal pins are used to connect one-to-one with the signal pins of the data center security control device.

[0087] The first processor is configured to generate target status information based on a first signal acquired by the first signal pin, wherein the target status information is used to indicate the current operating status of the host processor; and transmit the target status information to the second processor through the first transmission port.

[0088] The second processor is configured to determine, among a plurality of second signal pins, a third signal pin corresponding to the target information type to which the target status information belongs; and to send an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin.

[0089] Through the above, by configuring the first processor and the second processor, and further configuring the first signal pin of the first processor to be connected one-to-one with the signal pin of the host processor, the first transmission port of the first processor to be connected to a target pin on the external socket of the data center security controller, the second transmission port of the second processor to be connected to the signal pin corresponding to the target pin on the external socket, and multiple second pins of the second processor to be connected one-to-one with the signal pins of the data center security controller, multiple signal pins of the host processor and multiple signal pins of the data center security control device are connected through a data transmission line via the first and second processors. The first processor then generates target status information based on the first signal acquired from the first signal pin. The signal is transmitted to the second processor, which determines the third signal pin corresponding to the target information type from among multiple second signal pins. The second processor then sends an indication signal corresponding to the operating state indicated by the target status information to the data center security processor via the third signal pin. This achieves the transmission of status signals from multiple signal pins on the host processor to the data center security control device through a single transmission link. This process only requires one signal pin on the external socket of the data center security control device, avoiding the impact of insufficient signal pin configuration on signal transmission. Therefore, it can solve the problem of low signal transmission efficiency between the host processor and the data center security control device, thereby improving the signal transmission efficiency between them.

[0090] This embodiment provides a server signal transmission system. The server is equipped with: a signal transmission device, a host processor, a data center security control device, and an external socket for the data center security control device. The signal transmission device includes a first processor and a second processor. The first processor is configured with a plurality of first signal pins and a first transmission port. The second processor is configured with a plurality of second signal pins and a second transmission port. The plurality of first signal pins are used to connect one-to-one with the signal pins of the host processor. The first transmission port is connected to a target pin of the external socket. The second transmission port is used to connect to a signal pin corresponding to the target pin on the external socket. The plurality of second signal pins are used to connect one-to-one with the signal pins of the data center security control device.

[0091] The first processor is configured to generate target status information based on a first signal acquired by the first signal pin, wherein the target status information is used to indicate the current operating status of the host processor; and transmit the target status information to the second processor through the first transmission port.

[0092] The second processor is configured to determine, among a plurality of second signal pins, a third signal pin corresponding to the target information type to which the target status information belongs; and to send an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin.

[0093] Through the above, by configuring the first processor and the second processor, and further configuring the first signal pin of the first processor to be connected one-to-one with the signal pin of the host processor, the first transmission port of the first processor to be connected to a target pin on the external socket of the data center security controller, the second transmission port of the second processor to be connected to the signal pin corresponding to the target pin on the external socket, and multiple second pins of the second processor to be connected one-to-one with the signal pins of the data center security controller, multiple signal pins of the host processor and multiple signal pins of the data center security control device are connected through a data transmission line via the first and second processors. The first processor then generates target status information based on the first signal acquired from the first signal pin. The signal is transmitted to the second processor, which determines the third signal pin corresponding to the target information type from among multiple second signal pins. The second processor then sends an indication signal corresponding to the operating state indicated by the target status information to the data center security processor via the third signal pin. This achieves the transmission of status signals from multiple signal pins on the host processor to the data center security control device through a single transmission link. This process only requires one signal pin on the external socket of the data center security control device, avoiding the impact of insufficient signal pin configuration on signal transmission. Therefore, it can solve the problem of low signal transmission efficiency between the host processor and the data center security control device, thereby improving the signal transmission efficiency between them.

[0094] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0095] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A signal transmission device, Its features are, include: A first processor and a second processor, wherein the first processor is configured with a plurality of first signal pins and a first transmission port, and the second processor is configured with a plurality of second signal pins and a second transmission port, the server includes: a host processor and an external socket for a data center security control device, wherein the plurality of first signal pins are used to be connected one-to-one with the signal pins of the host processor, the first transmission port is used to be connected to a target pin of the external socket, the second transmission port is used to be connected to a signal pin corresponding to the target pin on the external socket, and the plurality of second signal pins are used to be connected one-to-one with the signal pins of the data center security control device; The first processor is configured to generate target status information based on a first signal acquired by the first signal pin, wherein the target status information is used to indicate the current operating status of the host processor; and transmit the target status information to the second processor through the first transmission port. The second processor is configured to determine, among a plurality of second signal pins, a third signal pin corresponding to the target information type to which the target status information belongs; and to send an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin; The first processor is further configured to: detect level change information for each of the plurality of first signal pins; when the level change information indicates a change in the level value of a fourth signal pin among the plurality of first signal pins, detect the current first level value on the fourth signal pin, wherein the first signal includes the first level value; obtain a first pin identifier for the fourth signal pin among the plurality of first signal pins; and generate a first status message based on the first pin identifier and the first level value, wherein the first status message indicates the level output status of the host processor on the fourth signal pin, and the target status information includes the first status message; The first processor is further configured to: add the first pin identifier to the first field position in the initial status message corresponding to the host processor to obtain a second status message, wherein the first field position is the field position in the initial status message used to store the pin identifier of the pin that has undergone a level change; add the first level value to the second field position in the second status message to obtain a third status message, wherein the second field position is the field position in the second status message used to store the level value of the pin after the level change; add a status change field to the header position of the third status message to obtain the first status message, wherein the status change field is used to indicate that a level change has occurred on the signal pin of the host processor.

2. The device according to claim 1, characterized in that, The second processor is further configured to: detect the fields carried in the header of the initial message received in the second transmission port; if the field carried in the header is a state change field, determine the initial message as a first state message sent by the host processor, wherein the target state information includes the first state message, the state change field is used to indicate that a level change has occurred on the signal pin of the host processor, and the first state message carries information for indicating the level value on the signal pins where level changes have occurred among a plurality of the first signal pins.

3. The device according to claim 1, characterized in that, The second processor is further configured to extract a first pin identifier carried in the first status message from a first field position in the first status message, and to extract a first level value carried in the first status message from a second field position in the first status message, wherein the first status message carries information for indicating the level value of a signal pin among a plurality of first signal pins that has undergone a level value change, the target status information including the first status message, the first pin identifier for indicating the signal pin among a plurality of first signal pins that has undergone a level value change, and the first level value being the current level value of the signal pin among a plurality of first signal pins that has undergone a level value change; determine the target information type of the information transmitted on the first signal pin indicated by the first pin identifier; determine the third signal pin corresponding to the target information type from the information types with corresponding relationships and the plurality of second signal pins; and control the third signal pin to output the indication signal corresponding to the first level value.

4. The device according to claim 1, characterized in that, The first processor is configured with a third transmission port, and the second processor is configured with a fourth transmission port. The third transmission port is used to connect to a reference pin of the external socket, and the fourth transmission port is used to connect to a signal pin corresponding to the reference pin on the external socket. The second processor is configured to generate target control information based on second signals acquired from multiple second signal pins, wherein the second signal is a signal output by the data center security control device for controlling the operating state of the host processor, and the target control information is used to characterize the operating state of the host processor to be switched; and transmit the target control information to the first processor through the fourth transmission port; The first processor is configured to determine, from a plurality of first signal pins, a fifth signal pin corresponding to the target state type controlled by the target control information; and to send a state control instruction corresponding to the operating state indicated by the target control information to the host processor via the fifth signal pin.

5. The device according to claim 4, characterized in that, The second processor is further configured to locate the sixth signal pin that acquired the second signal from among a plurality of second signal pins; add the second pin identifier of the sixth signal pin to the third field position of the reference status message corresponding to the data center security control device, and add the second level value of the second signal to the fourth field position of the reference status message to obtain a fourth status message, wherein the third field position is the field position in the reference status message used to store the pin identifier of the pin that generated the signal, and the fourth field position is the field position in the reference status message used to store the pin level value; add an identifier field to the header position of the fourth status message to obtain a fifth status message, wherein the identifier field is used to indicate that the data center security control device has issued a control command to the host processor, and the target control information includes the fifth status message.

6. The device according to claim 5, characterized in that, The first processor is further configured to extract from the fifth status message a second pin identifier carried in the fifth status message and a second level value of the second signal, wherein the target control information includes the fifth status message, the second pin identifier is used to indicate the pin among a plurality of second signal pins that detects the second signal; determine the fifth signal pin corresponding to the target status type from the corresponding status types and a plurality of first signal pins; and control the fifth signal pin to output the status control command corresponding to the second level value.

7. A server motherboard, characterized in that, The server motherboard is equipped with: a signal transmission device, a host processor, and an external socket for a data center security control device. The signal transmission device includes a first processor and a second processor. The first processor is configured with multiple first signal pins and a first transmission port. The second processor is configured with multiple second signal pins and a second transmission port. The multiple first signal pins are used to connect one-to-one with the signal pins of the host processor. The first transmission port is connected to a target pin of the external socket. The second transmission port is used to connect to the signal pin corresponding to the target pin on the external socket. The multiple second signal pins are used to connect one-to-one with the signal pins of the data center security control device. The first processor is configured to generate target status information based on a first signal acquired by the first signal pin, wherein the target status information is used to indicate the current operating status of the host processor; and transmit the target status information to the second processor through the first transmission port. The second processor is configured to determine, among a plurality of second signal pins, a third signal pin corresponding to the target information type to which the target status information belongs; and to send an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin; The first processor is further configured to: detect level change information for each of the plurality of first signal pins; when the level change information indicates a change in the level value of a fourth signal pin among the plurality of first signal pins, detect the current first level value on the fourth signal pin, wherein the first signal includes the first level value; obtain a first pin identifier for the fourth signal pin among the plurality of first signal pins; and generate a first status message based on the first pin identifier and the first level value, wherein the first status message indicates the level output status of the host processor on the fourth signal pin, and the target status information includes the first status message; The first processor is further configured to: add the first pin identifier to the first field position in the initial status message corresponding to the host processor to obtain a second status message, wherein the first field position is the field position in the initial status message used to store the pin identifier of the pin that has undergone a level change; add the first level value to the second field position in the second status message to obtain a third status message, wherein the second field position is the field position in the second status message used to store the level value of the pin after the level change; add a status change field to the header position of the third status message to obtain the first status message, wherein the status change field is used to indicate that a level change has occurred on the signal pin of the host processor.

8. A server signal transmission system, characterized in that, The server is equipped with: a signal transmission device, a host processor, a data center security control device, and an external socket for the data center security control device. The signal transmission device includes a first processor and a second processor. The first processor is configured with multiple first signal pins and a first transmission port. The second processor is configured with multiple second signal pins and a second transmission port. The multiple first signal pins are used to connect one-to-one with the signal pins of the host processor. The first transmission port is connected to a target pin of the external socket. The second transmission port is used to connect to the signal pin corresponding to the target pin on the external socket. The multiple second signal pins are used to connect one-to-one with the signal pins of the data center security control device. The first processor is configured to generate target status information based on a first signal acquired by the first signal pin, wherein the target status information is used to indicate the current operating status of the host processor; and transmit the target status information to the second processor through the first transmission port. The second processor is configured to determine, among a plurality of second signal pins, a third signal pin corresponding to the target information type to which the target status information belongs; and to send an indication signal corresponding to the operating status indicated by the target status information to the data center security control device through the third signal pin; The first processor is further configured to: detect level change information for each of the plurality of first signal pins; when the level change information indicates a change in the level value of a fourth signal pin among the plurality of first signal pins, detect the current first level value on the fourth signal pin, wherein the first signal includes the first level value; obtain a first pin identifier for the fourth signal pin among the plurality of first signal pins; and generate a first status message based on the first pin identifier and the first level value, wherein the first status message indicates the level output status of the host processor on the fourth signal pin, and the target status information includes the first status message; The first processor is further configured to: add the first pin identifier to the first field position in the initial status message corresponding to the host processor to obtain a second status message, wherein the first field position is the field position in the initial status message used to store the pin identifier of the pin that has undergone a level change; add the first level value to the second field position in the second status message to obtain a third status message, wherein the second field position is the field position in the second status message used to store the level value of the pin after the level change; add a status change field to the header position of the third status message to obtain the first status message, wherein the status change field is used to indicate that a level change has occurred on the signal pin of the host processor.

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