In-memory computing architecture

Abstract

The invention provides an in-memory computing architecture having a plurality of memories and a plurality of processing elements. Each processing element comprises a lookup table unit which is used for storing numerical values of a lookup table of the k-cluster residue system and outputting one of the numerical values of the lookup table according to the first remainder and the second remainder to serve as a remainder calculation result. Wherein the lookup table unit receives a first remainder and a second remainder from one of the memories;

Description

Technical Field

[0001] The present invention relates to a compute-in-memory (CIM) architecture, and more particularly to a CIM architecture using a lookup table, which can improve overall performance while consuming less power. Background Art

[0002] Compute-In-Memory (CIM) is becoming increasingly important for neural processing. By performing computations in the memory itself and supporting a large number of operations, CIM reduces data transfer and solves the memory bandwidth bottleneck problem. This technology has the potential to significantly increase the speed and efficiency of neural processing systems.

[0003] Please refer to Figure 1 and Figure 2 . Figure 1 is a schematic diagram of a prior art in-memory computing architecture 10, Figure 2 yes Figure 1 Schematic diagram of a processing element (PE) 16 of an in-memory computing architecture 10. The in-memory computing architecture 10 is generally divided into two chips: a memory chip 12 and a logic circuit chip 14. The memory chip 12 is stacked on top of the logic circuit chip 14, allowing data to be directly transferred from the memory chip 12 to the logic circuit chip 14. The logic circuit chip 14 includes a plurality of processing elements 16. Each processing element 16 includes a multiply-accumulate unit (MAC) 26 and a local memory 20. The multiply-accumulate unit 26 is used to perform calculations, while the local memory 20 is used to temporarily store data. A network-on-chip (NoC) solution is also used to connect all processing elements 16 and distribute data for parallel data processing. Each processing element 16 also includes an address register 18, a first register 22, and a second register 24. The address register 18 reads values ​​from the local memory 20. The first register 22 stores one of the values ​​read by the address register 18, and the second register 24 stores the other value read by the address register 18. The product-accumulation unit 26 calculates the product of the two values ​​stored in the first register 22 and the second register 24.

[0004] The in-memory computing platform can be used not only for digital architectures, but also for analog architectures. Figure 3 . Figure 3Schematic diagram of an analog processing element 30 in a prior art in-memory computing architecture. The analog processing element 30 includes a plurality of digital-to-analog converters (DACs) 32, a local memory 34, a first register 36, a second register 38, an analog multiplier 40, and a plurality of analog-to-digital converters (ADCs) 42. The DAC 32 is used to convert digital data into analog signals. The analog signals are stored in the local memory 34, and the local memory 34 is an analog memory. The first register 36 reads an analog signal from the local memory 34, and the second register 38 reads another analog signal from the local memory 34. The analog multiplier 40 performs an inner product (dot product) operation on the two analog signals read by the first register 36 and the second register 38, and outputs the final result to the ADC 42. The ADC 42 converts the final result into a digital domain. Summary of the invention

[0005] An embodiment of the present invention provides an in-memory computing architecture having a plurality of memories and a plurality of processing elements. Each processing element includes a lookup table unit for storing a value of a lookup table of a k-cluster residue system and outputting one of the values ​​of the lookup table according to a first remainder and a second remainder as a result of the residue calculation. The lookup table unit receives the first remainder and the second remainder from one of the plurality of memories.

[0006] The present invention discloses a new in-memory computing architecture that utilizes a lookup table approach and can be fully integrated with the memory. All calculations are performed using lookup tables instead of logic gates. The in-memory computing architecture of the present invention not only simplifies the design, but also improves overall performance while reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of a prior art in-memory computing architecture.

[0008] Figure 2 yes Figure 1 Schematic diagram of the processing elements of the in-memory computing architecture.

[0009] Figure 3 is a schematic diagram of digital processing elements in a prior art in-memory computing architecture.

[0010] Figure 4 is a schematic diagram of an in-memory computing architecture according to an embodiment of the present invention.

[0011] Figure 5yes Figure 4 Schematic diagram of the processing elements of the in-memory computing architecture.

[0012] Figure 6 It is a schematic diagram for explaining how to obtain an addition and subtraction lookup table according to an embodiment of the present invention by simplifying a two-dimensional addition lookup table in the prior art.

[0013] Figure 7 4 is a schematic diagram of a temporary multiplication lookup table according to an embodiment of the present invention.

[0014] Figure 8 Schematic diagram of a multiplication lookup table corresponding to when one of the coprime integers of the module set of the k-cluster residue system is 7 according to an embodiment of the present invention.

[0015] Fig. 9 yes Figure 4 A circuit diagram of a decoder included in the memory.

[0016] Fig.10 yes Fig. 9 The analog signal in Fig. 9 Diagram of the relationship between the output signals of the three inverters.

[0017] Fig.11 It is used to show the Fig. 9 When the analog signals in are at different voltage levels, Fig. 9 Schematic diagram of the digital signal output by the decoder.

[0018] Fig.12 yes Fig. 9 Circuit diagram of the inverter in .

[0019] Fig.13 Is used to replace Fig.12 Circuit diagram of two NMOS transistors connected in series.

[0020] Fig.14 and Fig.15 It is a schematic diagram for illustrating a six-way neural network according to an embodiment of the present invention.

[0021] Fig.16 and Fig.17 It is a schematic diagram for illustrating a ten-way neural network according to an embodiment of the present invention.

[0022] Reference numerals:

[0023] 10: In-memory computing architecture

[0024] 12: Memory chip

[0025] 14: Logic circuit chip

[0026] 16: Processing element

[0027] 18, 64: Address register

[0028] 20, 34, 68: Regional memory

[0029] 22, 36, 71: First register

[0030] 24, 38, 73: Second register

[0031] 26: Multiply-accumulate unit

[0032] 30: Analog processing elements

[0033] 32: Digital to Analog Converter

[0034] 40: Analog multiplier

[0035] 42: Analog-to-digital converter

[0036] 50: In-memory computing architecture

[0037] 60: Memory

[0038] 62: Processing element

[0039] 62C: Central Processing Unit

[0040] 64: Address register

[0041] 70: First floor

[0042] 72: Second floor

[0043] 74: Zero Detector

[0044] 76: Lookup table unit

[0045] 78: Lookup Table

[0046] 80: Addition and subtraction lookup table

[0047] 81: Storage Cell

[0048] 90: Multiplication Lookup Table

[0049] 92, 94: Diagonal

[0050] 100: Multiplication Lookup Table

[0051] 110: Decoder

[0052] 112, 114, 116, 118, 122: Inverter

[0053] 120: Anti-OR gate

[0054] 124: Anti-AND Gate

[0055] 140: Six-way neural network

[0056] 150: Ten-way Neural Network

[0057] A, B, C: Node

[0058] A1: According to the first address

[0059] A2: Second address

[0060] A7: Addition Lookup Table

[0061] B1, B2: Digital signal

[0062] C1, C2, C3: Curve

[0063] Q1: PMOS transistor

[0064] Q2, Q21, Q22:

[0065] V0, V1, V2, V3: voltage level Vin: analog signal

[0066] Vout, Vout1, Vout2, Vout3: output voltage Vt1, Vt2, Vt3: threshold voltage

[0067] Rc: The result of the residual calculation

[0068] rx: first remainder

[0069] ry: second remainder DETAILED DESCRIPTION

[0070] The present invention provides a new compute-in-memory (CIM) architecture that uses a lookup table method and can be fully integrated with the memory. All of its calculations are performed using a lookup table (LUT) instead of logic gates. This method also supports analog compute-in-memory and uses a decoder instead of an analog-to-digital converter at the output to generate a memory address to access a lookup table in another memory. The compute-in-memory architecture of the present invention is an architecture that truly performs calculations in memory, which not only simplifies the design, but also improves overall performance while consuming less power.

[0071] Lookup tables are a fast way to implement complex functions in digital logic. The address is the input to the function, and the value at the address is the output of the function. The advantage of a lookup table is that no matter how complex the function is, only one memory lookup is required to calculate the function, so it is very fast.

[0072] Please refer to Figure 4 and Figure 5 . Figure 4 is a schematic diagram of an in-memory computing architecture 50 according to an embodiment of the present invention, and Figure 5 yes Figure 4 Schematic diagram of a processing element (PE) 62 of an in-memory computing architecture 50 in FIG. The in-memory computing architecture 50 includes a plurality of processing elements 62 and a plurality of memories 60. The plurality of processing elements 62 are formed in a first layer 70, and the plurality of memories 60 are formed in a second layer 72, and the first layer 70 and the second layer 72 are stacked alternately. The first layer 70 is a processing circuit layer, and the second layer 72 is a memory layer. Each processing element 62 includes a lookup table unit 76. The lookup table unit 76 is used to store values ​​of a plurality of lookup tables 78 of a k-cluster residue system, and output one of the values ​​of the lookup table 78 according to a first remainder rx and a second remainder ry as a result Rc of the residue calculation. A plurality of memories 60 are coupled to the processing element 62, and are used to store values ​​output by the lookup table unit 76 of the processing element 62. The lookup table unit 76 receives the first remainder rx and the second remainder ry from one of the plurality of memories 60. The lookup table 78 may include an addition and subtraction lookup table 80 (such as Figure 6 ) and the multiplication lookup table 100 (as shown Figure 8 shown).

[0073] All computations of the in-memory computing architecture 50 are performed by the lookup table unit 76 of the processing element 62, rather than by logic gates. Figure 1 Compared with the in-memory computing architecture 10 of the prior art, the in-memory computing architecture 50 has the effect of improving overall performance and reducing power consumption. In addition, since the first layer 70 and the second layer 72 are stacked alternately, the data transmission path can be shortened, thereby significantly improving the speed and efficiency of the in-memory computing architecture 50.

[0074] Each processing element 62 may further include a local memory 68, an address register 64, a first register 71, and a second register 73. The local memory 68 is used to temporarily store data. The address register 64 is used to read the first remainder rx from the local memory 68 according to the first address A1, and to read the second remainder ry from the local memory 68 according to the second address A2. The first register 71 is used to store the first remainder rx, and the second register 73 is used to store the second remainder ry.

[0075] The in-memory computing architecture 50 is used to establish a residue number system (RNS). A residue number system is a digital system that first defines a modular set and converts numbers into integer remainders (also called "residues") through modular division. Arithmetic operations (addition, subtraction, and multiplication) can then be performed on the remainders. For example, when the modular set is defined as (7,8,9), the dynamic range is defined by the product of the three moduli of the modular set, 7*8*9=504. For the numbers 13 and 17, these two numbers are first converted into residues through three moduli, i.e., 13→(6,5,4) and 17→(3,1,8). Then, to perform addition and multiplication on 13 and 17, just perform addition and multiplication on their residues, (6,5,4)+(3,1,8)=(9,6,12)→(2,6,3), which is equal to 30. (6,5,4)*(3,1,8)=(18,5,32)→(4,5,5), which equals 221. Since the magnitude of the remainder is much smaller, only simple logic is required to perform parallel calculations.

[0076] For clarity, the dynamic range of the residual system can be defined as follows:

[0077]

[0078] in:

[0079] M is the dynamic range of the residual system; and

[0080] m i is the module set of the residue system (m0,m1,…,m n )’s ith modulus.

[0081] All arithmetic operations in the residual system can be performed by using a memory lookup table to achieve parallel distributed computing. However, in the residual system, when using a lookup table, its memory requirement is an important issue. The required memory size depends on the square of each modulus and the number of bits of the modulus, which can be expressed as the following equation (2):

[0082]

[0083] in:

[0084] Mem is the required memory size;

[0085] m i is the ith modulus; and

[0086] b i is the number of digits of the i-th modulus.

[0087] For example, when the residual system selects the module set as its module set, its dynamic range M = 15 × 17 = 2552. Since the length of the first module (i.e., 15) is 4 bits and the length of the second module (i.e., 17) is 5 bits, the total amount of memory required for all three arithmetic operations (i.e., addition, subtraction, and multiplication) is estimated to be 3 × (152 × 4 + 172 × 5) = 7035 bits. Compared with the logic circuit design (e.g., the processing element (PE) of the residual system), the wiring area required for its memory is too large.

[0088] In order to use the k-cluster residue number system (k-RNS) of the in-memory computing architecture 50 to represent n-bit integers and their negatives, a modular set of p relatively prime integers is first defined as (m0, m1, ..., m p ), and its dynamic range is based on the module set (m0,m1,…,m p ). For example, when the module set of 3 relatively prime integers is chosen to be (2 n / 2 -1,2,2 n / 2 +1), its dynamic range is set to [-(2 n -1),(2 n -2)]. The module set is not limited to only 3 coprime integers.

[0089] Processing element 62 uses one of the plurality of lookup tables 78 to perform addition and subtraction operations. The lookup table 78 used by processing element 62 to perform addition and subtraction operations may be referred to as an "addition and subtraction lookup table." According to the remainder theorem, the following equation (3) in the integer domain can be converted to the following equation (4) in the remainder domain:

[0090] Z=X+Y (3)

[0091] rz=rx+ry (4)

[0092] in:

[0093] X, Y and Z are three integers;

[0094] rx is equal to (X mod m i );

[0095] ry is equal to (Y mod m i );

[0096] rz is equal to (Z mod m i );and

[0097] m iis a modulus selected from the modulus set of k-cluster residue systems.

[0098] Figure 6 The diagram is used to illustrate how to obtain the addition and subtraction lookup table 80 of the in-memory computing architecture 50 by simplifying the two-dimensional addition lookup table A7 of the prior art. The addition and subtraction lookup table 80 is Figure 5 One of the multiple lookup tables 78 in the embodiment is obtained by simplifying the two-dimensional addition lookup table A7 of the prior art. In the present embodiment, one of the moduli of the module set selected by the processor 4 is 7. The addition and subtraction lookup table 80 is composed of 14 (i.e., 2×7) storage cells 81, which are used to record the values ​​from zero to 6 twice in an ascending power manner. The addition and subtraction lookup table 80 is a one-dimensional linear array, which is simplified from the two-dimensional addition lookup table A7 of the prior art, and is used for addition operations of the modulus 7. The addition lookup table A7 of the prior art contains 49 (i.e., 7×7) storage cells, which is larger than the fourteen storage cells 81 of the addition and subtraction lookup table 80. Each storage cell 81 is used to store the remainder when adding two remainders rx and ry or two integers X and Y, where rx=(X mod 7) and ry=(Y mod 7). Based on the periodic behavior of the modulus, the addition lookup table A7 is converted into the addition and subtraction lookup table 80. As Figure 6 As shown, the sum stored in each storage cell in the addition lookup table A7 differs from the value of the adjacent storage cell by 1. Therefore, the addition lookup table A7 can be simplified and converted into the addition and subtraction lookup table 80. The remainder rx (i.e., the summand) can be used as a table entry; and the remainder ry (i.e., the addend) can be used as a table index in the ascending power arrangement to retrieve the result of the addition operation from the addition and subtraction lookup table 80. In this embodiment, the starting position Ps will be initially set to be equal to the remainder rx (i.e., the summand), and the starting position Ps will be moved according to the remainder ry (i.e., the addend). Specifically, when the addition operation is performed on two integers X and Y, the value recorded in the storage cell 81 located at position Q of the addition and subtraction lookup table 80 is retrieved as the result of the addition operation, where Q=((Xmod m i )+(Y mod m i )), and m i is the modulus. Since m i =7, (X mod m i )=(X mod 7)=rx,(Y mod m i )=(Y mod 7)=ry, so Q=(rx+ry). For example, when rx=4 and ry=5, the starting position Ps is initially set to 4, and then the starting position Ps moves 5 positions to position 9 (i.e. 4+5=9), and the value recorded in the storage cell 81 at position 9 will be used as the search result of (rx+ry).

[0099] Similarly, according to the subtraction operation of the remainder theorem, the following equation (5) in the integer domain can be converted to the following equation (6) in the remainder domain:

[0100] Z = X - Y (5)

[0101] rz = rx - ry (6)

[0102] Since the addition-subtraction lookup table 80 can also be obtained by simplifying the subtraction lookup table S7 of the prior art, the addition-subtraction lookup table 80 can be used not only for addition operations but also for subtraction operations. i The sum of the two numbers can be used as table entries; and the remainder ry (i.e., the subtrahend) can be used as a table index in the descending power arrangement to retrieve the result of the subtraction operation from the addition and subtraction lookup table 80. In this embodiment, the starting position Ps is initially set to be equal to the remainder rx (i.e., the minuend) and the modulus m. i Specifically, when performing a subtraction operation on two integers X and Y, the value recorded in the storage cell 81 at position R in the addition and subtraction lookup table 80 is retrieved as the result of the subtraction operation, where R=(m i +(X mod m i )-(Y mod m i )). Due to m i =7, (X mod m i )=(X mod 7)=rx,(Y mod m i )=(Y mod7)=ry, so R=(m i + rx-ry). For example, when 4 is subtracted from 5, rx = 5 and ry = 4, and the table entry becomes (5 + 7) = 12, where 7 is equal to m i Then it moves 4 positions to the left and retrieves the value 1 in the storage cell 81 at position 8, which matches the result of (rx-ry)=1.

[0103] Figure 7 FIG. 9 is a schematic diagram of a temporary multiplication lookup table 90 according to an embodiment of the present invention. If one of the two integers X and Y is zero, the product of the two integers X and Y is zero, so all cells in the multiplication lookup table whose values ​​are equal to zero can be eliminated. Therefore, the data volume of the temporary multiplication lookup table 90 can be expressed as the following equation (7):

[0104]

[0105] in:

[0106] Mem2 is the data size of the temporary multiplication lookup table 90;

[0107] m i is the i-th modulus; and

[0108] b i is the number of digits of the i-th modulus.

[0109] According to equations (2) and (7), compared with the prior art, the size of the lookup table is reduced from Reduce to In addition, according to the commutative law of multiplication, the order of the multiplicand and the multiplier can be exchanged. Therefore, the product of the temporary multiplication lookup table 90 can be mirrored along the diagonal line 92 of the upper left corner and the lower right corner (TL / BR) and along the diagonal line 94 of the upper right corner and the lower left corner (TR / BL) (such as Figure 7 As shown in FIG. 1 , the temporary multiplication lookup table 90 can be divided into four equal areas to reduce the size of the lookup table. Therefore, the size of the lookup table for the multiplication operation can be reduced from Further reduced to Figure 8 FIG. 1 is a schematic diagram of a multiplication lookup table 100 corresponding to a k-cluster residue system when one of the coprime integers in the module set is 7 according to an embodiment of the present invention. Figure 5 The temporary multiplication lookup table 90 can be simplified by simplifying the temporary multiplication lookup table 90. The multiplication lookup table 100 has twelve storage cells 81, while the temporary multiplication lookup table 90 has thirty-six storage cells 81. Therefore, the size of the lookup table for multiplication operations is further reduced. Due to the mirroring property of the temporary multiplication lookup table 90 and the periodic behavior of the modulus, its four identical regions can be simplified to the multiplication lookup table 100 (such as Figure 8 The multiplication lookup table 100 corresponds to the modulus 7 (ie, m i =7). Processing element 62 can generate a multiplication lookup table 100 for each coprime integer in the module set (i.e., each modulus), and the coprime integers m i The multiplication lookup table is composed of S storage cells 81, where

[0110] According to the above description, the data volume of the multiplication lookup table 100 can be expressed by the following equation (8):

[0111]

[0112] in:

[0113] Mem3 is the data size of the multiplication lookup table 100;

[0114] m i is the i-th modulus; and

[0115] bi is the number of digits of the i-th modulus.

[0116] Please refer to Figure 5 In one embodiment of the present invention, each processing element 62 may further include a zero detector 74, which is coupled between the lookup table unit 76 and the first register 71 and the second register 73, and is used to detect whether any one of the first remainder rx and the second remainder ry is zero. Therefore, each processing element 62 can use the zero detector 74 to skip invalid operations. In addition, since the size of the residue is much smaller than the original integer, the zero detector 74 can be easily implemented by using a simple NOR gate. This method allows effective zero value detection in the system, thereby improving overall performance and reducing power consumption.

[0117] The multiple lookup tables 78 of the lookup table unit 76 may include an overflow table, and the processing element 62 uses the overflow table to detect overflow detection of addition and subtraction operations and overflow detection of multiplication operations. Unlike the binary system, the use of the overflow table does not require the expansion of binary numbers to accommodate overflow. This method of using the overflow table can maintain the size of the lookup table. For more information about overflow detection, refer to U.S. patent application No. 17 / 878,235 filed on November 27, 2022.

[0118] The method of the present invention can also support analog in-memory calculations and replace the analog-to-digital converter at the output with a decoder to generate a memory address for accessing another memory lookup table. In one embodiment of the present invention, each memory 60 can be an analog memory and include Fig. 9 The decoder 110 in FIG. Fig. 9 yes Figure 4 A circuit diagram of the decoder 110 of the memory 60 is shown in FIG. Fig. 9, a 2-bit decoder 110 is illustrated, while decoders of other embodiments of the present invention may support multi-bit (i.e., 4-bit, 8-bit, etc.) decoding. In other words, each cell of the memory 60 storing data may be a multi-level cell (MLC), a triple-level cell (TCL), a quad-level cell (QLC), etc. Each decoder 110 is used to decode an analog signal Vin output from one of the multiple memories 60 into digital signals B1 and B2. The decoder 110 includes inverters 112, 114, 116, 118, and 122, a NOR gate 120, and a NAND gate 124. The input terminals of the inverters 112, 114, and 116 receive the analog signal Vin output from one of the multiple memories 60. The threshold voltages of the inverters 112, 114, and 116 are Vt3, Vt2, and Vt1, respectively. The threshold voltages Vt3, Vt2, and Vt1 are different from each other. Therefore, due to the different threshold voltages Vt3, Vt2 and Vt1, the output voltages Vout3, Vout2 and Vout1 of the inverters 112, 114 and 116 may be different. The input terminal of the inverter 118 is coupled to the output terminal of the inverter 114. The first input terminal of the NOR gate 120 is coupled to the output terminal of the inverter 118, and the second input terminal of the NOR gate 120 is coupled to the output terminal of the inverter 116. The input terminal of the inverter 122 is coupled to the output terminal of the NOR gate 120. The first terminal of the NAND gate 124 is coupled to the output terminal of the inverter 112, and the second terminal of the NAND gate 124 is coupled to the output terminal of the inverter 122. The output terminal of the inverter 118 outputs the digital signal B1, and the output terminal of the NAND gate 124 outputs the digital signal B2. The digital signals B1 and B2 each represent one bit.

[0119] Fig.10 yes Fig. 9 The analog signal Vin in Fig. 9 The relationship between the output signals Vout1, Vout2 and Vout3 of the three inverters 116, 114 and 112 in FIG. Curve C1 represents the relationship between the analog signal Vin and the output voltage Vout1 of the inverter 116, curve C2 represents the relationship between the analog signal Vin and the output voltage Vout2 of the inverter 114, and curve C3 represents the relationship between the analog signal Vin and the output voltage Vout3 of the inverter 112. Fig.11 It is used to show when Fig. 9 When the analog signal Vin in is at different voltage levels V0, V1, V2 and V3, Fig. 9Schematic diagram of the digital signals B1 and B2 output by the decoder 110. When the analog signal Vin is equal to V0, the digital signals B1 and B2 are "0" and "0" respectively. When the analog signal Vin is equal to V1, the digital signals B1 and B2 are "0" and "1" respectively. When the analog signal Vin is equal to V2, the digital signals B1 and B2 are "1" and "0" respectively. When the analog signal Vin is equal to V3, the digital signals B1 and B2 are "1" and "1" respectively. Among them, V3>Vt3>V2>Vt2>V1>Vt1>V0. The truth table of the decoder 110 is as follows in Table 1:

[0120] Table 1

[0121]

[0122] Since the inverters 112, 114, and 116 have different threshold voltages Vt3, Vt2, and Vt1, the decoder 110 can decode the analog signal Vin output from one of the plurality of memories 60. In addition, the threshold voltages Vt3, Vt2, and Vt1 can be adjusted by changing the transistor size or connecting two or more transistors in series to change their saturation currents. Fig.12 yes Fig. 9 1 is a circuit diagram of an inverter 116 of a decoder 110 in FIG. The inverter 116 includes a PMOS transistor Q1 and an NMOS transistor Q2. The gate of the PMOS transistor Q1 and the gate of the NMOS transistor Q2 receive the analog signal Vin, and the drain of the PMOS transistor Q1 and the drain of the NMOS transistor Q2 are connected to the output terminal of the inverter 116 to output the output voltage Vout1. Another inverter 114 of the decoder 110 can be replaced by replacing the NMOS transistor Q2 with Fig.13 The two series-connected NMOS transistors Q21 and Q22 are shown to achieve this. Fig.12 and Fig.13 Nodes A, B, and C in are used to indicate corresponding connection nodes when the NMOS transistor Q2 is replaced by NMOS transistors Q21 and Q22. Therefore, the inverter 114 may include a PMOS transistor Q1 and two serially connected NMOS transistors Q21 and Q22. The gates of the two serially connected NMOS transistors Q21 and Q22 and the gate of the PMOS transistor Q1 of the inverter 114 are connected to the input terminal of the inverter 114 to receive the analog signal Vin, and the drain of the PMOS transistor Q1 of the inverter 114 and one end of the two serially connected NMOS transistors Q21 and Q22 (i.e., node B) are connected to the output terminal of the inverter 114 to output the output voltage Vout2.

[0123] Since the NMOS transistors Q21 and Q22 are connected in series, the threshold voltage Vt2 of the inverter 114 will be greater than the threshold voltage Vt1 of the inverter 116. Similarly, the inverter 112 of the decoder 110 can be implemented by replacing the NMOS transistor Q2 with three or more NMOS transistors connected in series, so that the threshold voltage Vt3 of the inverter 112 is greater than the threshold voltages Vt1 and Vt2.

[0124] The processing elements 62 of the in-memory computing architecture 50 may form a six-way or ten-way neural network. Fig.14 and Fig.15 It is a schematic diagram for illustrating a six-way neural network 140 according to an embodiment of the present invention. Fig.16 and Fig.17 1 is a schematic diagram for illustrating a ten-way neural network 150 according to an embodiment of the present invention. Fig.14 and Fig.15 As shown, the central processing element 62C of the processing element 62 is connected to the other six processing elements 62. Fig.16 and Fig.17 As shown, the central processing element 62C of the processing elements 62 is connected to the other ten processing elements 62 . Fig.14 and Fig.16 They are top views of the six-way neural network 140 and the ten-way neural network 150 respectively. Fig.15 The directions of the central processing element 62C and the six-way neural network 140 are depicted: up, down, front, back, left, and right. Fig.17 The directions of the central processing element 62C and the ten-way neural network 150 are depicted: up, down, front, back, left, right, front left, front right, back left, and back right. Each direction represents the location of the processing element 62 connected to the central processing element 62C. The ten-way neural network 150 of the in-memory computing architecture 50 will be composed of ten processing elements 62, which perform calculations together. The ten-way neural network 150 may also be referred to as a "ten-way switch."

[0125] The present invention discloses a new in-memory computing architecture that utilizes a lookup table approach and can be fully integrated with the memory. All calculations are performed using lookup tables instead of logic gates. The in-memory computing architecture of the present invention not only simplifies the design, but also improves overall performance while reducing power consumption.

[0126] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. An in-memory computing architecture, characterized in that: Include: multiple memories; and A plurality of processing elements, each processing element comprising: A lookup table unit is used to store the values ​​of a lookup table of a k-cluster residue system and output one of the values ​​of the lookup table according to a first remainder and a second remainder as a result of a remainder calculation, wherein the lookup table unit receives the first remainder and the second remainder from one of the multiple memories.

2. The in-memory computing architecture of claim 1, wherein: Each processing element further comprises: A regional memory for temporarily storing data; an address register, used for reading the first remainder from the local memory according to a first address, and reading the second remainder from the local memory according to a second address; A first register, used for storing the first remainder; as well as A second register is used to store the second remainder.

3. The in-memory computing architecture of claim 2, wherein: Each processing element further includes a zero detector coupled between the lookup table unit and the first register and the second register, for detecting whether any one of the first remainder and the second remainder is zero.

4. The in-memory computing architecture of claim 1, wherein the plurality of processing elements are formed in a plurality of first layers, the plurality of memories are formed in a plurality of second layers, and the plurality of first layers and the plurality of second layers are stacked alternately.

5. The in-memory computing architecture of claim 1, wherein: The plurality of processing elements form a ten-way switch, a central processing element of the ten-way switch being coupled to the other ten processing elements of the plurality of processing elements.

6. The in-memory computing architecture of claim 5, wherein: A central processing element of the ten-way switch is coupled to ten other processing elements above, below, front, rear, left, right, front left, front right, rear left, and rear right.

7. The in-memory computing architecture of claim 1, wherein: The lookup table unit is also used to store an addition and subtraction lookup table, which contains 2m i storage cells for recording the number of cells from zero to (m i -1) twice, where m i is a coprime integer in the module set of the k-cluster residue system.

8. The in-memory computing architecture of claim 7, wherein: When the first remainder and the second remainder are added, the lookup table unit retrieves the value recorded in the storage cell at position Q of the addition and subtraction lookup table, where Q=(rx+ry), rx is the first remainder, ry is the second remainder, and both the first remainder and the second remainder are integers.

9. The in-memory computing architecture of claim 7, wherein: When the first remainder and the second remainder are subtracted, the lookup table unit retrieves the value recorded in the storage cell at position R of the addition and subtraction lookup table, where R=(m i +rx-ry), rx is the first remainder, ry is the second remainder, and both the first remainder and the second remainder are integers.

10. The in-memory computing architecture of claim 1, wherein: The lookup table unit is also used to store a multiplication lookup table, and the multiplication lookup table is a coprime integer m of the module set of the k-cluster residue system. i prepared, the coprime integer m i is not equal to 2, and the multiplication lookup table consists of S cells, 11. The in-memory computing architecture of claim 1, wherein: The table lookup unit is also used to store an overflow table for overflow detection of addition and subtraction operations and overflow detection of multiplication operations.

12. The in-memory computing architecture as described in claim 1, wherein each memory includes a decoder for decoding an analog signal output by each multi-value analog memory into at least two bits, and the decoder supports multi-bit decoding.

13. The in-memory computing architecture of claim 12, wherein: The decoder contains: a first inverter having an input terminal for receiving the analog signal; a second inverter having an input terminal for receiving the analog signal; and a third inverter having an input terminal for receiving the analog signal; A first threshold voltage of the first inverter is smaller than a second threshold voltage of the second inverter, and the second threshold voltage of the second inverter is smaller than a third threshold voltage of the third inverter.

14. The in-memory computing architecture of claim 13, wherein: The first inverter comprises a PMOS transistor and an NMOS transistor, the gate of the PMOS transistor and the gate of the NMOS transistor receive the analog signal, and the drain of the PMOS transistor and the drain of the NMOS transistor are coupled to the output terminal of the first inverter; The second inverter comprises a PMOS transistor and two NMOS transistors connected in series, the gates of the two NMOS transistors connected in series and the gate of the PMOS transistor of the second inverter receive the analog signal, and the drain of the PMOS transistor of the second inverter and one end of the two NMOS transistors connected in series are coupled to the output end of the second inverter; and The third inverter includes a PMOS transistor and at least three NMOS transistors connected in series.

15. The in-memory computing architecture of claim 13, wherein: The decoder also contains: a fourth inverter having an input terminal coupled to the output terminal of the second inverter; an NOR gate having a first input terminal coupled to the output terminal of the fourth inverter and a second input terminal coupled to the output terminal of the first inverter; a fifth inverter having an input terminal coupled to the output terminal of the NOR gate; as well as an NAND gate having a first input terminal coupled to the output terminal of the third inverter and a second input terminal coupled to the output terminal of the fifth inverter; The fourth inverter is used to output the first bit of the at least two bits output by the decoder, and the NAND gate is used to output the second bit of the at least two bits output by the decoder.

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