Method and device for generating mask data file and electronic equipment

Abstract

The invention relates to the technical field of integrated circuits, and discloses a method for generating a mask data file, which comprises the following steps of: dividing an original data file into original data of a plurality of addresses and reading the original data; converting the read original data into an array format; encrypting the original data in the array format, and splicing the original data with an error correction code (ECC) to obtain mask data; and writing the mask data until the original data of all the addresses are converted into the mask data, and obtaining a mask data file. According to the method, an encryption calculation module in a hardware circuit is reused to encrypt original data, and the original data of different formats and different specifications can be flexibly processed by configuring parameters. The workload and time of mask data generation are reduced, and the development speed of the FPGA is increased. The invention further discloses a device for generating the mask data file and electronic equipment.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, for example, to a method and device for generating a mask data file, and an electronic device. Background Art

[0002] Currently, FPGA (Field-Programmable Gate Array) prototype verification is a mature technology for verifying the functions and performance of integrated circuits, application-specific standard products, and systems on chip. By porting RTL (Register Transfer Level) code to FPGA implementation, developers can verify the correctness of the design before chip tape-out, and perform software development and hardware / software co-verification.

[0003] As chip complexity increases, most storage units require special encryption and decryption processing, requiring that the data stored in the storage unit must be encrypted data. During FPGA prototype development, the encrypted data of the storage unit needs to be prepared before the netlist is generated to ensure that the storage unit contains correct and valid data during FPGA testing.

[0004] In order to realize data encryption in the storage unit, in the encryption method disclosed in the related art, FPGA developers develop corresponding software programs (such as C language or Python language) for different encryption algorithms to process the original data and generate a mask data file of the storage unit.

[0005] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0006] FPGA developers need to pay extra attention to the specific implementation of encryption algorithms. If the chip involves multiple encryption algorithms, each algorithm needs to develop a corresponding software program, which greatly increases the difficulty and time of FPGA development. At the same time, when the software program executes complex algorithms and large amounts of data, it will also consume a lot of time, and the encryption efficiency is low.

[0007] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0008] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0009] The embodiments of the present disclosure provide a method and device for generating a mask data file, and an electronic device to reduce the time of data encryption and improve encryption efficiency.

[0010] In some embodiments, the method for generating a mask data file includes: dividing an original data file into original data of multiple addresses and reading the original data; converting the read original data into an array format; encrypting the original data in the array format and assembling it with ECC (Error-Correcting Code) to obtain mask data; writing mask data until the original data of all addresses are converted into mask data to obtain a mask data file.

[0011] Optionally, the original data in the array format is encrypted and assembled with the error correction code ECC, including: splitting the original data in the array format into multiple groups of data to be encrypted; inputting the multiple groups of data to be encrypted into the hardware encryption module for encryption respectively, and assembling to obtain encrypted data; assembling the error correction code ECC calculated by the error correction code ECC calculation module with the encrypted data to obtain mask data.

[0012] Optionally, the error correction code ECC calculated by the error correction code ECC calculation module is assembled with the encrypted data, including: controlling the error correction code ECC calculation module to generate the error correction code ECC; filling the error correction code ECC before the encrypted data to assemble the encrypted data and the error correction code ECC into mask data.

[0013] Optionally, splitting the original data in array format into multiple groups of data to be encrypted includes: splitting the original data in array format into N groups of data to be encrypted; wherein N is a positive integer, and the size of each group of encrypted data is the same.

[0014] Optionally, the method for generating a mask data file further includes: splitting the original data in array format into 4 groups of data to be encrypted; when the size of the data to be encrypted is 2n bits, the calculated error correction code ECC is n bits.

[0015] Optionally, the method for generating a mask data file further includes: the bit width of the original data of each address is the same.

[0016] Optionally, the method for generating a mask data file further includes: modifying a bit width parameter used for reading and encryption processing according to development requirements of a field programmable gate array FPGA.

[0017] In some embodiments, the device for generating a mask data file includes: a file reading unit, configured to divide the original data file into original data of multiple addresses and read them; a data storage unit, configured to convert the read original data into an array format; a hardware encryption unit, configured to encrypt the original data in the array format and assemble it with the error correction code ECC to obtain mask data; a file writing unit, configured to write mask data until the original data of all addresses are converted into mask data to obtain a mask data file.

[0018] In some embodiments, the apparatus for generating a mask data file includes: a processor and a memory storing program instructions, and the processor is configured to execute the above-mentioned method for generating a mask data file when running the program instructions.

[0019] In some embodiments, the electronic device includes: an electronic device body; and the device for generating a mask data file as described above, installed in the electronic device body.

[0020] The method, device, and electronic device for generating a mask data file provided by the embodiments of the present disclosure can achieve the following technical effects:

[0021] In the disclosed embodiment, the original data file is divided into multiple blocks according to the address, the data of each address is read, and the data is converted into an array format for subsequent processing. The converted array data is encrypted by the hardware encryption unit to ensure the security of the data, and then combined with the error correction code ECC to form more reliable mask data. Finally, the mask data is written into the file until the data of all addresses are converted into mask data, and the generation of the mask data file is completed. The disclosed embodiment not only improves the efficiency of mask data file generation in FPGA prototype verification, reduces development time and workload, but also enhances data security and reliability through hardware-level encryption processing. In addition, the disclosed embodiment supports a variety of file formats and encryption algorithms, so that the system can flexibly adapt to different design specifications and FPGA prototype development requirements, speed up the development progress of the chip, and also provide convenience for chip upgrades and iterations, greatly saving the time cost of redevelopment and debugging due to chip upgrades.

[0022] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0024] Figure 1 is a schematic diagram of an implementation environment of a method for generating a mask data file provided by an embodiment of the present disclosure;

[0025] Figure 2 is a schematic diagram of a method for generating a mask data file provided by an embodiment of the present disclosure;

[0026] Figure 3 is a schematic diagram of another method for generating a mask data file provided by an embodiment of the present disclosure;

[0027] Figure 4 is a schematic diagram of another method for generating a mask data file provided by an embodiment of the present disclosure;

[0028] Figure 5 is a schematic diagram of a device for generating a mask data file provided by an embodiment of the present disclosure;

[0029] Figure 6 It is a schematic diagram of another device for generating a mask data file provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0031] The terms "first", "second", etc. in the technical solutions described in the embodiments of the present disclosure are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0032] Unless otherwise stated, the term "plurality" means two or more.

[0033] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0034] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0035] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0036] In the field of FPGA prototype verification, mask data files are mainly generated by converting encryption modules in hardware circuits into software programs. Although this meets the needs of prototype verification to a certain extent, it also exposes multiple problems. First, with the increasing complexity of integrated circuit design, the special encryption and decryption processing requirements of storage units require FPGA developers to develop corresponding software programs for different encryption algorithms, which not only increases the difficulty of development but also prolongs the development time. Secondly, when the chip design is upgraded and iterated, the original software program often needs to be modified and redeveloped to adapt to the new encryption algorithm, the update of the original data, and the change of FPGA storage specifications, which further increases the development cost and time. In addition, when the software program executes complex algorithms and processes large amounts of data, it consumes a lot of computing resources and time, which limits the efficiency of FPGA prototype verification.

[0037] Therefore, there is an urgent need for a mask data file generation method that can improve data processing speed and reduce development time to meet the rapidly developing integrated circuit design needs.

[0038] Figure 1 FIG. 1 is a schematic diagram of an implementation environment of a method for generating a mask data file according to an embodiment of the present disclosure. Figure 1 As shown, the implementation environment may include a control unit 100 , an original data file 200 , a file reading unit 300 , a data storage unit 400 , a hardware encryption unit 500 , a file writing unit 600 and a mask data file 700 .

[0039] It should be noted that the control unit 100 provided in the embodiment of the present disclosure controls the data specifications of the read and written files, and generates mask data files 700 of different specifications required for prototype verification. The control unit 100 controls the file reading unit 300, supports reading multiple file formats, and supports generating multiple file formats, so that the system can adapt to original input files 200 of different formats. After the file reading unit 300 reads the original data file 200, it converts all the original data from the text format to the array format, stores it in the storage unit, waits for the control signal of the control unit 100, and outputs the corresponding data in a specific order to the hardware encryption unit 500 for data processing. The hardware encryption unit 500 reuses different encryption modules in the actual hardware circuit, saving the time of developing software programs corresponding to different encryption algorithms. When the hardware is upgraded or the original data is iterated, since the hardware circuit is directly reused, the data can be directly encrypted and calculated, avoiding the development of encryption software programs.

[0040] Combination Figure 2 As shown, the embodiment of the present disclosure provides a method for generating a mask data file, comprising:

[0041] S201, the processor divides the original data file into original data of multiple addresses and reads the original data.

[0042] S202: The processor converts the read original data into an array format.

[0043] S203, the processor encrypts the original data in the array format and assembles it with the error correction code ECC to obtain mask data.

[0044] S204, the processor writes mask data until the original data of all addresses are converted into mask data, and obtains a mask data file.

[0045] The method for generating a mask data file provided by the embodiment of the present disclosure is adopted, the original data file is divided into multiple blocks according to the address, the data of each address is read, and the data is converted into an array format for subsequent processing. The converted array data is encrypted by the hardware encryption unit to ensure the security of the data, and then combined with the error correction code ECC to form more reliable mask data. Finally, the mask data is written into the file until the data of all addresses are converted into mask data, and the generation of the mask data file is completed. The embodiment of the present disclosure not only improves the efficiency of mask data file generation in FPGA prototype verification, reduces development time and workload, but also enhances data security and reliability through hardware-level encryption processing. In addition, the embodiment of the present disclosure supports a variety of file formats and encryption algorithms, so that the system can flexibly adapt to different design specifications and FPGA prototype development requirements, speed up the development progress of the chip, and also provide convenience for chip upgrade iteration, greatly saving the time cost of redevelopment and debugging due to chip upgrade.

[0046] Optionally, the original data in the array format is encrypted and assembled with the error correction code ECC, including: splitting the original data in the array format into multiple groups of data to be encrypted; inputting the multiple groups of data to be encrypted into the hardware encryption module for encryption respectively, and assembling to obtain encrypted data; assembling the error correction code ECC calculated by the error correction code ECC calculation module with the encrypted data to obtain mask data.

[0047] In the disclosed embodiment, the original data in array format is split into multiple data groups to be encrypted, which are then input into a hardware encryption module for encryption processing. Encryption at the hardware level can significantly improve the processing speed, because hardware encryption modules are usually faster and more efficient than software implementations. After the encryption is completed, the multiple groups of encrypted data obtained are reassembled to form a complete encrypted data set. Next, the error correction code ECC calculation module performs error detection and correction code calculation on these encrypted data to generate an error correction code ECC. The calculated error correction code ECC is assembled with the encrypted data to finally form the mask data.

[0048] Error correction code ECC can detect and correct errors that may occur during data transmission or storage, thus ensuring the security and reliability of data. Through hardware-accelerated encryption processing and the introduction of error correction code ECC, the generation speed of mask data files is accelerated and the iteration time of FPGA prototype verification is reduced. It is particularly suitable for complex integrated circuit design projects that require rapid response to design changes and upgrades. In addition, due to the reduced dependence on software encryption programs, the cost of development and maintenance is also reduced, and the flexibility and adaptability of the system are improved, so that the system can be adjusted more quickly and flexibly when facing different design specifications and encryption requirements.

[0049] Optionally, the error correction code ECC calculated by the error correction code ECC calculation module is assembled with the encrypted data, including: controlling the error correction code ECC calculation module to generate the error correction code ECC; filling the error correction code ECC before the encrypted data to assemble the encrypted data and the error correction code ECC into mask data.

[0050] In the disclosed embodiment, first, the encrypted data processed by the hardware encryption module is input into the error correction code ECC calculation module. Then, the error correction code ECC calculation module calculates the corresponding error correction code ECC according to a specific algorithm, and the algorithm can ensure that even if an error occurs during data transmission or storage, it can be detected and corrected. The generated error correction code ECC is filled in front of the encrypted data according to a predetermined format, and the error correction code ECC is physically spliced ​​with the encrypted data to form complete mask data. Finally, the assembled mask data is written into the mask data file for subsequent FPGA prototype verification.

[0051] In this way, the reliability of data and the fault tolerance of the system are improved. By filling the ECC in front of the data, even if single or multiple bit errors occur during data transmission or storage, the system can detect and correct these errors through the ECC, thereby ensuring the integrity and accuracy of the data. In addition, this method improves the efficiency of ECC generation and data assembly through hardware-level processing, reduces dependence on software programs, thereby speeding up the generation of mask data files and shortening the iteration cycle of FPGA prototype verification.

[0052] Optionally, splitting the original data in array format into multiple groups of data to be encrypted includes: splitting the original data in array format into N groups of data to be encrypted; wherein N is a positive integer, and the size of each group of encrypted data is the same.

[0053] In the disclosed embodiment, first, the total size of the original data is determined, and the data is evenly split into N groups as needed to ensure that the size of each group of data to be encrypted is consistent. Then, the N groups of data to be encrypted are sent to the hardware encryption module respectively, ready for encryption processing. By evenly splitting the data, each group of data can be processed in parallel, thereby speeding up the overall encryption speed, especially when the hardware encryption module can process multiple groups of data at the same time, which can significantly reduce waiting time and improve throughput. In addition, evenly splitting data also helps to balance the use of hardware resources, avoid certain modules from becoming bottlenecks due to excessive data volume, and ensure the stability and performance of the entire system.

[0054] Optionally, the method for generating a mask data file further includes: splitting the original data in array format into 4 groups of data to be encrypted; when the size of the data to be encrypted is 2n bits, the calculated error correction code ECC is n bits.

[0055] In the disclosed embodiment, first, the size of the data to be encrypted is determined to be 2n bits. Then, according to the size of the data to be encrypted, the corresponding error correction code ECC is calculated, wherein the size of the error correction code ECC is n bits, and the proportional relationship ensures that the error correction code ECC can effectively detect and correct errors in the data. Then, the calculated error correction code ECC is assembled with the encrypted data to form mask data. Usually, the error correction code ECC will be placed in front of or behind the encrypted data to facilitate error detection and correction during data transmission or storage.

[0056] The method of dynamically calculating the error correction code ECC based on the data size in the disclosed embodiment can improve the reliability of data transmission and storage. The error correction code ECC can detect and correct common single-bit or double-bit errors, thereby ensuring the integrity and accuracy of the data. Secondly, the use of storage space is optimized. The size of the error correction code ECC is proportional to the data size, avoiding unnecessary storage overhead, so that the system has high storage efficiency while maintaining high reliability.

[0057] Optionally, the method for generating a mask data file further includes: the bit width of the original data of each address is the same.

[0058] Combination Figure 3 As shown, the embodiment of the present disclosure provides another method for generating a mask data file, comprising:

[0059] S301, the processor divides the original data file into original data at multiple addresses and reads the original data, and the bit width of the original data at each address is the same.

[0060] S302, the processor converts the read original data into an array format.

[0061] S303, the processor encrypts the original data in the array format and assembles it with the error correction code ECC to obtain mask data.

[0062] S304, the processor writes mask data until the original data of all addresses are converted into mask data, and obtains a mask data file.

[0063] In the disclosed embodiment, first, the system determines that the original data blocks of each address have the same bit width size. The standardized data block bit width size helps to simplify the data processing process. Then, the system sends these data blocks of the same size to the hardware encryption module for encryption processing. Since each data block is of the same size, the encryption module can process each data block efficiently and consistently. Then, the encrypted data is sent to the error correction code ECC calculation module, which calculates the corresponding error correction code ECC for each data block of the same size. Subsequently, the error correction code ECC of each data block is assembled with the corresponding encrypted data to form mask data. Finally, these mask data are written into the mask data file until the original data of all addresses are converted into mask data.

[0064] The processing flow and time required for each data block are the same, which helps optimize the overall processing time and resource allocation, and improves the consistency and predictability of data processing. Secondly, it simplifies hardware design and software programming. Processing data blocks of the same size can reduce the need for processing logic for different data blocks and reduce the complexity of the system. In addition, it helps to improve the scalability and flexibility of the system. When it is necessary to process larger or smaller data blocks, the data processing logic only needs to be adjusted once, without having to process each data block separately.

[0065] Optionally, the method for generating a mask data file further includes: modifying a bit width parameter used for reading and encryption processing according to development requirements of a field programmable gate array FPGA.

[0066] Combination Figure 4 As shown, the embodiment of the present disclosure provides a method for generating a mask data file, comprising:

[0067] S401, the processor divides the original data file into original data of multiple addresses and reads them.

[0068] S402, the processor converts the read original data into an array format.

[0069] S403, the processor encrypts the original data in the array format and assembles it with the error correction code ECC to obtain mask data.

[0070] S404, the processor writes mask data until the original data of all addresses are converted into mask data, and obtains a mask data file.

[0071] S405, the processor modifies the bit width parameters used for reading and encryption processing according to the development requirements of the field programmable gate array FPGA.

[0072] In the disclosed embodiment, the system determines the bit width parameters used for reading and encryption processing according to the design specifications and development requirements of the FPGA, and adjusts the bit width settings of the file reading unit and the hardware encryption unit through the control unit to adapt to different data formats and encryption algorithm requirements.

[0073] The method of dynamically adjusting the bit width parameters based on FPGA development requirements can improve the flexibility and adaptability of data processing, because the adjustment of the bit width parameters enables the system to process data of different specifications and formats to meet the diverse FPGA development requirements. Secondly, the data processing process is optimized. By accurately matching the bit width parameters, the errors and redundancies in the data reading and encryption process are reduced, and the efficiency and accuracy of data processing are improved. In addition, the dynamic adjustment of the bit width parameters also helps to improve the scalability and flexibility of the system. When the design specifications of the FPGA change, only the bit width parameters need to be adjusted without redesigning or programming the entire system.

[0074] In practical applications, an original data file with a size of 32KB and a bit width of 128 bits is encrypted by the embodiment of the present disclosure.

[0075] After starting the system, the control unit controls the file reading unit to read 32KB of original data according to 128bit for each address, and then sends the data to the data storage unit. The data storage unit splits each 128bit data into 4 32bit data and sends them to four 32bit encryption modules respectively to obtain 4 32bit encrypted data. The control unit controls the hardware encryption unit to assemble the 4 32bit encrypted data into 128bit, send it to the error correction code ECC calculation module, and assemble the calculated error correction code ECC with the encrypted data to obtain 144bit of mask data. At this point, the mask data of one address can be obtained and written into the mask data file through the file writing unit. After processing 32KB of data, the mask data file required by the FPGA can be obtained. The entire process only requires the hardware circuit import and parameter setting time.

[0076] Combination Figure 5 As shown, the embodiment of the present disclosure provides a device 50 for generating a mask data file, a file reading unit 300, a data storage unit 400, a hardware encryption unit 500 and a file writing unit 600. The file reading unit 300 is configured to divide the original data file into original data of multiple addresses and read them. The data storage unit 400 is configured to convert the read original data into an array format. The hardware encryption unit 500 is configured to encrypt the original data in the array format and assemble it with the error correction code ECC to obtain the mask data. The file writing unit 600 is configured to write the mask data until the original data of all addresses are converted into mask data to obtain the mask data file.

[0077] The device 50 for generating a mask data file provided by the embodiment of the present disclosure is used to divide the original data file into multiple blocks according to the address, read the data of each address, and convert the data into an array format for subsequent processing. The converted array data is encrypted by the hardware encryption unit to ensure the security of the data, and then combined with the error correction code ECC to form more reliable mask data. Finally, the mask data is written into the file until the data of all addresses are converted into mask data, and the generation of the mask data file is completed. The embodiment of the present disclosure not only improves the efficiency of mask data file generation in FPGA prototype verification, reduces development time and workload, but also enhances data security and reliability through hardware-level encryption processing. In addition, the embodiment of the present disclosure supports a variety of file formats and encryption algorithms, so that the system can flexibly adapt to different design specifications and FPGA prototype development requirements, speed up the development progress of the chip, and also provide convenience for chip upgrade iteration, greatly saving the time cost of redevelopment and debugging due to chip upgrade. .

[0078] Optionally, the hardware encryption unit further includes a plurality of encryption modules and an error correction code ECC calculation module. The encryption module is configured to encrypt the received original data. The error correction code ECC calculation module is configured to generate an error correction code ECC after encryption processing and assemble the error correction code ECC with the encrypted data.

[0079] Combination Figure 6 As shown, the embodiment of the present disclosure provides a device 60 for generating a mask data file, including a processor 604 and a memory 601. Optionally, the device 60 may also include a communication interface 602 and a bus 603. The processor 604, the communication interface 602, and the memory 601 may communicate with each other through the bus 603. The communication interface 602 may be used for information transmission. The processor 604 may call the logic instructions in the memory 601 to execute the method for generating a mask data file of the above embodiment.

[0080] In addition, the logic instructions in the memory 601 described above can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0081] The memory 601 is a computer-readable storage medium that can be used to store software programs, computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 604 executes the function application and data processing by running the program instructions / modules stored in the memory 601, that is, the method for generating a mask data file in the above embodiment is implemented.

[0082] The memory 601 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 601 may include a high-speed random access memory and may also include a non-volatile memory.

[0083] The embodiments of the present disclosure provide an electronic device, comprising: an electronic device body, and the above-mentioned device for generating a mask data file. The device for generating a mask data file is installed in the electronic device body. The installation relationship described here is not limited to placement inside the electronic device body, but also includes installation connections with other components of the electronic device, including but not limited to physical connections, electrical connections or signal transmission connections, etc. Those skilled in the art can understand that the device for generating a mask data file can be adapted to a feasible electronic device body, thereby realizing other feasible embodiments.

[0084] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0085] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0086] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0087] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0088] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A method for generating a mask data file, characterized in that: include: Divide the original data file into original data of multiple addresses and read them; Convert the read raw data into array format; The original data in array format is encrypted and assembled with the error correction code ECC to obtain the mask data; The mask data is written until the original data of all addresses are converted into mask data to obtain a mask data file.

2. The method according to claim 1, characterized in that: The original data in array format is encrypted and assembled with the error correction code ECC, including: Split the original data in array format into multiple groups of data to be encrypted; Input multiple groups of data to be encrypted into the hardware encryption module for encryption respectively, and assemble them to obtain the encrypted data; The error correction code ECC calculated by the error correction code ECC calculation module is assembled with the encrypted data to obtain the mask data.

3. The method according to claim 2, characterized in that Assembling the error correction code ECC calculated by the error correction code ECC calculation module with the encrypted data, including: Controlling the error correction code ECC calculation module to generate the error correction code ECC; The error correction code ECC is filled before the encrypted data to assemble the encrypted data and the error correction code ECC into mask data.

4. The method according to claim 2, characterized in that: Split the original data in array format into multiple groups of data to be encrypted, including: The original data in array format is split into N groups of data to be encrypted; wherein N is a positive integer, and the size of each group of encrypted data is the same.

5. The method according to claim 2, characterized in that: Also includes: Split the original data in array format into 4 groups of data to be encrypted; When the size of the data to be encrypted is 2n bits, the calculated error correction code ECC is n bits.

6. The method according to any one of claims 1 to 5, characterized in that: Also includes: The bit width of the original data at each address is the same.

7. The method according to any one of claims 1 to 5, characterized in that: Also includes: According to the development requirements of the field programmable gate array FPGA, the bit width parameters used for reading and encryption processing are modified.

8. A device for generating a mask data file, characterized in that: include: A file reading unit is configured to divide the original data file into original data of a plurality of addresses and read the original data; The data storage unit is configured to convert the read raw data into an array format; The hardware encryption unit is configured to encrypt the original data in the array format and assemble it with the error correction code ECC to obtain the mask data; The file writing unit is configured to write mask data until the original data of all addresses are converted into mask data to obtain a mask data file.

9. A device for generating a mask data file, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the method for generating a mask data file according to any one of claims 1 to 7 when running the program instructions.

10. An electronic device, characterized in that: include: Electronic device body; The device for generating a mask data file as described in claim 8 or 9 is installed in the electronic device body.

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