Cutting method, device, equipment and medium

Abstract

The invention discloses a cutting method and device, equipment and a medium. The cutting method comprises the steps that a user design file is recognized, and high-quality nodes are determined and marked; analyzing the user design file to generate a hypergraph; coarsening the hypergraph based on a user design hierarchy to obtain a node cluster, and segmenting the node cluster to different field programmable gate arrays (FPGAs); and refining and optimizing the FPGA by referring to the mark of the high-quality node based on the user design hierarchy. When FPGA cutting is carried out on a user design file, a user design hierarchy is considered in the coarsening and refining processes, and due to the fact that the user design hierarchy has the characteristics of high cohesion and low coupling, the problem that a segmentation result is unstable due to pure data angle segmentation is avoided when coarsening and refining are carried out; and moreover, high-quality nodes are referred to during refining, so that the high-quality nodes are prevented from being scattered, the nodes with high cohesion points are reserved, and the segmentation result is more accurate.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a cutting method, device, equipment and medium. Background Art

[0002] At present, electronic technology is developing rapidly, and the scale of program design is getting larger and larger. Users cannot realize large-scale complex design in one FPGA, which seriously restricts user development work. Usually, users will use automatic cutting tools to cut the design, divide the functions into several modules, and put them in multiple FPGAs. At the same time, according to the IO connection between FPGAs, the communication protocol is designed to realize the multi-FPGA collaborative work of the whole system.

[0003] At present, when cutting, a larger hypergraph is usually selected, and then the initial segmentation is performed by coarsening layer by layer, and then the final segmentation result is obtained by refining layer by layer based on the coarsening level. However, the current cutting method only coarsens from the perspective of pure data distance, thereby dispersing nodes with cohesive characteristics, making the coarsening effect unstable. Since the refinement is based on the coarsening level, it affects the overall segmentation effect. Summary of the invention

[0004] The present invention provides an FPGA cutting method based on user design level to achieve effective FPGA segmentation.

[0005] According to a first aspect of the present invention, there is provided a cutting method, comprising:

[0006] Identify the user design file, determine the high-quality nodes and mark them, wherein the user design file is a tree structure including multiple user design levels;

[0007] Parsing the user design file to generate a hypergraph;

[0008] Coarsening the hypergraph based on the user design level to obtain node clusters, and dividing the node clusters onto different field programmable gate arrays FPGA;

[0009] The FPGA is fine-tuned based on the user design level and with reference to the mark of the high-quality node.

[0010] According to another aspect of the present invention, there is provided a cutting device, comprising:

[0011] A high-quality node marking module, used to identify the user design file, determine the high-quality nodes and mark them, wherein the user design file is a tree structure including multiple user design levels;

[0012] A hypergraph acquisition module, used for parsing the user design file to generate a hypergraph;

[0013] A coarsening module, used for coarsening the hypergraph based on the user design level to obtain node clusters, and dividing the node clusters onto different field programmable gate arrays FPGA;

[0014] A refinement module is used to refine and tune the FPGA based on the user design level and with reference to the mark of the high-quality node.

[0015] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0016] at least one processor; and

[0017] a memory communicatively connected to the at least one processor; wherein,

[0018] The memory stores a computer program that can be executed by the at least one processor. The computer program is executed by the at least one processor so that the at least one processor can perform the method described in any embodiment of the present invention.

[0019] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the method described in any embodiment of the present invention when executed.

[0020] The technical solution of the embodiment of the present invention takes the user design level into consideration during the coarsening and refinement process when cutting the user design file into FPGA. Since the user design level itself has the characteristics of high cohesion and low coupling, the problem of unstable segmentation results caused by pure data angle segmentation is avoided during coarsening and refinement. In addition, high-quality nodes are referenced during refinement to avoid them being broken up, and nodes with high cohesion characteristics are further retained, making the segmentation results more accurate.

[0021] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 is a flow chart of a cutting method provided according to the first embodiment of the present invention;

[0024] Figure 2 is a schematic diagram of the structure of a user design file provided according to Embodiment 1 of the present invention;

[0025] Figure 3 is a schematic diagram of the structure of a hypergraph provided according to Embodiment 1 of the present invention;

[0026] Figure 4 is a schematic diagram of the result of coarsening the first layer of the hypergraph provided in the first embodiment of the present invention;

[0027] Figure 5 is a schematic diagram of the result of the second-layer coarsening of the hypergraph provided in the second embodiment of the present invention;

[0028] Figure 6 is a flow chart of a cutting method provided according to Embodiment 2 of the present invention;

[0029] Figure 7 is a schematic structural diagram of a cutting device provided according to Embodiment 3 of the present invention;

[0030] Figure 8 It is a schematic diagram of the structure of an electronic device provided by Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0032] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0033] Embodiment 1

[0034] Figure 1 A flow chart of a cutting method is provided for the first embodiment of the present invention. This embodiment is applicable to the case of performing FPGA cutting based on the user design level. The method can be executed by a cutting device, which can be implemented in the form of hardware and / or software. Figure 1 As shown, the method includes:

[0035] Step S101, identifying the user design file, determining the high-quality nodes and marking them.

[0036] Optionally, the user design file is identified to determine the high-quality nodes and mark them, including: scoring the nodes included in each user design level; taking the nodes whose scoring results meet the preset threshold as high-quality nodes, and marking the high-quality nodes.

[0037] Scoring the nodes included in each user design level includes: determining attribute information of the nodes included in each user design level, wherein the attribute information includes resource parameters, connection parameters, and clock parameters; determining the weight of each attribute information, and scoring each node according to the weight and the attribute information.

[0038] Among them, Figure 2 FIG. 1 is a schematic diagram of the structure of a user design file of the present embodiment. The user design file is a tree structure including multiple user design levels, such as Figure 2 The user design file shown includes four layers from top to bottom: the first layer includes nodes i, j, k, l, m, n, p, q, the second layer includes e, f, g, h, o, the third layer includes nodes b, c, d, and the fourth layer includes node a, and the layers are associated with each other. For example, nodes i and j in the first layer are subordinate to node e in the second layer, where node e can be a voltage regulator, node i can be a transformer, and node j can be a linear voltage regulator. For the connected nodes in the user design file, the upper layer node is a combined summary of the lower layer nodes, so node e has a higher cohesion characteristic with nodes j and j. The second layer node f can be a battery, and node e and node f have a lower coupling characteristic, so it can be known that the nodes with a connection relationship in the user design file in this embodiment have a high cohesion characteristic, while the nodes without a connection relationship have a low coupling characteristic. Of course, this embodiment is only an example, and the number and type of nodes included in the user design file are not specifically limited.

[0039] Specifically, in this implementation, all nodes in the user design file will be traversed and high-quality nodes will be determined. When making a high-quality determination, the attribute information of each node can be obtained, such as the attribute information including resource parameters, connection parameters and clock parameters, etc. Of course, this implementation is only an example, and the specific type of attribute information is not limited, and the weight corresponding to each attribute information will also be obtained, so as to determine the score of each node according to the attribute information and the weight. Among them, when scoring, the calculation can be specifically performed by calculating the product and sum of the parameter weights. For example, for node d, the corresponding resource parameter is X, the connection parameter is Y, and the clock parameter is Z. After normalizing different types of parameters to obtain a unit-unified value, it is determined that the weight corresponding to X is 0.3, the weight corresponding to weight Y is 0.5, and the weight corresponding to weight Y is 0.2, and the product of each normalized parameter and the corresponding weight is calculated, and the product results of each product are added to obtain the score of each node. Of course, this embodiment is only an example for illustration, and does not limit the specific values ​​of the weights corresponding to the parameters and the specific scoring method. Users can pre-determine them according to actual needs.

[0040] It should be noted that in this embodiment, after obtaining the score of each node, high-quality nodes will be determined from the user design file based on the score. There are many ways to determine high-quality nodes. A threshold can be determined in advance, and nodes that meet the threshold can be regarded as high-quality nodes. Alternatively, each node can be sorted in descending order according to the score, and a specified number of nodes in front of the sequence can be selected as high-quality nodes.

[0041] In a specific implementation, when it is determined through calculation that the score of node a is 9, the score of node b is 7.5, and the score of node c is 6, since the predetermined threshold is 8, only the score of node a is greater than the threshold, so node a is regarded as a high-quality node. Or when it is determined that the score of node a is 9, the score of node b is 7.5, and the score of node c is 6, the above nodes are sorted in descending order of scores to obtain a node sequence: abc. Since it is predetermined that two high-quality nodes need to be selected, nodes a and b at the front of the sequence are regarded as high-quality nodes. Of course, this embodiment only takes marking a high-quality node as an example for explanation, and in actual applications, the number of high-quality nodes determined includes multiple ones, which is not limited in this embodiment.

[0042] Among them, high-quality nodes refer to nodes in the user design file that are designed by the user and have high cohesion and low coupling characteristics. For these nodes, this application hopes to retain them unchanged during subsequent segmentation. Therefore, the determined high-quality nodes are pre-marked in the user design file to facilitate subsequent identification of high-quality nodes based on the identification.

[0043] Step S102, parsing the user design file to generate a hypergraph.

[0044] Optionally, the user design file is parsed to generate a hypergraph, including: parsing the user design file to obtain hypergraph nodes and the relationships between the hypergraph nodes; connecting the hypergraph nodes according to the relationships to construct a hypergraph.

[0045] Among them, in this embodiment, Figure 2 The hypergraph nodes are selected from the user design file shown in the figure. When selecting the hypergraph nodes, all nodes included in an instance can be selected from the user design file according to the attribute information of each node. For example, the large hypergraph nodes selected in this embodiment include e, k, l, m, n, h and o, etc. Of course, this embodiment is only an example, and the specific number of the selected hypergraph nodes is not limited. In addition, the relationship between the hypergraph nodes is determined according to the instance, and the hypergraph nodes are connected according to the determined relationship to construct a hypergraph, such as Figure 3 As shown, it is a schematic diagram of the structure of the hypergraph determined by connecting the above hypergraph nodes, and the hypergraph in this embodiment is able to describe the main design ideas of the user design file.

[0046] Specifically, in this embodiment, when selecting a hypergraph node, a comprehensive analysis is performed according to the attribute information of each node, such as resource parameters, connection parameters, and clock parameters, to select nodes that can reflect the main design ideas of the user design file, and the selected nodes are used as hypergraph nodes. Among them, when selecting a hypergraph, the nodes belonging to the same instance can be determined based on the above attribute information, and the number of calls of each instance can be analyzed to select the instance with the most calls, and all the nodes contained in the selected instance can be used as hypergraph nodes. Of course, this embodiment is only an example, and does not limit the specific method of determining the hypergraph node.

[0047] Step S103 , coarsening the hypergraph based on the user design level to obtain node clusters, and dividing the node clusters onto different field programmable gate arrays FPGA.

[0048] Optionally, the hypergraph is coarsened based on the user design level to obtain node clusters, and the node clusters are segmented onto different field programmable gate arrays FPGAs, including: obtaining node association information contained in each user design level; using the node association information as a constraint, coarsening the hypergraph nodes in a bottom-up manner to obtain node clusters, wherein each node cluster contains at least one hypergraph node; and using a specified segmentation algorithm to segment the node clusters onto different FPGAs, wherein each FPGA contains at least one node cluster.

[0049] Specifically, in this embodiment, after the hypergraph corresponding to the user design file is determined, the hypergraph nodes can be coarsened layer by layer based on the user design level. Figure 2 In the hypergraph shown in the figure, the node association information contained in each user design level is obtained in this embodiment. For example, the hypergraph nodes k and l are subordinate to the hypergraph node f, that is, k and l have a superior-subordinate relationship with f, and the hypergraph nodes m and n are subordinate to the hypergraph node g, that is, m and n have a superior-subordinate relationship with g. When the first layer is coarsened, k and l are coarsened to generate cluster k[node k] and cluster l[nodel]; m and n are coarsened to generate cluster 1[node m,node n], as shown in FIG. Figure 4 The figure shows the result of the first coarsening. In the second coarsening, the hypergraph node e is coarsened with cluster k and cluster l to generate cluster 2 [cluster l] and cluster 3 [node e, cluster k]; h and o are coarsened to generate cluster 4 [node h, node o], as shown in Figure 5 As shown, it is a schematic diagram of the result of the second coarsening. The bottom-up coarsening stops at layers b, c, and d, thereby finally generating four node clusters C1, C2, C3, and C4. Of course, this embodiment is only described by taking four node clusters as an example, and this embodiment does not limit the specific number of node clusters obtained by coarsening.

[0050] Among them, in this embodiment, when coarsening is performed, the hypergraph obtained is not simply coarsened according to the distance from the data perspective, but the node association information contained in the user design level is taken into account, and the node association information is used as the constraint condition for coarsening. For example, when coarsening is performed on the second layer, since e and f are subordinate to b, and k and l are subordinate to f, the hypergraph nodes e, k and l are coarsened, that is, coarsening is performed within the specified constraint range. Even when the data distance between e and node h is relatively close, node e is not coarsened with the hypergraph node h, thereby avoiding the problem of unstable coarsening results caused by simply using mathematical distance without considering the high cohesion and low coupling characteristics of the user design itself for segmentation.

[0051] It should be noted that, in this embodiment, after obtaining the node cluster, a specified algorithm will be used to divide the obtained node cluster into different FPGAs. For example, node clusters C1 and C2 are divided into FPGA1, and node clusters C3 and C4 are divided into FPGA2. Of course, this embodiment is only an example for illustration, and does not limit the specific division method of the node cluster on the FPGA. The user can use the specified division algorithm to divide according to actual needs.

[0052] Step S104 , performing detailed tuning on the FPGA based on the user design level and with reference to the marks of the high-quality nodes.

[0053] Optionally, the FPGA is fine-tuned based on the user design level and with reference to the markings of high-quality nodes, including: determining the node clusters used for connection between the FPGAs, and using the node clusters used for connection as edge node clusters; screening out the first type of edge node clusters with unmarked high-quality nodes from the edge node clusters; and breaking up the first type of edge node clusters based on the node association information contained in the user design level as a constraint condition.

[0054] Optionally, the method further includes: determining node clusters that are not connected and used between the FPGAs; screening out the second type of edge node clusters marked with high-quality nodes from the edge node clusters; and keeping the unconnected node clusters and the second type of edge node clusters unchanged in each FPGA.

[0055] Among them, in this embodiment, each FPGA will be traversed to determine the node cluster used when connecting with other FPGAs, and the node cluster used when connecting will be used as the edge node cluster, and in this embodiment, the edge node cluster will be identified to determine whether it is marked with high-quality nodes. If it is marked, the node cluster will be used as the first type of edge node cluster, and if it is not marked, it will be used as the second type of edge node cluster. Since the nodes of the second type of edge node cluster marked with high-quality nodes have the characteristics of high cohesion and low coupling, the second type of edge node cluster will be retained, and the unconnected node cluster will also be retained. Only the unmarked first type of edge node cluster will be refined and broken up to form a smaller node cluster for tuning to find a better segmentation result.

[0056] In a specific implementation, in this embodiment, the initial segmentation result obtained by the coarsening method mentioned above will be further refined and optimized based on the user design level. The first refinement: b is scattered to generate node e, cluster k, cluster l; c is scattered to generate cluster 1; since d is a high-quality node, it is skipped and not scattered. The segmentation tool optimizes node e, cluster k, cluster l, and d obtained by the refinement. The second refinement: cluster k is scattered to generate node k, cluster l is scattered to generate node l; cluster 1 is scattered to generate node m and node n. The segmentation tool optimizes node e, node k, node l, node m, and node n. When all levels are scattered, the final segmentation solution is obtained. Since the user design file is always highly cohesive and low coupled within the module, the coarsening and refinement are performed with reference to the user design level in order to obtain a stable segmentation result with good performance.

[0057] In the implementation manner of the present application, when the user design file is cut into FPGA, the user design level is taken into consideration during the coarsening and refinement process. Since the user design level itself has the characteristics of high cohesion and low coupling, the problem of unstable segmentation results caused by pure data angle segmentation is avoided during coarsening and refinement. In addition, when refining, high-quality nodes are referenced to avoid them being broken up, and nodes with high cohesion characteristics are further retained, making the segmentation results more accurate.

[0058] Embodiment 2

[0059] Figure 6 This is a flow chart of a cutting method provided in the second embodiment of the present invention. This implementation is based on the above embodiment. After fine-tuning the FPGA based on the user design level and referring to the mark of the high-quality node, it also includes: testing the fine-tuning result of the FPGA. Figure 2 As shown, the method includes:

[0060] Step S201, identifying the user design file, determining the high-quality nodes and marking them.

[0061] Optionally, the user design file is identified to determine the high-quality nodes and mark them, including: scoring the nodes included in each user design level; taking the nodes whose scoring results meet the preset threshold as high-quality nodes, and marking the high-quality nodes.

[0062] Step S202, parse the user design file to generate a hypergraph.

[0063] Optionally, the user design file is parsed to obtain a hypergraph describing the main line of the design, including: parsing the user design file to obtain hypergraph nodes and the relationships between the hypergraph nodes; connecting the hypergraph nodes according to the relationships to construct a hypergraph.

[0064] Step S203 , coarsening the hypergraph based on the user design level to obtain node clusters, and dividing the node clusters onto different field programmable gate arrays FPGA.

[0065] Optionally, the hypergraph is coarsened based on the user design level to obtain node clusters, and the node clusters are segmented onto different field programmable gate arrays FPGAs, including: obtaining node association information contained in each user design level; using the node association information as a constraint, coarsening the hypergraph nodes in a bottom-up manner to obtain node clusters, wherein each node cluster contains at least one hypergraph node; and using a specified segmentation algorithm to segment the node clusters onto different FPGAs, wherein each FPGA contains at least one node cluster.

[0066] Step S204 , performing detailed tuning on the FPGA based on the user design level and referring to the marks of the high-quality nodes.

[0067] Optionally, the FPGA is fine-tuned based on the user design level and with reference to the markings of high-quality nodes, including: determining the node clusters used for connection between the FPGAs, and using the node clusters used for connection as edge node clusters; screening out the first type of edge node clusters with unmarked high-quality nodes from the edge node clusters; and breaking up the first type of edge node clusters based on the node association information contained in the user design level as a constraint condition.

[0068] Optionally, the method further includes: determining node clusters that are not connected and used between the FPGAs; screening out the second type of edge node clusters marked with high-quality nodes from the edge node clusters; and keeping the unconnected node clusters and the second type of edge node clusters unchanged in each FPGA.

[0069] Step S205: testing the FPGA refinement tuning result.

[0070] In this embodiment, after obtaining the FPGA refinement and tuning results, the FPGA refinement and tuning results are further tested to further ensure the accuracy and stability of the segmentation results. In this embodiment, the test may be to test whether the nodes segmented to each FPGA meet the user design level or to test whether the segmentation results refer to the constraints of high-quality nodes.

[0071] In a specific implementation, when it is determined that node m is segmented onto FPGA1 and node n is segmented onto FPGA2 in the final segmentation result, since nodes m and n are both subordinate to node f of the previous user level, they have high cohesion and should theoretically be segmented onto the same FPGA. Therefore, the segmentation result is incorrect. In this case, an alarm prompt will be generated, such as "there is a risk of instability in the segmentation result this time."

[0072] In another specific implementation, when it is determined that nodes p and q are segmented to FPGA1 in the final segmentation result, but since node d has been marked as a high-quality node, nodes p and q are indirectly subordinate to node d and should not be broken up in theory, the segmentation result is due to, in this case, an alarm prompt will be generated, such as "there is a risk of segmentation error in this segmentation result". Of course, this implementation is only an example, and does not limit the specific items detected and the corresponding alarm methods. As long as it can serve as a prompt to the user, it is within the protection scope of this application and is not limited in this implementation.

[0073] It should be noted that, in this embodiment, after the alarm information is generated, the alarm prompt can be displayed in a visual manner, or sent to the supervisor's mobile terminal device in the form of a text message. Since the above problem may be caused by a problem with the segmentation algorithm in the software or a problem with the hardware device, it is convenient for the supervisor to obtain the message in time and perform maintenance.

[0074] In the implementation manner of the present application, when the user design file is cut into FPGA, the user design level is taken into consideration during the coarsening and refinement process. Since the user design level itself has the characteristics of high cohesion and low coupling, the problem of unstable segmentation results caused by pure data angle segmentation is avoided during coarsening and refinement. In addition, when refining, high-quality nodes are referenced to avoid them being broken up, and nodes with high cohesion characteristics are further retained, making the segmentation results more accurate.

[0075] Embodiment 3

[0076] Figure 3 This is a schematic diagram of the structure of a cutting device provided in Embodiment 3 of the present invention. Figure 3 As shown, the device includes: a high-quality node marking module 310, a hypergraph acquisition module 320, a coarsening module 330 and a refinement module 340.

[0077] A high-quality node marking module 310 is used to identify the user design file, determine the high-quality nodes and mark them, wherein the user design file is a tree structure including multiple user design levels;

[0078] A hypergraph acquisition module 320 is used to parse the user design file to generate a hypergraph;

[0079] A coarsening module 330, for coarsening the hypergraph based on the user design level to obtain node clusters, and dividing the node clusters onto different field programmable gate arrays FPGA;

[0080] The refinement module 340 is used to refine and tune the FPGA based on the user design level and with reference to the marks of the high-quality nodes.

[0081] Optional, high-quality node marking module, used to score the nodes included in each user's design hierarchy;

[0082] Nodes whose scoring results meet the preset threshold are regarded as high-quality nodes and marked.

[0083] Optionally, the high-quality node marking module is further used to determine the attribute information of the nodes included in each user design level, wherein the attribute information includes resource parameters, connection parameters and clock parameters;

[0084] Determine the weight of each attribute information, and score each node based on the weight and attribute information.

[0085] Optionally, a hypergraph acquisition module is used to parse the user design file to obtain hypergraph nodes and the relationships between the hypergraph nodes;

[0086] The hypergraph nodes are connected according to the relationships to construct a hypergraph.

[0087] Optionally, a coarsening module is used to obtain node association information contained in each user design level;

[0088] Taking node association information as a constraint, the hypergraph nodes are coarsened in a bottom-up manner to obtain node clusters, where each node cluster contains at least one hypergraph node;

[0089] The node clusters are divided into different FPGAs using a specified division algorithm, wherein each FPGA contains at least one node cluster.

[0090] Optionally, a refinement module is used to determine the node clusters used for connection between the FPGAs, and the node clusters used for connection are used as edge node clusters;

[0091] The first type of edge node clusters that screen out unlabeled high-quality nodes from edge node clusters;

[0092] The first type of edge node clusters are broken up using the node association information contained in the user-designed hierarchy as a constraint.

[0093] Optionally, the refinement module is further used to determine the node clusters that are not used for connection between the FPGAs;

[0094] Filter out the second type of edge node clusters marked with high-quality nodes from the edge node clusters;

[0095] The states of the unconnected node clusters and the second type of edge node clusters are kept unchanged in each FPGA.

[0096] The FPGA cutting device based on the user's design level provided in the embodiment of the present invention can execute the FPGA cutting method based on the user's design level provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0097] Embodiment 4

[0098] Figure 4 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0099] like Figure 4 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0100] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0101] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as the cutting method.

[0102] In some embodiments, the cutting method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the cutting method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the cutting method in any other appropriate manner (e.g., by means of firmware).

[0103] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0104] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0105] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0106] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0107] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0108] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0109] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0110] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A cutting method, characterized in that: include: Identify the user design file, determine the high-quality nodes and mark them, wherein the user design file is a tree structure including multiple user design levels; Parse the user design file to generate a hypergraph. ; Coarsening the hypergraph based on the user design level to obtain node clusters, and dividing the node clusters onto different field programmable gate arrays FPGA; The FPGA is fine-tuned based on the user design level and with reference to the mark of the high-quality node.

2. The method according to claim 1, characterized in that The step of identifying the user design file, determining the high-quality nodes and marking them includes: Scoring the nodes included in each of the user design levels; The nodes whose scoring results meet the preset threshold are regarded as the high-quality nodes, and the high-quality nodes are marked.

3. The method according to claim 2, characterized in that The scoring of the nodes included in each of the user design levels includes: Determining attribute information of nodes included in each of the user design levels, wherein the attribute information includes resource parameters, connection parameters, and clock parameters; The weight of each of the attribute information is determined, and each of the nodes is scored according to the weight and the attribute information.

4. The method according to claim 1, characterized in that The step of parsing the user design file to generate a hypergraph includes: Parsing the user design file to obtain hypergraph nodes and the relationships between the hypergraph nodes; The hypergraph nodes are connected according to the relationship to construct the hypergraph.

5. The method according to claim 1, characterized in that The step of coarsening the hypergraph based on the user design level to obtain node clusters, and dividing the node clusters onto different field programmable gate arrays FPGAs, includes: Acquire node association information contained in each of the user design levels; Taking the node association information as a constraint condition, coarsening the hypergraph nodes in a bottom-up manner to obtain the node clusters, wherein each of the node clusters contains at least one hypergraph node; The node clusters are divided into different FPGAs using a specified division algorithm, wherein each FPGA contains at least one node cluster.

6. The method according to claim 5, characterized in that The fine tuning of the FPGA based on the user design level and referring to the mark of the high-quality node includes: Determine a node cluster used for connection between the FPGAs, and use the node cluster used for connection as an edge node cluster; Filtering a first type of edge node cluster of unlabeled high-quality nodes from the edge node clusters; The first type of edge node clusters are broken up using the node association information included in the user design level as a constraint condition.

7. The method according to claim 6, characterized in that The method further comprises: Determine a node cluster that is not connected and used between the FPGAs; Filtering out a second type of edge node cluster marked with high-quality nodes from the edge node cluster; The states of the unconnected node cluster and the second-type edge node cluster are kept unchanged in each of the FPGAs.

8. A cutting device, characterized in that: The device comprises: A high-quality node marking module, used to identify the user design file, determine the high-quality nodes and mark them, wherein the user design file is a tree structure including multiple user design levels; A hypergraph acquisition module, used for parsing the user design file to generate a hypergraph; A coarsening module, used for coarsening the hypergraph based on the user design level to obtain node clusters, and dividing the node clusters onto different field programmable gate arrays FPGA; A refinement module is used to refine and tune the FPGA based on the user design level and with reference to the mark of the high-quality node.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the method according to any one of claims 1 to 7 when executed.

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