UVM register model automatic generation method, system and device and medium

Abstract

The invention relates to a UVM register model automatic generation method, system and device and a medium. The method comprises the following steps: dragging a word-format design specification of a to-be-tested module of the chip into a specified directory; running the Python script, capturing the attributes of each register in the design specification and storing the attributes as a first type of table, and capturing the attributes of each register domain under each register and storing the attributes as a second type of table; and matching registers in the first type of table with corresponding register domains in the second type of table through script parameters to obtain a csv file of the to-be-tested module of the chip, namely a third type of table, and converting according to the csv file to generate a UVM register model. By adopting the method, the design specification of the to-be-tested module of the chip can be dragged into the specified directory, and the UVM register model can be obtained after the python script is operated, so that the chip verification efficiency and the register model generation and development speed are greatly improved.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a UVM register model automatic generation method, system, device and medium. Background Art

[0002] Chip design and verification tools play a crucial role in this process. Design tools such as EDA (Electronic Design Automation) software continue to innovate, providing engineers with a more efficient and accurate design environment that supports development from circuit prototypes to large-scale integrated circuits. Verification tools, on the other hand, are crucial for ensuring chip functionality and performance. They cover multiple levels of verification, including functional verification, timing verification, and physical verification, ensuring reliable chip operation under a variety of conditions.

[0003] The advancement and innovation of these tools have driven continuous breakthroughs in chip technology. In terms of verification, for example, using the UVM (Universal Verification Methodology) register model allows engineers to more effectively verify chip register functionality and interoperability, ensuring the correctness and consistency of register operations. These models not only help capture the various properties and behaviors of registers but also enable tight integration with the verification environment, improving verification efficiency and reducing development cycles.

[0004] Currently, the main VCS tools on the market include RALGEN, which generates a RAL file through the test.ralf file after engineers fill in the relevant register table, and then enter the relevant RALGEN command to generate a register model. There is also the XML register model tool, which generates an XML intermediate file after engineers fill in the register attributes in the tool's table and enter relevant instructions to generate a register model.

[0005] As can be seen, current register model generation requires manual form filling, which can significantly increase the workload when dealing with a large number of registers, and correct filling cannot be guaranteed. This also creates intermediate files, requiring command input to generate the final file. This operation is time-consuming and cumbersome, making it inconvenient for workers. Given these issues, it is imperative to develop a method and system that improves verification efficiency and reduces the development cycle of register model generation. Summary of the Invention

[0006] Based on this, it is necessary to provide a UVM register model automatic generation method, system, device and medium to address the above technical problems.

[0007] A UVM register model automatic generation method, the method comprising: Drag the design specification of the chip module to be tested in Word format into the specified directory; Run the Python script to capture the attributes of each register in the design specification and store them as the first type of table, and capture the attributes of each register field under each register and store them as the second type of table; The registers in the first type of table are paired with the corresponding register fields in the second type of table through script parameters to obtain the CSV file of the chip module to be tested, also known as the third type of table, and the UVM register model is generated based on the CSV file conversion.

[0008] In one embodiment, before running the Python script, the method further includes: filling in relevant parameters generated by the UVM register model, including a lower parameter, a filelst_open parameter, a gen_csv parameter, and an x ​​parameter and a y parameter; Among them, the lower parameter is used to control the case of the names of each register and each register field captured from the design manual of the chip module to be tested; the filelst_open parameter is used to control whether to perform a list operation when the register field names of all registers except numbers in the register field are the same, that is, to store register fields with the same name in a queue for representation; the gen_csv parameter is used to control whether to generate a csv file for the chip module to be tested, among which the gen_sv parameter is used to control whether to generate a register model sv file and an env_cfg sv file; the x parameter corresponds to the number of parameterized register names; the y parameter corresponds to the number of register channels.

[0009] In one embodiment, a Python script is run to capture the attributes of each register in the design specification and store them as a first type of table, including: The Python script first extracts the name of the chip module to be tested and stores it; Then, according to the keywords set in the Python script, the properties of each register in the design specification of the chip module to be tested are captured, including the name, offset address, access attribute and reset value of each register, and stored as the first type table of the chip module to be tested.

[0010] In one embodiment, the attributes of each register field under each register are captured and stored as a second type of table, including: According to the keywords set in the Python script, the properties of each register field under each register in the design specification of the chip module to be tested are captured, including the name, offset address, access attribute, access permission, reset value, high bit and low bit of each register field, and stored as the second type table of the chip module to be tested.

[0011] In one embodiment, the registers in the first type of table are paired with the corresponding register fields in the second type of table through script parameters to obtain a CSV file of the chip module to be tested, including: Fill in the number of channels contained in the register and the number of repeated identical registers through script parameters, and use Python script to read the first and second tables of the chip module to be tested. If it is recognized that the register in the first table contains script parameters, expand the first table, increase the number of corresponding registers, and add numbers after the register name to distinguish them. At the same time, the corresponding register field in the second table is also added to the register, and the resulting csv file with the file name of the chip module to be tested is stored. The csv file contains the register name, register offset address, register read and write properties, register domain name, register domain access properties, register domain reset value, register domain low bit, register domain high bit, privileged attributes, and the path after the register domain.

[0012] In one embodiment, generating a UVM register model according to a CSV file conversion includes: Generate register model sv file, env_cfg sv file and reg_test file according to csv file conversion; The register model sv file includes the declaration of each register and the declaration of the total set of registers; wherein, in the declaration of each register, if the register number parameter and the register number channel number parameter are included, the register number parameter and the register number channel number parameter are deleted, and the register domain corresponding to the register is declared in sequence, wherein the register domain declaration includes the declaration of the covergroup function, the declaration of the new function, the declaration of the build function and the declaration of the sample function; in the declaration of the total set of registers, the registers containing the register number parameter and the register number channel number parameter are declared in a multi-dimensional queue, and the new function and the build function are declared, and each register is created or added in sequence; The env_cfg sv file includes the rand declaration of the RW and RO attributes in each register domain, as well as the declaration of the registers corresponding to each register domain, and declares an updata_reg function, which concatenates the corresponding bits of the register domain into a name corresponding to a register. This function is placed in the post_randomize function; the env_cfgsv file is mainly used for random use of the UVM register model; The reg_test file is used to directly generate test cases for UVM register model detection. The test cases are used to test the read and write properties, reset values, privileged modes, user access, and lock functions of the UVM register model.

[0013] In one embodiment, the method further includes: generating a reg_define file according to the first type of table conversion, wherein the reg_define file is used to replace the corresponding register offset address with the register name through macro definition.

[0014] A UVM register model automatic generation system, the system comprising: The document acquisition module is used to drag the design specification of the chip module to be tested in Word format into the specified directory; The attribute capture module is used to run the Python script to capture the attributes of each register in the design specification and store them as the first type of table, and to capture the attributes of each register field under each register and store them as the second type of table; The register model automatic generation module is used to pair the registers in the first type of table with the corresponding register fields in the second type of table through script parameters to obtain the CSV file of the chip module to be tested, also known as the third type of table, and generate the UVM register model based on the CSV file.

[0015] A computer device includes a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented: Drag the design specification of the chip module to be tested in Word format into the specified directory; Run the Python script to capture the attributes of each register in the design specification and store them as the first type of table, and capture the attributes of each register field under each register and store them as the second type of table; The registers in the first type of table are paired with the corresponding register fields in the second type of table through script parameters to obtain the CSV file of the chip module to be tested, also known as the third type of table, and the UVM register model is generated based on the CSV file conversion.

[0016] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the following steps: Drag the design specification of the chip module to be tested in Word format into the specified directory; Run the Python script to capture the attributes of each register in the design specification and store them as the first type of table, and capture the attributes of each register field under each register and store them as the second type of table; The registers in the first type of table are paired with the corresponding register fields in the second type of table through script parameters to obtain the CSV file of the chip module to be tested, also known as the third type of table, and the UVM register model is generated based on the CSV file conversion.

[0017] The above-mentioned UVM register model automatic generation method, system, device and medium can directly convert and generate a UVM register model by identifying the design specification in Word format of the chip module to be tested and running a Python script to capture the information of relevant registers and register fields. After processing and splicing the data into the required CSV file, it can greatly improve the chip verification efficiency and the register model generation and development speed. At the same time, the operation process is simple and easy for users to operate. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic flow chart of a UVM register model automatic generation method in one embodiment; Figure 2 A schematic diagram of a flow chart of Python script execution in one embodiment; Figure 3 A schematic diagram of the register model sv file output format in one embodiment; Figure 4 Schematic diagram of the env_cfg sv file output format in one embodiment; Figure 5 A schematic diagram of the output format of a reg_define file in one embodiment; Figure 6 A schematic diagram of the output format of a reg_test file in one embodiment; Figure 7 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0020] In one embodiment, Figure 1 As shown, a UVM register model automatic generation method is provided, comprising the following steps: Step 1: Drag the design specification of the chip module to be tested in Word format into the specified directory.

[0021] Step 2: Run the Python script to capture the attributes of each register in the design specification and store them as a first-type table, and capture the attributes of each register field under each register and store them as a second-type table.

[0022] Specifically, if Figure 2 As shown, before running the Python script, you also need to fill in the relevant parameters for UVM register model generation, including the lower parameter, filelst_open parameter, gen_csv parameter, and x and y parameters. Among them, the lower parameter is used to control the case of the names of each register and each register field captured from the design specification of the chip module under test; the filelst_open parameter is used to control whether to perform a list operation when the register field names of all registers other than numbers in the register field are the same, that is, register fields with the same name are stored in a queue for representation; the gen_csv parameter is used to control whether to generate a CSV file for the chip module under test, among which the gen_sv parameter is used to control whether to generate a register model .sv file and an env_cfg .sv file; the x parameter corresponds to the number of parameterized register names; the y parameter corresponds to the number of register channels.

[0023] Next, the Python script runs. It first extracts the name of the chip module under test from the design specification and stores it. Then, based on the keyword "Name" set in the Python script, it extracts the properties of each register in the chip module under test's design specification, including the register's name (Name), offset address (Address offset), access attribute (Access), and reset value (Reset value). These properties are stored as the first-class table for the chip module under test. Register access attributes include privileged attributes and user access.

[0024] Then, according to the keyword "Bit field" set in the Python script, the attributes of each register field under each register in the design specification of the chip module to be tested are captured, including the name (Name), offset address (Address offset), access attribute (Access), access permission (Attribute), reset value (Reset value) and high bit and low bit of each register field, and stored as the second type of table of the chip module to be tested.

[0025] Step 3, pair the registers in the first type of table with the corresponding register fields in the second type of table through script parameters to obtain the CSV file of the chip module to be tested, also known as the third type of table, and generate the UVM register model according to the CSV file conversion.

[0026] Specifically, the number of channels and the number of duplicate registers in a register are first filled in using script parameters. A Python script is then used to read the first and second tables of the chip module under test. If a register in the first table is found to contain script parameters, the first table is expanded, the corresponding register number is increased, and a number is added after the register name to distinguish it. The corresponding register field in the second table is also added to the register. The resulting CSV file, named the chip module under test, contains the register name (register), register offset address (address), register read / write attributes (reg_access), register field name (field), register field access attributes (field_access), register field reset value (reset_value), register field low bit (bitpos_start), register field high bit (bitpos_end), privilege attributes (attributes), and register field backdoor (backdoor). Read / write attributes include readable, writable, or read / write.

[0027] Then, the register model sv file, env_cfg sv file and reg_test file are generated according to the csv file conversion.

[0028] Among them, the output format of the register model sv file is as follows Figure 3 As shown, the file includes the declaration of each register and the declaration of the total set of registers (the total block); wherein, in the declaration of each register, if the register number parameter and the register number channel number parameter are included, the register number parameter and the register number channel number parameter are deleted, and the register domain corresponding to the register is declared in sequence, wherein the register domain declaration includes the declaration of the covergroup function, the declaration of the new function, the declaration of the build function and the declaration of the sample function; in the declaration of the total set of registers, the registers containing the register number parameter and the register number channel number parameter are declared in a multi-dimensional queue, and the new function and the build function are declared, and each register is created (create) or added (add_reg) in sequence.

[0029] The specific generation process of the register model sv file includes: generating the class code of the corresponding register based on the generated csv file, and including the new function, build function, covergroup function and sample function in the class code. In the build function, the register domains under the corresponding registers are created in sequence, and the bit width, read-write properties, reset value and other properties of the register domains are generated, and then the paths behind the registers are generated in sequence. In the covergroup function, coverage is created for the corresponding register domain. In the sample function, the coverage is sampled, and finally uvm_reg_block is generated, the corresponding registers are included in the class code, and each class is created in the build function of the class code, and a map is created, and the offset address and read-write properties of each register are added to the map. The register model sv file is finally output.

[0030] The output format of the env_cfg sv file is as follows Figure 4 As shown, the file includes the rand declaration of the RW (readable and writable) attributes and RO (read-only) attributes in each register domain, as well as the declaration of the registers corresponding to each register domain, and declares an updata_reg function, which concatenates the corresponding bits of the register domain into a name corresponding to a register. This function is placed in the post_randomize function; the env_cfg sv file is mainly used for random use of the UVM register model.

[0031] The specific process for generating the env_cfg.sv file involves generating the corresponding env_cfg.sv class code based on the generated CSV file, selecting register fields with the RW attribute and declaring them as rand variables, which in turn declare the corresponding registers as constants. The update_reg_cfg function is then generated, which performs randomization on the register fields and concatenates and assigns values ​​to the corresponding registers, achieving randomization verification. This ultimately outputs the env_cfg.sv file.

[0032] The output format of the reg_test file is as follows Figure 6As shown in the figure, this file is used to directly generate test cases for UVM register model detection. These test cases test the read and write properties, reset value, privileged mode, user access, and lock functions of the UVM register model. Specifically, the file captures the access properties and feature access permissions in the registers and generates functions such as calling privileged access functions for the corresponding registers, checking reset values ​​for the corresponding registers, checking lock functions for the corresponding registers, and checking read and write properties for the corresponding registers. This ultimately outputs the reg_test file. This file can save chip verification time.

[0033] Furthermore, the above method further comprises: converting and generating a reg_define file according to the first type table of the chip module to be tested. The output format of the reg_define file is as follows: Figure 5 As shown in the figure, this file uses macro definitions to replace the register names with their corresponding register offset addresses. This file is mainly used to replace parameter macros when accessing registers, which makes it easier to read and port projects.

[0034] In summary, the present application provides a UVM register model automatic generation method, which realizes the automatic capture of register and register domain attribute information in the design specification of the chip module to be tested through the operation of Python scripts, thereby automatically generating register model sv files, env_cfg sv files, reg_define files and reg_test files according to the captured information, greatly improving the chip verification efficiency of the verification personnel and reducing the development cycle of the UVM register model. At the same time, its operation process is simple and convenient for the verification personnel to operate.

[0035] In one embodiment, a UVM register model automatic generation system is provided, comprising: The document acquisition module is used to drag the design specification of the chip module to be tested in Word format into the specified directory; The attribute capture module is used to run the Python script to capture the attributes of each register in the design specification and store them as the first type of table, and to capture the attributes of each register field under each register and store them as the second type of table; The register model automatic generation module is used to pair the registers in the first type of table with the corresponding register fields in the second type of table through script parameters to obtain the CSV file of the chip module to be tested, also known as the third type of table, and generate the UVM register model based on the CSV file.

[0036] The specific limitation about UVM register model automatic generation system can refer to the limitation for UVM register model automatic generation method above, and will not be repeated here. Each module in above-mentioned UVM register model automatic generation system can be realized in whole or in part by software, hardware and combination thereof. Above-mentioned each module can be embedded in or be independent of the processor in the computer device in hardware form, and can also be stored in the memory in the computer device in software form, so that the processor calls the operation corresponding to each of the above modules.

[0037] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 7 As shown. The computer device includes a processor, a memory, a network interface, and a database connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a UVM register model automatic generation method is implemented.

[0038] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0039] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented: Drag the design specification of the chip module to be tested in Word format into the specified directory; Run the Python script to capture the attributes of each register in the design specification and store them as the first type of table, and capture the attributes of each register field under each register and store them as the second type of table; The registers in the first type of table are paired with the corresponding register fields in the second type of table through script parameters to obtain the CSV file of the chip module to be tested, also known as the third type of table, and the UVM register model is generated based on the CSV file conversion.

[0040] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: Drag the design specification of the chip module to be tested in Word format into the specified directory; Run the Python script to capture the attributes of each register in the design specification and store them as the first type of table, and capture the attributes of each register field under each register and store them as the second type of table; The registers in the first type of table are paired with the corresponding register fields in the second type of table through script parameters to obtain the CSV file of the chip module to be tested, also known as the third type of table, and the UVM register model is generated based on the CSV file conversion.

[0041] A person skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0042] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0043] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A UVM register model automatic generation method, characterized in that, The method comprises: Drag the design specification of the chip module to be tested in word format into the specified directory; Run the Python script to capture the attributes of each register in the design specification and store them as a first type of table, and capture the attributes of each register field under each register and store them as a second type of table; The registers in the first type of table are paired with the corresponding register fields in the second type of table through script parameters to obtain a csv file of the chip module to be tested, also known as the third type of table, and a UVM register model is generated according to the csv file conversion.

2. The method according to claim 1, characterized in that Before running the Python script, it also includes: filling in the relevant parameters generated by the UVM register model, including lower parameters, filelst_open parameters, gen_csv parameters, and x parameters and y parameters; Among them, the lower parameter is used to control the case of the names of each register and each register domain captured from the design specification of the chip module to be tested; the filelst_open parameter is used to control whether to perform a list operation when the register domain names of registers other than numbers in the register domain are the same, that is, the register domains with the same name are stored in a queue for representation; the gen_csv parameter is used to control whether to generate a csv file of the chip module to be tested, wherein the gen_sv in the parameter is used to control whether to generate a register model sv file and an env_cfg sv file; the x parameter corresponds to the number of parameterized register names; the y parameter corresponds to the number of register channels.

3. The method according to claim 2, characterized in that Run the Python script to capture the properties of each register in the design specification and store them as a first-class table, including: The Python script first extracts the name of the chip module to be tested and stores it; Then, according to the keywords set in the Python script, the properties of each register in the design specification of the chip module to be tested are captured, including the name, offset address, access attribute and reset value of each register, and stored as the first type table of the chip module to be tested.

4. The method according to claim 3, characterized in that: The attributes of each register field under each register are captured and stored as the second type of table, including: According to the keywords set in the Python script, the properties of each register field under each register in the design specification of the chip module to be tested are captured, including the name, offset address, access attribute, access permission, reset value, high bit and low bit of each register field, and stored as the second type table of the chip module to be tested.

5. The method according to claim 1, characterized in that The registers in the first type of table are matched with the corresponding register fields in the second type of table through script parameters to obtain a csv file of the chip module to be tested, including: The number of channels contained in the register and the number of repeated identical registers are filled in through script parameters, and the first and second tables of the chip module to be tested are read using Python scripts. If it is recognized that the registers in the first table contain script parameters, the first table is expanded, the number of corresponding registers is increased, and numbers are added after the register names to distinguish them. At the same time, the corresponding register domain in the second table is also added to the register, and a csv file with the file name of the chip module to be tested is stored. The csv file contains the register name, the offset address of the register, the read and write properties of the register, the register domain name, the access properties of the register domain, the reset value of the register domain, the low bit of the register domain, the high bit of the register domain, the privileged attribute, and the path behind the register domain.

6. The method according to claim 5, characterized in that Generate a UVM register model according to the csv file conversion, including: Generate register model sv file, env_cfg sv file and reg_test file according to the csv file conversion; The register model sv file includes declarations of each register and a total set of registers; wherein, in the declaration of each register, if a register number parameter and a channel number parameter contained in the register are included, the register number parameter and the channel number parameter contained in the register are deleted, and the declaration of the register domain corresponding to the register is performed in sequence, wherein the declaration of the register domain includes a covergroup function declaration, a new function declaration, a build function declaration, and a sample function declaration; in the declaration of the total set of registers, a multi-dimensional queue declaration is performed on the registers containing the register number parameter and the channel number parameter contained in the register, and the new function and the build function are declared, and each register is created or added in sequence; The env_cfg sv file includes a rand declaration for the RW attribute and the RO attribute in each register domain, and a declaration for the register corresponding to each register domain, and declares an updata_reg function, which splices the corresponding bits of the register domain into a name corresponding to a register, and the function is placed in the post_randomize function; the env_cfg sv file is mainly used for random use of the UVM register model; The reg_test file is used to directly generate a test case for UVM register model detection, and the read and write properties, reset value, privileged mode, user access and lock functions of the UVM register model are tested through the test case.

7. The method according to claim 1, characterized in that The method further comprises: A reg_define file is generated according to the first type of table conversion, wherein the reg_define file is used to replace the corresponding register offset address with the name of the register through macro definition.

8. A UVM register model automatic generation system, characterized in that, The system comprises: The document acquisition module is used to drag the design specification of the chip module to be tested in word format into the specified directory; An attribute capture module, used to run a Python script, capture the attributes of each register in the design specification and store them as a first type of table, and capture the attributes of each register field under each register and store them as a second type of table; The register model automatic generation module is used to pair the registers in the first type of table with the corresponding register fields in the second type of table through script parameters, obtain a csv file of the chip module to be tested, also known as the third type of table, and generate a UVM register model according to the csv file conversion.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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