Electrostatic discharge structure robustness evaluation method and device

Abstract

The invention provides an electrostatic discharge structure robustness evaluation method and device, and belongs to the technical field of semiconductors, and the method comprises the steps: carrying out the layer-by-layer removal of a chip, carrying out the circuit analysis of the obtained layout information, obtaining a schematic circuit diagram, carrying out the section dyeing processing according to the schematic circuit diagram, and obtaining the geometric information, and detecting the electrostatic discharge structure to obtain PN region distribution information, performing TCAD simulation by using the layout information, the geometric information and the PN region distribution information, and determining the robust performance of the electrostatic discharge structure of the chip according to the obtained electrical characteristic information. According to the electrostatic discharge structure robustness evaluation method and device provided by the invention, an electrostatic discharge structure robustness evaluation means based on structure extraction and TCAD simulation is provided, and a device design manufacturer does not need to provide a schematic circuit diagram and layout of the electrostatic discharge structure and does not need to provide process parameters; and the robustness evaluation efficiency of the ESD structure of the semiconductor device is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an electrostatic discharge structure robustness evaluation method and a device thereof. Background Art

[0002] Electrostatic Discharge (ESD) structure is an important part of protecting semiconductor devices from electrostatic discharge damage. ESD structure provides a low impedance path so that the electrostatic discharge current can quickly pass through the device where the device is located, thereby protecting the sensitive electronic components inside from damage.

[0003] The existing ESD robustness performance test of semiconductor devices has specific test standards, which specifically define the impact current waveform at each voltage level, how to calibrate the ESD pulse source and the test environment used for measurement. It also stipulates the different voltage ranges that semiconductor devices can withstand and the corresponding different levels.

[0004] When using this method for testing, the common practice is to start from a lower voltage and apply the voltage step by step until the semiconductor device fails. However, for large-scale integrated circuits, due to the large number of pins of semiconductor devices, the ESD test method is costly and time-consuming. Summary of the invention

[0005] The present invention provides an electrostatic discharge structure robustness evaluation method and device thereof, which are used to solve the defects of high cost, long time consumption and low efficiency in the prior art of blindly applying voltage.

[0006] The present invention provides an electrostatic discharge structure robustness evaluation method, comprising the following steps: removing a chip layer by layer to obtain layout information of the chip; Performing circuit analysis on the layout information to obtain a circuit schematic diagram of an electrostatic discharge structure in the chip; Performing cross-sectional coloring processing on the electrostatic discharge structure according to the circuit schematic diagram to obtain geometric information of the electrostatic discharge structure; Detecting a target area in the electrostatic discharge structure to obtain PN region distribution information of the electrostatic discharge structure, wherein the PN region distribution information includes positions of a P region and an N region and doping concentration information of each P region and each N region, wherein the target area is determined according to geometric information of the electrostatic discharge structure; The layout information, the geometric information and the PN region distribution information are used to perform TCAD simulation, and the robust performance of the electrostatic discharge structure of the chip is determined according to the obtained electrical characteristic information.

[0007] According to an electrostatic discharge structure robustness evaluation method provided by the present invention, removing the chip layer by layer to obtain the layout information of the chip includes: Based on physical grinding or chemical etching methods, each passivation layer, each metallization layer, and each polysilicon layer of the chip are removed layer by layer until the substrate is completely exposed; After each layer is removed, a microscope is used to record information about the next layer’s layout; The layout information includes the layout information of the chip, as well as the position and shape information of the components contained in each layer of the chip, the component size information, the component connection relationship information and the design rule information of the components.

[0008] According to a robustness evaluation method for an electrostatic discharge structure provided by the present invention, the cross-section coloring process is performed on the electrostatic discharge structure according to the circuit schematic diagram to obtain geometric information of the electrostatic discharge structure, including: Determining a target position for cutting the electrostatic discharge structure according to the circuit schematic diagram to perform cutting of the electrostatic discharge structure, wherein the target position is determined based on a core component that performs an electrostatic discharge protection function in the electrostatic discharge structure; dyeing the cut cross section with a dye to distinguish different material layers and structures on the cross section by different colors; According to the color distribution on the cross section, the geometric information of the electrostatic discharge structure is determined.

[0009] According to an electrostatic discharge structure robustness evaluation method provided by the present invention, the geometric information includes one or more of gate length, channel length, and junction depth.

[0010] According to an electrostatic discharge structure robustness evaluation method provided by the present invention, detecting a target area in the electrostatic discharge structure to obtain PN region distribution information of the electrostatic discharge structure includes: Performing scanning capacitance microscopy detection on the target area to determine the positions of the P region and the N region of the electrostatic discharge structure according to the detected doping distribution information of the target area; The positions of the P region and the N region are detected by scanning diffuse resistance microscopy to obtain the doping concentration information of each P region and each N region.

[0011] According to an electrostatic discharge structure robustness evaluation method provided by the present invention, the TCAD simulation is performed using the layout information, the geometric information and the PN region distribution information, and the robust performance of the electrostatic discharge structure of the chip is determined according to the obtained electrical characteristic information, including: Setting simulation parameters of TCAD simulation according to the layout information, the geometric information and the PN area distribution information; According to the simulation parameters, simulating the behavior of the electrostatic discharge structure under at least one electrostatic discharge impact, and obtaining electrical characteristic information of the electrostatic discharge structure; The robust performance of the electrostatic discharge structure is determined according to the acquired electrical characteristic information.

[0012] According to an electrostatic discharge structure robustness evaluation method provided by the present invention, the electrical characteristic information includes one or more characteristic information related to a current-time curve, a voltage-time curve, a current-voltage curve, and an internal temperature distribution; The characteristic information related to the current-time curve includes response speed, peak current, and duration; The characteristic information related to the voltage-time curve includes voltage clamping and voltage recovery time; The characteristic information related to the current-voltage curve includes breakdown voltage and post-breakdown behavior; The characteristic information related to the internal temperature distribution includes the internal hot spot magnitude distribution position and the hot spot temperature rise.

[0013] The present invention also provides an electrostatic discharge structure robustness evaluation device, comprising the following modules: A layout information acquisition unit, used to remove the chip layer by layer to obtain the layout information of the chip; A circuit principle analysis unit, used to perform circuit analysis on the layout information to obtain a circuit principle diagram of the electrostatic discharge structure in the chip; A geometric information acquisition unit, used to perform cross-sectional coloring processing on the electrostatic discharge structure according to the circuit schematic diagram to obtain geometric information of the electrostatic discharge structure; a doping concentration analysis unit, configured to detect a target region in the electrostatic discharge structure and obtain PN region distribution information of the electrostatic discharge structure, wherein the PN region distribution information includes positions of a P region and an N region and doping concentration information of each P region and each N region, wherein the target region is determined according to geometric information of the electrostatic discharge structure; The robust performance analysis unit is used to perform TCAD simulation using the layout information, the geometric information and the PN area distribution information, and determine the robust performance of the electrostatic discharge structure of the chip according to the obtained electrical characteristic information.

[0014] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the electrostatic discharge structure robustness evaluation method described above is implemented.

[0015] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the electrostatic discharge structure robustness evaluation method as described in any one of the above is implemented.

[0016] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the electrostatic discharge structure robustness evaluation method as described above is implemented.

[0017] The electrostatic discharge structure robustness evaluation method and device provided by the present invention provide an electrostatic discharge structure robustness evaluation means based on structure extraction and TCAD simulation, which does not require device design manufacturers to provide circuit schematics and layouts of the electrostatic discharge structure, nor does it require them to provide process parameters, thereby effectively improving the efficiency of ESD structure robustness evaluation of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a schematic flow chart of the electrostatic discharge structure robustness evaluation method provided by the present invention.

[0020] Figure 2 The figure is a schematic diagram of the circuit principle of an ESD structure provided by the present invention.

[0021] Figure 3 It is a schematic diagram of setting the cross-sectional coloring dimensions of an ESD structure provided by the present invention.

[0022] Figure 4 It is a schematic diagram of an SCM image of an ESD structure provided by the present invention.

[0023] Figure 5 It is a structural schematic diagram of the electrostatic discharge structural robustness evaluation device provided by the present invention.

[0024] Figure 6 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] It should be noted that in the description of the present invention, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "include one..." do not exclude the existence of other identical elements in the process, method, article or device including the elements. The orientation or position relationship indicated by the terms "upper", "lower" and the like is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. Unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a connection between the two elements. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] The terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" means at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0028] Electrostatic Discharge (ESD) structures are an important part of protecting devices from damage caused by electrostatic discharge. ESD structures are designed to safely direct static charges to ground, thereby preventing charges from accumulating inside the device and causing damage.

[0029] When a semiconductor device is struck by ESD, the components in the ESD structure respond quickly and direct the electrostatic charge to the ground. The specific working principle may vary depending on the type of component, but generally includes the following steps: (1) Charge induction and accumulation: Electrostatic charge accumulates on the device surface or pins.

[0030] (2) Charge discharge: Components in the ESD structure, such as diodes, MOS tubes, and silicon controlled rectifiers (SCRs), respond quickly and discharge the accumulated charge to the ground.

[0031] (3) Voltage clamping: By discharging the charge, the ESD structure clamps the voltage across the device within a safe range to prevent device damage.

[0032] Technology Computer Aided Design (TCAD) is a method that uses computer simulation technology to develop and optimize semiconductor devices and their processing technologies. It is a branch of EDA (Electronic Design Automation) that focuses on semiconductor process simulation and device simulation. It helps engineers predict and optimize device performance during the design phase by simulating the manufacturing process, working mechanism, and performance characteristics of semiconductor devices, thereby reducing the number of experimental wafers, shortening the development cycle, and reducing development costs.

[0033] For ESD robustness performance testing of semiconductor devices, especially for large-scale integrated circuits, the ESD testing method is costly and time-consuming due to the large number of device pins. TCAD, as a simulation tool based on physical principles, can accurately describe the transient large signal characteristics and degradation characteristics of semiconductor devices under extreme conditions.

[0034] Through TCAD simulation, we can deeply understand the physical phenomena and failure mechanisms of ESD protection circuits when they are subjected to ESD shocks. Therefore, it is often used to evaluate the robustness of ESD structures.

[0035] However, TCAD simulation requires obtaining process parameters such as gate length, channel length, junction depth, doping distribution, doping concentration of the device ESD structure and design parameters such as layout information of the ESD structure. However, these two types of parameters are often difficult to obtain. Therefore, the results of ESD simulation are quite different from the actual ESD test results.

[0036] The electrostatic discharge structure robustness evaluation method and device provided by the present invention aim to provide an ESD structure robustness evaluation method based on structure extraction and TCAD simulation, which does not require the device design manufacturer to provide the schematic diagram and layout of the ESD structure, nor does it require the device manufacturer to provide process parameters, thereby effectively improving the efficiency of the ESD structure robustness evaluation of semiconductor devices.

[0037] In general, the technical principle of the present invention is to obtain the layout information and circuit schematic diagram of the device ESD structure through chip delamination technology and circuit structure analysis, and then obtain the process parameter information of the semiconductor device ESD structure through cross-section staining technology and scanning technology. Finally, TCAD simulation is performed based on all the above information to obtain the ESD structural robustness of the semiconductor device.

[0038] Combine the following Figure 1-Figure 6 The present invention provides an electrostatic discharge structure robustness evaluation method and a device thereof, aiming to provide a new semiconductor device ESD structure robustness evaluation method based on structure extraction and TCAD simulation.

[0039] Figure 1 is a flow chart of the electrostatic discharge structure robustness evaluation method provided by the present invention, such as Figure 1 As shown, including but not limited to the following steps: Step 101, remove the chip layer by layer to obtain the layout information (LayoutInformation) of the chip. The purpose of performing this step is to obtain the layout information of each layer inside the chip, especially to obtain the ESD structure of the semiconductor device on the assembled chip.

[0040] Layout information refers to the detailed pattern and structure information of each level in semiconductor chip design. Layout information is very critical data in the chip design and manufacturing process. It describes in detail the position, shape, size and connection relationship of each component on the chip. Layout information usually includes hierarchical structure, component position and shape, size parameters, connection relationship and design rules.

[0041] Among them, the chip is composed of multiple layers, each of which has a specific function, such as metal layer, polysilicon layer, oxide layer, doping layer, etc. The hierarchical structure in the layout information will describe the structure and layout of each layer in detail.

[0042] Component location and shape refers to the layout information including the specific location and shape of various components on the chip (such as transistors, diodes, resistors, capacitors, etc.). These components are the basic units that constitute the circuit function.

[0043] The size and spacing of components have a significant impact on the performance of the chip. The layout information accurately defines these dimensional parameters, such as the gate length and width of the transistor, and the minimum spacing between components.

[0044] Layout information also shows how different components are connected, including wires, contact holes (vias) and other interconnect structures. These connection relationships are the key to realizing circuit functions.

[0045] Finally, the layout information follows specific design rules that are determined by the manufacturing process, including the maximum size, minimum size, alignment requirements, etc. of the components.

[0046] It should be noted that when peeling off the chips layer by layer, special attention should be paid to the ESD structure, for example, the position and connection method of the diodes should be well protected.

[0047] Based on the content of the above embodiment, as an optional embodiment, the execution process of step 101 may include but is not limited to the following steps: Based on physical grinding or chemical etching methods, the passivation layers, metallization layers, and polysilicon layers of the chip are removed layer by layer until the substrate is completely exposed. After each layer is removed, the layout information of the next layer is recorded using a microscope.

[0048] The layout information in this embodiment mainly includes the layout information of the chip, as well as the component position and shape information, component size information, component connection relationship information and component design rule information contained in each layer of the chip.

[0049] The above layout information can exist in the form of graphic files, such as GDS II (Graphic Data System II) or OASIS (Open Artwork System Interchange Standard) format. These graphic files contain all the necessary information for chip design and are an indispensable part of the chip manufacturing process.

[0050] Specifically, physical or chemical delamination needs to be performed first, including: using physical grinding or chemical etching methods to remove the passivation layer, metallization layer, and polysilicon layer on the chip surface layer by layer until the substrate is exposed.

[0051] Suppose a complementary metal-oxide-semiconductor (CMOS) chip with multiple layers of metallization and polysilicon layers needs to be evaluated. Through the de-layering technology, the passivation layer is first removed and the layout information of each metallization layer is recorded; then the metallization layer is continued to be removed, the layout information of the polysilicon layer is recorded, and finally the substrate is reached.

[0052] Step 102: Perform circuit analysis on the layout information to obtain a circuit schematic diagram of the electrostatic discharge structure in the chip.

[0053] The purpose of this step is to convert the layout information into a circuit schematic for circuit-level analysis. The specific steps can be described as follows: First, the layout information obtained after de-layering is analyzed to identify the various components and the connection relationships between them.

[0054] Then, based on the analysis results, draw the schematic diagram of the ESD structure, including the symbols and connection methods of each component.

[0055] Figure 2 Schematic diagram of a circuit principle of an ESD structure provided by the present invention, such as Figure 2 As shown in the figure, in the process of analyzing the layout information, an ESD structure was found, which is specifically composed of PMOS, resistors, NMOS, and diodes. Among them, the diode is the path from ground to power supply, and the PMOS tube is the path from power supply to ground. When the ESD pulse arrives, it is instantly coupled to the gate of the PMOS tube, and the gate voltage of the MOS is slightly turned on, reducing the breakdown voltage of the PMOS tube. Therefore, when drawing the circuit schematic diagram of the ESD structure, the structure of the PMOS tube is emphasized to clearly show the circuit connection and circuit principle of this ESD structure.

[0056] Step 103 , performing cross-section coloring processing on the electrostatic discharge structure according to the circuit schematic diagram to obtain geometric information of the electrostatic discharge structure.

[0057] The purpose of performing this step is to reveal the internal geometric features of the ESD structure by cross-sectional dyeing, which mainly includes but is not limited to the following steps: First, the key parts of the identified ESD structure are physically cut to expose its cross section.

[0058] The cut sections are then stained with a dye to differentiate between different materials and structures.

[0059] Finally, the dyed cross-section can be observed under a microscope to measure geometric parameters such as gate length, channel length, junction depth, etc.

[0060] For example, in the case where the ESD structure mainly includes a protection diode, the area where the protection diode is located can be physically cut and stained with a dye. Through microscopic observation, the geometric parameters can be measured as a gate length of 1 micron, a channel length of 0.5 micron, and a junction depth of 0.2 micron.

[0061] Step 104 , detecting the target area in the electrostatic discharge structure to obtain PN region distribution information of the electrostatic discharge structure.

[0062] The PN region distribution information includes the positions of the P region and the N region and the doping concentration information of each P region and each N region, and the target region is determined according to the geometric information of the electrostatic discharge structure.

[0063] In semiconductor physics, P region and N region refer to regions with different doping types: The P-type region refers to a semiconductor region doped with acceptor impurities (such as boron, gallium, etc.). The acceptor impurities accept electrons and leave holes, so the main carriers in the P region are holes.

[0064] N-type region refers to a semiconductor region doped with donor impurities (such as phosphorus, arsenic, etc.). Donor impurities provide additional electrons, so the main carriers in the N region are electrons.

[0065] In an ESD structure, the doping distribution of the P and N regions is critical to the performance of semiconductor devices. For example, an ESD structure may include N-type and P-type doped regions to form PN junctions or other structures with specific conductive properties that play a protective role in electrostatic discharge events. By accurately determining the location and doping concentration of these P and N regions, the design and performance of the ESD structure can be evaluated. This is critical for optimizing ESD protection design and improving the robustness of semiconductor devices.

[0066] Therefore, the purpose of executing step 104 is to detect the doping distribution to determine the distribution information of the P region, N region and PN region in the ESD structure. The specific execution steps can be simply described as follows: First, specific areas of the ESD structure are scanned and the doping concentration and type are inferred from the changes in capacitance.

[0067] Then, based on the SCM scanning results, the doping distribution is analyzed to determine the location and range of the P and N regions.

[0068] Furthermore, after the positions and ranges of the P regions and the N regions are determined, it is necessary to perform detailed scanning on each of the P regions and the N regions to determine the doping concentration of each of the P regions and the N regions.

[0069] For example, an SCM scan of a specific area where the protection diode in the ESD structure is located determines that there is a highly doped N region under the gate and a low-doped P region on the other side, and the doping concentration of the N region is 10 20 cm -3 , and the doping concentration of the P region is 10 18 cm -3 .

[0070] Step 105, performing TCAD simulation using the layout information, the geometric information and the PN region distribution information, and determining the robust performance of the electrostatic discharge structure of the chip according to the obtained electrical characteristic information.

[0071] The purpose of this step is to use the relevant information obtained in the above steps to perform TCAD simulation to simulate the performance of the ESD structure under actual working conditions. The main implementation steps can be described in detail as follows: First, the simulation parameters of the TCAD simulation are set according to the determined layout information, geometric parameters and PN area distribution information.

[0072] Then, run TCAD software to simulate the behavior of the ESD structure under electrostatic discharge shock.

[0073] Furthermore, the simulation results output by the TCAD simulation are analyzed to determine the electrical characteristic information of the ESD structure, such as the internal temperature distribution.

[0074] Finally, the robustness of the ESD structure can be accurately evaluated based on the electrical characteristics information of the ESD structure.

[0075] The electrostatic discharge structure robustness evaluation method provided by the present invention provides an electrostatic discharge structure robustness evaluation means based on structure extraction and TCAD simulation, which does not require device design manufacturers to provide circuit schematics and layouts of the electrostatic discharge structure, nor does it require them to provide process parameters, thereby effectively improving the efficiency of ESD structure robustness evaluation of semiconductor devices.

[0076] Based on the content of the above embodiment, as an optional embodiment, performing cross-section coloring processing on the electrostatic discharge structure according to the circuit schematic to obtain geometric information of the electrostatic discharge structure includes: Determining a target position for cutting the electrostatic discharge structure according to the circuit schematic diagram to perform cutting of the electrostatic discharge structure, wherein the target position is determined based on a core component that performs an electrostatic discharge protection function in the electrostatic discharge structure; dyeing the cut cross section with a dye to distinguish different material layers and structures on the cross section by different colors; According to the color distribution on the cross section, the geometric information of the electrostatic discharge structure is determined.

[0077] In the step of dyeing the cross section of the ESD structure, determining the target position for cutting is a crucial process for physical cutting, because different cutting positions will directly affect the quality and relevance of the obtained interface information.

[0078] The determination of the target location can generally be based on the following factors: (1) Consider the functional importance. First, it is necessary to identify the areas that are critical to the discharge protection function of the ESD structure, such as some key protection components, including diodes, MOSFETs, SCRs, etc.

[0079] (2) Consider design complexity. In the design of semiconductor devices, there are areas with complex structures or potential weaknesses, such as multi-layer interconnection areas and high-density doping areas.

[0080] (3) Reference to previous test results. If existing test or simulation results indicate that certain areas may have problems, these areas should be considered critical areas.

[0081] (4) Combined with the analysis of layout information. By analyzing the layout information, the key components and connections in the design can be identified. These areas can usually be used as the preferred locations for physical cutting.

[0082] For example, a CMOS chip with multiple metallization and polysilicon layers needs to be robustly evaluated. Since the chip is designed for high voltage applications and has a complex ESD protection structure, the target location for physical cutting can be determined in the following way: First, by reviewing the layout information, it was found that there was a specially designed ESD protection diode in the CMOS chip, which was connected between the power supply and the ground and was located in a high current density area. Considering the key role of this protection diode in ESD protection, it can be identified as a critical area.

[0083] Further analysis shows that the connection area of ​​the protection diode involves complex interconnections of multiple layers of metallization and polysilicon layers, which also increases the necessity of physical cutting to examine the connections and structural integrity of these layers in detail. Therefore, the so-called target location in the center area of ​​the diode can be selected for physical cutting, which can provide a comprehensive view of the multi-layer structure, including the connections of the metallization and polysilicon layers.

[0084] Cutting is done using high-precision tools such as a Focused Ion Beam (FIB) or a diamond saw to ensure smooth and precise cross-sections.

[0085] Once the cutting is complete, the cross section can be stained with a specific stain to differentiate between different material layers and structures.

[0086] As an optional embodiment, in the process of performing cross-section staining in the present invention, a stain is used to enhance the contrast between different material layers, so that each layer can be more clearly observed and distinguished under a microscope. The following is a specific implementation method of the cross-section staining step, which is explained in conjunction with an example: First, you need to choose the right stain. The choice of stain depends on the material characteristics that need to be observed and the contrast required. For example, to distinguish between silicon and silicon dioxide layers, you can use stains specifically for these materials. Suppose you need to evaluate a cross-section containing a silicon substrate and a silicon dioxide insulating layer, you can choose to use techniques such as selenium staining or indium staining, which can enhance the contrast between silicon and silicon dioxide.

[0087] Prior to staining, the sections may be cleaned to remove any debris or impurities that may have been introduced during the cutting process; this is typically accomplished by chemical cleaning or ultrasonic cleaning.

[0088] The cross section is exposed to the stain, which will selectively adsorb or react with the material depending on its properties. For example, a selenium stain may form selenides with silicon but not with silicon dioxide, resulting in a visible stain layer on the silicon layer. After staining, the cross section needs to be thoroughly dried to prevent dissolution or shedding of the stain.

[0089] Finally, the dyed cross-section can be observed using a scanning electron microscope (SEM) or a transmission electron microscope (TEM). The dye will show a specific color under the microscope, clearly showing the boundaries and structures of different material layers.

[0090] Through this staining and observation process, detailed information about the internal structure of the ESD protection structure can be obtained, which is crucial for understanding the working principle of the device and optimizing the design.

[0091] Figure 3 is a schematic diagram of setting the cross-sectional coloring size of an ESD structure provided by the present invention, Figure 3As shown in the figure, for example, the thickness of the n-type doped epitaxial layer grown on the single crystal silicon substrate Silicon Substrate by the Epitaxy process can be accurately determined to be 5μm, and the prepared P-region junction depth is 1.5μm. The electrostatic discharge structure robustness evaluation method provided by the present invention uses cross-sectional dyeing to obtain the geometric information of the ESD structure, which can clearly reveal the internal hierarchy and microstructure of the ESD structure. These parameters are crucial to understanding the electrical behavior of semiconductor devices in ESD events, and are helpful to comprehensively evaluate the performance of the ESD structure, including response speed, current discharge capability, and voltage clamping effect. TCAD simulation is an important tool for evaluating the robustness of ESD structures. The precise geometric information obtained by cross-sectional dyeing is used as simulation input to improve the accuracy of the simulation results, making the simulation closer to actual working conditions.

[0092] Based on the contents of the above embodiments, as an optional embodiment, the geometric information includes one or more of gate length, channel length, and junction depth.

[0093] The gate length is a key parameter for controlling current in MOSFETs. The gate length can be measured in SEM or TEM images using image analysis software. The channel length directly affects the switching characteristics and current drive capability of the device. Image analysis software is also used to measure the length of the channel region. Measuring the depth of the PN junction is critical for evaluating the electrical characteristics and ESD performance of the device.

[0094] Based on the content of the above embodiment, as an optional embodiment, detecting the target area in the electrostatic discharge structure to obtain the PN region distribution information of the electrostatic discharge structure includes: Performing scanning capacitance microscopy detection on the target area to determine the positions of the P region and the N region of the electrostatic discharge structure according to the detected doping distribution information of the target area; The positions of the P region and the N region are detected by scanning diffuse resistance microscopy to obtain the doping concentration information of each P region and each N region.

[0095] Scanning Capacitance Microscopy (SCM) is a technique used to characterize the doping concentration distribution of surface and near-surface regions of semiconductor materials. SCM infers the doping level by measuring the change in capacitance of the sample, as the doping concentration directly affects the capacitance properties of the material.

[0096] Figure 4 : is a schematic diagram of an SCM image of an ESD structure provided by the present invention, such as Figure 4As shown, the present invention mainly detects doping distribution by SCM scanning method. SCM detection infers the doping level by measuring the capacitance change of the sample, because the doping concentration directly affects the capacitance characteristics of the material. The following are the specific implementation steps of SCM detection: First, identify the target area in the ESD structure and use it as the sample for detection, and ensure that the sample surface is clean and free of oxide layers or other contaminants. If necessary, the sample can be properly surface treated, such as polishing or chemical treatment, to obtain a clear surface. SCM usually works in non-contact mode, using a very sharp probe (usually a conductive tip on a cantilever beam) to approach the sample surface but not actually touch it.

[0097] An AC bias is applied between the probe and the sample. This bias creates a capacitor between the sample surface and the probe. The change in capacitance between the probe tip and the sample surface is measured. Since changes in doping concentration affect the capacitance value, changes in doping concentration can be inferred by measuring the change in capacitance. The probe is scanned over the sample surface, usually in a grid-like path. The above measurement process is repeated at each scan point.

[0098] Finally, the capacitance data of each scanning point is collected and a doping concentration distribution map, namely SCM image, is generated. These images can intuitively show the doping concentration changes on the sample surface. In this way, the positions of the P and N regions in the PN region distribution information in the ESD structure can be accurately determined based on the doping concentration changes.

[0099] Scanning Spreading Resistance Microscopy (SSRM) is a technique used to characterize the micro-area resistivity distribution of semiconductor materials. It is particularly suitable for analyzing the doping concentration distribution in semiconductor devices, which is crucial for understanding and optimizing device performance. SSRM technology is widely used in semiconductor manufacturing and research, especially in process development and failure analysis.

[0100] The present invention can use SSRM to scan the determined P region and N region, and determine the doping concentration of different regions through the change of resistance. The main implementation steps include but are not limited to: A very sharp probe (usually a passivated tungsten or platinum-iridium alloy tip) is used, which is brought into contact with the sample surface. A known small current (usually in the nA to μA range) is injected through the probe, and the voltage change resulting from the injected current is measured.

[0101] Then, according to Ohm's law (V=IR), the resistance of the material under the probe is calculated from the measured voltage and the injected current. Since the geometric dimensions of the area where the probe contacts the sample are known, the resistivity of the material can be further calculated.

[0102] The probe scans the sample surface, usually in a grid-like path. The above measurement process is repeated at each scanning point. The resistivity data of each scanning point is collected and a resistivity distribution map, i.e., SSRM image, is generated. These images can intuitively show the resistivity changes on the sample surface, thereby reflecting the distribution of doping concentration.

[0103] It should be noted that the advantages of SSRM technology are its non-destructiveness and high spatial resolution, which can provide resistivity information at the microscopic scale without damaging the sample. SSRM can provide a two-dimensional or three-dimensional distribution map of the doping concentration in semiconductor materials, which is crucial for optimizing device design and manufacturing processes. Therefore, SSRM provides an effective means to study the resistivity characteristics and doping effects of materials.

[0104] Based on the content of the above embodiment, as an optional embodiment, the use of the layout information, the geometric information and the PN region distribution information to perform TCAD simulation, and determining the robust performance of the electrostatic discharge structure of the chip according to the obtained electrical characteristic information, includes: Setting simulation parameters of TCAD simulation according to the layout information, the geometric information and the PN area distribution information; According to the simulation parameters, simulating the behavior of the electrostatic discharge structure under at least one electrostatic discharge impact, and obtaining electrical characteristic information of the electrostatic discharge structure; The robust performance of the electrostatic discharge structure is determined according to the acquired electrical characteristic information.

[0105] The present invention mainly evaluates the robustness of the ESD structure by obtaining the electrical characteristic information of the ESD structure through TCAD simulation, including the current-time (It) curve, the voltage-time curve (Vt), the current-voltage curve (IV), characteristic information related to the internal temperature distribution, etc.

[0106] Assume that by collecting electrical characteristic information, it is found that under a 2000V electrostatic discharge shock, the current of the protection diode of the ESD structure rises rapidly, but the internal temperature does not exceed the thermal stability limit of the material. Therefore, it can be evaluated that this ESD structure has good robustness and can protect the chip from damage under high electrostatic discharge conditions.

[0107] As an optional embodiment, the electrical characteristic information includes one or more characteristic information related to a current-time curve, a voltage-time curve, a current-voltage curve, and an internal temperature distribution; The characteristic information related to the current-time curve includes response speed, peak current, and duration; The characteristic information related to the voltage-time curve includes voltage clamping and voltage recovery time; The characteristic information related to the current-voltage curve includes breakdown voltage and post-breakdown behavior; The characteristic information related to the internal temperature distribution includes the internal hot spot magnitude distribution position and the hot spot temperature rise.

[0108] When evaluating the ESD structural performance and robustness of semiconductor devices, it is crucial to analyze the It curve, Vt curve, IV curve, and internal temperature distribution information obtained from simulation. The following is a detailed description of these curves and information, and how they reflect ESD performance: The It curve shows how the current through the device changes over time during electrostatic discharge.

[0109] The response speed refers to the initial rise speed of the It curve, which indicates the speed at which the ESD structure responds to electrostatic discharge. If the fast response is ideal, it means that it can quickly discharge the charge and reduce damage to the device.

[0110] The peak current is the maximum value of the current in the It curve, which indicates the maximum current that the semiconductor device can withstand during an ESD event. This value should be lower than the maximum withstand capacity of the device to avoid thermal damage or structural destruction.

[0111] Duration refers to the length of time that the current is maintained at a high level. If a long high current duration is determined by the It curve, it may cause the device to overheat and affect the long-term stability and reliability of the ESD structure.

[0112] The Vt curve shows the change in voltage across the ESD structure over time.

[0113] An ideal ESD structure should be able to quickly clamp the voltage within a safe range to prevent device damage caused by excessive voltage. Therefore, the robustness of the ESD structure can be evaluated by focusing on voltage clamping.

[0114] Voltage recovery time is the time it takes for the voltage to drop from its peak value to a safe level. A fast recovery time is beneficial because it reduces the time a device is exposed to high voltage.

[0115] The IV curve describes the current through the ESD structure at different voltages.

[0116] The breakdown voltage is the voltage threshold at which the device begins to conduct electricity significantly. The breakdown voltage should be as high as possible to ensure that the ESD structure will not conduct under normal operating voltage and will only activate when an ESD event occurs.

[0117] Additionally, the IV curve can show the behavior of the device after breakdown, including whether it is able to limit current and prevent overcurrent damage.

[0118] The temperature distribution inside the ESD structure refers to the temperature distribution inside the device during an ESD event. The temperature distribution diagram can reveal hot spots inside the ESD structure, that is, areas with abnormally high temperatures. These areas may be the most vulnerable parts in an ESD event. At the same time, the temperature rise of the hot spot can indicate the thermal stability of the device during an ESD event. Excessive temperature rise may cause performance degradation or permanent damage to the ESD structure material.

[0119] In summary, the electrostatic discharge structure robustness evaluation method provided by the present invention can accurately evaluate the robustness of the ESD structure by combining the above electrical characteristic information. The ideal ESD structure should be able to respond quickly to ESD events, effectively limit current and voltage, and maintain a low internal temperature throughout the process. Through these detailed analyses, the performance of the ESD structure can be comprehensively evaluated and a scientific basis can be provided for further design optimization.

[0120] Furthermore, if the analysis finds that certain parameters are not ideal, such as slow response speed, too high peak current or too high internal hot spot temperature, the ESD structure design can be adjusted specifically, such as changing materials, adjusting device layout or adding heat dissipation measures.

[0121] Figure 5 is a schematic diagram of the structure of the electrostatic discharge structural robustness evaluation device provided by the present invention, such as Figure 5 As shown, it mainly includes: A layout information acquisition unit 51 is used to remove the chip layer by layer to obtain the layout information of the chip; A circuit principle analysis unit 52, configured to perform circuit analysis on the layout information to obtain a circuit principle diagram of an electrostatic discharge structure in the chip; A geometric information acquisition unit 53, configured to perform cross-sectional coloring processing on the electrostatic discharge structure according to the circuit schematic diagram to obtain geometric information of the electrostatic discharge structure; A doping concentration analysis unit 54 is used to detect a target area in the electrostatic discharge structure to obtain PN region distribution information of the electrostatic discharge structure, wherein the PN region distribution information includes the positions of the P region and the N region and the doping concentration information of each P region and each N region, and the target area is determined according to the geometric information of the electrostatic discharge structure; The robust performance analysis unit 55 is used to perform TCAD simulation using the layout information, the geometric information and the PN region distribution information, and determine the robust performance of the electrostatic discharge structure of the chip according to the obtained electrical characteristic information.

[0122] It should be noted that the electrostatic discharge structure robustness assessment device provided by the present invention can execute the electrostatic discharge structure robustness assessment method described in any of the above embodiments during specific operation, which will not be elaborated in this embodiment.

[0123] The electrostatic discharge structure robustness evaluation device provided by the present invention provides an electrostatic discharge structure robustness evaluation method based on structure extraction and TCAD simulation. It does not require device design manufacturers to provide circuit schematics and layouts of electrostatic discharge structures, nor does it require them to provide process parameters, thereby effectively improving the efficiency of ESD structure robustness evaluation of semiconductor devices.

[0124] Figure 6 is a schematic diagram of the structure of the electronic device provided by the present invention, such as Figure 6 As shown, the electronic device may include: a processor (processor) 610 , a communication interface (Communications Interface) 620 , a memory (memory) 630 and a communication bus 640 , wherein the processor 610 , the communication interface 620 , and the memory 630 communicate with each other through the communication bus 640 . The processor 610 can call the logic instructions in the memory 630 to execute the electrostatic discharge structure robustness evaluation method, which includes: removing the chip layer by layer to obtain the layout information of the chip; performing circuit analysis on the layout information to obtain the circuit schematic diagram of the electrostatic discharge structure in the chip; performing cross-sectional dyeing processing on the electrostatic discharge structure according to the circuit schematic diagram to obtain the geometric information of the electrostatic discharge structure; detecting the target area in the electrostatic discharge structure to obtain the PN region distribution information of the electrostatic discharge structure, the PN region distribution information includes the position of the P region and the N region and the doping concentration information of each P region and each N region, and the target area is determined according to the geometric information of the electrostatic discharge structure; using the layout information, the geometric information and the PN region distribution information to perform TCAD simulation, and determine the robust performance of the electrostatic discharge structure of the chip according to the obtained electrical characteristic information.

[0125] In addition, the logic instructions in the above-mentioned memory 630 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0126] On the other hand, the present invention also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the electrostatic discharge structure robustness evaluation method provided by the above-mentioned embodiments, the method including: removing the chip layer by layer to obtain the layout information of the chip; performing circuit analysis on the layout information to obtain the circuit schematic diagram of the electrostatic discharge structure in the chip; performing cross-sectional dyeing processing on the electrostatic discharge structure according to the circuit schematic diagram to obtain the geometric information of the electrostatic discharge structure; detecting the target area in the electrostatic discharge structure to obtain the PN region distribution information of the electrostatic discharge structure, the PN region distribution information including the position of the P region and the N region and the doping concentration information of each P region and each N region, and the target area is determined according to the geometric information of the electrostatic discharge structure; performing TCAD simulation using the layout information, the geometric information and the PN region distribution information, and determining the robust performance of the electrostatic discharge structure of the chip according to the obtained electrical characteristic information.

[0127] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which is implemented when the processor executes the electrostatic discharge structure robustness evaluation method provided in the above-mentioned embodiments, the method comprising: removing the chip layer by layer to obtain the layout information of the chip; performing circuit analysis on the layout information to obtain the circuit schematic diagram of the electrostatic discharge structure in the chip; performing cross-sectional dyeing processing on the electrostatic discharge structure according to the circuit schematic diagram to obtain the geometric information of the electrostatic discharge structure; detecting the target area in the electrostatic discharge structure to obtain the PN region distribution information of the electrostatic discharge structure, the PN region distribution information including the position of the P region and the N region and the doping concentration information of each P region and each N region, and the target area is determined according to the geometric information of the electrostatic discharge structure; performing TCAD simulation using the layout information, the geometric information and the PN region distribution information, and determining the robust performance of the electrostatic discharge structure of the chip according to the obtained electrical characteristic information.

[0128] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0129] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0130] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for evaluating the robustness of an electrostatic discharge structure, characterized in that: include: Removing the chip layer by layer to obtain layout information of the chip; Performing circuit analysis on the layout information to obtain a circuit schematic diagram of an electrostatic discharge structure in the chip; Performing cross-sectional coloring processing on the electrostatic discharge structure according to the circuit schematic diagram to obtain geometric information of the electrostatic discharge structure; Detecting a target area in the electrostatic discharge structure to obtain PN region distribution information of the electrostatic discharge structure, wherein the PN region distribution information includes positions of a P region and an N region and doping concentration information of each P region and each N region, wherein the target area is determined according to geometric information of the electrostatic discharge structure; The layout information, the geometric information and the PN region distribution information are used to perform TCAD simulation, and the robust performance of the electrostatic discharge structure of the chip is determined according to the obtained electrical characteristic information.

2. The electrostatic discharge structural robustness evaluation method according to claim 1, characterized in that: The chip is removed layer by layer to obtain the layout information of the chip, including: Based on physical grinding or chemical etching methods, each passivation layer, each metallization layer, and each polysilicon layer of the chip are removed layer by layer until the substrate is completely exposed; After each layer is removed, a microscope is used to record information about the next layer’s layout; The layout information includes the layout information of the chip, as well as the position and shape information of the components contained in each layer of the chip, the component size information, the component connection relationship information and the design rule information of the components.

3. The electrostatic discharge structural robustness evaluation method according to claim 1, characterized in that: The step of performing cross-section coloring processing on the electrostatic discharge structure according to the circuit schematic diagram to obtain geometric information of the electrostatic discharge structure includes: Determining a target position for cutting the electrostatic discharge structure according to the circuit schematic diagram to perform cutting of the electrostatic discharge structure, wherein the target position is determined based on a core component that performs an electrostatic discharge protection function in the electrostatic discharge structure; dyeing the cut cross section with a dye to distinguish different material layers and structures on the cross section by different colors; According to the color distribution on the cross section, the geometric information of the electrostatic discharge structure is determined.

4. The electrostatic discharge structural robustness evaluation method according to claim 3, characterized in that: The geometric information includes one or more of gate length, channel length, and junction depth.

5. The electrostatic discharge structural robustness evaluation method according to claim 1, characterized in that: The detecting the target area in the electrostatic discharge structure to obtain the PN region distribution information of the electrostatic discharge structure includes: Performing scanning capacitance microscopy detection on the target area to determine the positions of the P region and the N region of the electrostatic discharge structure according to the detected doping distribution information of the target area; The positions of the P region and the N region are detected by scanning diffuse resistance microscopy to obtain the doping concentration information of each P region and each N region.

6. The electrostatic discharge structural robustness evaluation method according to claim 1, characterized in that: The method of performing TCAD simulation using the layout information, the geometric information and the PN region distribution information, and determining the robust performance of the electrostatic discharge structure of the chip according to the obtained electrical characteristic information, includes: Setting simulation parameters of TCAD simulation according to the layout information, the geometric information and the PN area distribution information; According to the simulation parameters, simulating the behavior of the electrostatic discharge structure under at least one electrostatic discharge impact, and obtaining electrical characteristic information of the electrostatic discharge structure; The robust performance of the electrostatic discharge structure is determined according to the acquired electrical characteristic information.

7. The electrostatic discharge structural robustness evaluation method according to claim 6, characterized in that: The electrical characteristic information includes one or more of characteristic information related to a current-time curve, a voltage-time curve, a current-voltage curve, and an internal temperature distribution; The characteristic information related to the current-time curve includes response speed, peak current, and duration; The characteristic information related to the voltage-time curve includes voltage clamping and voltage recovery time; The characteristic information related to the current-voltage curve includes breakdown voltage and post-breakdown behavior; The characteristic information related to the internal temperature distribution includes the internal hot spot magnitude distribution position and the hot spot temperature rise.

8. An electrostatic discharge structural robustness evaluation device, characterized in that: include: A layout information acquisition unit, used to remove the chip layer by layer to obtain the layout information of the chip; A circuit principle analysis unit, used to perform circuit analysis on the layout information to obtain a circuit principle diagram of the electrostatic discharge structure in the chip; A geometric information acquisition unit, used to perform cross-sectional coloring processing on the electrostatic discharge structure according to the circuit schematic diagram to obtain geometric information of the electrostatic discharge structure; a doping concentration analysis unit, configured to detect a target region in the electrostatic discharge structure and obtain PN region distribution information of the electrostatic discharge structure, wherein the PN region distribution information includes positions of a P region and an N region and doping concentration information of each P region and each N region, wherein the target region is determined according to geometric information of the electrostatic discharge structure; The robust performance analysis unit is used to perform TCAD simulation using the layout information, the geometric information and the PN area distribution information, and determine the robust performance of the electrostatic discharge structure of the chip according to the obtained electrical characteristic information.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the electrostatic discharge structure robustness evaluation method according to any one of claims 1 to 7 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the electrostatic discharge structure robustness evaluation method according to any one of claims 1 to 7 is implemented.

11. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the electrostatic discharge structure robustness evaluation method according to any one of claims 1 to 7 is implemented.

Images