A broadband millimeter wave packaging method and packaging device for radio frequency MMIC PA chip

Abstract

The present invention provides a broadband millimeter wave packaging method and packaging device for a radio frequency MMIC PA chip, and relates to the field of broadband millimeter wave packaging technology. The present invention significantly improves the design accuracy and reliability by introducing a closed-loop optimization mechanism based on simulation and actual test data. By dynamically adjusting the design requirements, the scheme effectively solves the error accumulation problem existing in the traditional packaging design process, ensures the performance balance of equivalent thermal resistance and compressive strength, and thus meets the multi-objective optimization requirements. At the same time, the optimized packaging structure can exhibit excellent heat dissipation performance and mechanical stability in harsh working environments, reduces development costs and shortens the R&D cycle, and provides important support for the industrial application of layered wafer packaging technology.

Description

Technical Field

[0001] The present invention relates to the technical field of broadband millimeter wave packaging, and in particular to a broadband millimeter wave packaging method and a packaging device for a radio frequency MMIC PA chip. Background Art

[0002] In recent years, with the development of wireless communication technology, the demand for radio frequency microelectronic integrated circuits (RF MMIC) has been growing, especially in the application of millimeter wave frequency bands. However, the traditional plastic packaging method has some problems in the millimeter wave frequency band, such as poor heat dissipation and poor reliability. Therefore, how to improve the high-performance broadband millimeter wave high-reliability packaging solution of RF MMIC PA chips has become an important issue in the current technological development. In traditional methods, it is usually based on preliminary simulation analysis and limited experimental verification, which makes it difficult for design parameters to accurately match actual application requirements. Especially in multi-objective optimization scenarios (such as the coexistence of low thermal resistance and high compressive strength), traditional methods often produce performance deviations due to the error between the simulation model and the actual measurement results. In addition, the existing technology lacks a quantitative error correction mechanism when dealing with material performance fluctuations and complex process conditions, resulting in extended design cycles and unstable product performance. Faced with the packaging requirements of high-power chips, high-frequency circuits and harsh working environments, there is an urgent need for a design method that can dynamically correct design requirements and fully optimize thermal management and mechanical properties.

[0003] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0004] The object of the present invention is to provide a broadband millimeter wave packaging method and packaging device for a radio frequency MMIC PA chip, so as to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A broadband millimeter wave packaging method for a radio frequency MMIC PA chip, the specific steps comprising:

[0007] S1: In the simulation software, design a multi-layer stacked layered wafer packaging structure and build a corresponding simulation model, and set a π-type matching network in the simulation model;

[0008] S2: Determine the material type and material thickness of each layer in the layered wafer packaging structure based on the design requirements, perform simulation analysis on the layered wafer packaging structure, and generate corresponding simulation parameters;

[0009] S3: After changing the composition ratio of the polymer layer in the layered wafer packaging structure, simulation analysis is performed again, and the process is repeated multiple times to generate a relationship equation between the composition ratio of the polymer and the simulation parameters;

[0010] S4: Repeat steps S2 to S3, iteratively solve the relationship equation based on the design requirements, obtain the optimal proportion of different components in the polymer, and construct the test sample based on the optimal proportion;

[0011] S5: measuring the test samples to obtain actual parameters, comparing the actual parameters with the simulation parameters to obtain error coefficients, using the error coefficients to correct the design requirements, and obtaining the final layered wafer packaging structure based on the corrected design requirements.

[0012] Preferably, the simulation parameters and actual parameters are the equivalent thermal resistance and equivalent compressive strength of the layered wafer packaging structure during simulation analysis and actual measurement, respectively;

[0013] The design requirements include impedance of the RF port and chip, center frequency, target compressive strength, target thermal resistance, target thickness and cost budget.

[0014] Preferably, the π-type matching network is arranged between the RF port and the chip of the layered wafer packaging structure, and includes two capacitors and an inductor, the inductor is connected in series between the RF port and the chip, and the two capacitors are respectively connected in parallel at both ends of the inductor and the other end is grounded;

[0015] In the π-type matching network, the two capacitors and the inductor are calculated as follows:

[0016] ;

[0017] ;

[0018] ;

[0019] In the formula , Represent the impedance of the RF port and chip respectively, Indicates the capacitance of the capacitor close to the RF port. Indicates the capacitance value of the capacitor close to the chip. Indicates the inductance value of the inductor, Indicates the preset center frequency.

[0020] Preferably, the method for determining the material type and material thickness of metal, ceramic and polymer in the layered wafer packaging structure is:

[0021] Calculate the thermal resistance and compressive strength of each material layer of the layered wafer packaging structure under different material categories;

[0022] Calculate the overall equivalent thermal resistance and equivalent compressive strength of the layered wafer packaging structure based on the thermal resistance and compressive strength of each material layer;

[0023] A scoring function among equivalent thermal resistance, equivalent compressive strength and material cost is constructed. The thickness requirement and cost budget of the layered wafer packaging structure are used as constraints. The calculation equations of thermal resistance and compressive strength are solved simultaneously using a genetic algorithm. The material thickness of each material corresponding to the highest score function value is taken as the final solution.

[0024] Preferably, the calculation method of the equivalent thermal resistance and equivalent compressive strength of the layered wafer packaging structure is:

[0025] ;

[0026] ;

[0027] In the formula , They represent the equivalent thermal resistance and equivalent compressive strength of the layered wafer packaging structure as a whole, , , Respectively represent Material thickness, thermal conductivity and compressive strength of each material layer, subscript Indicates the index of the material layer, , Indicates the total number of layers, Represents the cross-sectional area of ​​a material layer, and the cross-sectional areas of all material layers are the same.

[0028] Preferably, the score function is expressed as:

[0029] ;

[0030] In the formula represents the score function, , , Both represent the weight coefficients of the score function, where ,and , , , represent the target compressive strength, target thermal resistance and cost budget respectively, Represents the material cost, which is calculated as:

[0031] ;

[0032] in , Respectively represent The density and unit price of each material layer;

[0033] The constraints are expressed as:

[0034] ;

[0035] In the formula Indicates the target thickness.

[0036] Preferably, when the relationship equation between the polymer component ratio and the simulation parameters is fitted by a regression analysis method, the relationship equations between the polymer component ratio and the equivalent thermal resistance and the equivalent compressive strength are respectively expressed as:

[0037] ;

[0038] ;

[0039] In the formula , They represent the relationship equations between the polymer composition ratio and the equivalent thermal resistance and equivalent compressive strength, respectively. Indicates the polymer The proportion of ingredients in represents the index of the component in the polymer, and , Indicates the total number of ingredients.

[0040] Preferably, the error coefficient is calculated as follows:

[0041] ;

[0042] In the formula represents the error coefficient, , Respectively represent the equivalent thermal resistance and equivalent compressive strength measured on the test sample;

[0043] The calculation method for modifying the design requirements is:

[0044] ;

[0045] .

[0046] A packaging device includes an MMIC PA chip package, and the MMIC PA chip package is designed using the above-mentioned design method.

[0047] Compared with the prior art, the present invention has the following beneficial effects:

[0048] The present invention significantly improves the design accuracy and reliability by introducing a closed-loop optimization mechanism based on simulation and actual test data. By dynamically adjusting the design requirements, the solution effectively solves the error accumulation problem existing in the traditional packaging design process, ensures the performance balance of equivalent thermal resistance and compressive strength, and thus meets the multi-objective optimization requirements. At the same time, the optimized packaging structure can exhibit excellent heat dissipation performance and mechanical stability in harsh working environments, reducing development costs and shortening the R&D cycle, providing important support for the industrial application of layered wafer packaging technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a schematic diagram of the overall method flow of the present invention. DETAILED DESCRIPTION

[0050] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments.

[0051] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0052] Example:

[0053] See also Figure 1 , the present invention provides a technical solution:

[0054] A broadband millimeter wave packaging method for a radio frequency MMIC PA chip, the specific steps comprising:

[0055] S1: In the simulation software, design a multi-layer stacked layered wafer packaging structure and construct a corresponding simulation model, and set a π-type matching network in the simulation model.

[0056] The π-type matching network is arranged between the RF port of the layered wafer packaging structure and the chip, and includes two capacitors and an inductor. The inductor is connected in series between the RF port and the chip, and the two capacitors are connected in parallel at both ends of the inductor, and the other end is grounded.

[0057] In the π-type matching network, the calculation methods of the two capacitors and inductor are:

[0058] ;

[0059] ;

[0060] ;

[0061] In the formula , Represent the impedance of the RF port and chip respectively, Indicates the capacitance of the capacitor close to the RF port. Indicates the capacitance value of the capacitor close to the chip. Indicates the inductance value of the inductor, Indicates the preset center frequency.

[0062] In this embodiment, it is assumed that the RF port impedance of the package , the impedance of the chip , the preset center frequency is 28GHz, then the goal of the π-type matching network is to convert 50Ω to 10Ω, , , .

[0063] By designing a π-type matching network between the RF port and the chip input, it is not only possible to achieve impedance matching, but also to improve the transmission efficiency of millimeter-wave signals, reduce signal reflection and loss, and ensure the optimization of packaging performance. Specifically, the capacitor in the π-type matching network , Both can be realized by using microstrip line open branches or chip capacitors. This can be achieved using microstrip line short-circuit branches or chip inductors.

[0064] In this step, the layered wafer packaging structure is used to reduce the package size and increase the packaging density to improve the reliability of the PA chip. By introducing a π-type matching network between the RF port and the chip, it can adapt to the requirements of different RF ports and chip impedances, making the packaging solution more versatile and adaptable. For example, there is no need to change the impedance of the chip or the RF port itself, but to achieve matching through a π-type network, which has higher design flexibility and reduces design complexity and R&D costs. In addition, the wideband matching characteristics of the π-type matching network can also provide guarantees for the stable performance of the package in the high-frequency range, which is more suitable for broadband millimeter-wave packaging, and plays a role in improving the transmission efficiency of millimeter-wave signals and reducing signal reflection losses. It has the advantages of simple structure, high flexibility, and suitability for high-frequency environments.

[0065] S2: Determine the material category and material thickness of each layer in the layered wafer packaging structure based on design requirements, including the impedance of the RF port and chip, center frequency, target compressive strength, target thermal resistance, target thickness and cost budget, and perform simulation analysis on the layered wafer packaging structure to generate corresponding simulation parameters.

[0066] The method for determining the material category and material thickness of metals, ceramics, and polymers in layered wafer packaging structures is:

[0067] Calculate the thermal resistance and compressive strength of each material layer of the layered wafer packaging structure under different material categories;

[0068] Calculate the overall equivalent thermal resistance and equivalent compressive strength of the layered wafer packaging structure based on the thermal resistance and compressive strength of each material layer;

[0069] A scoring function among equivalent thermal resistance, equivalent compressive strength and material cost is constructed. The thickness requirement and cost budget of the layered wafer packaging structure are used as constraints. The calculation equations of thermal resistance and compressive strength are solved simultaneously using a genetic algorithm. The material thickness of each material corresponding to the highest score function value is taken as the final solution.

[0070] The calculation method of the equivalent thermal resistance and equivalent compressive strength of the layered wafer packaging structure is:

[0071] ;

[0072] ;

[0073] In the formula , They represent the equivalent thermal resistance and equivalent compressive strength of the layered wafer packaging structure as a whole, , , Respectively represent Material thickness, thermal conductivity and compressive strength of each material layer, subscript Indicates the index of the material layer, , Indicates the total number of layers, Represents the cross-sectional area of ​​the material layer, and the cross-sectional area of ​​all material layers is the same. It is understandable that due to the characteristics of the chip's environment, one of the indicators that most affects its working performance is the heat dissipation capacity, and in actual use, the chip surface is generally covered with a device such as a heat sink, so its compressive strength is a factor that needs to be considered. Although compressive strength is related to the inherent properties of the material (such as crystal structure, density, and manufacturing process), and usually does not change directly due to changes in thickness, after forming a layered wafer packaging structure, when calculating its overall equivalent compressive strength, the thickness and compressive strength of each layer of material will jointly determine its contribution to the overall equivalent compressive strength, so its specific thickness needs to be considered.

[0074] The score function is expressed as:

[0075] ;

[0076] In the formula represents the score function, , , Both represent the weight coefficients of the score function, where ,and , , , They represent the target compressive strength, target thermal resistance and cost budget respectively. It can be seen that the larger the score function, the greater the equivalent strength, and the smaller the equivalent thermal resistance and material cost. The weight coefficient is set here to take into account the need to give priority to meeting the quality requirements of the PA chip, then meet its performance requirements, and finally meet its cost requirements. By adjusting the size of the weight coefficient, the design goal can be flexibly adjusted (for example, paying more attention to heat dissipation performance or compressive performance), providing designers with a clear decision-making basis and optimization direction.

[0077] Represents the material cost, which is calculated as:

[0078] ;

[0079] in , Respectively represent The density and unit price of each material layer;

[0080] The constraints are expressed as:

[0081] ;

[0082] In the formula Indicates the target thickness.

[0083] Traditional packaging design often focuses on a single performance such as thermal management or mechanical strength, ignoring the comprehensive optimization of multiple physical properties. For example, excessive pursuit of low thermal resistance may lead to insufficient mechanical strength of the package or excessive material cost. By introducing thermal resistance, compressive strength and cost into a unified scoring function, a comprehensive balance of performance can be achieved through global optimization. This design method that comprehensively considers packaging performance, mechanical reliability and cost is more scientific and reasonable, and can meet the multi-dimensional needs in practical applications.

[0084] In this step, by generating the optimal solution for the type and thickness of each layer of material, clear guidance is provided for the specific implementation of the layered wafer packaging structure, laying the foundation for the packaging structure and ensuring the feasibility and effectiveness of subsequent designs. In addition, through multi-dimensional solutions, thermal resistance, compressive strength, thickness and cost can be fully optimized. Intelligent optimization methods improve design efficiency and ensure the integrity and economy of packaging performance.

[0085] S3: After changing the composition ratio of the polymer layer in the layered wafer packaging structure, simulation analysis is performed again, and repeated multiple times to generate the relationship equation between the composition ratio of the polymer and the simulation parameters. In the layered wafer packaging structure, the polymer layer (such as epoxy resin, polyimide, etc.) is used to provide a certain mechanical elasticity, thermal expansion matching and processing flexibility. By adjusting the composition ratio of the polymer, its thermal conductivity and mechanical strength can be significantly affected, thereby affecting the equivalent thermal resistance and compressive strength of the entire packaging structure.

[0086] When the relationship equation between the polymer component ratio and the simulation parameters is fitted, the regression analysis method is used for fitting. The relationship equations between the polymer component ratio and the equivalent thermal resistance and equivalent compressive strength are expressed as follows:

[0087] ;

[0088] ;

[0089] In the formula , They represent the relationship equations between the polymer composition ratio and the equivalent thermal resistance and equivalent compressive strength, respectively. Indicates the polymer The proportion of ingredients in represents the index of the component in the polymer, and , Indicates the total number of ingredients.

[0090] In this embodiment, it is assumed that the polymer layer of the layered wafer packaging structure is mainly composed of three components, namely: thermal conductive filler (such as aluminum oxide particles or boron nitride particles), which improves the thermal conductivity of the polymer, numbered 1; matrix material (such as epoxy resin), which provides basic mechanical strength and bonding performance, numbered 2; reinforcing agent (such as glass fiber or carbon fiber), which improves the compressive strength of the polymer, numbered 3. Then correspondingly, , , ,and By using finite element simulation software (such as ANSYS, COMSOL Multiphysics) to perform thermal-structural coupling analysis and then using regression analysis methods (such as multivariate linear regression, nonlinear regression or machine learning algorithms) to fit the data set, the relationship equation between the component ratio and thermal resistance and compressive strength can be obtained.

[0091] In this step, by establishing the relationship equation between the proportion of polymer components and the equivalent thermal resistance and equivalent compressive strength, not only the thermal management performance and mechanical reliability of the layered wafer packaging structure are improved, but also more accurate material optimization and performance prediction are supported, providing both theoretical and practical support for packaging design, and providing quantitative guidance for subsequent adjustments to the polymer formula.

[0092] S4: Repeat steps S2 to S3, iteratively solve the relationship equation based on the design requirements, obtain the optimal proportion of different components in the polymer, and construct the test sample based on the optimal proportion.

[0093] Specifically, during the initial simulation modeling analysis, a benchmark formula needs to be used for the proportion of polymer components, such as 30% for thermal conductive materials, 50% for collective materials, and 20% for reinforcing agents. The material thickness of each layer of material is calculated using this formula, and then the proportions of each component are fine-tuned, and the corresponding relationship equation is fitted to obtain the proportion of components that minimizes the equivalent thermal resistance and maximizes the equivalent compressive strength. The optimal material thickness is then calculated based on the new equivalent thermal resistance and equivalent compressive strength. After repeated iterations and updates several times, the final proportion of components can be used as the optimal proportion to construct the test sample. The specific number of iterations can be set based on expert experience or simulation results.

[0094] In this step, through repeated iterations, the error is gradually reduced in each optimization, so that the polymer formula is constantly close to the design requirements, and the optimal component ratio with the minimum equivalent thermal resistance and the maximum equivalent compressive strength can be found. Combined with the results of the previous simulation modeling (S2) and regression analysis (S3), the component ratio and thickness are optimized in each iteration, forming a "closed-loop control" optimization mechanism, which significantly reduces the number of manual trial and error, improves design efficiency, and can effectively deal with practical problems such as material performance fluctuations and process control errors. The final solution is more robust and can adapt to various restrictions under actual production conditions.

[0095] S5: Measure the test samples to obtain actual parameters, compare the actual parameters with the simulation parameters to obtain error coefficients, use the error coefficients to correct the design requirements, and obtain the final layered wafer packaging structure based on the corrected design requirements. The simulation parameters and actual parameters are the equivalent thermal resistance and equivalent compressive strength of the layered wafer packaging structure during simulation analysis and actual measurement, respectively.

[0096] The error coefficient is calculated as:

[0097] ;

[0098] In the formula represents the error coefficient, , Respectively represent the equivalent thermal resistance and equivalent compressive strength measured on the test sample;

[0099] The calculation method for modifying the design requirements is:

[0100] ;

[0101] .

[0102] In this step, by introducing the error coefficient, the comparative relationship between the simulation parameters and the actual parameters can be reflected, providing quantitative indicators for optimizing the design, so that the subsequent layered wafer packaging structure is more in line with the actual process conditions and physical properties, thereby significantly improving the design accuracy and the consistency between theory and practice, reducing the workload of repeated experiments and new designs, and making the R&D process more efficient.

[0103] In summary, the present invention significantly improves the design accuracy and reliability by introducing a closed-loop optimization mechanism based on simulation and actual test data. By dynamically adjusting the design requirements, this solution effectively solves the error accumulation problem existing in the traditional packaging design process, ensures the performance balance of equivalent thermal resistance and compressive strength, and thus meets the multi-objective optimization requirements. At the same time, the optimized packaging structure can exhibit excellent heat dissipation performance and mechanical stability in harsh working environments, reducing development costs and shortening the R&D cycle, providing important support for the industrial application of layered wafer packaging technology.

[0104] The present invention further provides a packaging device, including an MMIC PA chip package, and the MMIC PA chip package is designed using the above-mentioned design method.

[0105] The above formulas are all dimensionless and numerical calculations. The formula is a formula for the most recent real situation obtained by collecting a large amount of data and performing software simulation. The preset parameters in the formula are set by technicians in this field according to actual conditions.

[0106] The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination thereof. When implemented by software, the above embodiments may be implemented in whole or in part in the form of a computer program product. Those skilled in the art may appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein may be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed by hardware or software methods depends on the specific application and design constraints of the technical solution.

[0107] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, and may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0108] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A broadband millimeter wave packaging method for a radio frequency MMIC PA chip, characterized in that: The specific steps include: S1: In the simulation software, design a multi-layer stacked layered wafer packaging structure and build a corresponding simulation model, and set a π-type matching network in the simulation model; S2: Determine the material type and material thickness of each layer in the layered wafer packaging structure based on the design requirements, perform simulation analysis on the layered wafer packaging structure, and generate corresponding simulation parameters; The simulation parameters and actual parameters are respectively the equivalent thermal resistance and equivalent compressive strength of the layered wafer packaging structure during simulation analysis and actual measurement; The design requirements include impedance of the RF port and chip, center frequency, target compressive strength, target thermal resistance, target thickness and cost budget; The method for determining the material category and material thickness of metals, ceramics, and polymers in layered wafer packaging structures is: Calculate the thermal resistance and compressive strength of each material layer of the layered wafer packaging structure under different material categories; Calculate the overall equivalent thermal resistance and equivalent compressive strength of the layered wafer packaging structure based on the thermal resistance and compressive strength of each material layer; Construct a scoring function between equivalent thermal resistance, equivalent compressive strength, and material cost, and use the overall thickness requirements and cost budget of the layered wafer packaging structure as constraints. Use a genetic algorithm to solve the calculation equations of thermal resistance and compressive strength simultaneously, and take the material thickness of each material corresponding to the highest score function value as the final solution; S3: After changing the composition ratio of the polymer layer in the layered wafer packaging structure, simulation analysis is performed again, and the process is repeated multiple times to generate a relationship equation between the composition ratio of the polymer and the simulation parameters; S4: Repeat steps S2 to S3, iteratively solve the relationship equation based on the design requirements, obtain the optimal proportion of different components in the polymer, and construct the test sample based on the optimal proportion; S5: measuring the test samples to obtain actual parameters, comparing the actual parameters with the simulation parameters to obtain error coefficients, using the error coefficients to correct the design requirements, and obtaining the final layered wafer packaging structure based on the corrected design requirements.

2. The broadband millimeter wave packaging method of a radio frequency MMIC PA chip according to claim 1, characterized in that: The π-type matching network is arranged between the RF port of the layered wafer packaging structure and the chip, and includes two capacitors and an inductor, wherein the inductor is connected in series between the RF port and the chip, and the two capacitors are connected in parallel at both ends of the inductor and the other end is grounded; In the π-type matching network, the two capacitors and the inductor are calculated as follows: In the formula , Represent the impedance of the RF port and the chip respectively, Indicates the capacitance of the capacitor close to the RF port. Indicates the capacitance value of the capacitor close to the chip. Indicates the inductance value of the inductor, Indicates the preset center frequency.

3. The broadband millimeter wave packaging method of a radio frequency MMIC PA chip according to claim 1, characterized in that: The calculation method of the equivalent thermal resistance and equivalent compressive strength of the layered wafer packaging structure is: In the formula , They represent the equivalent thermal resistance and equivalent compressive strength of the layered wafer packaging structure as a whole, , , Respectively represent Material thickness, thermal conductivity and compressive strength of each material layer, subscript Indicates the index of the material layer, , Indicates the total number of layers, Represents the cross-sectional area of ​​a material layer, and the cross-sectional areas of all material layers are the same.

4. The broadband millimeter wave packaging method of a radio frequency MMIC PA chip according to claim 3, characterized in that: The score function is expressed as: In the formula represents the score function, , , Both represent the weight coefficients of the score function, where ,and , , , represent the target compressive strength, target thermal resistance and cost budget respectively, Represents the material cost, which is calculated as: in , Respectively represent The density and unit price of each material layer; The constraints are expressed as: In the formula Indicates the target thickness.

5. The broadband millimeter wave packaging method of a radio frequency MMIC PA chip according to claim 1, characterized in that: When the relationship equation between the polymer component ratio and the simulation parameters is fitted, the regression analysis method is used for fitting. The relationship equations between the polymer component ratio and the equivalent thermal resistance and equivalent compressive strength are expressed as follows: In the formula , They represent the relationship equations between the polymer composition ratio and the equivalent thermal resistance and equivalent compressive strength, respectively. Indicates the polymer The proportion of ingredients in represents the index of the component in the polymer, and , Indicates the total number of ingredients.

6. The broadband millimeter wave packaging method of a radio frequency MMIC PA chip according to claim 5, characterized in that: The error coefficient is calculated as follows: In the formula represents the error coefficient, , Respectively represent the equivalent thermal resistance and equivalent compressive strength measured on the test sample; The calculation method for modifying the design requirements is: 。 7. A packaged device, characterized in that: The packaged device includes an MMIC PA chip package, and the MMIC PA chip package is designed using the broadband millimeter wave packaging method of the radio frequency MMIC PA chip according to any one of claims 1 to 6.

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